76
How does the CPU execute programs? Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren and Niek Janssen)

How does the CPU execute programs? - Radboud Universiteit · 2017-12-06 · 2 Overview So far… • Circuits • Memory • ALU Today… • How are instructions executed? • Fetch-decode-execute

  • Upload
    others

  • View
    7

  • Download
    0

Embed Size (px)

Citation preview

How does the CPU execute programs?Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren and Niek Janssen)

2

Overview

2

Overview

So far…• Circuits• Memory• ALU

2

Overview

So far…• Circuits• Memory• ALU

Today…• How are instructions executed?

• Fetch-decode-execute cycle• Data Path

• RUN1718 CPU - your own processor in the practicum

3

Recall: A Six-level Computer

3

Recall: A Six-level Computer

recall the levels and their meaning

3

Recall: A Six-level Computer

gates get signals 0 or 1, compute output functions (AND, OR),

may form memory or even computing engine

ALU (Arithmetic Logic Unit), registers

controls data path between ALU and registers

human-understandable

machine language

recall the levels and their meaning

4

“Von Neumann”-architecture

4

“Von Neumann”-architecture recall the structure

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

4

“Von Neumann”-architecture

Screen Keyboard

Program

Memory

recall the structure

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

4

“Von Neumann”-architecture

Screen Keyboard

Program

Memory

recall the structure

How to execute programs?

5

Program Inside the Memory

• Consists of machine code

• RUN1718 CPU: Each machine code instruction consists of 32 bits

• Other processors: 8–120 bits

Details next week!

6

Microarchitecture — Program Execution Cycle

1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)

6

Microarchitecture — Program Execution Cycle

1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)

Decode, ExecuteFetch

6

Microarchitecture — Program Execution Cycle

1.Read instruction (PC) (Fetch)2.Increase PC3.Decode instruction (Decode)4.Execute instruction (Execute)

Decode, ExecuteFetch

���@ O@; ����������

EZ =:' '=�QQ @W-PE #QW�W:' :@W ��R UU EPC6P�? 'CZ@W-P 8C=+Q �++P-QQ C3 @-]W :@QWPQW�W:' :@W ��R UU W8- �''Z?Z=�WCP* � P-6:QW-P 3CP +C:@6 �P:W8?-W:'QW�W:' :@W :@QWPR UU � 8C=+:@6 P-6:QW-P 3CP W8- 'ZPP-@W :@QWPZ'W:C@QW�W:' :@W :@QWP W^E-R UU W8- :@QWPZ'W:C@ W^E- FCE'C+-GQW�W:' :@W +�W� =C'R UU W8- �++P-QQ C3 W8- +�W�* CP �D :3 @C@-QW�W:' :@W +�W�R UU 8C=+Q W8- 'ZPP-@W CE-P�@+QW�W:' CC=-�@ PZ@ :W 1 WPZ-R UU � :W W8�W '�@ - WZP@-+ C33 WC 8�=W W8- ?�'8:@-

EZ =:' QW�W:' [C:+ :@W-PEP-WF:@W ?-?CP^% &* :@W QW�PW:@6 �++P-QQG #UU �8:Q EPC'-+ZP- :@W-PEP-WQ EPC6P�?Q 3CP � Q:?E=- ?�'8:@- \:W8 :@QWPZ'W:C@Q 8�[:@6UU C@- ?-?CP^ CE-P�@+I �8- ?�'8:@- 8�Q � P-6:QW-P �� F�''Z?Z=�WCPG* ZQ-+ 3CPUU �P:W8?-W:'I �8- ��� :@QWPZ'W:C@ �++Q �@ :@W-6-P :@ ?-?CP^ WC W8- ��* 3CP -]�?E=-IUU �8- :@W-PEP-W-P <--EQ PZ@@:@6 Z@W:= W8- PZ@ :W :Q WZP@-+ C33 ^ W8- ���� :@QWPZ'W:C@IUU �8- QW�W- C3 � EPC'-QQ PZ@@:@6 C@ W8:Q ?�'8:@- 'C@Q:QWQ C3 W8- ?-?CP^* W8-UU EPC6P�? 'CZ@W-P* W8- PZ@ :W* �@+ W8- ��I �8- :@EZW E�P�?-W-PQ 'C@Q:QW C3UU C3 W8- ?-?CP^ :?�6- �@+ W8- QW�PW:@6 �++P-QQI

�� 1 QW�PW:@6 �++P-QQR\8:=- FPZ@ :WG #:@QWP 1 ?-?CP^%��&R UU 3-W'8 @-]W :@QWPZ'W:C@ :@WC :@QWP�� 1 �� J DR UU :@'P-?-@W EPC6P�? 'CZ@W-P:@QWP W^E- 1 6-W :@QWP W^E-F:@QWPGR UU +-W-P?:@- :@QWPZ'W:C@ W^E-+�W� =C' 1 3:@+ +�W�F:@QWP* :@QWP W^E-GR UU =C'�W- +�W� F�D :3 @C@-G:3 F+�W� =C' 71 `G UU :3 +�W� =C' :Q �D* W8-P- :Q @C CE-P�@++�W� 1 ?-?CP^%+�W� =C'&R UU 3-W'8 W8- +�W�

-]-'ZW-F:@QWP W^E-* +�W�GR UU -]-'ZW- :@QWPZ'W:C@$

$

EP:[�W- QW�W:' :@W 6-W :@QWP W^E-F:@W �++PG # III $EP:[�W- QW�W:' :@W 3:@+ +�W�F:@W :@QWP* :@W W^E-G # III $EP:[�W- QW�W:' [C:+ -]-'ZW-F:@W W^E-* :@W +�W�G # III $

$

�%":1� 9$8/ �8 38M&F<F&M&F +:F � G37<6& :7<PM&F =RF3MM&8 38 �Q�>@

�8 #& 3#& R1&M1&F M1&T R�8M M: �P36# � 1�F#R�F& <F: &GG:F M: &S& PM& <F:.F�7G38 � #3F& M6T :F R1&M1&F M1&T R�8M M: RF3M& �8 38M&F<F&M&F M: 38M&F<F&M <F:.F�7G 38� 38GM&�#@ + M1&T 1::G& M: RF3M& �8 38M&F<F&M&F" M1&T 7PGM �6G: <F:Q3#& G:7&1�F#R�F& 7� 138& M: FP8 M1& 38M&F<F&M&F@ �&FM�38 1T�F3# :8GMFP M3:8G �F& �6G:<:GG3�6&" R3M1 G:7& 1�F#R�F& &S& PM3:8 �G R&66 �G G:7& G:+MR�F& 38M&F<F&M�M3:8@

�8 38M&F<F&M&F �F&�5G M1& 38GMFP M3:8G :+ 3MG M�F.&M 7� 138& 38M: G7�66 GM&<G@�G � :8G&BP&8 &" M1& 7� 138& :8 R13 1 M1& 38M&F<F&M&F FP8G �8 �& 7P 1 G37<6&F�8# 6&GG &S<&8G3Q& M1�8 � 1�F#R�F& <F: &GG:F +:F M1& M�F.&M 7� 138& R:P6# �&@�13G G�Q38. 3G &G<& 3�66T G3.83+3 �8M 3+ M1& M�F.&M 7� 138& 1�G � 6�F.& 8P7�&F :+38GMFP M3:8G �8# M1& 38GMFP M3:8G �F& +�3F6T :7<63 �M&#" R3M1 7�8T :<M3:8G@ �1&

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

7

Fetch-Phase: Read Instruction

Screen Keyboard

Memory

Program

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

7

Fetch-Phase: Read Instruction

Screen Keyboard

Memory

Program

Instruction

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

8

Fetch-phase: Increase PC

Screen Keyboard

Memory

Program

Instruction

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

8

Fetch-phase: Increase PC

Screen KeyboardPC

Memory

Program

Instruction

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

9

Decode-phase

Screen Keyboard

Memory

Program

Instruction

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

9

Decode-phase

Screen Keyboard

Memory

Program

Instruction

what is done in the decode phase?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

9

Decode-phase

Screen Keyboard

Memory

Program

Instruction

Next week: • READ: 110000

• WRITE: 111000

what is done in the decode phase?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

10

Execute-phase: Computation

Screen Keyboard

Memory

Program

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

10

Execute-phase: Computation

Screen Keyboard

Memory

Program

what is done during a computation?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

10

Execute-phase: Computation

Screen Keyboard

Memory

Program

operands

what is done during a computation?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

10

Execute-phase: Computation

Screen Keyboard

Memory

Program

flags

resultoperands

what is done during a computation?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

11

Execute-phase: Write

Screen Keyboard

WRITE

Memory

Program

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

11

Execute-phase: Write

Screen Keyboard

WRITE

Memory

Program

what is done during writing?

Tanenbaum, Structured Computer Organization, Fifth Edition, © 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

11

Execute-phase: Write

Screen Keyboard

WRITE

Memory

Program

WRITE

what is done during writing?

12

Data Path (MIPS processor)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

12

Data Path (MIPS processor)

ADD R1, R2, R2 (R2 := R1 + R2)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

13

Data Path (MIPS processor): Fetch

ADD R1, R2, R2 (R2 := R1 + R2)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

14

Data Path (MIPS processor): Decode

ADD R1, R2, R2 (R2 := R1 + R2)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

15

Data Path (MIPS processor): Execute

ADD R1, R2, R2 (R2 := R1 + R2)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

15

Data Path (MIPS processor): Execute

ADD R1, R2, R2 (R2 := R1 + R2)

Read address Instruction

Instruction Register

Readreg. 1 Read data1

Registers

Readreg. 2

Writereg.Write data Read data2

Address Read data

Data Memory

Write data

The Practicum: RUN1718 CPUNils Jansen December 5, 2017 (Based on slides by Jeroen Keiren)

17

Finite automaton Fetch-D+Execute Cycle

Decode+ ExecuteFetch

17

Finite automaton Fetch-D+Execute Cycle

Decode+ ExecuteFetch

What is a finite automaton?

18

How to construct the RUN1718 CPU

3 phases:

18

How to construct the RUN1718 CPU

3 phases:1. Fetch read instructions

18

How to construct the RUN1718 CPU

3 phases:1. Fetch read instructions2. Test preconditions satisfied?

18

How to construct the RUN1718 CPU

3 phases:1. Fetch read instructions2. Test preconditions satisfied?3. D(ecode) + Execute decoding only combinatorial

19

Decode+ ExecuteFetch

Test

Pause

CLK↘ [TEST_SUCCEEDS=1]CLK↗

CLK↘ CLK↗

Finite automaton for RUN1718 CPU

19

Decode+ ExecuteFetch

Test

Pause

CLK↘ [TEST_SUCCEEDS=1]CLK↗

CLK↘ CLK↗

CLK↘ [TEST_SUCCEEDS=0]

Finite automaton for RUN1718 CPU

20

Run of the finite automaton

clock pulse

20

Run of the finite automaton

clock pulse

20

Run of the finite automaton

Fetch

clock pulse

20

Run of the finite automaton

Fetch

Test

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test Pause

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test Pause

Fetch

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test Pause

Fetch

Test

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test Pause

FetchFetch

Test

clock pulse

20

Run of the finite automaton

Decode+ ExecuteFetch

Test Pause

FetchFetch

Test Test

clock pulse

21

Reset

Halted

Decode+ ExecuteFetch

Test

Pause

Finite automaton for RUN1718 CPU

21

Reset

Halted

Decode+ ExecuteFetch

Test

Pause

Finite automaton for RUN1718 CPU

21

Reset

Halted

Decode+ ExecuteFetch

Test

Pause

Finite automaton for RUN1718 CPU

22

Structure of the RUN1718 CPU

22

Structure of the RUN1718 CPU

• ALU

22

Structure of the RUN1718 CPU

• ALU • registerbank

22

Structure of the RUN1718 CPU

• ALU • registerbank • control unit ▪ flag register bank ▪ tester ▪ timer ▪ instruction decoder with instruction register

23

Structure of the RUN1718 CPU (Overview)

23

Structure of the RUN1718 CPU (Overview)

24

How do I start?

24

How do I start?

1. Data Path: How do the components interact?

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

3. Combined data path

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

3. Combined data path▪ necessary connections (and multiplexers)

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

3. Combined data path▪ necessary connections (and multiplexers)

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

3. Combined data path▪ necessary connections (and multiplexers)

Afterwards: design your own parts.

24

How do I start?

1. Data Path: How do the components interact?▪ during the fetch phase?▪ during the test phase?▪ during the execution phase?

2. Interfaces for each component▪ based on given information

3. Combined data path▪ necessary connections (and multiplexers)

Afterwards: design your own parts. (HADES is no design tool)

25

Summary

• Finite automatonReset ➔ Fetch ➔ Test ➔ (Decode+Execute) ➔ Pause ➔ Halted

• Data path: which data is required when for execution of instruction?

• Start working on the processor, plan carefully!