How to Create Area Constraints with PlanAhead

Xilinx Training

Objectives

After completing this module, you will be able to:

Add Pblocks to your design with the Hierarchy viewer, Schematic viewer, and the Timing Report generator

Pblocks

Pblocks are used to group logic– Assignment of a Pblock to a range of locations on the die makes it an area

constraint– When starting to floorplan, the intent is to minimize the routing between

Pblocks– A single Pblock should not occupy over 20 percent of the design resources– If so, try to make two Pblocks from logic at a lower level

UCF Syntax

Pblocks are used to group logic

Pblocks form a group– INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";

Area constraints form a range constraint– AREA_GROUP "pblock_usbEngine1“ RANGE=SLICE_X0Y60:SLICE_X43Y119;

Making a Pblock

To create a Pblock – Select a level of hierarchy or a

component from the Netlist window and use the popup menu > New Pblock

– Select a block from the Hierarchy viewer and use the popup menu > New Pblock command

– From a timing report, use the popup menu > New Pblock command

Auto-create Pblock

From the horizontal toolbar use the Tools > Auto-create Pblocks command

If more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules

Device Viewer

Create or view Pblocks easily using the Device viewer.

The vertical toolbar has the following controls

– Show/Hide I/O Nets – Show/Hide Bundle Nets– Show/Hide Loc Constraints– Show connections for selected

instances– Draw Pblock

Pblock Properties

After selecting a Pblock use the popup menu > Pblock Properties command

– Shows device utilization of Pblock• CLB• Block RAM• DSP slice• Number of clocks• Best way to determine

Analyzing Connectivity

Use the Show Connectivity popup menu command to identify

– Widely dispersed routing– Tightly clumped logic modules

Use Shift-click to select source and destination logic

– Use the popup menu > Show Connectivity command

You can use this command sequentially to expand a cone of logic

Analyzing Timing Results

Examine your timing results– Generated timing reports make it easy to display all

or some paths that are failing to meet a timing constraint

• Helps you see patterns• Simply select the paths to be displayed from the

report or use Shift + click to select a group of paths• To remove, reselect the group and click the

Hide All Timing Paths button from the vertical toolbar

– After selecting a path use the popup menu > View Path Report command to see a more detailed timing report

Analyzing Timing Results with the Schematic

View critical paths with the Schematic viewer

– Select the path(s) and use the popup menu > Schematic command

– Helps you visualize the levels of hierarchy

– Analyze logic modules for floorplanning – Create Pblocks from selected modules– Use the popup menu > Select Primitive

Parents command to select the smallest modules containing all of the selected primitives

Visualizing Hierarchy

Hierarchy view displays logic hierarchy

– Visualize relative size and location of selected logic in Hierarchy view

– Easily select parent modules of selected logic to floorplan

– Use the popup menu > Show Hierarchy command to view a selected module with this view

– Note that this only shows size; it does not show how many signals are connected between the modules

– Likewise, after selecting a component, use the popup menu > New Pblock command to assign the logic

Case Study

Design has been implemented with no area constraints

Import the design into the PlanAhead™ software and perform a timing analysis

– Display all of the paths that are

failing to meet timing to get ideas

– Note the hierarchical blocks that are

part of the failing paths

– In this example, note that there are

long routing delays between some of

the block RAMs

Case Study

Failing paths displayed with the Schematic viewer

– Confirmed from the timing reports that most of these paths can be constrained within a few area constraints

– In this case, usbEngine1 is a good candidate, but there may be others

Case Study

Placement reviewed in the Device view

– Timing critical nets and logic in green (20% of design)

– Note the use of block RAM

• Is there anything wrong?

– Note the pin layout • Is there anything

wrong?

Case Study

Top-level floorplan examined (this is just Pblocks with no area constraints)

– These will have to be made by

the user and are based on the

design hierarchy• The white box is usbEngine1

– Note the green lines• These are the connections

from logic to I/O pins• Is there anything wrong?

– Note the red lines • They represent the greatest

concentration of routes between hierarchical blocks

• Where should each Pblock go?

2

1

34

6

5

Case Study

If all the timing errors were only in usbEngine1, then an area constraint for Pblock 5 might be able to be made

– Saves some work

The block RAMs and DSP slices within usbEngine1 could also be placed in the upper left corner of the die

– This would in effect force the tools to place the logic closer to its I/O pins

2

1

34

6

5

Case Study

There were also timing errors in the usbEngine0 component

– In the end, this also required similar floorplanning

So the final solution is shown here

UCF Syntax

The following constraints are the output of this exercise– INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";– AREA_GROUP "pblock_usbEngine1" RANGE=SLICE_X0Y60:SLICE_X43Y119;– AREA_GROUP "pblock_usbEngine1" RANGE=DSP48_X0Y24:DSP48_X2Y47;– AREA_GROUP "pblock_usbEngine1" RANGE=RAMB18_X0Y24:RAMB18_X2Y47;– AREA_GROUP "pblock_usbEngine1" RANGE=RAMB36_X0Y12:RAMB36_X2Y23;

List of Questions (Revisited)

In hindsight, maybe there could have been a few more questions– Were proper pin planning decisions made?– Is there any central logic that needs to be placed in the middle of the die?– Are all my area constraints touching appropriately?– Should any of my area constraints be used to place logic near dedicated

hardware (such as GTs, the PCI core, or memory controllers, for example)?

Pblocks– Are used to group logic– Support a user-programmable utilization

• 90%+ for low speed• 70–87% for high speed

There are a number of utilities in the PlanAhead software that can help you make good area constraints

– Hierarchy viewer, Schematic viewer, and Timing Report generator– Automatic Pblock assignment and placement

Summary

More Information

To learn more, visit the PlanAhead tool web site www.xilinx.com/planahead– Articles, documentation, white papers, and training enrollment

User Guide– PlanAhead Software Tutorial, Design Analysis and Floorplanning for

Performace, UG676– Floorplanning Methodology Guide, UG633

View the PlanAhead tool video demonstrations– Quick Tour of the PlanAhead Design and Analysis Tool– I/O pin planning with PinAhead Technology– Improve Design Performance with the PlanAhead Design and Analysis tool

Where Can I Learn More?

Xilinx Education Services courses– www.xilinx.com/training

• Xilinx tools and architecture courses• Hardware description language courses• Basic FPGA architecture, Basic HDL Coding Techniques, and other free

Videos!

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