IC fabrication process trends SOI technology SiGe ... · Transistor scaling – conclusion Jiří Jakovenko – katedra mikroelektroniky ČVUT-FEL ... 3D Tri-Gate CMOS Transistors

Jiří Jakovenko – katedra mikroelektroniky ČVUT-FEL

Sub-micron technology IC fabrication process trends

SOI technology SiGe …


Goodbye Microelectronics Welcome Nanoelectronics

The thickness of gate oxide= 1.2 nm !!!

Today we move to 22 nm process - Gate oxide 0.8 nm

Virus Tranzistor in 50nm process


Development of CMOS technology

When will that ends ???


“Strained Silicon”

The thickness of gate oxide = 1.2 nm


Why do we need smaller transistors ?

Scalilng of IC technology (180, 130, 90, 65, 45, 32… nm)

Speed

Less power dissipation and consumption on the functional block

The density of transistors

Less functional block cost

Hlavní problémy

Ultra-thin gate oxide - parasitic leakage current

Very shallow S / D diffusion regions

Interconnection: the problem of shrinking - grows RC

Etc.

A potential solution is a high dielectric material for gate insulation, metal gate, a new CMOS structure, etc..


Technology problems due to scaling

Vdd decreases with the new technological generation

Maintain a dynamic power dissipation (C.Vdd2 .f)

Vt remains relatively constant

Keep low Ioff ==> keep the dynamic power dissipation at a reasonable level

MOSFET (Vdd-Vt), considerably reduced ==> hard to ensure the desired Ion


Technology problems due to scaling

Potential solution:

SOI

Increase effective (Vdd-Vt)

Multi-Vt, dynamic Vt

increase the acceptable Ioff reduce Vt

Reduce Vdd more slowly

Various power and speed for the individual blocks

Use of new materials

Long-term: new MOSFET structure


Solution: alternative technologies

SOI

Dual gate SOI

Vertical FETs

SiGe, Strained Silicon, Etc.


Scaling of transistors


Speed never sufficient …

Clock frequencies grows exponentially

Moore low

1,000,000

100,000

10,000

1,000

10

100

1

1975 1980 1985 1990 1995 2000 2005 2010

8086

80286 i386

i486 Pentium®

Pentium® Pro

K 1 Billion

Transistors

Zdroj: Intel

Year

Pentium® II Pentium® III

Pentium® IV

Nahalem


Scaling of transistors

Transistor dimensions are reduced by 30% each 2-3 years

Transistors are cheaper

They are also faster

Metallic connection speed, however, does not improve

Scale factor S

Typical steps:

Year

0.1

1

10

1965 1970 1975 1980 1985 1990 1995 2000 2005

Fe

atu

re S

ize

(

m)

10

6

3

1.51

0.80.6

0.350.25

0.180.13

0.09

2S


Scaling preconditions

What changes moving to the new technology node?

starting point: Preserving a constant electric field

We customize all dimensions (x, y, z => W, L tox)

Supply voltage (VDD)

The values of diffusion fields of subsidies

Metallization must be adapt

Some materials do not comply with their properties


Transistor scaling with S factor

Parameter Reduction

Channel length L 1/S

Channel width W 1/S

Thickness of gate oxide tox 1/S

Supply voltage VDD 1/S

Threshold voltage Vt 1/S

Wafer doping NA S

Downsize

1/5


Transistor scaling with S factor

Parameter Reduction factor Note

Current factor b S

Current IDS 1/S b(VDD-Vt)2

Resistance 1 VDD/IDS

Gate capacitance 1/S W.L/Cox

Delay 1/S RC

Clocking frequency S 1/t

dynamic losses 1/S2 C .V2 / f

Chip area 1/S2

Transistor properties


Transistors are faster (+)

Dynamic consumption decreases (+)

Current density is growing (-)

Growing resistance of contacts (-)

Transistor scaling – conclusion


Metallization scaling

Thickness of copper jumpers

It remains constant

distance connections

Local / reduced by a factor of S

Global - unchanged


Sub-micron IC structure in real scale :

TRANZISTORS

Copper

Conductors

(8 Levels)

Low-k

Dielectric

Copper

Plugs


Sub-micron IC structure in real scale :

Metal #6

Metal #5

Metal #4

Metal #3

Metal #2

Metal #1

Trench izolation PolySi Gate

Passivation

SiO2 (500nm) + Si3N4 (200 nm)


Interconnection resistivity

Ro = square

resistance

Reliability Decreasing

Have an impact on performance

Classification of parasitic effects

Capacity

Resistivity

Inductance


Reciprocal capacity

creates crosstalk


Metallization scaling with S factor

Parametr Reduction

factor

Metallization width W 1/S

The distance 1/S

Metallization thickness t 1/S

Insulator thickness 1/S

Redukce 1/5 Parametr Reduction

factor

Note

The resistance per unit length S2 1/W.t

Capacity in the same layer 1 t/s

Capacity between the layers 1 W/h

The total capacity 1 W.L/Cox

RC constant per unit length S2


Metallization scaling

Consequence of downsizing

Delays reached a minimum at 180 to 90 nm, further the delay will only worsen

But ...

[SIA97]


ITRS – Future ?

Intl. Technology Roadmap for Semiconductors


Development of MOSFET structures below 70 nm

Bulk MOSFET SOI/ MOSFET Dual-Gate MOSFET

Vertical MOSFET

SOI Technology Silicon On Insulator

Jiří Jakovenko – Struktury integrovaných systémů - Katedra mikroelektroniky – ČVUT FEL Jiří Jakovenko – katedra mikroelektroniky ČVUT-FEL

SOI Technology

SOI - Silicon On Insulator


SOI Benefits

Improved performance through elimination of parasitic capacities PN junctions and "Body Effect" - 25-35% higher performance than Si CMOS

SOI can operate at lower voltages with the same performance as Si CMOS - 40-50%

Better use of chip area - smaller surface insulation Reduced Body Effect Prevention of leakage currents into the substrate Increased integration density Preventing of latch-up effect Increased operating temperature (250 ° C) Resistance to radiation


Latch-up effect


SOI disdadvantages

Very few disadvantages:

Thermal properties

More expensive substrates of 3 to 10% over CMOS

Hysteresis of threshold voltage


SOI Types

– Partially-Depleted

- Fully-Depleted


Floating - body effect

Parasitic bipolar transistor

Change of threshold voltage


Application of SOI

Suitable for circuits with low and very low power consumption

Microprocessors with higher clock speeds

Graphics processors

Circuits for high-speed serial communication: 100 Gbps

Ultra-low power systems on a chip: watch for solar energy

RFID

All technologies below 90 nm on SOI


SOI wafer production technology

SOS - silicon on sapphire (1978)

SIMOX - separation by implantation of oxygen (1983)

ZMR - zone melting and recrystallisation (1983)

BESOI - bond and etch back SOI (1989)

Smart-Cut SOI (1996)


SIMOX wafer technology

1. implantation of oxygen ions

● implantation energy determines the depth and thickness

of the burried oxide layer and the thickness of top Si layer

2. annealing - a gradual increase in temperature from

1050 to 1350 ° C

● formation of the oxide layer

● avoidance of dislocations in the top layer of silicon


Smart Cut Technology


SOI vs conventional CMOS comparison

30% faster

30% greater integration density

20% fewer manufacturing steps

50% power consumption

Strained Silicon Technology


Strained silicon technology

Strain

It uses a different lattice constant of Si and Ge


Implementing to CMOS structure


Tranzistor photo


Advantages of strained silicon

Only about 2% higher costs Higher speed - up to 35%

Increase of the mobility of carriers by 50%

Simplicity

No need to shrink the thickness of oxide

Possible combination with other technologies for the future

SSOI – Strained SOI

Combination of SOI and strained silicon technology

Jiří Jakovenko – Mikrovlnný seminář 2011 - Katedra mikroelektroniky – ČVUT FEL

mpi-halle.de 25 nm FDSOI tranzistor , CEA-Léti,

Technology of High-k dielectrics, in combination with metal gates

Development of HKMG took more than ten years

Today it is used in 45 nm and 32 nm technologies node

Transistors performance is up to 22% higher

The leakage currents of 5 - 10 times lower


45 nm tranzistor HKMG, : Intel

SiGe HBT Technology

SiGe Technology has been known for a long time, but no one could combine SiGe layer with a layer of Si without defects in the crystalline structure

In the 90 years the development occurs in bipolar transistors caused by SiGe HBT technology


Intel

The pros and cons of SiGe HBT

+ Higher fT~ 550GHz

+ Higher performance (efficiency)

+ Lower power consumption

- Higher production costs

- More challenging manufacturing

Better performance than Si BiCMOS Lower price than the III-V Semiconductors (GaAs) Use for RF circuits Speed 300 – 550 GHz


3D Tri-Gate CMOS Transistors - MuGFET


Planar tranzistor 22 nm tri-gate transistor

Full depletion region Costs only about 2-3% higher

Increased speed by 18 - 37%

Year of Implementation:2012

Intel

3D chip Technology


3D Ics – Full SOC

SOC – System On Chip


3-D ICs : Several active Si layers

Advantages:

Reducing the length of interconnection

Better chip performance

Smaller chip area

Heterogeneous integration: digital, analog, optical…


New design architecture necessary

Replacement of horizontal connections in the vertical


The problem with cooling


3-D Technology


Today surface SOC


GaAs Technology

Increased electron mobility


carriers mobility for common semiconductors


Material properties of GaAs

Max. electron velocity = 2 x Silicon = 2 x 107 cm/sec Hole mobility of GaAs (= 400) < Si (489 cm2V/sec) No complementary logic possible !!! Electron mobility of GaAs (4000-9000) >> Si (500-1200) Max. El. field (max. speed) GaAs (0.3 V/m) < Si (1 V/m) Low voltage supply

Fragile Materials 3 to 4 inch wafers

The high density of defects

High QSS and Qox

No MOS structure possible!


The best component: MESFET

Large changes in threshold voltage on one wafer (100 – 200 mV)


I-V Characteristic


High Electron Mobility Transistor (HEMT)

Pohyblivost v nedopovaném GaAs > 8500 cm2/Vsec (4500 cm2Vsec v dopov. GaAs)

Až do 50,000 cm2/Vsec v kapalném dusíku


MEMS technologies


Electrostatic micromirrors

Radiofrequency electronics


Semiconductor materials

• III-V's (GaAs, InP

AlGaAs, InGaAs, InAlAs, …)

• Si

• SiGe

• Wideband semiconductors

(SiC, GaN, AlGaN)

Commercial electronics Mikroprocesor, memory, sensors systems…

Semiconductor materials

• Si

Transistors types

• MOSFET (98 % of applications) • Bipolar: BJT

RF electronics

Transistors types

•Bipolar:

- BJT

- HBT (Heterojunction Bipolar Transistor)

•FET

- MESFET (Metal Semiconductor FET)

- HEMT (High Electron Mobility Transistor)

- MOSFET (Metal Oxide Semiconductor FET)

Evolution of microwave technologies


Trends in RF technology:

•Transistor Cutoff frequency Increasing fT a fmax (III-V)

• Growth of output power (semiconductors with wide band gap)

• Low cost silicon technology (CMOS and SiGe technology)

1960 1970 1980 1990 20001

10

100

1000

InP HBT

*

*

Transferred substrate

fT

fmax

AlGaAs/GaAs HEMT

InP HEMT

Si BJT

AlGaAs/GaAs HEMT

GaAs pHEMTInP HEMT

InP HBT

GaAs MESFET

Ge BJT

f max , f T

, G

Hz

YearRok

0 50 100 150 2000

1

2

3

GaAs

In0.53

Ga0.47

As

InP

Si

Ve

locity,

10

7 c

m/s

Electric field, kV/cm

Pohybliv

ost

Elektrické pole

Growth of frequency limit of MOS transistors


0.1 110

100

500

0.05

Upper limit nMOSFET

Exp. data nMOSFET

Exp. data pMOSFET

Cu

toff

fre

qu

ency,

GH

z

Gate length, µm

Rapid increase of CMOS technologies for applications of microwave circuits

Thanks to new CMOS technology, transistors reached almost the same speed as a special RF technology

CMOS 32 nm fT / fMAx - 380 GHz/440 GHz

Documents

IC fabrication process trends SOI technology SiGe ... · Transistor scaling – conclusion Jiří Jakovenko – katedra mikroelektroniky ČVUT-FEL ... 3D Tri-Gate CMOS Transistors