Engaging Undergraduate Students in Nano-Scale Circuit Research using Summer Internship

Hamid Mahmoodi1, Jesus Garcia2, Joshua Lohse2, John Paulino2, Hector Prado2, Atul Balani1, Sridevi Lakshmipuram1, Cheng Chen1, Amelito G. Enriquez2, Hao Jiang1, Wenshen Pong1, Hamid Shanasser1

1School of Engineering, San Francisco State University, San Francisco, CA 2Cañada College, Redwood City, CA

1E-mail: mahmoodi@sfsu.edu Abstract

Semiconductor technology has been scaling at a steady pace following Moore’s law. The current generations of the technology have reached dimensions well below 100nm where nano-scale phenomena are prominent. Transistors in such a small scale behave very differently than the classic long channel devices taught in most undergraduate level textbooks. Moreover, there are new challenges in nano-scale circuit design, such as process variations and reliability issues that are not taught in undergraduate level courses. Working on latest technology issues is typically an opportunity available only to graduate level students working on related research projects. To address this gap, using a NASA Curriculum Improvements Partnership Award for the Integration of Research (CIPAIR) grant, we have created a summer internship program that engages community college students in research projects on the latest challenges of circuit design in nano-scale semiconductor technology. Through this program, four community college students were mentored by two graduate students in a research project to analyze performance degradation of integrated circuits due to transistor aging effects in nano-scale. In this research, analysis of transistor breakdown was performed through computer simulations to understand effects on circuit power and performance. A ring oscillator circuit was utilized as a generic logic circuit for this research. The breakdown was modeled by resistors placed between the transistor terminals. The value of the resistor represents the severity of the breakdown; large resistors represent fresh transistors, whereas low resistors represent a fully broken transistor. In addition to computer simulations, real ICs were studied by taking power measurements experimentally. This research aims to offer better insight into the impact of transistor breakdown and to improve IC design in nano-scale. Through this internship program, the undergraduate students not only contributed to research and discovery, but also gained valuable experience and knowledge of nano-scale circuits that could have not been achieved in traditional educational methods.

Keywords: Internship, Nano-scale, Reliability, Undergraduate Research. 1. Introduction

Since the invention of integrated circuit in 1961, the

semiconductor technology has evolved following Moore’s law [1] to offer ever more high performance and complex computing systems. This evolution has been realized

primarily by technology scaling which is about scaling the transistor dimensions. Modern CMOS technologies offer transistors with feature sizes well below 100nm, a regime commonly referred to as nano-scale CMOS. Scaling of transistors to such nano-scale poses new challenges to the design. These design challenges include high power consumption, increased leakage and process variations, non-classical device structure and behavior, degraded device reliability, and emergence of non-silicon type nano-scale devices. Due to the fast pace of technology scaling and emergence of new design methods to cope with technology scaling challenges, designing reliable and energy efficient high-performance computing circuits in nano-scale remains to be an issue that is not covered in traditional undergraduate engineering programs. To address this gap, we have implemented a summer undergraduate research program funded by a CIPAIR grant from NASA. This summer internship is aimed to involve undergraduate students in cutting-edge research and give them experience and knowledge of nano-scale circuits that they could not traditionally gain in a typical undergraduate program.

The planned research project focuses on the issue of transistor reliability challenges in nano-scale. More specifically, it deals with the analysis of transistor aging effects and more specifically Time Dependent Dielectric Breakdown (TDDB) [2] on circuit performance in nano-scale. The research involves both simulationbased analysis and experimental data collection.

2. Research Project Description With the scaling of technology and shrinking of gate

oxide, the oxide reliability is degrading. Time Dependent Dielectric Breakdown (TDDB) is becoming a major oxide reliability concern in nano-scale [2]. Soft Oxide Breakdown (SBD) (the early stage of TDDB) is a type of degradation that involves the formation of traps in the gate oxide layer of the transistor. These traps, which are defects in the SiO2 gate oxide, form conduction paths and develop leakage current from the polysilicon gate to the silicon substrate, as shown in Fig. 1. TDDB results in increase of device gate current mostly in the form of gate-to-source and gate-to-drain current [3]. This will result in an increase in the power consumption of the circuit. Although the physical reason for TDDB is an active topic of research, TDDB is a progressive breakdown that results from gradual accumulation of defects through a stressed transistor [4].

978-1-4673-5112-6/13/$31.00 ©2013 IEEE 139 Interdisciplinary Engineering Design Education Conference

The aim of this research project is to analyze the impact of TDDB on performance and power consumption of digital circuits. A ring oscillator circuit (Fig. 2) is used as a circuit under test. The TDDB is modeled as a resistor placed between the grate and source or the gate and drain terminals of a transistor (Fig. 3) [4]. Since occurrence of TDDB is not deterministic and therefore chance of multiple TDDB events is rare, we consider only one TTDB event for the circuit under test (i.e. only one transistor in the ring oscillator circuit experiences TDDB). The value of the resistor modeling TDDB is time dependent with infinitely large value for an ideal transistor and decaying values for a defective transistor, as describe by the model presented in [5]. Circuit simulations are performed using Synopsys Custom Designer tool [6] and the 32nm Predictive Technology Models [7]. The aim of the simulations is to measure the impact of TDDB on the ring oscillator frequency and power consumption. Fig. 4 shows typical simulation waveforms of two successive nodes of the ring oscillator circuit with measurements of oscillation period and the inverter delay.

Fig. 1. Cross section of NMOS transistor showing formation

of traps and conduction path in the gate oxide region

Fig. 2. Schematic of a 5-stage ring oscillator

Fig. 3. Locations for adding resistors modeling TDDB

Fig. 4. Inverter delay and oscillation period measurements

In addition to simulations, the project aims to allow

students to experimentally measure the impact of TDDB on a real integrated circuit. This is facilitated by a sample test chip and a probe station and device parameter analyzer.

3. TDDB Modeling The value of the resistance (Fig. 3) added to model TDDB (also called SBD) indicates the severity of the breakdown. Hence, the value of this resistance should decrease over the life time of the circuit, starting with infinitely large value at the beginning. According to Afzal et al. [8], the relationship between Soft Breakdown Resistance RSBD and time can be modeled by

)exp(0

tGRI

VR dd

SBD −=

(1)

where Vdd is the supply voltage, I0 is the Initial leakage or defect current, and GR is the defect current growth rate. GR can be computed using the equation

GR = K1exp(θ1Vg – θ2Tox), (2)

where Vg is gate stress voltage, Tox is gate oxide thickness, and θ1, θ2, and K1 are constants from experimental data. There are no industrial data available for GR; however from [8], three different values for GR are used: 1.6, 3.2, and 6.4×10-8s-1. There are many proposed methods to calculate the initial defect current, I0. We biased the gate of an NMOS transistor at VDD and the source and drain at ground as shown in Fig. 5 and measured the current of the gate voltage source as a measure of I0.

Fig. 5. Measurement setup used to determine I0

Using Eq. 1, plots of resistance vs. time are obtained as shown in Fig. 6. The value GR is an inherent characteristic of the technology; hence, the lowest GR value represents a circuit with a very short life span, and the highest GR value represents a very durable circuit. It is also observed that the leakage resistance does not decrease linearly over time. Rather, it experiences exponential decay.

Fig. 6: Leakage resistance vs. time for various GR values

4. Research Results and Discussion The results shown in Fig. 7, from the three stage ring oscillator circuits with NMOS Gate to Source breakdown, shows no perceptible difference in delay up to the 10 kΩ average life limit. The measurements show an average change of 1-2 ps in period which is an insignificant change in performance.

(a)

(b)

Fig. 7: NMOS Gate-to-Source breakdown effect on ring oscillator performance: (a) Period vs. Time and (b) inverter delay vs. breakdown resistance

Significant differences occur when the inverter is close to Hard Breakdown (HBD) at about 3-4 kΩ, which causes the circuit to fail completely. These failures correspond to about 11-12 years of use, which is more than double the time a typical consumer will use a device. Delay of a single affected inverter vs. the gate-to-drain breakdown resistance is shown in Fig. 8. It does show an initial increase in performance because of the decrease in delay which is caused by the feedback effect. Fig. 9 shows the power of a ring oscillator as the gate-to-source TDDB progresses. In the soft breakdown phase, the power increase; however as the circuit experiences hard breakdown, the power drops due to the sudden decline in frequency.

Fig. 8: Inverter delay vs. NMOS/PMOS Gate-to-Drain

breakdown resistance

Fig. 9: Impact of gate-to-source TDDB on power of a ring oscillator

5. Experimental Results This section investigates the experimental validation of the simulations conducted on a ring oscillator circuit. Using the Cascade B11000 Probe Station and Agilent B1500A Device Parameter Analyzer, a test chip was probed (Fig. 17). This test is a digital signal processing chip manufactured in a 0.18um CMOS process and does not contain any ring oscillator circuits. Hence, we can only test for impact of break down on standby power. First, a fresh chip is powered at its nominal supply if 1.8V at 20°C, its I-V graph is measured by sweeping its supply voltage from 0 to 1.8V and measuring its standby current. In order to induce breakdown in a reasonable time span, the chip is then voltage stressed with a Semi-Conducting Pulse Generator (SPGU) at 3.5 V at 140°C for approximately one hour at 90% duty cycle with 1ms period to accelerate the process of SBD. After stress, the chip was probed to original biasing and its I-V graph was re-measured. The same process was performed except at 100°C and a I-V graphs were created (Fig. 11). Fig. 11 clearly shows the defect current of the chip due to the breakdown.

Fig. 10: Probing power supply pads of a chip under test

Fig. 11: I-V characteristic of fresh IC and IC after stress

6. Student Surveys Table 1 summarizes the results of post-program student survey designed to measure perception of over-all usefulness of the research internship program. Results show that the research internship program was successful in its achieving its goals of helping students prepare for transfer, solidify their choice of major, increase their confidence in applying for other internships, and enhance their interest in pursuing graduate degrees. Overall, students were satisfied with the program, and would recommend it to a friend. The internship program was successful in achieving its goals of developing students’ skills needed for academic success. Table 2 shows a summary of student perception of how much they have learned from participating in the internship program, as determined from a post-program survey. Note that for each of the categories, the average response is between “Quite a bit” and “A lot.”

7. Conclusions A successful engagement of undergraduate students in nano-scale circuit research is presented that has not only impacted the students but also produced valuable knowledge that advances the understanding of nano-scale issues.

Table 1. Summary of student responses to the post-program survey measuring the perceived benefit of participating in the research internship program.

Question: Tell us how much you agree with each of the following statements.

Response Scale: 1 – Strongly Disagree; 2 – Disagree; 3 – Neutral; 4 – Agree; 5 – Strongly Agree.

Average Rating

The internship program was useful. 4.9

I believe that I have the academic background and skills needed for the project. 4.1

The program has helped me prepare for transfer. 4.5

The program has helped me solidify my choice of major. 4.3

As a result of the program, I am more likely to consider graduate school. 4.6

As a result of the program, I am more likely to apply for other internships. 4.8

I am satisfied with the NASA CIPAIR Internship Program. 4.8

I would recommend this internship program to a friend. 4.8

Table 2. Summary of student satisfaction with the summer research internship program.

Question: How much did you learn about each of the following?

Response Scale: 1 – Nothing; 2 – A little; 3 – Some; 4 – Quite a bit; 5 – A lot.

Average Rating

Performing research 4.8

Designing/performing an experiment 4.9

Creating a work plan 4.8

Working as a part of a team 4.8

Writing a technical report 4.8

Creating a poster presentation 4.7

Making an oral presentation 4.6

Performing research 4.8

8. Acknowledgment The authors would like to acknowledge Synopsys for

electronic design automation tools and technical support. The summer internship was funded by a NASA CIPAIR grant.

References [1] P.K. Bondyopadhyay, “Moore’s law governs the silicon

revolution,” Proceedings of the IEEE, vol. 86, no. 1, pp. 78-81, 1998

[2] I.S. Han, et. al, “Time-dependent dielectric breakdown of La2O3 doped high-k/metal gate stacked NMOSFETs,” IEEE Electron Device Letters, vo. 30, no. 3, pp. 298-301, 2009

[3] R. O’Connor, et. al, “Time dependent dielectric breakdown and stress induced leakage current characteristics of 8A° EOT HfO2 N-MOSFETs,” IEEE Reliability Physics Symposium, pp. 799-803, 2010

[4] M. Renovell, et. al, “modeling the random parameters effects in non-split model of gate oxide short,” Electronic testing, 2003

[5] J. Qin, X. J. Li, and J. B. Bernstein, “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI,” in Proc. IEEE IIRW, Oct. 2007, pp. 33-37.

[6] Synopsys Inc: www.synopsy.com [7] Predictive technology Models: Available online:

http://ptm.asu.edu/ [8] B. Afzal, B. Ebrahimi, A. Afzali-Husha, H. Mahmoodi.

“Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability,” Elsevier Microelectronics Reliability Journal