IEEE P1149.8.1™/D0.7 Draft Standard for Boundary-Scan ...btw.tttc-events.org/material/BTW09/Presentations/Session 3.2.pdf2 Draft Standard for Boundary-Scan-3 Based Stimulus of Interconnections

IEEE P1149.8.1/D0.7, August 2009

Copyright © <year> IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change.

IEEE P1149.8.1™/D0.7 1

Draft Standard for Boundary-Scan-2

Based Stimulus of Interconnections to 3

Passive and/or Active Components 4

Prepared by the Boundary-Scan Selective Toggle Working Group of the 5

IEEE Computer Society Test Technology Standards Committee 6

Copyright © <year> by the Institute of Electrical and Electronics Engineers, Inc. 7 Three Park Avenue 8 New York, New York 10016-5997, USA 9 All rights reserved. 10

This document is an unapproved draft of a proposed IEEE Standard. As such, this document is subject to 11 change. USE AT YOUR OWN RISK! Because this is an unapproved draft, this document must not be 12 utilized for any conformance/compliance purposes. Permission is hereby granted for IEEE Standards 13 Committee participants to reproduce this document for purposes of international standardization 14 consideration. Prior to adoption of this document, in whole or in part, by another standards development 15 organization, permission must first be obtained from the IEEE Standards Activities Department 16 ([email protected]). Other entities seeking permission to reproduce this document, in whole or in part, must 17 also obtain permission from the IEEE Standards Activities Department. 18 IEEE Standards Activities Department 19 445 Hoes Lane 20 Piscataway, NJ 08854, USA 21

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Abstract: <Select this text and type or paste Abstract—contents of the Scope may be used> 1 Keywords: <Select this text and type or paste keywords> 2 3

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This is an unapproved IEEE Standards Draft, subject to change.

Introduction 1

This introduction is not part of IEEE P1149.8.1/D0.7, Draft Standard for Boundary-Scan-Based Stimulus of 2 Interconnections to Passive and/or Active Components. 3

<Select this text and type or paste introduction text> 4

Notice to users 5

Laws and regulations 6

Users of these documents should consult all applicable laws and regulations. Compliance with the 7 provisions of this standard does not imply compliance to any applicable regulatory requirements. 8 Implementers of the standard are responsible for observing or referring to the applicable regulatory 9 requirements. IEEE does not, by the publication of its standards, intend to urge action that is not in 10 compliance with applicable laws, and these documents may not be construed as doing so. 11

Copyrights 12

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Updating of IEEE documents 18

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Errata 28

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Interpretations 1

Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee/interp/ 2 index.html. 3

Patents 4

Attention is called to the possibility that implementation of this standard may require use of subject matter 5 covered by patent rights. By publication of this standard, no position is taken with respect to the existence 6 or validity of any patent rights in connection therewith. The IEEE is not responsible for identifying 7 Essential Patent Claims for which a license may be required, for conducting inquiries into the legal validity 8 or scope of Patents Claims or determining whether any licensing terms or conditions provided in 9 connection with submission of a Letter of Assurance, if any, or in any licensing agreements are reasonable 10 or non-discriminatory. Users of this standard are expressly advised that determination of the validity of any 11 patent rights, and the risk of infringement of such rights, is entirely their own responsibility. Further 12 information may be obtained from the IEEE Standards Association. 13

Participants 14

At the time this draft standard was completed, the Boundary-Scan Selective Toggle Working Group had the 15 following membership: 16

Jeffrey Burgess, Chair 17

Stephen Sunter, Vice Chair 18

Kenneth P. Parker, Editor 19

20 Scott Bowden 21 Steve Butkovich 22 Floyd Conner 23 Adam Cron 24 Dave Dubberke 25 Ted Eaton 26

Heiko Ehrenberg 27 James J. Grealish 28 Robert Kelly 29 Tom Langford 30 Adam W. Ley 31 Sophocles Metsis 32

Thai-Minh Nguyen 33 David Paul 34 Dirk Reese 35 Anthony Suto 36

37

The following members of the individual balloting committee voted on this standard. Balloters may have 38 voted for approval, disapproval, or abstention. 39

40 (to be supplied by IEEE) 41

IEEE P1149.8.1/D0.7, August 2009

vi Copyright © <year> IEEE. All rights reserved.


CONTENTS 1

1. Overview .................................................................................................................................................... 1 2 1.1 Scope ................................................................................................................................................... 1 3 1.2 Purpose ................................................................................................................................................ 1 4 1.3 Context ................................................................................................................................................ 1 5 1.4 Organization of the standard................................................................................................................ 2 6 1.5 Background reading............................................................................................................................. 3 7

2. Normative references.................................................................................................................................. 4 8

3. Definitions .................................................................................................................................................. 4 9

4. Technology................................................................................................................................................. 5 10 4.1 Evolution of printed circuit assembly technology ............................................................................... 5 11 4.2 Shifts in board testing challenges ........................................................................................................ 6 12 4.3 Signal pin types ................................................................................................................................... 7 13

4.3.1 Classification of pins.................................................................................................................... 7 14 4.3.2 Differential pins ........................................................................................................................... 8 15

4.4 Defects targeted by the standard........................................................................................................ 11 16 4.5 Selective Toggle Theory of Operation............................................................................................... 13 17

5. Instructions ............................................................................................................................................... 14 18 5.1 IEEE Std 1149.1 instructions............................................................................................................. 14 19

5.1.1 Rules .......................................................................................................................................... 14 20 5.1.2 Description................................................................................................................................. 14 21

5.2 Instructions for selective toggling and guarding................................................................................ 14 22 5.3 The TOGGLE_SETUP instruction.................................................................................................... 14 23

5.3.1 Rules .......................................................................................................................................... 15 24 5.3.2 Permissions ................................................................................................................................ 15 25 5.3.3 Description................................................................................................................................. 15 26

5.4 The SELECTIVE_TOGGLE instruction........................................................................................... 15 27 5.4.1 Rules .......................................................................................................................................... 15 28 5.4.2 Permissions ................................................................................................................................ 17 29 5.4.3 Description................................................................................................................................. 17 30

6. Pin implementation specifications............................................................................................................ 20 31 6.1 Pin classification................................................................................................................................ 20 32

6.1.1 Rules .......................................................................................................................................... 20 33 6.1.2 Recommendations...................................................................................................................... 20 34 6.1.3 Description................................................................................................................................. 20 35

6.2 Implementation of normal pins.......................................................................................................... 21 36 6.2.1 Rules .......................................................................................................................................... 21 37 6.2.2 Description................................................................................................................................. 21 38

6.3 Implementation of ST-pins ................................................................................................................ 22 39 6.3.1 Single-ended output pins............................................................................................................ 23 40

6.3.1.1 Rules................................................................................................................................... 23 41 6.3.1.2 Recommendations .............................................................................................................. 23 42 6.3.1.3 Description ......................................................................................................................... 23 43

6.3.2 Single-ended input pins.............................................................................................................. 26 44 6.3.2.1 Rules................................................................................................................................... 26 45 6.3.2.2 Recommendations .............................................................................................................. 26 46 6.3.2.3 Permissions ........................................................................................................................ 26 47 6.3.2.4 Description ......................................................................................................................... 27 48

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vii Copyright © <year> IEEE. All rights reserved.


6.3.3 Single-ended bidirectional pins.................................................................................................. 28 1 6.3.3.1 Rules................................................................................................................................... 28 2 6.3.3.2 Description ......................................................................................................................... 28 3

6.3.4 Differential output pins .............................................................................................................. 28 4 6.3.4.1 Rules................................................................................................................................... 29 5 6.3.4.2 Permissions ........................................................................................................................ 29 6 6.3.4.3 Description ......................................................................................................................... 29 7

6.3.5 Differential input pins ................................................................................................................ 30 8 6.3.5.1 Rules................................................................................................................................... 30 9 6.3.5.2 Description ......................................................................................................................... 30 10

6.4 Toggle Behavior for ST-pins ............................................................................................................. 30 11 6.4.1 Rules .......................................................................................................................................... 31 12 6.4.2 Description................................................................................................................................. 31 13

7. The Toggle Control register ..................................................................................................................... 32 14 7.1 Rules .................................................................................................................................................. 33 15 7.2 Permissions........................................................................................................................................ 33 16 7.3 Recommendations ............................................................................................................................. 33 17 7.4 Description ........................................................................................................................................ 33 18

8. Conformance and documentation requirements ....................................................................................... 34 19 8.1 Conformance ..................................................................................................................................... 34 20

8.1.1 Rules .......................................................................................................................................... 34 21 8.1.2 Description................................................................................................................................. 34 22

8.2 Documentation................................................................................................................................... 35 23 8.2.1 Rules .......................................................................................................................................... 35 24 8.2.2 Description................................................................................................................................. 35 25

8.3 BSDL package for Selective Toggle description (STD_1149_8_1_2009) ........................................ 35 26 8.4 BSDL extension structure.................................................................................................................. 35 27 8.5 BSDL attribute definitions................................................................................................................. 36 28 8.6 Example BSDL.................................................................................................................................. 36 29

Annex A (informative) Unpowered Testing for Open Connections on Printed Circuit Assemblies ............ 37 30 A.1 Problem Description ......................................................................................................................... 37 31 A.2 Unpowered Capacitive Opens Detection .......................................................................................... 37 32 A.3 Replacing Tester AC Stimulus with Boundary-Scan Stimulus......................................................... 41 33 A.4 Coverage Deficiencies ...................................................................................................................... 42 34

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IEEE P1149.8.1/D0.7, August 2009

1 Copyright © <year> IEEE. All rights reserved.


Draft Standard for Boundary-Scan-1

Based Stimulus of Interconnections to 2

Passive and/or Active Components 3

1. Overview 4

1.1 Scope 5

This standard specifies extensions to IEEE Std 1149.1 that define the boundary-scan structures and 6 methods required to facilitate boundary-scan-based stimulus of interconnections to passive and/or active 7 components. Such networks are not adequately addressed by existing standards, including those networks 8 that are AC-coupled or differential. The selective AC stimulus generation enabled by this standard, when 9 combined with non-contact signal sensing, will allow testing of the connections between devices adhering 10 to this standard and circuit elements such as series components, sockets, connectors, and integrated circuits 11 that do not implement IEEE Std 1149.1. This standard also specifies Boundary-Scan Description Language 12 (BSDL) extensions to IEEE Std 1149.1 required to describe and support the new structures and methods. 13

1.2 Purpose 14

The purpose of this standard is to codify testability circuitry added to an integrated circuit incremental to 15 the testability provisions specified by IEEE Std 1149.1. This will enable selective AC stimulus generation 16 that, when combined with non-contact signal sensing, allows testing signal paths between devices adhering 17 to this standard and passive and/or active components. 18

[Editor’s note: We may elect to re-word the purpose (extracted from the PAR) to also include 19 facilities to test for shorted nodes we once had direct access to. This will follow from amending the 20 PAR.] 21

1.3 Context 22

Figure 1 shows a printed circuit assembly containing many types of devices. Of these, some could be 23 compliant with IEEE Std 1149.1 for the support of testing activities. These devices contain Boundary-Scan 24 testability circuitry which allows them to participate in manufacturing tests that detect and diagnose faults 25 such as open solder joints, shorts and missing devices. 26

IEEE P1149.8.1/D0.7, August 2009



The additional testability elements added by this standard to these same integrated circuits (ICs) allow this 1 interconnect testing, to be conducted between these ICs and passive or active components that do not 2 support IEEE Std 1149.1, when these testability elements are operated in conjunction with alternative 3 sensing technologies. 4

Figure 1 —A printed circuit assembly containing a variety of components interconnected by 5 printed wiring. Some ICs contain IEEE Std 1149.1 features that support Boundary-Scan 6

interconnect testing. 7 This standard is built on top of IEEE Std 1149.1 using the same Test Access Port and Boundary-Scan 8 architecture. It adds new instructions that cause drivers to emit AC waveforms that are compatible with 9 alternative sensing technologies. 10

[Editor’s note: We may elect to re-word the context to also mention facilities to test for shorted nodes 11 we once had direct access to. This will follow from amending the purpose above.] 12

There are two audiences addressed by this document. The first is made up of integrated circuit device 13 designers (device designers) and the second is a more general class of integrated circuit device users 14 (device users). Device designers will use this standard while creating new devices that adhere to the rules 15 of this standard. Device users will make use of those features. Device users include board and system 16 designers, design-for-test consultants and test engineers. In many cases, it is expected that there will be 17 communication and negotiation between the two groups, as the device users will lobby for investments in 18 the silicon made by device designers who will balance these requests against various factors (schedule, 19 cost) and trade those off for enhanced testability and defect coverage. 20

1.4 Organization of the standard 21

Clause 1, Overview, provides an overview and context for this standard. 22

Clause 2, Normative references, provides references necessary to understand this standard. 23

Clause 3, Definitions, defines terminology and acronyms used in this standard. 24

IEEE P1149.8.1/D0.7, August 2009



Clause 4, Technology, is a tutorial that outlines the technologies addressed and utilized by this standard. 1 This clause does not contain rules. 2

Clause 5, Instructions, provides rules for instructions used for testing. 3

Clause 6, Pin implementation specifications, provides rules for I/O pin implementation. 4

Clause 7, The Toggle Control register, provides rules for the design and behavior of a toggle control 5 register used to control the operation of the SELECTIVE_TOGGLE instruction. 6

Clause 8, Conformance and documentation requirements, provides rules for conformance and documen-7 tation of devices designed to this standard. 8

Annex A, (informative) Unpowered Testing for Open Connections on Printed Circuit Assemblies, 9 describes a capacitively sensed test technology for testing for open connections between printed circuit 10 assemblies and device pins. 11

1.5 Background reading 12

Readers unfamiliar with IEEE Std 1149.1 might find it helpful to study some of the following books and 13 papers, some of which also discuss unpowered capacitive testing: 14

Parker, K. P., The Boundary-Scan Handbook, 3rd Edition, Analog and Digital, Kluwer Academic 15 Publishers, 2003. 16

A description of the design and use of IEEE Std 1149.1, 1149.4, 1149.6 and 1532, written from the point of 17 view of practicing test engineers. 18

Turner, T., Capacitive Leadframe Testing, Proceedings, International Test Conference, pg 925, Washington 19 DC, October 1996. 20

Part of a lecture series (ITC 1996 Lecture Series on Unpowered Opens Testing) that described a taxonomy 21 of unpowered techniques for detecting open joints between devices and boards. 22

Dubberke, D., Grealish, J. J. and Van Dick, B. I., Solving In-Circuit Defect Coverage Holes with a Novel 23 Boundary Scan Application, Proceedings, International Test Conference, paper 11.2, Santa Clara CA, 24 October 2008. 25

This paper describes the types of board designs that benefit from a marriage of capacitive sensing 26 technology with Boundary-Scan stimulus and postulates some precursor technology to features 27 incorporated by this standard. 28

Norrgard, D. and Parker, K. P., Augmenting Boundary-Scan Tests for Enhanced Defect Coverage, 29 Proceedings, International Test Conference, paper 11.3, Santa Clara CA, October 2008. 30

A companion to Dubberke (above) that shows experimental results of using Boundary-Scan stimulus 31 provided by the EXTEST instruction for performing capacitive defect sensing. This paper points out the 32 shortcomings of EXTEST-based capability which leads to features implemented by this standard. 33

Sunter, S. and Parker, K. P., Testing Bridges to Nowhere - Combining Boundary Scan and Capacitive 34 Sensing, Proceedings, International Test Conference, paper 2.1, Austin TX, November 2009. 35

IEEE P1149.8.1/D0.7, August 2009



This paper describes technology and design options for implementing chip-based AC stimuli for capacitive 1 sensing. Its intention is to alert the test community about this on coming standard. 2

Tee, C. L., Tan, T. H. and Ng, C. C., Augmenting Board Test Coverage with New Intel Powered Opens 3 Boundary-Scan Instruction, Proceedings, International Test Conference, paper 10.21, Austin TX, 4 November 2009. 5

This paper describes experiments with silicon implementations of precursors to the SELECTIVE_TOGGLE 6 instruction. 7

2. Normative references 8

The following referenced documents are indispensable for the application of this document (i.e., they must 9 be understood and used, so each referenced document is cited in text and its relationship to this document is 10 explained). For dated references, only the edition cited applies. For undated references, the latest edition of 11 the referenced document (including any amendments or corrigenda) applies. 12

1) IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture 13 2) IEEE Std 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks 14

3. Definitions 15

For the purposes of this draft standard, the following terms and definitions apply. The Authoritative 16 Dictionary of IEEE Standards Terms should be referenced for terms not defined in this clause. 17

3.1 Balun cell: A cell in the Boundary register used to select the “balanced/unbalanced” (abbreviated as 18 “balun”) behavior of a differential pin driver. Balanced behavior means a differential driver has both legs 19 operating in completely complementary fashion as would be their normal system function. Unbalanced 20 behavior means they are no longer complementary.. 21

3.2 Bed-of-nails: A test fixture that contains many spring-loaded probes positioned to contact conductive 22 targets on the surface of a printed circuit assembly. Each probe is mapped via fixture wiring to one or more 23 tester resources provided in a regular array below the fixture. 24

3.3 Defect: An unacceptable deviation from a norm. A defect requires action which may include repairing 25 the defect or discarding the assembly containing the defect. This justifies investment in tests and diagnostic 26 procedures aimed at discovering and eliminating defects. Examples of manufacturing defects on printed 27 circuit assemblies are: missing solder causing open connections, bridging solder causing shorts, missing 28 components, incorrect components, dead components, components that are misaligned, etc. 29

3.4 Device designer: The person(s) responsible for implementing circuitry within an integrated circuit 30 device, and who make tradeoff decisions for circuit features, performance levels, cost and producibility. 31 Device designers are charged with making additional tradeoffs in their designs that affect the producibility 32 of subsequent levels of product hierarchy, such as printed circuit assemblies and systems. 33

3.5 Device user: Persons who utilize integrated circuits provided by device designers. These include 34 printed circuit assembly and system designers, as well as testability consultants and test engineers. Device 35 users will provide information to inform tradeoff decisions made by device designers. 36

IEEE P1149.8.1/D0.7, August 2009



3.6 Differential pins: A pair of input or output pins that are complementarily dependent. For example, the 1 (ideal, noise-free) voltage waveforms seen during data passage are mirror images of each other. Contrast 2 with single-ended pins. 3

3.7 Loaded board test: A set of tests performed on printed circuit assemblies that determine if the 4 printed circuit assembly has been constructed properly and does not contain defects. 5

3.8 Normal pins: Device pins defined as those that will not be provisioned with the Selective Toggle 6 capability. (Contrast with “ST-pins”.) 7

3.9 Opens: An “open” is a defect condition which breaks an intended electrical connection. Typically this 8 may occur when an electrical device on a printed circuit assembly has a missing or broken connection, for 9 example, a missing ball joint in a ball grid array, a pin with missing solder, or a pin that has been bent or 10 broken off of its device. 11

3.10 Printed circuit assembly: (Also known as PCA.) A printed circuit board that has had circuit 12 components attached to it such that those components can receive and/or transmit signals among their 13 connections. 14

3.11 Printed circuit board: (Also known as PCB.) A substrate containing embedded wiring and metallic 15 planar structures. A PCB serves as a mounting substrate for numerous electrical devices, with the 16 embedded wiring forming interconnections between device pins. 17

3.12 Selective Toggle: The name of the principle feature enabled by this standard; the ability to cause some 18 pins to toggle output drive states while other remain at pre-assigned static output drive levels. 19

3.13 Single-ended pin: an input or output pin that is not part of a pin pair but is an independent path for 20 information. Contrast with differential pins. 21

3.14 ST-pins: Device pins defined as those in need of the Selective Toggle capability defined by this 22 standard and requiring an output drive capability. (Contrast with “normal pins”.) 23

3.15 Test pad: A conductive target on the surface of a printed circuit assembly that can be contacted by a 24 test probe in a bed-of-nails fixture. This provides electrical access to a circuit node that can be used for 25 testing. 26

3.16 Toggle: A single transition of a signal from one stable state (of two possible states) to a second stable 27 state. 28

3.17 Unbalanced differential pins: The outputs of a differential driver (negative and positive legs) that, 29 under the influence of instructions defined by this standard, have a non-complementary and asymmetrical 30 behavior. 31

3.18 Unpowered opens test: A test for open pin connections between a printed circuit assembly and 32 device pins that does not require the assembly to have power applied to support the test. 33

4. Technology 34

4.1 Evolution of printed circuit assembly technology 35

It is the nature of the electronics industry to undergo large technological change on a regular basis. The 36 driving force for these changes can be traced mainly to “Moore’s Law” that observes that integrated 37

IEEE P1149.8.1/D0.7, August 2009



circuits double in density periodically, typically every 18 months. This has both increased the capabilities 1 of products while driving down their costs. For printed circuit assemblies, change has manifested itself in 2 several ways. 3

• IC packages have become physically smaller while pin counts have risen dramatically. This leads 4 to concomitant increases in board layout density. Other devices (for example, termination resis-5 tors) have also decreased in size to match up better with the decreasing dimensions in board 6 layouts. Increased layout density may lead to increased board layer counts in order to pack more 7 interconnects into smaller areas. 8

• IC operating frequencies have risen dramatically. This leads to the need for controlled impedance 9 board layout technology. Controlled impedance layout rules are much stricter and will sometimes 10 lead to increases in board layer counts as intervening layers may need ground planes between 11 them. As a result, board layouts may contain more interconnect on inner layers that are not visible 12 at the surface layers, and, layout rules may not permit the application of standard test pads to 13 surface traces. 14

• While densities and operating frequencies have risen adding complexity to designing and 15 manufacturing printed circuit assemblies, there has been contrary pressure to lower the cost of 16 these assemblies, even though the scaling effects of Moore’s law have not been as accessible to 17 board technology beyond the integrated circuit level.1 For testing printed circuit assemblies, this 18 has translated into doing far more over time, but with pressure for an overall reduction in cost. 19

High level architecture has also played a role. For example, many product categories consist of multi-board 20 implementations. These boards are connected directly to each other (or via backplanes) in the final product, 21 but during individual board test, there may be vacant connectors which do not have mating boards attached. 22 Global manufacturing, customs and tax laws also create conditions where boards are manufactured and 23 tested while certain components (typically large, costly components) are missing. Such components are 24 thus socketed so that they can be added later. Thus, vacant sockets become a test problem – how can they 25 be tested for proper assembly and attachment? 26

4.2 Shifts in board testing challenges 27

These evolutionary trends create board test issues and can be categorized as density-driven, or architecture-28 driven. Density-driven problems come from growing difficulty in physically accessing specific points 29 within a board for test purposes. Access limitations have been predicted for over 20 years and some design-30 for-testability technologies such as IEEE Std 1149.1 Boundary-Scan have been developed and adopted to 31 varying degrees across the electronics industry. However, adopting Boundary-Scan has a lesser effect on 32 solving architecturally-driven problems; that of large amounts of interconnect that cannot be tested in 33 traditional ways even when Boundary-Scan is available to counteract declining access. A major example of 34 this problem is when Boundary-Scan devices are connected to non-Boundary-Scan devices, even passive 35 devices like connectors and sockets. While Boundary-Scan can test interconnections between compliant 36 devices, it was not specifically intended to test interconnections to devices that cannot cooperate via that 37 standard.2 38

In the middle of the 1990s, a novel test technology was invented which quickly became widely adopted, 39 known generically as unpowered capacitive opens testing. This technology is described in Annex A, where 40 sections A.1 and A.2 describe a test coverage problem, and a solution presented by unpowered capacitive 41 opens testing. Section A.3 then discusses how this test technique, originally developed for boards where 42 significant physical access is possible, can be updated by using Boundary-Scan to provide test stimulus 43 1 Gains provided by Moore’s law, it is argued, should not be dissipated at the board and system levels. 2 Note that conventional digital ICs may be tested with Boundary-Scan resources that exist in surrounding compliant devices, if enough of those resources exist to support such a test, and any timing requirements of the test can be honored by such an approach.

IEEE P1149.8.1/D0.7, August 2009



where physical access is no longer possible. Note that the “unpowered” property is eliminated when 1 Boundary-Scan is utilized. While Boundary-Scan can indeed provide some relief, there are some significant 2 defect coverage deficiencies, described in section A.4, that remain. In essence, the IEEE 1149.1 standard 3 does not provide enough capability to adequately solve this problem. New capabilities added to Boundary-4 Scan that can provide a solution are the subject of this standard and are provided in following clauses. 5

4.3 Signal pin types 6

4.3.1 Classification of pins 7

When implementing this standard, a device designer should take note of the intended use of a device and 8 then categorize the signal pins as “normal” or in need of “selective toggle” functionality. This standard will 9 refer to these categories as normal pins and as “ST-pins”. The normal pins will be implemented in full 10 compliance with IEEE Std 1149.1. The ST-pins will also have full compliance with IEEE Std 1149.1, but 11 will respond to new instructions provided by this standard. ST-pins will have more capability in these 12 significant ways: 13

⎯ All pins identified as ST-pins that would normally be implemented as inputs only will be given 14 drive capability as well. This effectively converts them to bidirectional pins and they must be pro-15 visioned with Boundary-Scan capabilities per IEEE Std 1149.1 rules for bidirectional pins. The 16 system behavior of these drivers could be permanently disabled, with the test mode behavior 17 controlled by a boundary register control cell. 18

⎯ Single-ended pins identified as ST-pins will be provided with self-monitoring observe capability, 19 per option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001. The threshold used to determine the logic 20 level should not be close to the level that two adjacent drivers might reach when they are at 21 opposite states and shorted together. The self-monitoring feature is intended for use with EXTEST. 22

⎯ Differential pins identified as ST-pins will be provided with self-monitoring observe capability. 23 The self-monitoring feature is intended for use with EXTEST. 24

⎯ All pins identified as ST-pins will be provided with new drive functionality under the control of 25 new testing instructions provided by this standard. 26

⎯ Differential drivers will have an “unbalancing” feature added so that the two normally-27 complementary legs will exhibit differentiated waveforms while under the control of new instruc-28 tions provided by this standard. Because of this, both pins of a differential pair (never just one) are 29 classified either as normal or as ST-pins. 30

Normal pins will perform as if EXTEST has been loaded when these new testing instructions are in effect. 31

The decision on pin classification is made with respect to the anticipated board architecture that a device is 32 intended to reside within, and to the goals required for adequate test coverage for the board architecture. 33 The principle example of board test technology is described in Annex A, but others exist or may be 34 developed as a result of the capabilities offered by this standard. An example of a board architecture that 35 would require pin classification is shown in Figure 2. In this example, device U1 will be given a Boundary-36 Scan capability, but is also being considered for compliance to this standard. 37

The signal pins of U1 are circled and labeled as normal (in black) or ST-pins (in blue). The decision is 38 based on whether Boundary-Scan can test the interconnections to other devices. The interconnections 39 between U1 and both U2 and U3 are fully provisioned with 1149.1 in all these devices. Those pins of U1 40 that connect to U2 and U3 are classified as normal. However the interconnect between U1 and the socket 41 S1 and the connectors C1, C2 and C3 are untestable for open connections, since all of the devices S1, C1-42 C3 will be vacant during test. The pins involved here are classified as ST-pins as devices S1, C1-C3 are 43 incapable, by themselves, in participating in a Boundary-Scan test. The test strategy is to use capacitive 44

IEEE P1149.8.1/D0.7, August 2009



opens test to supply coverage for these device interconnects. Note that U1 will need additional drive 1 capability (bidirectional) on those ST-pin signals that propagate to U1 from a socket or connector (circled 2 in red). This has the added benefit that the functional inputs, since they are to be provisioned with 3 bidirectional capability, can be tested with Boundary-Scan tests for shorts. 4

Figure 2 — Board architecture determining pin classification. 5 So the device designer, utilizing information about board architecture and test coverage needs, will 6 categorize device pins into “normal pin” and “ST-pin” types at the outset of implementing this standard. 7 The device designer may also incorporate scheduling, technology and economic factors into the decision, 8 trading off defect coverage. 9

4.3.2 Differential pins 10

A specific requirement for this standard is that differential drivers of ST-pins, under the influence of an 11 instruction from this standard, become unbalanced. It is instructive to look at a “typical” differential driver 12 circuit and its normal behavior. A simplified circuit is shown in Figure 3. This circuit is a steering network 13 for a current source IS and a termination RS. When data 0 is applied, two of the four FETs (Field Effect 14 Transistors) turn on steering the current I0 in one direction through RS. When a data 1 is applied the 15 opposite FETs turn on (while the original FETs turn off) reversing the current I1 in RS. Since the 16 magnitudes of IS = I0 = I1, this means the voltage drop across RS will switch so that the voltage drop 17 changes sign, but otherwise has the identical value for either polarity of data. A downstream differential 18 receiver will ignore voltage offsets and respond only to the voltage drop. The net effect is the two leg 19 voltage waveforms will appear to be nearly perfectly symmetric to each other centered at some offset 20 voltage. 21

The capacitive opens test technique (see Annex A) depends on a signal being capacitively coupled into a 22 sense plate. If the capacitance from signals Pos and Neg in Figure 3 are coupled to a sense plate with 23 approximately equal capacitance, then, being symmetric they will cancel and the sense plate will see no net 24 signal. To get an observable signal at the sense plate, one of the legs of the differential amplifier, under 25 control of a specific condition set up by this standard, must be made different, or unbalanced with respect 26 to its complementary signal. 27

S1:Large socket for a silicon device that is not present during board

testing.

U1:Silicon device

undergoing pin classification.

U2:BoundaryScan

device

U3:BoundaryScan

device

C3: Memory connector (empty)

C2: Memory connector (empty)

C1: Memory connector (empty)ST-pins Normal

pins

IEEE P1149.8.1/D0.7, August 2009



One way to do this is to examine the effect of the current source IS. The amount of current produced by the 1 current source determines the voltages seen at the outputs Pos and Neg. The two waveform charts in Figure 2 3 show the voltages at Pos and Neg when IS is set to 6 mA and 12 mA. The voltage swing at the pins 3 changes by a factor of 2, and there is an offset change which is a function of the voltage drops across the 4 FETs. 5

6

Figure 3 — Simplified schematic for a differential driver. 7 By adding a control signal to the current source, it can switch between two levels of current. This allows 8 controlled unbalancing. During testing the Data signal would be held constant while the current control 9 signal would be toggled, producing waveforms on the two legs, as seen in Figure 4. There is action on both 10 legs, but both legs are now in phase instead of being perfectly symmetrical. Thus a defect-free pair of legs 11 will now generate a visible signal in a sense plate rather than the null signal seen before due to cancellation 12 by symmetry. However, setting Data to 0 or 1 causes one of the two pins to have somewhat more swing 13 than the other, but, since the measurement of capacitance (at the sense plate) is largely independent of 14 signal amplitude, two pins worth of capacitance would be measured in either case. This means this scheme 15 could detect one pin being open, but not allow reliable indication which of the two was open. If both were 16 open, then no signal would be detected indicating both pins were open. 17

Volta

ge (I

S=

12 m

A)

Time

Neg

Pos

Data

1200 mV

Volta

ge (I

S=

6 m

A)

Time

Neg

Pos

Data

600 mV

Current Source IS

RS I1I0

Data 0,1

Differential Driver

Pos

Neg

1.05v

2.25v

2.175v

2.775v

01

01

IEEE P1149.8.1/D0.7, August 2009



Figure 4 — Driver with a controllable dual-current source. 1 Both Figure 3 and Figure 4 show a source termination resistance RS that provides a path for the current 2 flow. RS could be implemented within the IC, or be provided as part of external circuitry. If RS is part of the 3 external circuitry, this path may not exist. For example, the path could be broken due to an open defect at a 4 device pin, or, because the termination is located on a plug-in assembly that will not be present during 5 testing. (The device itself is assumed to be defect-free, meaning the current path would not be interrupted 6 on-chip.) In the first case a defect causes the open path where in the second, a defect-free path will not pass 7 current. 8

[Editor’s note: On my (potentially flawed) analysis, for the case where the current path is open, we 9 could get nearly rail-to-rail complementary signals in Figure 3, and in Figure 4, we would NOT get 10 the unbalancing, but also get rail-to-rail complementary signals. If this is true, then maybe we have 11 to mandate that differential signals have termination before these differential signals can be declared 12 to be “ST-pin” signals. The termination could be on-chip, or, by agreement with the device users, be 13 implemented on the PCA. If PCA-based termination is expected, then maybe this fact should be 14 documented in the BSDL for checking.] 15

The current sources in Figure 3 and Figure 4 could be implemented as shown in Figure 5. (Note the 16 selectable current source implementation shown is one of several that are possible.) 17

The control of the data and current select signals in Figure 3 and Figure 4 are given in clauses 5 and 6. 18

Time

Volta

ge (D

ata

= 0)

Pos

Neg

Volta

ge (D

ata

= 1)

Time

Current SourceIS=6,12 mA

RS I1I0

Data 0,1

Differential Driver

Pos

Neg

Current Select 0, 1

Current Select 6 mA12 mA

1.05v

2.250v2.175v

2.775v

1.125 v

0.525 v

Current Select 6 mA12 mA

Neg

Pos

1.05v

2.250v2.175v

2.775v

1.125 v

0.525 v

IEEE P1149.8.1/D0.7, August 2009



Figure 5 — Current source implementations. 1 [Editor’s note: What should the specs be on the output waveforms in the loaded and unloaded case? 2 Steve Sunter suggests “AC sum of the differential signals should meet the same spec as for single-3 ended signals”.] 4

4.4 Defects targeted by the standard 5

This standard (as well as IEEE Std 1149.1) provides test support for detecting “manufacturing process 6 defects” that are found on printed circuit boards coming out of the manufacturing process. These defects 7 include missing devices (ICs, resistors, capacitors, etc.), improperly mounted devices (e.g., rotated 180 8 degrees), open solder joints, shorted solder joints, misaligned and dead devices. This standard focuses on 9 those defects concentrated in interconnect between devices that support this standard and other devices, 10 passive or active, that do not, but are testable by virtue of a non-contact sense technology. (See Annex A.) 11

Figure 6 — Interconnects between a stimulating device and a device being tested. 12 Figure 6, along with Table 1, show a group of interconnect defects between a device U1 that implements 13 this standard and device S1 that is to be tested. U1 is in test mode so all of its ST-pins have drive and self-14

Current Select

Current Select

Standard Current Source Selectable Current Source

Device implementing this standard, in test mode.

Device being sensed.

1

2U1 S1

C1

1

2

3

4

3

4

56

5

6C2

C3

1 2

1 21 2

R11

2

R21

2

Pwr

GndPwr

Gnd7

8

7

8

Node1

Node2 Node3

Node4

Node5

Node6 Node7

Node8 Node9

IEEE P1149.8.1/D0.7, August 2009



monitor capability. Device S1 has a non-contact test sensor in place. Other devices such as coupling 1 capacitors and termination resistors exist. A listing of possible defects and their effects is shown in Table 1. 2

Table 1 — Potential defects for the circuit in Figure 6 3 Defect

ID Defect site (Note 1) Possible defect cause(s) Typical failure syndrome(s)

1 Node1 shorted to fixed voltage (power or ground) Excess solder Fails EXTEST self-monitor;

reduced signal at sense plate 2 U1 pin 1 open Missing solder, bent pin Reduced signal at sense plate 3 C1 pin 1 open (Note 3) Missing solder, missing capacitor Reduced signal at sense plate

4 Node1 shorted to Node2 Excess solder Fails EXTEST self-monitor; reduced signal at sense plate

5 Node3 shorted to fixed voltage (power or ground) Excess solder Reduced signal at sense plate

6 Node2 shorted to Node3 Excess solder, defective capacitor Not detected

7 Node4 shorted to Node5 Excess solder, defective resistor

Fails EXTEST self-monitor; excess amplitude in unbalanced mode may be sensed, but depends on driver technology.

8 R1 pin 1 open Missing solder, missing resistor Not detected

9 U1 pin 4 open Missing solder, bent pin Reduced signal at sense plate (Note 2)

10 U1 pin 7 open Missing solder

Reduced signal at sense plate when testing pin 5. Increased signal at sense plate when testing pin 6 (Note 2)

11 Node5 shorted to Node7 Excess solder Increased signal at sense plate when testing U1 pin 5. Reduced signal at sense plate when testing U1 pin 7

12 S1 pin 7 open Missing solder, bent pin Reduced signal at sense plate

13 Node7 shorted to Node9 Excess solder, defective resistor

Increased signal at sense plate when testing either U1 pin 7 or U1 pin 8. Possibly detected dependent on driver technology. (Note 4)

14 R2 pin 1 open Missing solder, missing resistor Not detected

15 Both U1 pins 4 and 5 open Missing solder, bent pins

No signal sensed when driver is complementary. Reduced signal at sense plate when driver is unbalanced.

16 Node1 shorted to Node7 Excess solder Increased signal at sense plate when testing U1 pin 1. Reduced signal at sense plate when testing U1 pin 7

NOTE 1— Defects that are equivalent or symmetric in behavior have only one entry in this table.

NOTE 2— Some syndromes will depend on terminations.

NOTE 3— Assumes the coupling capacitance is large compared to the sensed capacitance. This is typically true by several orders of magnitude.

NOTE 4— For example, LVDS technology can give a reduced sensed signal, but CML may produce complementary (cancelling) signals.

In Table 1 all defects except 6, 8 and 14 are testable with conventional Boundary-Scan and/or capacitive 4 sensing. 5

IEEE P1149.8.1/D0.7, August 2009



4.5 Selective Toggle Theory of Operation 1

This is a high-level discussion of how board testing for manufacturing defects, using Boundary-Scan and 2 capacitive sensing measurements are facilitated by Selective Toggle. Details, rules and recommendations 3 follow in clauses 5 and 6. 4

Before Boundary-Scan-type tests are conducted, many board testers will conduct tests with the board in an 5 unpowered state. Such testers depend on nodal access to many points on surface(s) of the board. Shorts 6 testing is conducted at this time, as well as the measurement of many passive component values, as 7 supported by nodal access. In some cases, access limitations will not allow some components or potential 8 shorts to be tested. These are then left for other test techniques to follow that require the board to be 9 powered. Defects found in the unpowered state (particularly shorts) may be repaired before proceeding. 10

As with all Boundary-Scan-type tests, a PCA is first properly conditioned to support the test. Conditioning 11 includes powering up the necessary portions of the board in an appropriate sequence, and then asserting 12 control states on important nodes, such as power-on reset signals, oscillator disables and bus disables as 13 needed to bring the board to a stable state conducive to the test. Note that part of a Boundary-Scan test 14 strategy may be to use Boundary-Scan driver resources to condition certain board signals to high or low 15 values to further support the needs of the test during its execution. This becomes a “background pattern” of 16 node states needed to support the test. In some cases, this background pattern must be held constant for the 17 duration of the test and thus supersedes testing of those nodes. Analysis of such cases is a part of test 18 engineering. 19

Conventional Boundary-Scan testing using the 1149.1 EXTEST instruction may then be run since it 20 focuses on finding shorts and open connections between Boundary-Scan devices. If shorts are indeed 21 detected, power may be quickly removed from the board to prevent damage. These may be repaired before 22 continuing; a decision made by the test engineering. The detection of opens may not precipitate such action 23 since they are less likely cause damage. Indeed, a test engineer may run a selection of Boundary-Scan tests 24 that focus on various defects, ordered to find dangerous shorts quickly, followed by less damaging defects 25 later. Each such test may be “stand-alone” meaning it is entirely responsible for setup of the test conditions 26 it needs and is not dependent on other preceding tests to leave these conditions behind. Such tests can be 27 rearranged in order, or even skipped if desired. Such tests will start and end in the Test-Logic-Reset state. 28

When a Boundary-Scan test making use of the features in this standard is first initiated, all the ICs that 29 participate are in system mode, meaning their I/O pins are controlled by their system functionality. Using 30 the PRELOAD instruction, boundary register states are set up as will be needed by the test when it enters 31 test mode, controlled by either EXTEST or the SELECTIVE_TOGGLE instruction provided by this 32 standard.. To simplify this discussion, assume there is only one IC being used to test one device-under-test 33 (DUT) with the SELECTIVE_TOGGLE instruction. The normal pins will behave as per EXTEST, but the 34 ST-pins will perform as specified by SELECTIVE_TOGGLE. 35

The preload sequence is used to deliver a background pattern of necessary hold states, and also, an initial 36 state pattern for all normal and ST-pins. This can be a simple all-zero or all-one pattern for the ST-pins, or 37 a more random-looking pattern needed to enhance test performance. For example, some ST-pins might fan 38 out to an array of memory ICs and it is necessary to assure that all the chip-select lines of this array are all 39 one, while the write enables are all zero. This would become part of an initial state shifted in by 40 PRELOAD. 41

Once the initial state is set up, then the SELECTIVE_TOGGLE instruction is loaded and activated. This 42 causes all normal and ST-pin drivers to take on their initial states. The boundary register is still in place for 43 shifting and updating. However, the normal pins behave as EXTEST mandates, meaning any new states 44 updated to these pins will change their states. The ST-pins will interpret ones shifted into their register cells 45 not as new data, but as a command for that pin to toggle from and back to its initial state while in the Run-46 Test/Idle TAP state. One or more transitions may occur depending on how long the Run-Test/Idle TAP 47 state persists. If a zero is shifted in, that is a command for that pin to retain its initial state for the duration 48

IEEE P1149.8.1/D0.7, August 2009



in Run-Test/Idle. On subsequent shifting, new pins can be selected to toggle while previously toggled pins 1 again become quiescent. For testing with capacitive sense plates, only one pin (per plate) is selected for 2 toggling while all the rest are held at static states. The number of transitions sensed by the capacitive plate 3 is determined by the technology used to convert transitions into test information. Depending on this 4 technology, 1 transition (a step function), 2 transitions (an impulse function) or many transitions (producing 5 a frequency) may be required. The SELECTIVE_TOGGLE instruction is designed to offer this flexibility. 6

5. Instructions 7

IEEE Std 1149.1 is the foundation for this standard. All instructions provided by IEEE Std 1149.1 perform 8 as specified in that standard for all pins. 9

5.1 IEEE Std 1149.1 instructions 10

5.1.1 Rules 11

a) All instructions specified by IEEE Std 1149.1 shall perform as specified in that standard, and for any 12 such instruction that controls or observes pins, all pins shall also perform as specified by that 13 standard, with one exception: for any output or bidirectional pair of pins controlled by a differential 14 driver, there shall be a logical inversion between the boundary register data cell and one of the driven 15 pins. 16

5.1.2 Description 17

IEEE Std 1149.1 allows a single data register cell to control a differential driver, but treats this situation as 18 a digital-to-analog boundary, where no rules are given to govern the behavior of the analog portion. IEEE 19 Std 1149.1 does maintain that there be no signal inversion between data register cells and digital pins. Rule 20 a) in 5.1.1 clarifies that a single data register cell providing data to a differential driver that controls a pair 21 of pins will have no inversion with one pin and signal inversion with the other. 22

5.2 Instructions for selective toggling and guarding 23

This standard mandates the addition of two new instructions. The first is TOGGLE_SETUP (see 5.3) and 24 the second is SELECTIVE_TOGGLE (see 5.4). The TOGGLE_SETUP instruction is used to control 25 parametric performance features of the SELECTIVE_TOGGLE instruction. The SELECTIVE_TOGGLE 26 instruction provides the ability to cause ST-pin drivers to either hold stable logic values, or to toggle 27 selected pins a precise number of times, and at a toggle frequency determined by the TCK frequency. The 28 toggle frequency is a divided value of TCK controlled by toggle control register loaded by the 29 TOGGLE_SETUP instruction. 30

5.3 The TOGGLE_SETUP instruction 31

This standard specifies a mandatory normal mode instruction, TOGGLE_SETUP, which allows parameters 32 that control the behavior of SELECTIVE_TOGGLE to be loaded into a toggle control register (see Clause 33 7). While this instruction is in effect, the I/O pins of the device are in their system mode of operation. 34

IEEE P1149.8.1/D0.7, August 2009



5.3.1 Rules 1

a) A TOGGLE_SETUP instruction shall be provided for components that possess ST-pins. 2 b) The TOGGLE_SETUP instruction shall become effective at the falling edge of TCK in the Update-IR 3

TAP Controller state. 4 c) While the TOGGLE_SETUP instruction is in effect, the device system pins shall operate in system 5

mode. 6 d) The TOGGLE_SETUP instruction shall select only the toggle control register to be connected for 7

serial access between test data in (TDI) and test data out (TDO) in the Shift-DR TAP Controller state. 8 e) While the TOGGLE_SETUP instruction is in effect, data bits shall be shifted into the toggle control 9

register upon rising edges of TCK while in the Shift-DR TAP controller state. 10 f) While the TOGGLE_SETUP instruction is in effect, data bits shall be loaded into the parallel hold 11

portion of the toggle control register upon the falling edge of TCK in the Update-DR TAP controller 12 state. 13

NOTE— The meaning of the data bits in the toggle control register is described in Clause 7. 14

5.3.2 Permissions 15

a) The binary value(s) for the TOGGLE_SETUP instruction may be selected by the device designer. 16


The TOGGLE_SETUP instruction is used to load configuration data into a toggle control register. This is a 18 data register that operates as defined by IEEE Std 1149.1 for data registers. The configuration data controls 19 the performance of the SELECTIVE_TOGGLE instruction (see 5.4). The TOGGLE_SETUP instruction is 20 a system mode instruction, so the normal behavior of the device and its I/O is unaffected by this instruction. 21 It is intended that this instruction be used to configure the toggle control register with bits appropriate for 22 the SELECTIVE_TOGGLE instruction’s subsequent operation before entering test mode 23

5.4 The SELECTIVE_TOGGLE instruction 24

This standard specifies a mandatory test mode instruction, SELECTIVE_TOGGLE, which governs new 25 capabilities defined for ST-pins (see 4.3.1). All normal pins will perform as if the IEEE Std 1149.1 26 EXTEST instruction is operating whenever the SELECTIVE_TOGGLE instruction is effective. 27

5.4.1 Rules 28

a) A SELECTIVE_TOGGLE instruction shall be provided for components that possess ST-pins. 29 NOTE 1— ST-pins are identified by the classification process described in 4.3.1 and 6.1. 30

NOTE 2— ST-pins are provisioned with drive capability (see 6.3.2) and self-monitoring capability (see 6.3.1). 31

NOTE 3— ST-pins that are differential are provisioned with unbalancing capability described in 6.3.4. 32

b) The SELECTIVE_TOGGLE instruction shall become effective at the falling edge of TCK in the 33 Update-IR TAP Controller state. 34

IEEE P1149.8.1/D0.7, August 2009



NOTE—By “effective” it is meant that (enabled) system pins shall respond to the content of the boundary 1 register as specified below 2

c) The SELECTIVE_TOGGLE instruction shall select only the boundary register to be connected for 3 serial access between test data in (TDI) and test data out (TDO) in the Shift-DR TAP Controller state. 4

NOTE—The boundary register is the same register, in length, organization, and construction as that targeted 5 by the EXTEST instruction. 6

d) Normal pins shall perform exactly as specified for the EXTEST instruction by IEEE Std 1149.1 7 whenever the SELECTIVE_TOGGLE instruction is effective, based on the content of the boundary 8 register. 9

NOTE—Normal pins are identified by the classification process described in 4.3.1 and 6.1. 10

e) With the SELECTIVE_TOGGLE instruction shifted into the Instruction Register, then upon the 11 falling edge of TCK in the Update-IR state, the ST-pin drivers will behave identically to the behavior 12 of EXTEST, based on the content of the boundary register. 13

NOTE— The content of the boundary register driver control cells will determine which drivers are enabled. 14

f) With the SELECTIVE_TOGGLE instruction in effect and when a falling TCK edge occurs in the 15 Update-DR TAP state, the update flip-flop of the data cells associated with ST-pins shall retain their 16 current state. 17

NOTE—Normal pins will transfer the content of their capture flip-flops to the update flip-flops as per IEEE Std 1149.1. 18

g) With the ST-pin driver in an active (enabled) state, the SELECTIVE_TOGGLE instruction in effect 19 and when a toggle select condition exists for that pin, the output signal on that ST-pin shall be 20 controlled as follows: 21 1) the output signal shall transition to the opposite of the state resulting from rule 5.4.1e) on the 22

first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state, and 23 2) the output signal shall invert its state on subsequent selected falling edges of TCK while still in 24

the Run-Test/Idle TAP Controller state, and 25 3) the output signal shall not change its driven state at any other time that the 26

SELECTIVE_TOGGLE instruction remains effective, and 27 4) upon exiting the Run-Test/Idle state, the final state of the output signal shall be held in the 28

associated boundary register data cell update flip-flop. 29 NOTE 1— From IEEE Std 1149.1, a driver may have an optional control cell in the boundary register that controls 30 whether it is enabled to drive a valid state or produces an undriven state. These control cells may be updated with 31 different data each time the Update-DR state is passed while SELECTIVE_TOGGLE is in effect. When enable data is 32 changed, drivers may become enabled or disabled, and the results of this should be factored into test algorithm design. 33

NOTE 2— The “toggle select condition” exists for an ST-pin when the capture flip-flop for that pin’s data cell contains 34 a ‘1’. If the cell contains a ‘0’, then the condition does not exist. 35

NOTE 3— The “selected falling edge” of TCK is that determined by the TCK divisor held in the toggle control register, 36 as loaded by the TOGGLE_SETUP instruction. See the discussion in 6.4. 37

NOTE 4— When toggling of an ST-pin is concluded the final state is recorded in the boundary register data cell for that 38 ST-pin, and this may be the opposite state that was originally established by rule 5.4.1e). 39

h) When an ST-pin driver is disabled, the input to that driver shall still behave as mandated in rule g) 40 above. 41

IEEE P1149.8.1/D0.7, August 2009



NOTE—Only part 4) in rule g) can be observed by examining subsequent pin behavior, that is, when the driver is later 1 enabled. 2

i) With the ST-pin driver in an active (enabled) state, the SELECTIVE_TOGGLE instruction in effect 3 and a toggle select condition absent for that pin, the output signal on that AC pin shall be controlled 4 exactly as specified for the EXTEST instruction by IEEE Std 1149.1, with its state determined by the 5 content of the update flip-flop of the associated boundary register data cell. 6

5.4.2 Permissions 7

a) The binary value(s) for the SELECTIVE_TOGGLE instruction may be selected by the device 8 designer. 9


The SELECTIVE_TOGGLE instruction implements new stimulus behaviors for ST-pins and simultan-11 eously behaves identically to IEEE Std 1149.1 EXTEST for normal pins. The SELECTIVE_TOGGLE 12 instruction causes data produced by selected ST-pin drivers to be inverted on the first falling edge of TCK 13 after entering the Run-Test/Idle TAP Controller state, and to be subsequently toggled on selected falling 14 edge of TCK while remaining in the Run-Test/Idle state. Upon exiting the Run-Test/Idle TAP Controller 15 state, the driver may be in its original or inverted states. ST-pin drivers that are not selected, and drivers on 16 normal pins, remain constant. 17

NOTE—Drivers implementing EXTEST_TRAIN from IEEE Std 1149.6 may change state one-half TCK cycle after 18 leaving the Run-Test/Idle TAP Controller state so that the state of the driver is the same as when Run-Test/Idle was 19 entered. This behavior is not implemented by SELECTIVE_TOGGLE. This should be kept in mind when 20 implementing both IEEE Std 1149.6 AC-pin behavior and ST-pin behavior on the same pins of a device. 21 Before the SELECTIVE_TOGGLE instruction is loaded into the Instruction Register, the toggle control 22 register is preloaded with initial data using the TOGGLE_SETUP instruction. This determines the TCK 23 divisor that will be used to determine the number of TCK falling edges that separate ST-pin transitions 24 when in the Run-Test/Idle TAP controller state. 25

Also, before the SELECTIVE_TOGGLE instruction is loaded into the Instruction Register, the boundary 26 register is preloaded with initial data using the PRELOAD instruction. This initial data will be used by 27 SELECTIVE_TOGGLE to define the initial static states of each ST-pin. Each ST-pin will then either hold 28 this state, or toggle this state at the appropriate times, when not enabled or enabled for toggling, 29 respectively. The selection of holding or toggling is determined by subsequent data loads shifted into the 30 boundary register while SELECTIVE_TOGGLE is in effect. This PRELOAD sequence used to prepare for 31 SELECTIVE_TOGGLE operation is shown in Figure 7, where at the time flagged by Note 1 (falling edge 32 of TCK in the Update-DR state) the shifting of preload data is just being completed and the data is being 33 updated in the Update flip-flops of the boundary register cells. After that time, the Instruction Register 34 shifting for loading the SELECTIVE_TOGGLE opcode is performed. Then at the time flagged by Note 2 35 (falling edge of TCK in the Update-IR state) the SELECTIVE_TOGGLE instruction is updated into the 36 Instruction Register. As a result of this, the boundary register takes control of the output drivers as the 37 device moves from system mode to test mode. Two ST-pin traces are shown; one that is in hold mode 38 (labeled the “hold driver”) and one that is going to be enabled for toggling (labeled the “toggle driver”). 39 Figure 7 shows both of these ST-pins taking the low state, although either pin may take any desired initial 40 state. The right side of this diagram contains ellipses that form a starting point for some following diagrams 41 that illustrate important SELECTIVE_TOGGLE behaviors. 42

IEEE P1149.8.1/D0.7, August 2009



Figure 7 — PRELOAD sequence used to set up SELECTIVE_TOGGLE operation. 1 The diagram in Figure 8 begins at the end of shifting data into the boundary register (see the right side of 2 Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary register 3 determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold their 4 current state (signified by a 0), while in the Run-Test/Idle state. At the time flagged by Note 3 (the first 5 falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays 6 stable. The Run-Test/Idle state is exited after just one TCK cycle, so the toggle driver remains static in the 7 new state. Subsequent shifting of new data into the boundary register could change the current toggle 8 driver(s) into hold driver(s) and another hold driver could be selected for toggling. Again note that this 9 example showed both the hold driver and toggle driver starting in the low state, but either could have been 10 high at the start, depending on the preloaded data. 11

This behavior can be used to support test algorithms (and associated tester hardware) that utilize a step 12 function as the measurement stimulus. Typically, the step function is sensed by tester hardware that 13 responds to a single transition at a known point in time. It may also require that no new stimulus events 14 occur for some time after the step function occurs in order not to interfere with the measurement. This time 15 between events could be assured by the length of time that it takes to shift a new toggle/hold pattern into 16 the combined chain boundary registers. If the underlying test algorithm finds the shift time is insufficient, 17 then more time can be inserted by programming a higher TCK divider value and waiting in the Run-18 Test/Idle state for a lesser time, such that no additional transition occurs before leaving the Run-Test/Idle 19 state. Time delay can also be inserted by passing to the Pause-DR state for some arbitrary length of time 20 during the shifting of new data. The fact that the toggled pin is left in the opposite state must also be 21 accounted for by the test algorithm, as appropriate. 22

Figure 8 — Using SELECTIVE_TOGGLE to perform a step function. 23

PRELOAD SELECTIVE_TOGGLE

SDRUDRE1DR SDRS SIRS CIR SIR

PRELOAD

E1IR

(System Mode)

(System Mode)

TCK

TAP State

Instruction

Hold Driver

Toggle Driver

UIR

(Test Mode)

(Test Mode)

SDRS CDR

Note 1 Note 2

UDRE1DR RTI SDRS CDR

TCK

TAP State

Instruction

Hold Driver

Toggle Driver

SDR

(Test Mode)

(Test Mode) (Test Mode)

SDR

Note 3

SELECTIVE_TOGGLE

IEEE P1149.8.1/D0.7, August 2009



Figure 9 — Using SELECTIVE_TOGGLE to perform an impulse function. 1 The diagram in Figure 9 also begins at the end of shifting data into the boundary register (see the right side 2 of Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary register 3 determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold their 4 current state (signified by a 0), while in the Run-Test/Idle state. In this example, assume the TCK divisor is 5 0, meaning no extra TCK cycles are waited between pin transition events. At the two times flagged by Note 6 3 (falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays 7 stable. The Run-Test/Idle state is exited after two TCK cycles, so the toggle driver returns to its initial state. 8 Subsequent shifting of new data into the boundary register could change the current toggle driver(s) into 9 hold driver(s) and another hold driver could be selected for toggling. Again note that this example showed 10 both the hold driver and toggle driver starting in the low state, but either could have been high at the start, 11 depending on the preloaded data. 12

This behavior can be used to support test algorithms (and associated tester hardware) that utilize an impulse 13 function for the measurement stimulus. One parameter of importance may be the width of this impulse, 14 which can range from one TCK period, to 1/8000th of a second per the rules of the TCK divider (see 6.4). It 15 may also require that no new stimulus events occur for some time after the impulse function occurs in order 16 not to interfere with the measurement. This time between impulse events could be assured by the length of 17 time that it takes to shift a new toggle/hold pattern into the combined chain boundary registers. If the 18 underlying test algorithm finds the shift time is insufficient, then more time can be inserted by waiting in 19 the Run-Test/Idle state for a lesser time than the TCK delay time such that no additional transition occurs 20 before leaving the Run-Test/Idle state. Time delay can also be inserted by passing to the Pause-DR state for 21 some arbitrary length of time during the shifting of new data. 22

Figure 10 — Using SELECTIVE_TOGGLE to create a frequency signal. 23 The diagram in Figure 10 again begins at the end of shifting data into the boundary register (see the right 24 side of Figure 7) after SELECTIVE_TOGGLE has become effective. The bits shifted into the boundary 25 register determine which ST-pins will be enabled for toggling (signified by a 1) and those that will hold 26 their current state (signified by a 0), in the Run-Test/Idle state. In this example, assume the TCK divisor is 27 0, meaning no extra TCK cycles are waited between pin transition events. At several times flagged by Note 28

UDRE1DR RTI RTI

TCK

TAP State

Instruction

Hold Driver

Toggle Driver

SDR

(Test Mode)

(Test Mode)

SDRS CDR SDR

Note 3

SELECTIVE_TOGGLE

UDRE1DR RTI RTI RTI

TCK

TAP State

Instruction

Hold Driver

Toggle Driver

SDR

(Test Mode)

(Test Mode)

SDRS CDR SDRRTIRTI

Note 3 Note 3 Note 3

SELECTIVE_TOGGLE SELECTIVE_TOGGLE

IEEE P1149.8.1/D0.7, August 2009



3 (falling edge of TCK in the Run-Test/Idle state) the toggle driver changes state while the hold driver stays 1 stable. The Run-Test/Idle state is exited after multiple TCK cycles, so the toggle driver returns to its initial 2 state if the cycle count is even, or stays in the opposite state if the cycle count is odd. Subsequent shifting of 3 new data into the boundary register could change the current toggle driver(s) into hold driver(s) and another 4 hold driver could be selected for toggling. Again note that this example showed both the hold driver and 5 toggle driver starting in the low state, but either could have been high at the start, depending on the 6 preloaded data. 7

This behavior can be used to support test algorithms (and associated tester hardware) that utilize a 8 frequency signal for the measurement stimulus. One parameter of importance will be the frequency, which 9 can range from ½ the TCK frequency to around 8kHz, per the rules of the TCK divider (see 6.4). The 10 amount of time spent in the Run-Test/Idle state will depend on the amount of averaging needed by the 11 frequency-based measurement. 12

6. Pin implementation specifications 13

6.1 Pin classification 14

6.1.1 Rules 15

a) The device designer shall survey the expected use of a device’s system pins and shall designate those 16 that need to support the selective toggle functionality as being “ST-pins”. 17

b) All other system pins not selected in a) shall be designated as “normal” pins. 18 NOTE—This nomenclature, ST-pins and normal pins (see 4.3.1), will be used in subsequent rules, recommendations 19 and descriptions. The concept of “system pin” is defined by IEEE Std 1149.1. 20

c) In the case of differential pairs of signals, both shall be considered together during classification. 21 NOTE—Thus both will either be classified as normal or as ST-pins. 22

6.1.2 Recommendations 23

a) The device designer should consult with device users as to the expected uses of pins, and should also 24 take into account tradeoffs of device costs and design time versus enhanced defect coverage during 25 testing. 26


Adding selective toggle functionality will cost a device designer some design time and will consume some 28 on-chip resources. This must be traded off against benefits gained at PCA testing which may include lower 29 overall product cost and the acceleration of product development. A designer may be somewhat aware of 30 these tradeoffs but should consult with board designers and test engineers who know the details of the PCA 31 application of the device, and who can quantize the benefits of this new functionality. 32

IEEE P1149.8.1/D0.7, August 2009



6.2 Implementation of normal pins 1

6.2.1 Rules 2

a) Normal pins shall be implemented exactly as mandated by IEEE Std 1149.1 for all instructions 3 defined by that standard. 4

b) For the SELECTIVE_TOGGLE instruction defined by this standard, normal pins shall behave exactly 5 as they would for the EXTEST instruction defined by IEEE Std 1149.1. 6

6.2.2 Description 7

Normal pins implement EXTEST behavior when the SELECTIVE_TOGGLE instruction is active. This 8 means they can hold logic states or be inactive (high impedance) depending on their implementation and 9 the content of their controlling boundary register cells. Thus they can participate in selective toggle testing 10 by holding background logic states needed for the stability of the test. 11

Figure 11 —Conceptual implementation of a single-ended normal pin boundary register cell. 12

NOTE—Figure 11 is not normative. The circuitry shown implements the rules for single-ended output driver cells 13 found in IEEE Std 1149.1, but is one of many possible designs. 14 A possible implementation of a normal pin output boundary register cell is shown in Figure 11, taken from 15 IEEE Std 1149.1 (called a “BC_1” cell) and is reproduced here as a basis for describing boundary register 16 cells needed for this standard. The mode table in this figure has a new entry for the 17 SELECTIVE_TOGGLE instruction. The ‘Mode’ signal is provided by instruction decode circuitry, and 18 would only change value on the falling edge of TCK in the Update-IR TAP state, or the Test-Logic-Reset 19 TAP state. The “SI” input is the shift input for the cell. The “SO” output is the shift output. These signals 20 pass boundary register shift data in and out of the cell. The “PI” signal is the parallel input of the cell, 21 which in this context (an output pin cell) receives data from the system logic of the IC. The “ShiftDR” 22 signal is derived from the TAP controller and determines whether the R1 flip-flop gets data from “SI” 23 (during shifting in the Shift-DR TAP state) or from “PI” (during parallel capture in the Capture-DR TAP 24 state). The “PO” signal is used to provide data to the output driver. Finally, there are two clock signals, 25 “ClockDR” which loads data into the R1 flip-flop, also often referred to as the “Capture” flip-flop. 26 ClockDR is derived from the rising edge of TCK and is active in the Capture-DR and Shift-DR TAP states. 27

G1

1

1

G1

1

1

1D

C1

1D

C1

ShiftDRPO

PI

Mode

ClockDR UpdateDR

SO

SI

M1

M2

R1 R2

Boundary Register Cell BC_1 from Figure 11-30, IEEE Std 1149.1-2001

OutputDriver

SystemLogic

Mode

0

Instruction

BYPASS

SAMPLE and PRELOAD

EXTEST

0

1

SELECTIVE_TOGGLE 1

IEEE P1149.8.1/D0.7, August 2009



The “UpdateDR” clocks data into the R2 flip-flop, often referred to as the “Update” flip-flop. UpdateDR is 1 derived from the falling edge of TCK, and is active in the Update-DR TAP state. 2

The “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001 can be used in 3 normal pin cell design to increase testability of the board. This option takes the pin state of the device and 4 feeds it back to the Capture flip-flop so that the pin’s actual state is captured. This enables detection of 5 shorts, where a driver cannot achieve the state it is trying to reach, Cell BC_10 offers self-monitoring 6 capability, as shown in Figure 12 but does not support the INTEST instruction. Cell BC_9 does support the 7 INTEST instruction, at the cost of an extra multiplexer. 8

Figure 12 — A self-monitoring cell for an output pin. 9 Boundary register cells that service normal pins for device inputs an bidirectional pins would be similarly 10 changed, meaning they would be identical to those designs given in IEEE Std 1149.1, but would have an 11 entry in their mode tables for the SELECTIVE_TOGGLE instruction, and that mode entry would be 12 identical to that for EXTEST. This is similarly true for boundary register cells that act as driver enable 13 control cells for output drivers on normal pins. 14

6.3 Implementation of ST-pins 15

Pins designated by the designer as ST-pins start out having system definitions as inputs, outputs and 16 bidirectional, either single-ended or differential. This standard requires some additional features for these 17 pins that are to be available in test mode. One example is an ST-pin that in system mode is a simple, single-18 ended input. In test mode it will be required to have a drive capability, so one way to implement this pin 19 would be to choose a bidirectional design for that pin. This implies a control signal for the drive enable. 20 The control signal would not exist in the system definition of the device, so the drive capability would not 21 be accessible in the device while in system mode. In effect, the test mode capability of the pin is a superset 22 of its system requirement. Note that the BSDL description of this pin will describe this superset, so it will 23 list this pin as “inout” even though the system mode use of the pin is a simple input. 24

G

0

1

D

CK

Q

SOOutputDriver

G

0

1

D

CK

Q

ClockDRUpdateDRSI

Mode

ShiftDR

Boundary Register Cell BC_10 from Figure 11-33, IEEE Std 1149.1-2001

Mode

0

Instruction

BYPASS

SAMPLE and PRELOAD

EXTEST

0

1

SELECTIVE_TOGGLE 1

R1R2

SystemLogic

PIPO

M1

M2

IEEE P1149.8.1/D0.7, August 2009



6.3.1 Single-ended output pins 1

6.3.1.1 Rules 2

a) An enabled single-ended output pin, when designated as an ST-pin and when the SELEC-3 TIVE_TOGGLE instruction first becomes effective (at the falling edge of TCK in the Update-IR TAP 4 state) shall produce a low voltage or a high voltage on the pin when the related boundary register cell 5 contains a 0 or a 1 respectively. 6

b) An enabled single-ended output pin, when designated as an ST-pin, during execution of the SELEC-7 TIVE_TOGGLE instruction, and when selected for toggling, shall transition between one stable 8 voltage level to another stable voltage level only at the times given by rule 5.4.1g). 9

c) The change in voltage prescribed in rule b) shall be monotonic. 10 d) The change in voltage prescribed in rule b) shall occur in a time period no greater than fivc 11

microseconds as measured from the 10% to 90% levels of change. 12 e) The conditions for verifying rules b), c) and d) shall be provided by the device manufacturer in the 13

device's datasheet section for measuring AC performance. 14 f) A single-ended output pin, when designated as an ST-pin, during execution of the EXTEST 15

instruction, shall load a digitized representation of the driven pin state into the capture flip-flop of the 16 data cell for that driver in the boundary register, at the rising edge of TCK in the Capture-DR state. 17

NOTE— This is the “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001. 18

6.3.1.2 Recommendations 19

a) The change in voltage prescribed in rule 6.3.1.1b) should be no less than 400 millivolts. 20 b) For rule 6.3.1.1f), the threshold voltage used to digitize the output pin state should be significantly 21

different than the voltage that would appear on the pin when that pin driver was shorted to an adjacent 22 pin driver. 23

c) For rule 6.3.1.1f), the point in the driver-to-pin circuitry where the pin voltage is monitored should be 24 as close to the pin as possible. 25

6.3.1.3 Description 26

Rule 6.3.1.1b) mandates that a toggling pin transition between two voltage levels when so enabled during 27 operation of SELECTIVE_TOGGLE. One way to do this is to use the existing native driver with its drive 28 levels and switching time, which should have no difficulty in meeting (exceeding) the requirement of rules 29 6.3.1.1c) and d). This approach will likely also exceed the minimum voltage swing recommendation of 30 6.3.1.2a) as well. A robust voltage swing is important to capacitive sensing to help differentiate a toggle 31 signal from local noise contributions. Indeed, when considering capacitive sense testing it is advised that 32 test engineers consider the capabilities of their measurement systems with respect to the voltage swings 33 generated by ST-pins. 34

ST-pins will often be those which drive PCA signals that have no tester resources, or, complementary 35 Boundary-Scan facilities, somewhere else on the PCA to support testing for shorted pins. Since driven pins 36 on devices are very often adjacent to each other, it is likely that a manufacturing defect might cause a short 37 between two drivers. If one or both of these pins is an ST-pin, then the self-monitor capability can be used, 38 during conventional Boundary-Scan (i.e., EXTEST-based) testing to detect these shorts. Rule 6.3.1.1f) 39 requires the device designer to select option 2 when implementing rule 11.6.1a) of IEEE Std 1149.1-2001. 40 The self-monitor feature is also active during SELECTIVE_TOGGLE, allowing verification of a driver’s 41 last output state after exiting the Run-Test/Idle TAP state. 42

IEEE P1149.8.1/D0.7, August 2009



Recommendations 6.3.1.2b) and c) offer design guidance to help detect shorted drivers. If the voltage that 1 appears on two shorted driver pins is very close to the threshold voltage, and there are some voltage drops 2 along the current paths, it is possible for each monitor to digitize the driven values that are above/below the 3 actual pin’s voltage. This can occur when the short-circuit voltage at the pin, plus or minus the voltage 4 drops along the current path, gives a voltage seen by the monitor that is above or below the threshold, even 5 though it is not a valid logic level. If this happens, then both self-monitors may observe “correct” data 6 when there is a short between the driver pins. 7

A possible boundary register cell design to support single-ended ST-pin drivers is found in Figure 13. 8 Multiplexers M1 and M2, plus flip-flops R1 and R2 are the same as seen in Figure 12, as are the signals 9 labeled Mode, PI, PO, ShiftDR, SI, SO, ClockDR, and UpdateDR. Toggle_TCK is the divided version of 10 TCK given in section 6.4. TogHold is a signal that is 1 only when the effective instruction is 11 SELECTIVE_TOGGLE. RTIState is a signal that is 1 only when the TAP is in the Run-Test/Idle state. A 12 new multiplexer M3 is inserted between R1 and R2. Its purpose is to allow a selection of two data sources 13 to be updated into R2 from R1. Those two choices are 14

1) The content of R1, used to support normal 1149.1 instruction execution, and 15 2) The content of R2 when the state of flip-flop R1 is 0, or, the complemented content of R2 when 16

the state of flip-flop R1 is 1. This content is derived from Exclusive-Or gate E. 17 The control and multiplexers M1 and M2 are the same as seen before in Figure 12. Clocking of R1 is also 18 the same. The R2 flip-flop is clocked by one of two signals: 19

1) the UpdateDR clock, which only clocks R2 when a falling TCK occurs in the Update-DR TAP 20 state while the SELECTIVE_TOGGLE instruction is not in effect, or 21

2) the UpdateRTI signal which is generated by new logic in the form of gates A, B, C, D and latch 22 R3. 23

24

25

26

27

28

29

IEEE P1149.8.1/D0.7, August 2009



Figure 13 — Conceptual implementation of a single-ended ST-pin boundary register cell. 1

NOTE—Figure 13 is not normative. The circuitry shown implements the rules for single-ended output driver cells 2 found in IEEE Std 1149.1 and in this standard, but is one of many possible designs. 3 The UpdateRTI signal produces clocks only when the SELECTIVE_TOGGLE instruction is in effect, 4 when the TAP is in the Run-Test/Idle state, and when Toggle_TCK is falling (see 6.4). This allows the 5 loading of R2 with the output of the new M3 multiplexer. Then the capture flip-flop (R1) contains a 0, then 6 R2 stays constant as Toggle_TCK clocks occur in the Run-Test/Idle state. If R1 contains 1, then each 7 successive falling edge of Toggle_TCK will invert the state of R2. The state or R2 supplies data to the 8 output driver which will thus either remain constant or toggle. Latch R3 is only present to suppress a race 9 condition between RTIState and Toggle_TCK; this race could otherwise improperly clock R2 at incorrect 10 times. Note that gates A, B, C, D and latch R3 are common to all ST-pins and thus can be located near the 11 TAP with signals T-UpdateDR and UpdateSelect distributed to all ST-pins. 12

With this structure, data loaded into R1 becomes a selector that determines if a given ST-pin will hold data 13 (R1 contains 0) or toggle data (R1 contains 1) while in the Run-Test/Idle state. The initial state of the pin is 14

G

0

1

D

CK

Q

SOOutputDriver

D

CK

Q

ClockDRSI

Mode

ShiftDR

Mode

0

Instruction

BYPASS

SAMPLE and PRELOAD

EXTEST

0

1

SELECTIVE_TOGGLE 1

R1R2

SystemLogic

PIPO

M1

M2

UpdateDR

TogHold

TogHold is ‘1’ when SELECTIVE_TOGGLE is the effective instruction. (Note TogHold only changes in the Update-IR TAP state, when RTIState is ‘0’.)

Toggle_TCK

RTIState

T-UpdateDR

A BD

Gates A, B, C, D and latch R3 can be located near the TAP, with T-UpdateDR and UpdateSelect distributed to all ST-pins.

UpdateSelect

D Q

G

UpdateDel UpdateRTI

R3

Latch R3 suppresses a race condition between TCK and RTIState.

C

M3G

0

1

E

G

0

1

Located near pins

Located near TAP

The Toggle_TCK signal comes from the TCK divider subsystem.

RTIState is 1 when the TAP is in the Run-Test/Idle state.

IEEE P1149.8.1/D0.7, August 2009



determined by the data that was updated into the R2 flip-flop by the PRELOAD instruction (at the falling 1 edge of TCK in the Update-DR TAP state). On subsequent passages through Update-DR while 2 SELECTIVE_TOGGLE is in effect, the data in R2 is not reloaded from R1, but stays at the last value it had 3 while in the Run-Test/Idle TAP state. 4

6.3.2 Single-ended input pins 5

6.3.2.1 Rules 6

a) A single-ended input pin, when designated as an ST-pin, when the SELECTIVE_TOGGLE 7 instruction first become effective (at the falling edge of TCK in the Update-IR TAP state) shall 8 produce a low voltage or a high voltage on the pin when the related boundary register cell contains a 0 9 or a 1 respectively. 10

b) A single-ended input pin, when designated as an ST-pin, during execution of the SELEC-11 TIVE_TOGGLE instruction, and when selected for toggling, shall transition between one stable 12 voltage level to another stable voltage level only at the times given by rule 5.4.1g). 13

c) The change in voltage prescribed in rule b) shall be monotonic. 14 d) The change in voltage prescribed in rule b) shall occur in a time period no greater than fivc 15

microseconds as measured from the 10% to 90% levels of change. 16 e) The conditions for verifying rules b), c) and d) shall be provided by the device manufacturer in the 17

device's datasheet section for measuring AC performance. 18 f) A single-ended input pin, when designated as an ST-pin, during execution of the EXTEST instruction, 19

shall load a digitized representation of the driven pin state into the capture flip-flop of the data cell for 20 that driver in the boundary register, at the rising edge of TCK in the Capture-DR state. 21

NOTE—This is the “self-monitor” capability given in option 2 of rule 11.6.1a) in IEEE Std 1149.1-2001. 22

6.3.2.2 Recommendations 23

a) The change in voltage prescribed in rule 6.3.2.1b) should be no less than 400 milivolts. 24 b) For rule 6.3.2.1f), the threshold voltage used to digitize the output pin state should be significantly 25

different than the voltage that would appear on the pin when that pin driver was shorted to an adjacent 26 pin driver. 27

c) For rule 6.3.2.1f), the point in the driver-to-pin circuitry where the pin voltage is monitored should be 28 as close to the pin as possible. 29

d) For rule 6.3.2.1f), the voltage levels produced should be compatible with expected Boundary-Scan 30 receiver levels of other devices that may be connected to these pins. 31

6.3.2.3 Permissions 32

a) A single-ended input pin, when designated as an ST-pin, may be given the capability of disabling its 33 driver capability, during execution of the EXTEST and SELECTIVE_TOGGLE instructions, under 34 the control of the content of a boundary register control cell for that pin. 35

IEEE P1149.8.1/D0.7, August 2009




An important goal of this standard is for ST-pins to have stimulus capability. When a device pin, in its 2 system definition, is an input, which means a drive capability must be added in test mode so that during 3 testing (with EXTEST, for shorts, and SELECTIVE_TOGGLE, for opens) defects can be sensed. The rules 4 and recommendations given in 6.3.2 provide: 5

• that a drive capability be added to ST-pins that are system inputs, 6

• the change in driven levels be greater than a minimum amplitude and 7

• the driven levels can be self-monitored. 8

The boundary register cell shown in Figure 13 contains the drive capability needed to support the 9 transformation of an input pin to an ST-pin input pin. 10

Since this drive capability is only present during testing, that implies an ability to turn it off (for system 11 operation) that could be made controllable by a boundary register control cell, as allowed by permission 12 6.3.2.3a). While this adds cost in the form of a new boundary register cell, it adds flexibility for automatic 13 program generators that analyze PCA interconnections and create Boundary-Scan tests for them. 14

One way to add output drive capability to a system input pin is to implement the pin as a bidirectional pin, 15 where the system mode input to its control cell is fixed at the disabled state. Another is to eliminate the 16 control cell and only enable the driver when the EXTEST or SELECTIVE_TOGGLE instructions are 17 effective. Figure 14 shows options on how a normal input pin may be equipped for drive control when they 18 are designated as ST-pins. 19

NOTE—Cells BC_1, BC_2, BC_7 and BC_8 shown in Figure 14 are boundary register cells defined in IEEE Std 20 1149.1. 21 [Editor’s note: We will have to replace BC_1 (etc.) in Figure 14 and this note with “TH_1” (etc.) as 22 we refine this document. New cells introduced by this standard contain the extra logic to implement 23 selective toggle behavior, and while not important for ATPG of Boundary-Scan tests, are useful for 24 cueing synthesis tools for automated Boundary-Scan insertion.] 25

IEEE P1149.8.1/D0.7, August 2009



Figure 14 —Normal input pin and two implementations of an ST-pin input pin. 1

6.3.3 Single-ended bidirectional pins 2

6.3.3.1 Rules 3

a) Single-ended bidirectional pins shall obey the same rules as for single-ended output pins as given in 4 6.3.1.1 and shall consider the same recommendations given in 6.3.1.2. 5


Single-ended bidirectional pins already have the ability to control and observe their connected nodes, so for 7 the purpose of this standard, it is sufficient to support the drive capabilities required for 8 SELECTIVE_TOGGLE as given for single-ended output pins in 6.3.1. Also, these pins shall be able to 9 self-monitor their drivers to detect shorts to other nodes during EXTEST based testing. This implies a cell 10 design based on the BC_7 or BC_8 cells designs from IEEE Std 1149.1. 11

[Editor’s note: This will need updating when we define cells for this standard, probably named TH_7 12 and TH_8.] 13

14

6.3.4 Differential output pins 15

Differential drivers normally output two complementary signals that, when sensed by a capacitive sense 16 plate, may cancel almost completely, yielding no reliably discernable signal at the plate. However, if one 17 signal path has an open connection, then that path will have an attenuated signal and the sense plate will see 18 the signal from the opposite leg. The phase of the observed signal thus indicates the leg that is open. 19

For some defect cases, notably, a short across the two legs, or, opens on both legs, there will be little or no 20 observable signal at a sense plate. The driver is made self-monitoring and can thus detect shorts, and it can 21 also be operated in an unbalanced mode where the two legs are no longer complementary. This unbalanced 22

C U C U

BC_1 Cell BC_7 Cell

C U

BC_2 Cell

ST-pin Input Pin with control cellNormal Input Pin

C U

BC_8 Cell

ST-pin Input Pin

EXTEST

SELECTIVE_TOGGLE

IEEE P1149.8.1/D0.7, August 2009



mode provides a detectable signal when there are no defects present, and will provide a means of detecting 1 the case of both legs having open defects. 2

6.3.4.1 Rules 3

a) If a device contains differential ST-pin drivers, then there shall be at least one additional cell in the 4 boundary register which is designated as a balance/unbalance bit and be called a “balun” bit, and this 5 cell shall be denoted as “internal” in the BSDL description of the device boundary register. 6

b) When the SELECTIVE_TOGGLE instruction is in effect, all enabled differential drivers shall be 7 influenced by a balun bit value as follows: 8 1) If the balun bit is 0, then the differential driver shall operate normally with complementary 9

voltages appearing on the two legs. 10 2) If the balun bit is 1, then the differential driver shall operate in an unbalanced mode with the 11

voltage at the negative leg substantially tracking the voltage appearing at the positive leg. 12 NOTE—“Substantially tracking” means the waveforms seen at each pin are similar in shape but may differ in the 13 actual voltages produced. See the example shown in Figure 4 in 4.3.2. 14

c) When the SELECTIVE_TOGGLE instruction is in effect, the positive leg of an enabled differential 15 driver shall obey rules 6.3.1.1a) through e) given for single-ended outputs. 16

d) When the SELECTIVE_TOGGLE instruction is in effect, the negative leg of an enabled differential 17 driver shall either be complementary to the positive leg (balun = 0) or it shall substantially track the 18 positive leg (balun = 1). 19

e) When the EXTEST instruction is in effect, the states of the two differential pins shall be compared by 20 a hysteretic comparator and the digitized result captured by the boundary register cell that provides 21 data for the driver. 22

NOTE—This is a self-monitor concept for a differential pair. The hysteresis provides for a stable result when a dead 23 short appears across the two differential pins. 24

f) The hysteresis of the comparator shall be between 10 and 40 percent of driver’s normal voltage 25 swing. 26

[Editor’s note: the 10-40% figures are a rank guess on my part. We want to reject noise that may 27 make two shorted legs appear to be momentarily different. We should pick values that are easily 28 implemented.] 29

6.3.4.2 Permissions 30

a) More than one balun bit may be added to the boundary register by a designer as needed to alleviate 31 layout routing problems. 32


Figure 15 shows an example of a set of differential drivers that share an output enable cell and a balun cell. 34

35

36

37

IEEE P1149.8.1/D0.7, August 2009



Figure 15 : Differential drivers with enable control and balun cells. 1 The balun cell is an internal cell with no connection to the system logic. It may be located anywhere in the 2 boundary register that is convenient for signal distribution, and more balun cells can be added if needed. 3 All differential outputs that are ST-pins must be controlled by a balun cell somewhere in the boundary 4 register. 5

6.3.5 Differential input pins 6

6.3.5.1 Rules 7


6.4 Toggle Behavior for ST-pins 9

A clock signal named Toggle-TCK is used to trigger transition events on selected, enabled ST-pins. This 10 signal is generated by a set of decodes derived from the TAP state machine, TCK and the instruction 11 decoder. This signal can have a frequency derived from TCK under control of the toggle control register 12 content (see clause 7). The value stored in the toggle control register is a delay counter value that governs 13 the number of TCK falling edges that occur between enabled ST-pin transition events. This value may 14 range from 0 to 2N-1 where N is the number of bits in the toggle control register. Thus the maximum 15

Positive Leg

Negative LegData

Balun

C U

C U

C U

C U

C U

SystemLogic Balun Cell

(Internal)

Enable

C U

C U

ControlCell

IEEE P1149.8.1/D0.7, August 2009



frequency of ST-pin transitions is ½ TCK (for a delay count of 0) and correspondingly lower frequencies as 1 the delay count increases. 2

6.4.1 Rules 3

a) When the SELECTIVE_TOGGLE instruction is in effect, a Toggle-TCK signal that triggers 4 transition events on the selected, enabled ST-pin drivers shall be provided to all ST-pins. 5

b) The Toggle-TCK signal shall trigger a first transition event on the first falling edge of TCK after 6 entering the Run-Test/Idle TAP state. 7

c) Subsequent transition events shall be triggered only while the TAP remains in the Run-Test/Idle TAP 8 state. 9

d) The Toggle-TCK signal shall trigger a subsequent transition event when the number of falling TCK 10 edges that have occurred since the last transition event is equal to the number stored in the toggle 11 control register. 12

NOTE—These rules produce transitions on enabled ST-pins that satisfy requirements specified by rule 13 5.4.1g), parts 1), 2) and 3). 14


The following waveform diagrams show how enabled ST-pins toggle when the toggle control register is set 16 to 0, meaning no falling TCK edges are ignored; when the toggle control register is set to 1, meaning 17 exactly 1 falling TCK edge is ignored; and when the toggle control register is set to C meaning C falling 18 TCK edges are ignored, where 1 < C ≤ 2N-1. 19

In these diagrams the TAP state name (abbreviated) is indicated along with TCK at the top. Then a “Count” 20 of the number of skipped TCK falling edges is shown. The Toggle_Clk signal is shown next which, on 21 falling edges, triggers transitions of enabled ST-pin drivers. The bottom trace shows the state of an enabled 22 ST-pin driver and when it changes. 23

Figure 16 — Waveforms for delay count 0. 24 Figure 16 shows the case where the count of falling edges to ignore is 0. This results in enabled ST-pins 25 that change with frequency ½ TCK. In this example, the Run-Test/Idle TAP state was entered an even 26 number of times, so upon exiting that state, the toggling driver had returned to its initial state. If Run-27 Test/Idle had been entered an odd number of times, the final driver state would be inverted. 28

UDRE1DR RTI

Initial State

TCK

TAP State RTI RTI

Inverted State

Initial State

Inverted State

RTI SDRS CDR

Initial StateToggle Driver State

Toggle-Clk

Count 0 0 0 0 0 0 0

IEEE P1149.8.1/D0.7, August 2009



Figure 17 — Waveforms for delay count 1. 1 Figure 17 shows the case where the count of falling edges to ignore is 1. This results in enabled ST-pins 2 that change with frequency ¼ TCK. In this example, the driver was left in its inverted state after three 3 transitions. 4

Figure 18 — Waveforms for delay count C, where 1 < C ≤ 2N-1. 5 Figure 18 shows the case where the count of falling edges to ignore is C. Now C falling TCK edges are 6 ignored between ST-pin transitions. 7

With proper initialization of the toggle control register and choice of the number of TCK cycles spent in the 8 Run-Test/Idle state, this system can produce a step function, an impulse function with a width of C+1 TCK 9 cycles, or a specific frequency divided down from that of TCK, within the frequency resolution determined 10 by the choice of FMax and N. (See 7.4.) 11

[Editor’s note: No implementation example is given. Do we want to provide one, a’la my email of 12 6/23/2009 that showed up up-counter with equality checker?] 13

7. The Toggle Control register 14

A mandatory, toggle control register is provided as a target for the mandatory TOGGLE_SETUP 15 instruction (see 5.3). This register is used to control the behavior of the SELECTIVE_TOGGLE instruction 16 as described in 6.4. This register is required in addition to those registers (bypass, boundary-scan, and 17 optionally, the device identification register) prescribed by IEEE Std 1149.1. 18

[Editor’s note: The only control function now specified is the TCK delay counter.] 19

Count

SDRS CDRUDRE1DR RTI

Initial State

TCK

TAP State RTI

Inverted State

RTI RTI RTI RTI

Initial State Inverted StateToggle Driver State

Toggle_Clk

0 0 1 0 1 0 0

UDRE1DR RTI

Initial State

TCK

TAP State

Toggle Driver State

RTI RTI

Inverted State

RTI RTI

Initial StateInverted State

RTI RTI SDRS CDR

Toggle_Clk

Count 0 0 1 2 C-2 C-1 C 0 0

IEEE P1149.8.1/D0.7, August 2009



7.1 Rules 1

a) A data register named “toggle control” containing N bits (with N > 0) shall be provided. 2 b) The toggle control register shall load each bit with a ‘1’ on the rising edge of TCK in the Capture-DR 3

TAP controller state. 4 c) The toggle control register shall shift bits from TDI to TDO on rising edges of TCK in the Shift-DR 5

TAP controller state, when the TOGGLE_SETUP instruction is in effect. 6 NOTE— The TOGGLE_SETUP instruction is described in 5.3. 7

d) The toggle control register content shall be used to specify the delay between successive transition 8 events on enabled ST-pins when the SELECTIVE_TOGGLE instruction is in effect and when the 9 TAP is in the Run-Test/Idle state. 10

NOTE— This integer, between 0 and 2N-1, is loaded into delay counter after the issuance of each ST-pin toggle and 11 thus governs the delay (in TCK cycles) between all transition events when the SELECTIVE_TOGGLE instruction is in 12 effect. 13

e) The value of N shall be an integer greater than or equal to the base-2 logarithm of the quotient of FMax 14 divided by 8000, where FMax is the maximum TCK frequency (in hertz) supported by the design of the 15 device. 16

NOTE— The equation expressing this is: ⎡ ⎤)8000/(log2 MaxFN = 17

7.2 Permissions 18

a) The parallel hold portion of the toggle control register (if implemented) may be utilized in the design 19 of the delay counter circuitry provided in section 6.4. 20

7.3 Recommendations 21

a) The maximum TCK frequency (FMax) of the device should be greater than 1 megahertz. 22

7.4 Description 23

The toggle control register contains N bits placed between TDI and TDO when the TOGGLE_SETUP 24 instruction is in effect. This register captures a deterministic pattern (all ones) when passing through the 25 Capture-DR TAP controller state. These bits come out upon shifting in the Shift-DR TAP controller state, 26 while an N-bit integer is being placed in the toggle control register. This integer is then used as an upper 27 limit for a counter used to determine the number of falling TCK edges that are ignored until the next 28 transition event on currently selected ST-pins governed by the SELECTIVE_TOGGLE instruction. The all-29 one pattern can be observed on TDO during shifting to verify the existence of the toggle control register, 30 and it also serves as a default divider (2N-1) if shifting is skipped by passing around the Shift-DR state by 31 route of the Exit1-DR to Update-DR states. Details of the TCK divider are found in 6.4. 32

When a chain of devices must be used during a test, some devices may not be used for toggling signals (or 33 may not support the features of this standard). In this case, those devices will not have a toggle control 34 register set up during the test and would typically remain in BYPASS mode. Those devices that do need to 35 have the toggle control register set to specific patterns would capture the all-one pattern upon passing the 36 Capture-DR tap control state while those in BYPASS would capture ‘0’ bits. This allows a test algorithm 37 an opportunity to validate that the chained instruction registers are operating properly. 38

IEEE P1149.8.1/D0.7, August 2009



A test algorithm which sets a given TCK clock rate will then calculate a count integer that will achieve the 1 relatively longer time delay between transition events needed to satisfy the requirements of the capacitance 2 measurement system. The frequency F of pin toggling based on a divider integer C, where 0 ≤ C ≤ 2N-1, is: 3

F = TCK / (2*(C + 1)) 4

Rule 7.1e) assures that a toggling pin can achieve a frequency as low as 8 kilohertz from a TCK running at 5 the rated maximum for the device. The 8 kilohertz number is a legacy of capacitive opens testing metrology 6 systems that use 8 kilohertz stimulus sources. Recommendation 7.2a) gives a lower limit for TCK 7 frequency that could achieve an 8 kilohertz toggle rate at an ST-pin. At the low limit of 1 MHz, the count 8 would need to be 61 (requiring N = 6) and the toggle frequency achieved would be 8065 Hz. A count of 62 9 would produce a toggle frequency of 7937 Hz. The value of each count at this TCK rate is 128 hertz. For a 10 maximum TCK frequency of 20 MHz, a count of 1249 (requiring N = 11) would produce a toggle 11 frequency of exactly 8000 hertz, and a count of 1250 would produce 7994 hertz. The value of each count at 12 this TCK rate is 6 hertz. In general, for a given TCK and count C, the frequency resolution of one count 13 increment is (in hertz): 14

ΔFC, C+1 = TCK / (2C2 + 6C + 4) 15

Note for low values of C, the frequency resolution of each count may be quite large. 16

8. Conformance and documentation requirements 17

8.1 Conformance 18

8.1.1 Rules 19

a) A component conforming to this standard shall comply with all rules provided herein. 20 NOTE 1— Due to rule 5.1.1a), this also implies conformance with the rules set out in IEEE Std 1149.1. 21

NOTE 2— If compliance enable pins are present, the enabled state indicates compliance to all requirements of both 22 IEEE Std 1149.1 and this specification. See IEEE Std 1149.1-2001, section 4.8, Subordination of this standard within a 23 higher-level test strategy. 24


Conformance to the rules set out herein and in IEEE Std 1149.1 is essential for testing boards and other 26 assemblies containing interconnections, allowing manufacturing defects such as shorted or open solder 27 joints to be found and repaired before shipment. Conformance allows: 28

• IC vendors to provide testability features in a standardized way, so that each new IC design 29 does not need new engineering investment to provide testability. 30

• makers of Automatic Test Equipment to develop and continually refine standardized tools for 31 the automation of test development, test execution, and diagnosis of failures. 32

• end-users to develop test methodologies in a way that is both standard and in line with a 33 strategic direction, making full use of the automation provided by tools, to allow them to 34 produce very large and complex boards and systems more rapidly and efficiently. 35

IEEE P1149.8.1/D0.7, August 2009



8.2 Documentation 1

Because adherence to this standard implies adherence to IEEE Std 1149.1, all devices conforming to this 2 standard shall have a description supplied in Boundary-Scan Description Language (BSDL) provided with 3 IEEE Std 1149.1. 4

8.2.1 Rules 5

a) A component conforming to this standard shall be documented with a BSDL description. 6 NOTE—See IEEE Std 1149.1 for a description of IEEE BSDL. The precursor to IEEE BSDL developed in 1990 7 cannot be used for documentation because it does not support the concept of “BSDL Extensions.” 8

b) When the SELECTIVE_TOGGLE instruction is implemented in a component, then this instruction 9 shall have both the register relationship and optional provisions documented via the syntax provided 10 by BSDL and the BSDL extension provided by this standard. 11

NOTE— New BSDL syntax (contained within a “BSDL extension”) for describing concepts and structures introduced 12 by this standard are given in 8.4. A BSDL extension is a mechanism provided by IEEE Std 1149.1-2001 (see User 13 extensions to BSDL, B.8.17) which allows proprietary syntax to be provided that will allow tools to work that are 14 unaware of this syntax. 15

c) Prime and second source devices shall have nominally identical implementations of publicly 16 accessible test circuitry, with the sole exception of the device identification code. 17

NOTE—This includes boundary register cell ordering and the nominal values of analog parameters such as voltage 18 levels of output transitions. 19

d) Other properties of a device shall be documented by the manufacturer, including: 20 1) <property 1> 21 2) <property 2> 22 3) <property 3> 23

NOTE— In addition, the manufacturer would also specify typical electrical parameters for device pins, including TAP 24 signal voltage level requirements, and the power requirements of the device. 25


<Fill in BSDL body detail here.> 27

8.3 BSDL package for Selective Toggle description (STD_1149_8_1_2009) 28

29

8.4 BSDL extension structure 30

31

IEEE P1149.8.1/D0.7, August 2009



8.5 BSDL attribute definitions 1

2

8.6 Example BSDL 3

4

IEEE P1149.8.1/D0.7, August 2009



Annex A 1

(informative) 2

Unpowered Testing for Open Connections on Printed Circuit Assemblies 3

A.1 Problem Description 4

The problem space described here is that of finding defects in printed circuit assemblies. This type of 5 testing is referred to as “Loaded Board Test” and is typically the first type of testing performed on loaded 6 circuit boards after they come out of the attachment step (typically soldering). Loaded board test focuses on 7 finding “manufacturing defects”. One class of such defects results in open connections between board 8 signals and the intended connection points of various components. Another class is that of shorts (unwanted 9 connectivity) between pins.) 10

There are several types of test approaches to discovering manufacturing defects such that remedial action 11 can be taken. Such actions include repair of the board, discarding the board, and process monitoring and 12 control. A common type of test used heavily across the industry is known as “In-Circuit Test” (ICT). It uses 13 a “bed-of-nails” access technology to provide access to board signals for test purposes. With ICT 14 equipment, there come a variety of testing tools that can be focused on finding the relevant defects that may 15 occur in manufacturing. These tools typically set up “stimulus experiments” that are monitored by other 16 ICT resources to judge whether any defects are present in the area of focus. Many such experiments are 17 used in concert to test an entire board of arbitrary complexity. The next subclauses describe one type of test 18 technology, invented over 15 years ago and known in industry as “TestJet3 ®”. This technology is 19 sometimes described generically as “unpowered capacitive opens detection”. 20

A.2 Unpowered Capacitive Opens Detection 21

Unpowered capacitive opens detection technology is aimed at finding open solder joints between printed 22 circuit assemblies (PCA) and devices mounted on the board. Considered here is one class4 of device: 23 connectors. A connector on a board is intended (ultimately) to mate with another connector on some other 24 assembly such as a plug-in daughter board, a memory or I/O card, etc. However, during manufacturing 25 board test, the connector is present, but the mating assembly is not present. Thus there are connections from 26 board signals to the vacant connector, but there is nothing active in the connector itself which can be used 27 for testing. 28

One approach to testing this connector for opens between it and the board is to plug in a mating connector 29 that has additional wiring and/or other resources to support testing. The problem with this is one of 30 practicality, it takes time to plug in this mating connector, and if the board being tested has numerous 31 connectors, it can become time consuming and error-prone to do this. There are also maintenance issues 32 with these mating units. Thus this approach has limited viability. 33

The heart of this problem of connector testing is that of sensing. Given access to the board’s nodes via the 34 bed-of-nails fixture, how can open solder joints between the connector and board be detected? The answer 35 is to sense whether signals on the board can get into the connector. The mating connector idea supports 36

3 TestJet® is a registered trademark of Agilent Technologies. Any trademarks referenced in this document are the property of their respective owners. 4 Many other types of device are also testable with this technology, such as sockets, termination network packages, Integrated Circuits, etc. This example is simple and illustrative, and represents a widespread problem across industry.

IEEE P1149.8.1/D0.7, August 2009



this, but is not generally practical. Another is to think about an alternative way of sensing the presence of 1 these signals. 2

The unpowered capacitive opens detection idea does this with capacitive sensing. A small signal sensor is 3 mounted over the open mouth of the connector, in close physical proximity, but not actually inserted into it 4 as shown in Figure A.1. 5

Figure A.1— BGA Connector and sense plate, with In-Circuit Test access to board signals. 6 The sense plate has a conductor that is thus hovering over the connector, and in close proximity to the 7 topmost tip of each connector pin, of which there may be hundreds. There is a small capacitive coupling 8 between this sense plate and the tip of each connector pin. The In-Circuit tester has access to each board 9 node that is attached (via solder) to the connector. It can then ground all but one of these pins and stimulate 10 one in particular with an AC signal. This AC signal couples into the sense plate with a magnitude 11 proportional to capacitance, where a local buffer amplifies the signal. This buffered signal is passed back to 12 the ICT system which measures the capacitance of the coupling. An equivalent circuit of this measurement 13 is shown in Figure A.2. The measured capacitance in the defect-free case is called CS and it can be 14 compared to a known-good expected value. In the earlier history of this measurement technology, typical 15 values of CS were greater than 100 femtofarads (fF). This was due to larger geometries of devices in the 16 past. With the relentless progress in miniaturization, these values may now be much lower, with many less 17 than 40 fF. 18

SenseplateBuffer

Signal(to Tester)

PC Board

Ball Connections

In-Circuit access

Tester AC Source stimulates one pin, all others are grounded

Test access pad

Vacant Connector

(internal conductors)

IEEE P1149.8.1/D0.7, August 2009



Figure A.2— An equivalent circuit of a capacitance measurement in the defect-free case. 1 In the event of an open defect that disconnects the connector pin from the board, there is an equivalent 2 circuit seen in Figure A.3. Here there is a series of two capacitors, the original CS and a new one formed by 3 the board’s solder pad and the connector’s solder point, which is labeled CO. The series combination of 4 capacitances is lower in value than CS was by itself. It is not unusual to see defective pin measurement 5 values that are less than 5 fF. If CS for this measurement is 40 fF, then solving for CO gives about 6 fF of 6 open joint capacitance. 7

Figure A.3— An equivalent circuit of a capacitance measurement when the stimulated pin 8 is open. 9

As long as the change in measured capacitance is greater than the measurement uncertainty in the detector, 10 open joints can be detected reliably. 11

Some notes about the AC source are in order. It is typically a sinusoid, with no DC offset, with a magnitude 12 of 400 millivolts or less. This prevents current flow in other devices on the same board net that are 13 connected to it which may contain semiconductor junctions (typically ESD protection diodes), because a 14 voltage 200 millivolts above or below ground will not turn these on. The frequency of the source may be 15 relatively low, for example, around 8 kHz. Higher frequencies can begin to introduce other problems with 16 crosstalk coupling or attenuation in the bed-of-nails fixture. 17

The original capacitive opens detection technique is an unpowered test technology, meaning it is used with 18 the board in an unpowered state. This also allows the connection of the other nodes to ground without fear 19 of shorting critical signals or power leads. This “guarding” of the other signals helps quiet the board for this 20 fairly sensitive measurement. Notice also that because of the bed-of-nails access, shorts between these 21

AC Detector

AC Source

Defect-Free ConnectionSense Plate

Connector PinCS

Measured Capacitance = CS

AC Detector

AC Source

With Open Solder Defect

Sense Plate

Connector PinConnector Lead

Solder Pad

CS

CO

Measured Capacitance =

CS CO

CS + CO

IEEE P1149.8.1/D0.7, August 2009



nodes are detectable by a “shorts test” that examines each node for independence from the others. This 1 important class of defects is usually detected in a different phase of testing and they are assumed to be 2 absent at the time of unpowered opens testing. 3

It is important to note that there are additional defect coverage opportunities presented by capacitive opens 4 test. Figure A.4 shows a case where, due to the positioning of a tester nail, it is possible to detect several 5 open solder joints along the path between the nail and the sensed connector, and also if the resistor R is 6 present. The value of R is unlikely to interfere with the stimulus of the connector pin, unless it is a very 7 large resistance such as 10 Megohms or larger. On typical boards, it would likely be a series termination 8 resistor with a value of 50 to 100 ohms. 9

Figure A.4—Three solder joints and the presence of resistor R are tested. 10 The sense plate is typically an inexpensive piece of simple, two-sided printed circuit board stock, cut to fit 11 the general outline of the device being sensed. The top side is where a buffer amplifier is mounted, and is 12 also a ground plane. The bottom side is positioned over the device being sensed and its conductive plate 13 forms the top half of the sensed capacitance. An example of a sense plate/buffer assembly is shown in 14 Figure A.5. 15

Figure A.5—Top and side views of a sense plate and buffer amplifier. 16 Often, a device to be sensed is visible on the top side of a board. The sense plate/buffer assembly is 17 suspended over the target device by the two spring-loaded supports attached to the top portion of the test 18

Board

ConnectorR

Soldered Connections

Test Pad

Tester Nail

Printed Trace

Sense Plate

Sense Plate

(Top View)(Side View)

Buffer Amplifier

Spring-loaded Supports

IEEE P1149.8.1/D0.7, August 2009



fixture. As this portion is lowered into position the spring-loaded supports compress slightly as the sense 1 plate comes into position over the target device. Figure A.6 shows an example of a sense plate/buffer 2 assembly inside a fixture, contacting a target device. The two spring-loaded supports also supply power and 3 retrieve sense information from the buffer/amplifier. 4

Figure A.6—A sense plate/buffer assembly inside a fixture in testing position. 5 If the target device is located on the bottom of the board, then the sense plate is mounted in a milled recess 6 in the test fixture board support platen. 7

A.3 Replacing Tester AC Stimulus with Boundary-Scan Stimulus 8

As noted in clause 4, it is increasingly difficult to gain electrical access to test points on a board to be 9 tested. Capacitive opens test is a “forgiving” technology in that (unlike some other test technologies) the 10 loss of some test point access causes a linear degradation in defect coverage for opens. However, as access 11 becomes increasingly difficult, the loss of coverage for opens has become a major concern. 12

The question becomes how to substitute a “limited access” technology for the bed-of-nails and use it to 13 perform guarding and stimulation needed for the capacitive technique. The answer is that IEEE 1149.1 14 Boundary-Scan can be used for this. Boundary-Scan drivers under the control of the EXTEST instruction 15 can be used to hold most nodes steady while stimulating just one. This differs from conventional capacitive 16 opens testing in certain ways: first, the native drive levels of a driver are being used which may be more or 17 less than the 200 millivolts used in the past. Second, those signals doing “guard” functions are not all 18 grounded as in the past, but held to some logic value which is not necessarily ground (0 volts). Experiments 19 have shown these differences are not problematic. The measurement system is AC coupled at the sense 20 plate, so grounded guards are not important; they just need to be held constant. (There is negligible current 21

Board under test

Mounting block in top cover Buffer

Spring postsSense Plate

DUT

IEEE P1149.8.1/D0.7, August 2009



flow in the guarded pins.) The act of guarding can be done with either high or low logic values, and since 1 signals are not being connected together by relays, they can have different states. Since the power is applied 2 when using Boundary-Scan, conventional guarding with relays would not be possible anyway due to that 3 shorting many active signals together. The change in stimulus signal strength can also be accommodated. 4 The final big difference is that power must be applied to the board such that the Boundary-Scan facilities 5 become active. Thus extraneous signals may be present that may add noise into the capacitve 6 measurements. 7

The fact that access have been lost, but replaced with Boundary-Scan capability, means that shorts between 8 inaccessible nodes that are both driven and observed by Boundary-Scan can still be detected. 9

A capacitive opens test implementation that uses Boundary-Scan stimulation has been demonstrated in a 10 commercial ICT system, testing real production boards. However, there are some issues that can cause loss 11 of defect coverage. 12

A.4 Coverage Deficiencies 13

In Figure A.7 there is a Boundary-Scan IC (U1) that is connected to the pins of a connector, but not all 14 Boundary-Scan pins are equivalent. Some of U1’s pins have drivers and can be used (when EXTEST is in 15 effect) to support capacitive opens measurements. However, some of U1’s pins are only capable of 16 receiving signals and thus cannot either guard (hold the associated signal at a fixed potential) or stimulate 17 their associated signals. Opens on these signals will not be covered by capacitive opens test based on 18 Boundary-Scan resources in U1. Shorts between these signals are also not detectable by conventional 19 Boundary-Scan tests since their states are not controllable. 20

A second problem arises when a Boundary Register cell supplies data to a differential driver, rather than a 21 single-ended driver. This will mean that two, logically complementary signals are driven to the connector. 22 When one goes from low-to-high, the other signal will move high-to-low in (near) perfect symmetry. This 23 means there are canceling signals at the sense plate and, the sense plate buffer sees no signal at all in the 24 defect-free case. If one pin is open, there will no longer be signal cancellation at the sense plate and the 25 defect can be seen. However, there are other defects (for example, both pins being open) that cannot be 26 seen. In general it is not a good testing practice to have the lack of signal indicate a passing result. 27

Finally, to emulate an AC stimulus frequency, for example, 8 kHz, it is necessary to update the content of 28 the Boundary Register rapidly enough (with EXTEST in effect) to cause a given pin to move at this 29 frequency. But, the number of (combined) Boundary Register cells in the chain of devices that must be 30 shifted will effectively form a frequency divider on TCK. If this divider ratio is high, there may be practical 31 problems creating the target stimulus frequency. This could prevent the technique from being applicable at 32 all in some cases. 33

IEEE P1149.8.1/D0.7, August 2009



Figure A.7— A Boundary-Scan device that drives and observes signals that go to a 1 connector. 2

It is the mission of this standard to provide solutions for these problems, such that maximum coverage is 3 achievable in practice. This will allow the retention of significant test coverage as electrical access with 4 conventional bed-of-nails declines. 5

TDITCKTMS

TDO

Vacant Connector

BScan Device U1

TDI TDOTCK TMS

Bscan Driven Bscan Observed

Documents

IEEE P1149.8.1™/D0.7 Draft Standard for Boundary-Scan ...btw.tttc-events.org/material/BTW09/Presentations/Session 3.2.pdf2 Draft Standard for Boundary-Scan-3 Based Stimulus of Interconnections