Imperial War Museum, London

Matt is busy looking at tanks today – but wants me to report what he’s been up to...

Firmware: The Good

Made a block for reading the SHT71 Very similar to I2C, so I extended it

Mainly just provides a means talking to the bus

all chip specific stuff needs to done in software As such should handle all I2C devices Also has room to add other protocols

will very shortly be adding the SPi "protocol”

Firmware: The Bad

• Recent firmware seems to be less robust– may be due to "optimisations" in the deserialiser– problem visible during long scans in B180– hard to diagnose

• Latest firmware should improve things– Need to add a "loop-back" test that forces these errors

• BUT:

Firmware: The UglyThe old "CRC status = 0" on configure has re-appeared.- Very odd problem where the Xilinx tools make a file for

the FPGA that doesn't work!- VHDL code dependent(!)

- Changes to the source code can remove problem– Don't know what is making the difference though.

-Currently if I compile with stavelet streams in the build

I get the problem.->1 day spent trying different options and roll-backs

- nothing makes it better-Even tried the newest ISE - v14.1.

- Have seen this problem since v10, so wasn't optimistic- It's likely they Xilinx stopped dev of the Virtex4 compiler then anyway

-Also realised it's not a CRC error really, - it's the FPGA status register reading back all 1's after configuration- something is going very wrong.

- The web has been scoured - no answers!

What I’ve done This Week

Instead of testing the CofM Stavelet

Peter W Phillips, RAL

Stave(let) DCS

• Before running a stave(let) at lower temperatures– Need to know RH of environment– Need to know temperatures of coldest point in the

system• Armed with this data, we can verify that the

stave(let) remains above the dewpoint at all times– Or at least we know if it doesn’t!

• Cue the Sensirion Mezzanine Card!

Sensirion SHT71 Sensorwith digital RH & T output

Mount on IN pipe Mount on OUT pipe

Environmental Sensor:Mount at far end of stave(let)

40 WAY 0.1” pitch SAMTECBottom side mates with EoSTop side mates with cable

Pipes should be the coldest points:If we’re OK there, we’re OK!

More details• Each sensor shares an I2C bus with one of the EoS ADCs

– Although SHT71 are serial, rather than I2C devices, this should still work• Firmware from Matt nearly ready to support this

– Have read SHT71 using HSIO, but not yet in parallel with ADC (will check on Monday, should work according to specs)

• Assuming this works OK– Will procure 10 PCBs and components for two prototypes

• Cheap as chips: no solder resist

• Assuming these work OK– Will make one for each stave(let) as a permanent fit

• Although may provide one SHT71 only– Could be mounted on Strips Interface board for use with single modules

• Likely that the Cambridge interlock will provide similar functionality in time

• Have checked with Martin– Height is no problem for assembly tooling

Yet More details

Adding sensors is one thing:What are you going to do with them?• Can have two applications monitoring HSIO packets

– Can have two SCTDAQs if you like• Plan to have standalone “mini dcs” program

monitoring and plotting DCS data and (potentially) making interlock decisions– Will probably be ROOT based in the first instance– May look at PVSS later (ATLAS compatibility)– Both approaches independent of SCTDAQ

Anything else?

• Do we want anything else of this mezzanine card?– Extra ADC?– 3V3 monitoring?– One wire breakout?– A “cheap” temperature sensor on board?

• SHT71 ~ £18 each• AD7416 ~ £1 each

Actually I did run one stavelet test this week...

• CM removal capacitors initially fitted with 6 bonds/pad• Ashley suggested the number of bonds be increased to reduce the

series inductance of this link• Increased the number of bonds from 6 to 18

– No difference to ENC– No difference to DTN

• I think this says that impedances elsewhere in the referencing system dominate within the CM removal path– Notably the (4 bonds/pad) ties between the hybrids and the referencing plane

• Indicates that, for 130nm, a single hybrid would be best, with the “symmetric pair” of hybrids linked by copper tabs coming a close second.– But I think we’d figured that out already...

Implementation