Implementing Bead Probe Technology for

In-Circuit Test: A Case Study

Mike Farrell Agilent Technologies Loveland, Colorado

michael_farrell at agilent dot com

Glen Leinbach Caber Contacts, LLC Fort Collins, Colorado

glen_leinbach at comcast dot net

Copyright © 2007 IEEE. Reprinted from 2007 ITC International Test Conference, Paper 18.1 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Agilent Technologies' products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions at ieee dot org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Paper 18.1 INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00©2007 IEEE

Implementing Bead Probe Technology for In-Circuit Test: A Case Study

Mike Farrell Glen Leinbach Agilent Technologies Caber Contacts, LLC Loveland, Colorado Fort Collins, Colorado michael_farrell at agilent dot com glen_leinbach at comcast dot net 970-679-5526 970-217-1051

Abstract

A major OEM implements bead probe technology on a new design to gain test access and coverage of high-speed circuits. Conventional probing techniques are incompatible with the density and speed requirements of the board. The experiences of a first implementation of bead probe technology are discussed here, including CAD issues at board layout, test fixture construction and debug, soldering process difficulties, and test probing problems during the ramp to high- volume production.

Introduction

A major OEM was developing a high-volume graphics board which used DDR21 technology. Product quality would be assured by a combination of in-circuit test (ICT) and functional test. High-speed busses connecting the two DDR2 memory devices, a DDR2 DIMM connector, and the controller ASIC and other components could not accommodate conventional ICT probe pads due to signal integrity requirements and layout limitations. This would result in a significant test coverage reduction of the board, specifically the DDR2 section. No test access to the DDR2 section at ICT meant testing this section at functional test only, complicating component level diagnosis and increasing repair costs in manufacturing.

Conventional ICT Probing

The established method of probing boards at ICT has been complicated by the industry’s transition to lead-free processes. Most manufacturers already used a “no-clean” process, where all solder flux residue is left on the board covering the solder joints.

Switching to lead-free solder and its higher soldering temperatures caused flux breakdown, increas-ing solder defect rates such as opens and poor wetting. Many manufacturers switched to higher flux content solder pastes to reduce defects by improving the flow

1 Double-data-rate two synchronous dynamic random access memory

and wetting of SAC2 solders. The additional flux residue left on test points plus the poorer wetting characteristics of lead-free solder have required the use of some best practices to assure reliable probe contact at ICT. [Rein05]

Bare copper (SMOBC-OSP3) test pads and vias make unreliable test contacts due to the buildup of copper oxide on the surface. The thin copper will not prevent board damage during multiple probings. Solder-coated vias are not recommended for probing since solder paste applied to them often runs down into the hole, resulting in the probe contacting either a flux-filled hole or a flux-covered annular copper ring around the hole. Neither results in reliable contact.

Solid copper test pads covered with reflowed solder paste, or loaded and soldered through-hole leads, are the only recommendation for use as test points. [Rein06]

Test Access vs. Test Coverage

Although the terms are often used interchangeably, in this paper “test access” is defined as electrical access to a circuit node for testing. “Test coverage” is defined as the ability to electrically test the board’s components. Improving test access is usually a part of improving test coverage, but other factors play a part in test coverage.

On a previous board similar to this design, test access using conventional probing technology also was not able to test the DDR2 section of the board and DIMM connector, resulting in only about 55 percent test coverage at ICT through direct and indirect test methods. The DDR2 section of the controlling ASIC and the DDR2 memory devices were tested at functional test only. Defects were difficult and expensive to isolate. Also, pull-up and pull-down resistors and capacitors associated with the DDR2 section could not be tested at functional test. 2 Tin(Sn)-silver(Ag)-copper(Cu) lead-free solders 3 Solder Mask On Bare Copper with Organic Solderablility Protection: Provides a solderable finish to the PCB pads and through holes.

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Alternative test methods such as AOI, X-Ray, and visual inspection were options to increase the test coverage of the DDR2 section of the board, but the OEM wanted to use the existing in-circuit test process if possible and not add another step to the manufacturing process.

Implementation

This project was selected by the OEM to conduct an opportunistic experiment: Implement Agilent Bead Probe Technology (ABPT) [Park04], [Park05] [DoGr06] in the DDR2 section of the board to increase test access. The additional test access to previously inaccessible nodes should increase the board’s test coverage, driving yield improvements at the down-stream steps of functional test and final assembly. If yields of this board improved, bead probe technology would then be implemented on future designs.

This product is a high-volume graphics formatter board. It uses SMOBC-OSP metallization and is assembled in a no-clean lead-free process.

Board Layout

The first step in the process was to develop a layout component (test attribute) for the CAD design system for a bead probe test access point. The designers worked with Agilent’s bead probe experts to develop a bead probe test geometry containing the size and shape for the apertures in the solder mask and in the solder paste stencil which would be compatible with 4-mil-wide traces. The resulting geometry was an obround opening in the solder mask, providing a test pad 20 mils long on a 4-mil trace on which to build a bead probe. The OEM’s standard layout rules which had been established for test vias and test pads were used to place the bead probe test access points on the board. It was jointly decided by the OEM and Agilent to implement bead probe test access only on the DDR2 section and the USB 2.0 section where it was impractical to place conventional test pads. (Figure 1)

Figure 1: Six bead probe locations on DDR2 bus on bare board.

The layout designer assigned the test attribute to the bead probe locations. The derived files from the CAD used for test development show the test access points

by node name. The test access points information contains the X-Y location, the geometry type (through-hole pin, solid pad, via, bead probe), and the side of the board (top or bottom) for the test access point. This information was instrumental in ensuring that bead probe access points were limited to nodes in the DDR2 and USB sections. Also, since the bead probe geometry was identified as a via due to CAD system limitations, it was possible that the test access location could appear as a possible access point on both the top and bottom of the board when the CAD was translated. It was imperative to ensure that the translation process provided the correct side of the board on which each bead probe access point was located. Until the translation process was validated, a manual review of the translated data and CAD was required to ensure that bead probe test access points were assigned to the correct side of the board. In some cases, this required modification of the translation software.

Verification Review

Once the layout of the product was complete, the CAD was reviewed for the following issues:

• Verifying that the resulting board_xy file (used to construct the in-circuit test fixture) contained the bead probe locations.

• Determining which nodes used bead probe test access points and ensuring that only the DDR2 and USB 2.0 sections of the board used bead probe test access.

• Ensuring that the resulting board_xy file correctly identified the placement of the bead probe on either the top or bottom of the board.

During the test access review, the following prob-lems were discovered:

Layout Driven Problems

• The first problem found was that the bead probe locations were not being translated over to the board_xy file. The problem was that bead probe locations were identified in the CAD data file as vias with a 2-mil pad. The CAD translation has the option of setting the minimum acceptable via pad size. Changing the acceptable via pad size to match the bead probe geometry fixed this problem.

• The next problem was related to the first: The bead probe locations were identified as accessible from both the top and bottom of the board because they had been interpreted as vias in the CAD data file. The CAD translation software had an option to only allow test access to the side of the board identified in the CAD data file for

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each individual via. Turning on this feature cor-rected the problem.

• One of the common problems found during the test access review was that some bead probes had been placed too close to components. With stan-dard test access points such as test vias and solid test pads, the designer has standard tools to help ensure that proper spacings and keepouts are maintained. Additionally, the diameter of a con-ventional test pad is larger than that of its test probe so the probe will never hit the component body or leads. However, the size of a bead probe is very small and the diameter of the flat face of the test probe is larger. A bead can be placed so close to a component that the flat-faced probe may hit the body or leads of the component. The Agilent 3070 software has a tool to help remove a test point that is either under or too close to a component. It relies on the component outline being correct in the board_xy file.

The final board design had 148 nodes that used bead probe test access locations. The additional test access to these nodes allowed testing the DDR2 section of the board: Two DDR2 memory devices, the DDR2 DIMM connector, associated resistors and capacitors, and the DDR2 section of the ASIC. The added test access of the 148 nodes increased the board’s test access from 46 percent to 70 percent of circuit nodes. Test coverage prior to adding test access to the DDR2 section was approximately 45 percent. This additional test access improved the total test coverage for the board from 45 percent to 85 percent: a significant increase.

Figure 2: Twin, dual-well ICT fixture for testing four boards

The ICT Fixture

Building the in-circuit test fixture was a straight-forward process. New probes designed by Everett Charles Technologies (ECT) for BPT (Bead Probe Test) were used. These were headless flat-faced probes

with the same diameter as the probe shaft. The probe face is smooth. The fixture was a dual-well vacuum box fixture with top and bottom side probing which can test four boards at a time. (Figure 2)

For standard test access, 8-ounce probes were used. For bead probe locations, 6-ounce probes were used. The only issue was that the fixture vendor used sharp chisel probes in some of the bead probe locations. These were replaced with flat-faced probes during fixture debug. (Figure 3)

Figure 3: Close-up of ICT probes. Red = standard chisel probe. Blue = .100” spacing flat-faced probes for BPT. Green = .075” spacing flat-faced probes for BPT

Fixture Cost

Fixture cost for adding top side probing to this four-board fixture added less than $5,000 to the cost of the fixture, but this one-time cost is outweighed by the increase in test coverage in the high-speed areas of the board. If double-sided probing was already required for this board, the additional cost to add bead probes would have been negligible. Fixture Debug After receiving the in-circuit fixture, debugging and testing of the in-circuit program was done with five prototype boards built for the OEM by a contract manufacturer (CM) in the US. The bead probe locations were examined with a microscope. The beads were well formed and flux residue was minimal. The bead probe locations performed well with good electrical contact. (Figure 4)

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Figure 4: Nine bead probes on the DDR2 bus.

Debugging and testing of the DDR2 section of the board where bead probes were used went well. There were no noticeable differences between the tests using standard test access and bead probes. The presence of bead probes allowed the direct debugging of a DDR2 digital test model and also allowed testing the DDR2 DIMM connector using TestJet/VTEP. Functional test did not cover the DIMM connector.

Bead Probe Durability

On the top side of some of the boards used for debugging the test, boards several beads had been flattened. It was not known if being probed multiple times was damaging the beads or there was a problem with the ICT fixture (Figure 5).

. Figure 5: Beads crushed during test debug.

To determine the durability of bead probes during multiple test actuations, a single board was pulled down on the vacuum-actuated ICT fixture over 300 times. Photomicrographs were taken of bead probes several times during the test (Figure 6.)

It was observed that the deformation (flattening) of the beads increased with the number of probings. This implied that the action of the test probe on the bead probe involved some kind of wiping or rolling action, and not just simple orthogonal pressure. This action could improve probe contact by displacing flux residues Note in Figure 6 the “fuzzy” area of flux residue around the bead.

Figure 6: Deformation of a single bottom-side bead probe after multiple probings. The number of probe cycles is shown in yellow.

This test also implied that since the bead probe was still nominally shaped after 50 to 100 cycles, the problem of crushed beads was due to a fixture problem..

To determine if a wiping action actually occurred, a test bed was assembled using a single flat faced probe and a small test board with a bead probe mounted on a vise (Figure 7).

Figure 7: Flat faced probe (right) and test board with bead probe (right) mounted on test bed. Arrows indicate direction of travel of probe.

The vise pressed the probe onto the bead probe and released it at low speed (Figure 8.)

Figure 8: Flat faced probe coming down on bead probe (left) and in contact with bead probe (right.)

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High magnification video was also taken and analyzed. As the flat-faced probe began its release, it slightly but visibly wiped across the face of the bead probe, confirming the theory about a wiping action.

It was then found that the original cause of the crushed beads was that the probes in the ICT fixture had not been completely seated, resulting in the probe running out of travel and bottoming out. This put very large forces on the bead probes, crushing them.

The First Large Prototype Build

For the prototype build, the CM moved the product to a high-volume facility offshore. The OEM made minor modifications to the board layout, and the fixture and test suites were updated. Over 600 boards were built by this CM’s high volume offshore facility and sent to the Agilent Loveland facility for test.

These boards had major probe contact problems. A visual review of the bead probe locations using a microscope found the following solder problems with the bead probe sites (Figure 9):

• No solder • Insufficient solder • Large amounts of flux residue • Poor wetting

Figure 9: One acceptable bead probe (top left), one with insufficient solder (top center), one with poor wetting (lower right) and two with no solder at all.

There were also areas on this board unrelated to bead probes which exhibited missing and insufficient solder, indicating that the soldering problems may not have been unique to bead probes. (Figure 10)

Contact issues were a major problem in testing the 600+ boards. To resolve the contact issue for this batch of boards, the test plan was modified to first cycle the vacuum 10 times and then run the probe-contact test. If a board would then pass the pins contact test, the in-circuit test was allowed to continue.

Figure 10: Missing solder on unloaded resistor pack land patterns.

If the board failed pins test, it was put aside and tested later. Some of the boards that passed the pins contact tests had failures during unpowered analog measurement test, such as resistors reading high and capacitors measuring high or missing. The boundary-scan test for the DDR2 section of the ASIC also failed intermittently. Boards were retested until they passed or a real failure was found. Boards that did not pass pins test after cycling the fixture 10 times were retested. If they did not pass after a number of tries, the test suite was reduced to ensure that there were no shorts, that the major power devices had been tested and that the EEPROM was programmed. Boards with real failures were tagged. About ten of the 600+ boards were reviewed under a microscope by an SMT process engineer to determine probable causes of the soldering problems. A report was generated and communicated to the OEM and the CM.

After testing the 600+ prototype boards and dis-cussing the results with the OEM, two things became apparent: The high-volume CM may not have known about the bead probes in general or about the experiment with this board. Also, there had been high turnover of new product introduction (NPI) engineers covering this project leading to possible communication problems.

The OEM then rolled the board design. A number of the resistor packs that had provided serial termination to the DDR2 DIMM connector were eliminated. The ICT fixture and program were modified to accommodate the design change. The OEM worked with the high-volume CM’s engineers to ensure that they understood bead probes. An Agilent application engineer (AE) from the Loveland facility visited the high-volume CM to discuss bead probe technology and its uses in future products. The AE recommended adding automated optical inspection (AOI) to monitor the application of solder to the bead probe locations,

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and recommended exploring methods to reduce flux residue on the bead probe locations. The AE learned that the CM had used at least two different stencils: One used the recommended diamond-shaped apertures for bead probe locations, and the other used circular apertures. At the time of this publication the results comparing their performance were not complete.

Second Large Prototype Run

The high-volume CM built the next run of prototype boards and paid closer attention to the bead probe quality. (Figure 11)

Figure 11: Two well-formed bead probes after in-circuit testing.

Approximately 275 boards were sent to the Agilent Loveland facility for testing. There were five variations of the board using different component loading options. Test engineers in Loveland suspect that the two paste stencils were divided between different versions of boards and are awaiting confirmation from the OEM. Depending on which version of board was tested, the first-pass yield for pins contact test (where pin contact integrity is verified) was between 45% and 80%. Testing on this batch was much smoother and quicker. There were limited cases where a small number of bead probe locations had minimal solder, mainly around the two USB connectors. Boards that failed the pins contact test usually would pass after repeated (between 2 and 15) cycles of activating the vacuum fixture. The SMT process engineer again reviewed about ten boards from this build and generated a report. The flux residue was still a potential problem, although it had been reduced from the previous build. The OEM is not sure if the high-volume CM will be able to reduce the amount of flux residue any further. (Figure 12)

Figure 12: Single bead probe at high magnification showing flux residue.

Early Production: The First Run

The first production run again exhibited considerable bead probe contact problems at ICT. This time the first-pass yield at pins contact test fell to only about 35 percent. To do a quick check to see if there was solder flux residue on the bead probes preventing contact, the engineer lightly rubbed the top and bottom surfaces of the boards while wearing an ESD-safe cotton glove. Upon testing, the yield for pins contact test rose to almost 100 percent. This indicated that the problem was probably flux residue and not presence of a harder oxide or a problem with the fixture. Research indicated that the lead-free SAC solder paste used was a standard formulation from a leading solder paste manufacturer. This manufacturer also offers the same paste formulation in a version designed to “offer increased in-circuit pin test yields.” Most leading solder paste manufacturers also offer similar products.

Early Production: The Second Run

For a solder paste to be compatible with in-circuit probe testing, any flux residue left on the bead probes and conventional test pads should flake away during probing (Figure 13) or be soft enough to allow good contact.

Figure 13: SEM images show unprobed and probed beads. Note flux flaked away from probed bead.

For the second run, the solder paste manufacturer’s “in-circuit test friendly” formulation of solder paste was used. Upon microscopic examination of boards from both batches, differences in the properties of the flux

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residues were apparent. A small needle probe was used to scrape the residue along the side of several bead probes and larger pads. Residue on boards from the first run was comparatively gummy and waxy, much like candle wax. It was easy to scrape a hard, curl-shaped flake of this residue. (Figure 14)

Figure 14: Large flake of flux residue on board built with conventional solder paste. Boards from the second run with the “test friendly” solder paste had residue which was either still liquid or weak and brittle when probed with the needles probe. This should provide better electrical contact. (Figure 15)

Figure 15: Soft, liquid flux residue from “test-friendly” solder paste. Probing Results: 108 boards with the new solder paste were tested. There was a fixture construction problem resulting in three probes being off target. 50 of the boards failed probe contact test due to this problem. Of the remaining 58 boards where the probes contacted the bead probes, 100% passed the probe contact test. This demonstrates that using a solder paste formulated for pin probe testing results in excellent probe contact.

Best Practices

• For a first-time implementation of bead probe technology, the designer should add bead probes

to nodes which are inaccessible to standard probing or to those which are not critical to the production and test processes. Using established conventional probing methods wherever possible reduces risk.

• Constant communication with the CAD layout team, stencil manufacturer, CM, and fixture manufacturer on the how to design, implement, and use bead probes is important since it still is a new technology. Particular care in communication when personnel changes occur is imperative.

• Use of a pin probe testable solder paste if a no-clean process is used will reduce probe contact problems. Most solder paste manufacturers offer these kinds of paste.

• Once the manufacturer has demonstrated the ability to implement and use bead probes for ICT, the next logical step for the designer is to use bead probes on circuit nodes where conventional probing is possible to take advantage of the low impact of bead probes on circuit geometries and the layout process.

Summary:

• Bead probes provided significant increases in test access and test coverage to areas and components of these boards. Conventional probe access was impossible. Test access increased from 46% to 70% of circuit nodes, increasing component test coverage from 45% to 85%.

• Since the bead probe is a unique new feature, the existing CAD systems did not have automatic tools for adding bead probes or setting keep-out distances from component bodies. However, new tools were becoming available as introduction of this board proceeded.

• The type and amount of solder flux on no-clean lead-free boards was critical to probe contact integrity.

• Changing to a “test-friendly” solder paste version of the CM’s standard solder paste which was formulated for probe testing compatibility resulted in a significant improvement in probe contact results. Residues were soft, not hard, gummy or tacky. This allowed good probe contact without preventing a buildup of flux residue on the probes. [SuPa08], [Smit09]

Conclusions:

• Close cooperation and communication among the OEM, the CM and particularly the CM’s process engineering group is imperative. The solder paste, fixture, and the stencil manufacturers also

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require training and communication for successful bead probe implementation.

• Solder paste and flux choice is critical for successful implementation of bead probes in no-clean processes. Probe contact may be poor if a solder paste leaves hard, gummy, or waxy residues.

• Fixture construction factors such as accuracy of probe location and proper seating of the probes is critical.

• Since this product was designed and bead probes were implemented, a layout tool has become commercially available which adds bead probes to the design, sets keepout distances, selects those to be used for test, and analyzes test access. [PaDe07]

References [DoGr06] “Implementation of Solder-Bead Probing in High

Volume Manufacturing”, M. Doraiswamy and J. J. Grealish, Proceedings, International Test Conference, paper 5.4, Santa Clara CA, Oct 2006

[Park04] K. P. Parker, “A New Probing Technique for High-Speed/High-Density Printed Circuit Boards,” Proceedings IEEE International Test Conference, 2004, pp 365-374

[Park05] K. P. Parker, “Bead Probes in Practice,” Pro-ceedings IEEE International Test Conference, Paper 26.2, Austin TX, Nov 2005

[Rein05] R. D. Reinosa, “Effect of Lead Free Solders on In-Circuit Test Process”, Proceedings, International Test Conference, Paper 26.3, Austin TX, Nov 2005

[Rein06] R. D. Reinosa, “Lead-free Through-Hole Techno-logy (THT) and Contact Repeatability in In-Circuit Test”, Proceedings, International Test Conference, Paper 5.3, Santa Clara CA, Oct 2006

[PaDe07] K. P. Parker and D. DeMille, “A Bead Probe CAD Strategy for In-Circuit Test”, Proceedings, International Test Conference, Paper 18.2, Santa Clara CA, Oct 2007

[SuPa08] D. Suraski and M. Parker, “Considerations for the Pin Probe Testing of No-Clean Solder Paste”, www.aimsolder.com

[Smit09] B. Smith, “No-Clean Solder Paste Innovations”, Surface Mount Technology (SMT), November

1999