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Input (P6247 probe, averaged) bKLM RPC Frontend – Discriminator & TDC Output @ threshold = 3.3 mV New discriminator circuit: • lower power, single supply • balanced line receiver • robust input protection • modern SMT components • analog test pulser V TH DAC per channel breadboard prototype results New TDC: • 48 channels / FPGA • Xilinx XC6SLX25 • low latency data concentrator (≈530 ns ) • daisy-chain 2x to backplane per FEE board 250 MHz synchronous edge detector N x 16 FIFO discrim. to concentrator 250 MHz clock counter (global) To FE FPGA output; not total system latency W. Jacobs, B. Kunkler, G. Visser, A. Vossen, Indiana University

Input (P6247 probe, averaged)

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bKLM RPC Frontend – Discriminator & TDC. W. Jacobs, B. Kunkler , G. Visser , A. Vossen , Indiana University. New discriminator circuit: lower power, single supply balanced line receiver robust input protection modern SMT components analog test pulser V TH DAC per channel. - PowerPoint PPT Presentation

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Input (P6247 probe, averaged)

bKLM RPC Frontend – Discriminator & TDC

Output @ threshold = 3.3 mV

New discriminator circuit:• lower power, single supply• balanced line receiver• robust input protection• modern SMT components

• analog test pulser• VTH DAC per channel

breadboard prototype results

New TDC:• 48 channels / FPGA• Xilinx XC6SLX25

• low latency data

concentrator (≈530 ns†)• daisy-chain 2x to backplane per FEE board

250 MHz synchronous edge

detector N x 16 FIFO

discrim.

toconcentrator

250 MHz clock counter (global)

† To FE FPGA output; not total system latency

W. Jacobs, B. Kunkler, G. Visser, A. Vossen, Indiana University

• Existing Belle bKLM crates and RPC signal cables are re-used.• Each Belle-II RPC FEE crate consists of thirteen FEE boards and one concentrator board. 6U x 160mm.• One FEE board signal connector handles positive detector pulses, the other negative.• Crate uses VME-J1 backplane in point-to-point protocol – five data lines dedicated to each FEE board. No added latency from bus protocols or sharing.• Belle-II bKLM RPC overall uses 16 fibers (Belle2Link) to DAQ and 16 fibers feeding hit info to trigger decision logic tree.

System Block Diagram (per crate, 16x)

48 c

hann

els

inpu

t

JTAG

(chi

psco

pe)

out

put

• Stackable prototype board now in final stages of layout; fab 12/2011•Plan to run tests with bKLM modules in Belle, early 2012• 2 – 3 layers read out (synchronously)

VME CRATE

TDC BOARD 1 CONCENTRATORBOARD

.

.

.

FPGA

FPGA

J2

J1

J3

5

POS PULSE (X48)

NEG PULSE (X48)

TDC BOARD 13

FPGA

FPGA

J2

J1

J3

5

POS PULSE (X48)

NEG PULSE (X48)

FPGAJ1

TXRX

DAQFIBER XCVR

VME BACKPLANE

TXRX

TRIGGERFIBER XCVR

bKLM RPC Frontend – System & Status