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CS61C L21 State Elements : Circuits that Remember (1) Long Wei, Spring 2010 © UCB Long Wei inst.eecs.berkeley.edu/~cs61c-te inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #21 State Elements: Circuits that Remember 2010-3-09 Steam comes to Macs Hello to James Muerle in the back row

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Page 1: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (1)! Long Wei, Spring 2010 © UCB!

! !Long Wei!! !inst.eecs.berkeley.edu/~cs61c-te!

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures

Lecture #21 State Elements: Circuits that Remember

2010-3-09!

Steam comes to Macs!

Hello to James Muerle!in the back row!

Page 2: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (2)! Long Wei, Spring 2010 © UCB!

Review!• ISA is very important abstraction layer!

• Contract between HW and SW!

• Clocks control pulse of our circuits!• Voltages are analog, quantized to 0/1!• Circuit delays are fact of life!• Two types of circuits:!

• Stateless Combinational Logic (&,|,~)!• State circuits (e.g., registers)!

Page 3: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 © UCB!

Uses for State Elements!

1.  As a place to store values for some indeterminate amount of time:!

•  Register files (like $1-$31 on the MIPS)!•  Memory (caches, and main memory)!

2.  Help control the flow of information between combinational logic blocks.!

•  State elements are used to hold up the movement of information at the inputs to combinational logic blocks and allow for orderly passage.!

Page 4: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (4)! Long Wei, Spring 2010 © UCB!

Accumulator Example!

Want: !S=0; for (i=0;i<n;i++)

S = S + Xi

Why do we need to control the flow of information?!

Assume:!•  Each X value is applied in succession, one per cycle.!•  After n cycles the sum is present on S.!

Page 5: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (5)! Long Wei, Spring 2010 © UCB!

First try…Does this work?!

Nope! !Reason #1… What is there to control the next iteration of the ʻforʼ loop?!Reason #2… How do we say: ʻS=0ʼ?!

Feedback!

Page 6: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (6)! Long Wei, Spring 2010 © UCB!

Second try…How about this?!

Rough timing…!

Register is used to hold up the transfer of data to adder.!

Page 7: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (7)! Long Wei, Spring 2010 © UCB!

Register Details…Whatʼs inside?!

• n instances of a “Flip-Flop”!• Flip-flop name because the output flips and

flops between and 0,1 !• D is “data”, Q is “output”!• Also called “d-type Flip-Flop”!

Page 8: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (8)! Long Wei, Spring 2010 © UCB!

Whatʼs the timing of a Flip-flop? (1/2)!

• Edge-triggered d-type flip-flop!• This one is “positive edge-triggered”!

• “On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”!• Example waveforms:!

Page 9: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (9)! Long Wei, Spring 2010 © UCB!

Whatʼs the timing of a Flip-flop? (2/2)!

• Edge-triggered d-type flip-flop!• This one is “positive edge-triggered”!

• “On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”!• Example waveforms (more detail):!

Page 10: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (10)! Long Wei, Spring 2010 © UCB!

Accumulator Revisited (proper timing 1/2)!•  Reset input to register is

used to force it to all zeros (takes priority over D input).!

•  Si-1 holds the result of the ith-1 iteration.!

•  Analyze circuit timing starting at the output of the register.!

Page 11: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (11)! Long Wei, Spring 2010 © UCB!

Accumulator Revisited (proper timing 2/2)!•  reset signal shown.!•  Also, in practice X might

not arrive to the adder at the same time as Si-1!

•  Si temporarily is wrong, but register always captures correct value.!

•  In good circuits, instability never happens around rising edge of clk.!

Page 12: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (12)! Long Wei, Spring 2010 © UCB!

Maximum Clock Frequency!

• What is the maximum frequency of this circuit?!

Max Delay = !Setup Time + CLK-to-Q Delay!! ! ! ! ! +!CL Delay!

Hint… Frequency = 1/Period

Page 13: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (13)! Long Wei, Spring 2010 © UCB!

Pipelining to improve performance (1/2)!

Timing…!

Extra Register are often added to help speed up the clock rate.!

Note: delay of 1 clock cycle from input to output.!Clock period limited by propagation delay of adder/shifter.!

Page 14: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (14)! Long Wei, Spring 2010 © UCB!

Pipelining to improve performance (2/2)!

Timing…!

•  Insertion of register allows higher clock frequency.!

•  More outputs per second.!

Page 15: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (15)! Long Wei, Spring 2010 © UCB!

Recap of Timing Terms!• Clock (CLK) - steady square wave that

synchronizes system!

• Setup Time - when the input must be stable before the rising edge of the CLK!

• Hold Time - when the input must be stable after the rising edge of the CLK!

•  “CLK-to-Q” Delay - how long it takes the output to change, measured from the rising edge!

• Flip-flop - one bit of state that samples every rising edge of the CLK!

• Register - several bits of state that samples on rising edge of CLK or on LOAD!

Page 16: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (16)! Long Wei, Spring 2010 © UCB!

Finite State Machines (FSM) Introduction!

• You have seen FSMs in other classes.!• Same basic idea.!• The function can be

represented with a “state transition diagram”.!• With combinational

logic and registers, any FSM can be implemented in hardware.!

Page 17: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (17)! Long Wei, Spring 2010 © UCB!

Finite State Machine Example: 3 ones…!

Draw the FSM…!

FSM to detect the occurrence of 3 consecutive 1ʼs in the input.!

Assume state transitions are controlled by the clock:!on each clock cycle the machine checks the inputs and moves to a new state and produces a new output…!

Page 18: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (18)! Long Wei, Spring 2010 © UCB!

Hardware Implementation of FSM!

+!

=! ?!

… Therefore a register is needed to hold the a representation of which state the machine is in. Use a unique bit pattern for each state.!

Combinational logic circuit is used to implement a function maps from present state and input to next state and output.!

Page 19: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (19)! Long Wei, Spring 2010 © UCB!

Hardware for FSM: Combinational Logic!

1!00!1!10!0!00!0!10!0!10!1!01!0!00!0!01!0!01!1!00!0!00!0!00!

Output!NS!Input!PS!Truth table…!

Next lecture we will discuss the detailed implementation, but for now can look at its functional specification, truth table form.!

Page 20: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (20)! Long Wei, Spring 2010 © UCB!

General Model for Synchronous Systems!

•  Collection of CL blocks separated by registers.!•  Registers may be back-to-back and CL blocks may be back-to-

back.!•  Feedback is optional.!•  Clock signal(s) connects only to clock input of registers.!

Page 21: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (21)! Long Wei, Spring 2010 © UCB!

Peer Instruction!

A.  HW feedback akin to SW recursion!B.  The period of a usable

synchronous circuit is greater than the CLK-to-Q delay!

C.  You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input. !

ABC A: FFF B: FTF C: TFF D: TTF E: TTT

Page 22: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (22)! Long Wei, Spring 2010 © UCB!

Peer Instruction Answer!

A.  HW feedback akin to SW recursion!B.  We can implement a D-Q flipflop

as simple CL (And, Or, Not gates) !C.  You can build a FSM to signal

when an equal number of 0s and 1s has appeared in the input. !

ABC A: FFF B: FTF C: TFF D: TTF E: TTT

A.  It needs ʻbase caseʼ (reg reset), way to step from i to i+1 (use register + clock). ! !True!!

B.  If not, will loose data!!! !!True! !C.  How many states would it have? Say itʼs n. How

does it know when n+1 bits have been seen?!!False!!

A.  HW feedback akin to SW recursion!B.  The period of a usable

synchronous circuit is greater than the CLK-to-Q delay!

C.  You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input. !

Page 23: inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structurescs61c/sp10/lec/21/2010Sp61C-L21-lw-STATE.pdfCS61C L21 State Elements : Circuits that Remember (3)! Long Wei, Spring 2010 ©

CS61C L21 State Elements : Circuits that Remember (23)! Long Wei, Spring 2010 © UCB!

“And In conclusion…”!

• State elements are used to:!• Build memories!• Control the flow of information between other state

elements and combinational logic!

• D-flip-flops used to build registers!

• Clocks tell us when D-flip-flops change!• Setup and Hold times important!

• We pipeline long-delay CL for faster clock!

• Finite State Machines extremely useful!• Youʼll see them again 150,152, 164, 172…!