Integrated Circuit Technology Challenges · 2020-06-14 · Directed Self Assembly Progress Di-block Copolymer self assembly on patterned Molecular monolayer: Goal reduce LER P. Nealey,

Integrated Circuit Technology Challenges

C. Michael GarnerTechnology & Manufacturing Group

Technology StrategyApril 27, 2006

April 27, 2006

Technology & Manufacturing Group Technology Strategy Organization

2

Key MessagesSilicon Nanoelectronics is production reality and follows Moore’s law

New materials are needed to extend CMOS

Long term: Novel devices will be needed to enhance CMOS

New materials, metrology, and modeling are required

Increased collaboration between Industry, Universities & Gov’t is essential!!!

April 27, 2006


3

Agenda

Moore's Law

Extending CMOS

Emerging Research Memory Devices

Revolutionary CMOS

Device options to enhance CMOS (Beyond CMOS)

Nanomaterial Challenges

Summary

April 27, 2006


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Moore’s Law Will Outlive CMOS

1960 1970 1980 1990 2000 2010 2020 2030

Tran

sist

ors/

Die

Tran

sist

ors/

Die

PMOSPMOSBipolarBipolar CMOSCMOS

1µm 100nm 10nm10µm

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010 1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessorMemoryMemory

1010111110101212

10101313 VoltageVoltageScalingScaling

PwrPwr EffEffScalingScaling

New NanoNew Nano--structuresstructures

NMOSNMOS

KiloXtor

MegaXtor

GigaXtor

TeraXtor

Beyond CMOS?Beyond CMOS?Spin based?Spin based?Molecular?Molecular?Other?Other?

Through Innovation

Source: IntelSource: Intel

April 27, 2006


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Si Substrate

Metal Gate

High-kTri-Gate

S

G

D

III-V

S

Carbon Nanotube FET

Innovation-Enabled Pipeline in Place

50 nm35 nm

30 nm

SiGe S/DSiGe S/DStrained Strained SiliconSilicon

Future options subject to changeFuture options subject to change

SiGe S/DSiGe S/DStrained Strained SiliconSilicon

90 nm90 nm65 nm65 nm

45 nm45 nm32 nm32 nm

2003200320052005

2007200720092009

2011+2011+

Technology Generation

Technology Generation

20 nm

Manufacturing Development Research

10 nm

5 nm

Nanowire


April 27, 2006


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PPT ShrinkSource: Intel

Material Challenges

Materials Challenges Everywhere

Low K Interlevel Dielectric Micelle Assembled….

10nm10nm

What Device Next?What Device Next?What Materials?What Materials?How to Assemble?How to Assemble?

Barrier Layer ~20nm

Printed Features: Line Edge Roughness (LER)Resist Nano-domains

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Si Technology: Complexity Increasing Exponentially

Decade of new materials

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Directed Self Assembly Progress

Di-block Copolymer self assembly on patternedMolecular monolayer: Goal reduce LERP. Nealey, U. Wisc.

Di-block Copolymer self assembly of magnetic materials in a confined space.C. Ross, MIT

Progress in aligning self assembled structures with lithographically defined structures

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Sublithographic Directed Self Assembly Lithography

Isolated Sublithographic

Features

Periodic features: variable pitch

and size on the same layer

Level to Level Alignment

•Self Assembly may be used in nonaligned applications•To Extend lithography, the challenges are significant!!

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High-k Dielectric reduces leakage substantially

Silicon substrate

Gate

3.0nm High-k

Silicon substrate

1.2nm SiO2

Gate

High-k vs. SiO2 Benefit

Capacitance 60% greater Much faster transistors

Gate dielectric leakage > 100x reduction Far cooler

Benefits compared to current process technologiesBenefits compared to current process technologies

Robert Chau, Nov., 2003

April 27, 2006


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High-k Materials Require New Manufacturing Techniques

Step 1

Step 2

Step 3

Step 4

HighHigh--k Materials Are Deposited One Molecular Layer at a Timek Materials Are Deposited One Molecular Layer at a TimePrecursors must be Designed for Monolayer AssemblyPrecursors must be Designed for Monolayer Assembly

April 27, 2006


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New Interconnect Materials

Metal linesMetal linesAl CuAl Cu

InsulatingInsulatingdielectricdielectric

SiOSiO22 SiOFSiOFCDOCDO

(low(low--k)k)

FutureFutureOptionsOptions

Ultra Ultra LowLow--kk

DielectricDielectric

InterconnectsInterconnects

NewThinner Barrier Layers

Lower K Dielectrics NeededLower K Dielectrics NeededLower K Dielectrics Needed

ChangesChangesMadeMade

April 27, 2006


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Small Line Conductivity

10 100 10000

1

2

3

4

5sidewall

grain boundary

bulk resistivity

Res

istiv

ity [µ

Ω c

m]

Line width [nm]

ChallengeReduce grain scatteringIncrease grain sizeReduce sidewall scatteringReduce line width roughnessNew smoother materials??

Semiconductor Industry Association The International Technology Roadmap for Semiconductors, 2005 edition SEMATECH: Austin, TX, 2005

April 27, 2006


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Metal Barrier Thickness Trend

1

10

100

2005

2009

2013

2017

Year

Size

(nm

)

Metal Half Pitch(MPU)

M1 CuCladdingThickness

Barrier Options•PVD•CVD•ALD Ti, Ta, W

Oxides & NitridesNovel Materials

Ru, etc


Cu Barrier Cladding Layer

April 27, 2006


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Could Nanomaterials Extend Interconnect Scaling?

Challenges

•Control of location and orientation

•Control of nanostructure and properties

•Reproducibility of nanometer scale contacts

Technology Research NewsOct. 10, 2001

http://www.trnmag.com/Photos/2001/101001/Tiny tubes make logic circuits Image 101001.html

April 27, 2006


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0

2

4

6

8

10

1.61.822.22.42.62.83

k

GPa

ModulusHardness

Lines do not represent any fitting. They are added tohelp read the data points

Lower K ILD Required for Future Technologies

•Mechanical strength dropping dramatically with lower K•Reducing K below 2.4 achieved with pores

April 27, 2006


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Pores are exposed to chemicals in Via Etch

Metal line trench etch exposes pores to even more chemicals

Chemical Mechanical Polish & Packaging• Cohesive failure• Cracking• Delamination

Can novel materials protect pores from chemicals???Can novel materials protect pores from chemicals???

Porous ILD Integration Challenge

April 27, 2006


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Emerging Research Memory

Ferroelectric FET has many material options

• Combinations of Group II, Transition & Lanthanide oxides

Insulator Resistance Change Memory has many material and mechanism options


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Revolutionary CMOS

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Options for sub 20nm technologies

Challenges: Placement and property control

Nanomaterial Transistors

Growth Conditions & Catalysts are CriticalGrowth Conditions & Catalysts are Critical

April 27, 2006


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1D Characterization & Modeling Challenges

1D Material Challenges

• Control Structure and composition (nm scale)

• Reproducible electronic properties & interactions with interface materials

• nm Scale Placement & Alignment

• Atomic Impurities & Defects

• Wafer & Device Level Property Mapping

Improved Synthesis, Models & Metrology Improved Synthesis, Models & Metrology Needed!!!!Needed!!!!

April 27, 2006


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Beyond CMOS

Vision: Devices with new functionality integrated with CMOSVision: Devices with new functionality integrated with CMOS

April 27, 2006


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What are we looking for?

Required characteristics:

• Scalability

• Performance

• Energy efficiency

• Gain

• Operational reliability

• Room temp. operation

Preferred approach:

• CMOS process compatibility

• CMOS architectural compatibility

Alternative state variables

Spin–electron, nuclear, photon

Phase

Quantum state

Magnetic flux quanta

Mechanical deformation

Dipole orientation

Molecular state

New Nanoscale Devices, Materials & Interfaces

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New State Variables: Potential Material Needs

•Materials that support at least 2 stable “states”

•Passivation materials to prevent undesired state changes

•Materials that enable changes of the “state”

•Materials that enable reading the “state” of a device

•Materials to transmit “state” information between “devices”

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nm Scale Materials & Characterization

New materials to enable

•Room temperature operation

•State amplification (Gain) & transport

•nm Scale devices

New nm scale metrology needs

•State generation, lifetimes, propagation mechanisms, diffusion lengths• State interface transport, reflection • State coupling & interaction with intrinsic & extrinsic fields

April 27, 2006


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Spin State Material Progress

Spin Injection Efficiency

0

0.2

0.4

0.6

0.8

1

1998 2000 2002 2004

Year

Spin

Inje

ctio

n Ef

ficie

ncy Low Temp FerroM Spin

Injection

RT Metallic Spin Injection

Need Room Temp FM Semiconductor & Spin Gain

Maximum Curie Temperature

0100200300400500600700

1990 1995 2000 2005

Year

Cur

ie T

empe

ratu

re (T

c (K

)) Doped Oxides(III.Mn)V

Carrier mediated exchange

Overlapping Bound Magnetic Polarons, Coey, Nature 2005

Room temperature ferromagnetic semiconductors (T curie)

Efficient Spin Injection

Spin GAIN ?????

April 27, 2006


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Novel short-range energy transfermechanisms

Plasmons – Atwater, Caltech

Coherent phonons –Stoyananov, MITOrbitron waves, Tokura, U of Tokyo

Spin waves, Nikonov, Intel

April 27, 2006


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Characterization of coupled phenomena at the nanoscale

Challenges:

Resolving single spin, charge and impurities

Spin wave entanglement and propagation

Magnetic coupling between and among nano-domains

Nano-characterization of interface and surface effects

Novel test structures/methods to deconvolveeffects, when possible

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Nanomaterial Challenges

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Nano-structured Materials

Source: J. Brinker, UNM/Sandia National LabsSource: J. Brinker, UNM/Sandia National Labs

Dendrimers Source: S. Stupp

Property Control, Contact Resistance and Metrology are Critical

Sub 100nm particles

Molecular Assembly (directed & self assembly)

Macromolecules

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Nano-material Challenges

Significantly improve material performance

Low integration complexity

Controlled assembly into useful forms

Control & reproducibility of properties

Purity

Metrology

Environmental Health & Safety Data

Cost

Nano-materials are often difficult to use!!!

April 27, 2006


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Summary

April 27, 2006


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SummarySilicon Nanoelectronics is production reality and follows Moore’s law

New materials are needed to extend CMOS

Long term: Novel devices will be needed to enhance CMOS

New materials, metrology, and modeling are required

Increased collaboration between Industry, Universities & Gov’t is essential!!!

Documents

Integrated Circuit Technology Challenges · 2020-06-14 · Directed Self Assembly Progress Di-block Copolymer self assembly on patterned Molecular monolayer: Goal reduce LER P. Nealey,