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Integrated, Dual RF Transceiver with Observation Path

Data Sheet AD9371

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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FEATURES Dual differential transmitters (Tx) Dual differential receivers (Rx) Observation receiver (ORx) with 2 inputs Sniffer receiver (SnRx) with 3 inputs Tunable range: 300 MHz to 6000 MHz Tx synthesis bandwidth (BW) to 250 MHz Rx BW: 8 MHz to 100 MHz Supports frequency division duplex (FDD) and time division

duplex (TDD) operation Fully integrated independent fractional-N radio frequency (RF)

synthesizers for Tx, Rx, ORx, and clock generation JESD204B digital interface

APPLICATIONS 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells FDD and TDD active antenna systems Microwave, nonline of sight (NLOS) backhaul systems

GENERAL DESCRIPTION The AD9371 is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTS equipment in both FDD and TDD applications. The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.

The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.

An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.

FUNCTIONAL BLOCK DIAGRAM

OBSERVATIONRxORX1+

ORX1–

ORX2+ORX2–

JESD

204B

JESD

204B

JESD

204B

SPI

DEV

_CLK

_IN

+,D

EV_C

LK_I

N–

CTR

L I/F

RX_EXTLO+RX_EXTLO–

ADCLPFRX2

ADCLPF

RX1RX1+

RX1–

LOGENERATOR

RFSYNTHESIZER

RX2+

RX2–

DECIMATION,pFIR,

DC OFFSETQEC,

TUNING,RSSI,

OVERLOAD

MICRO-CONTROLLER

SPIPORT

ADCLPF

SNIFFERRx

ADCLPF

TX_EXTLO+TX_EXTLO–

DACLPFTX2

DACLPF

TX1TX1+

TX1–

TX2+

TX2– pFIR,QEC,

INTERPOLATION

GPIOAUXADCAUXDAC

CLOCKGENERATOR

EXTERNALOPTION

LOGENERATOR

RFSYNTHESIZER

RFSYNTHESIZER

LOGENERATOR

EXTERNALOPTION

SNRXA+SNRXA–SNRXB+SNRXB–SNRXC+SNRXC–

DECIMATION,pFIR,AGC,

DC OFFSET,QEC,

TUNING,RSSI,

OVERLOAD

AD9371

1465

1-00

1

NOTES1. FOR JESD204B PINS, SEE FIGURE 4.

Figure 1.

The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

A 1.3 V supply is required to power the core of the AD9371, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9371 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

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AD9371* PRODUCT PAGE QUICK LINKSLast Content Update: 04/27/2017

COMPARABLE PARTSView a parametric search of comparable parts.

EVALUATION KITS• ADRV9371-N/PCBZ and ADRV9371-W/PCBZ Boards

DOCUMENTATIONApplication Notes

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Data Sheet

• AD9371: Integrated, Dual RF Transceiver with Observation Path Data Sheet

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SOFTWARE AND SYSTEMS REQUIREMENTS• AD9371 Highly Integrated, Wideband RF Transceiver

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REFERENCE MATERIALSInformational

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AD9371 Data Sheet

Rev. B | Page 2 of 57

TABLE OF CONTENTS Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Current and Power Consumption Specifications ..................... 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 12

Reflow Profile .............................................................................. 12

Thermal Resistance .................................................................... 12

ESD Caution ................................................................................ 12

Pin Configuration and Function Descriptions ........................... 13

Typical Performance Characteristics ........................................... 16

700 MHz Band ............................................................................ 16

2.6 GHz Band .............................................................................. 26

3.5 GHz Band .............................................................................. 36

5.5 GHz Band .............................................................................. 46

Theory of Operation ...................................................................... 54

Transmitter (Tx) ......................................................................... 54

Receiver (Rx) ............................................................................... 54

Observation Receiver (ORx) ..................................................... 54

Sniffer Receiver (SnRx) ............................................................. 54

Clock Input .................................................................................. 54

Synthesizers ................................................................................. 55

Serial Peripheral Interface (SPI) Interface .............................. 55

GPIO_x AND GPIO_3P3_x Pins ............................................ 55

Auxiliary Converters .................................................................. 55

JESD204B Data Interface .......................................................... 55

Power Supply Sequence ............................................................. 56

JTAG Boundary Scan ................................................................. 56

Outline Dimensions ....................................................................... 57

Ordering Guide .......................................................................... 57

REVISION HISTORY 3/2017—Rev. A to Rev. B Change to Table 1 ............................................................................. 6 Deleted Figure 230 through Figure 239; Renumbered Sequentially ..................................................................................... 55 Changes to Sniffer Receiver (SnRx) Section ............................... 55

11/2016—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 6 Changes to Table 2 ............................................................................ 9 Changes to L3, L4 Description Column, Table 6; M3, M4 Description Column, Table 6; and M13, M14 Description Column, Table 6 .............................................................................. 16 Changes to Figure 46 Caption ....................................................... 23 Changes to Figure 48 Caption ....................................................... 24 Changes to Figure 56 Caption and Figure 57 Caption .............. 25 Changes to Figure 82 Caption ....................................................... 30

Changes to Figure 105 Caption .................................................... 33 Changes to Figure 107 Caption .................................................... 34 Changes to Figure 115 Caption and Figure 116 Caption .......... 35 Changes to Figure 141 Caption .................................................... 40 Changes to Figure 164 Caption .................................................... 43 Changes to Figure 166 Caption .................................................... 44 Changes to Figure 174 Caption and Figure 175 ......................... 45 Changes to Figure 194 and Figure 199 Caption ......................... 49 Changes to Figure 222 Caption .................................................... 53 Changes to Figure 224 Caption .................................................... 54 Added Figure 230 to Figure 235; Renumbered Sequentially .... 55 Added Figure 236 to Figure 239 ................................................... 56 Added External LO Inputs Section .............................................. 58

7/2016—Revision 0: Initial Version

Data Sheet AD9371


SPECIFICATIONS Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V, VDDA_DES = 1.3 V, JESD_VTT_DES = 1.3 V, VDDA_1P31 = 1.3 V, VDIG = 1.3 V, VDDA_1P8 = 1.8 V, VDD_IF = 2.5 V, and VDDA_3P3 = 3.3 V; all RF specifications based on measurements that include printed circuit board (PCB) and matching circuit losses, unless otherwise noted.

Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments TRANSMITTERS (Tx)

Center Frequency 300 6000 MHz Tx Large Signal Bandwidth (BW) 100 MHz Tx Synthesis BW2 250 MHz Wider bandwidth for use in

digital processing algorithms BW Flatness ±0.5 dB 250 MHz BW, compensated

by programmable finite infinite response (FIR) filter

±0.15 dB Any 20 MHz BW span, compensated by programmable FIR filter

Deviation from Linear Phase 10 Degrees 250 MHz BW Power Control Range 0 42 dB Increased calibration time,

reduced QEC3, LOL4 performance beyond 20 dB

Power Control Resolution 0.05 dB ACLR5 (Four Universal Mobile

Telecommunications System (UMTS) Carriers)

−11.2 dBFS rms, 0 dB RF attenuation

700 MHz Local Oscillator (LO) −64 dB 2600 MHz LO −64 dB 3500 MHz LO −63 dB 5500 MHz LO −61 dB

In-Band Noise −155 dBFS6/Hz Tx to Tx Isolation

700 MHz LO 70 dB 2600 MHz LO 65 dB 3500 MHz LO 65 dB 5500 MHz LO 65 dB

Image Rejection Up to 20 dB RF attenuation, within large signal BW, QEC3 active


Maximum Output Power 0 dBFS, 1 MHz signal input, 50 Ω load, 0 dB RF attenuation

700 MHz LO 7 dBm 2600 MHz LO 7 dBm 3500 MHz LO 6 dBm 5500 MHz LO 4 dBm

Output Third-Order Intercept Point OIP3 −5 dBFS rms, 0 dB RF attenuation


AD9371 Data Sheet


Parameter Symbol Min Typ Max Unit Test Conditions/Comments Carrier Leakage After calibration, LOL

correction active, CW7 input signal, 3 dB RF and 3 dB digital attenuation, 40 kHz measurement BW

700 MHz LO −81 dBFS6 2600 MHz LO −81 dBFS6 3500 MHz LO −81 dBFS6 5500 MHz LO −75 dBFS6

Error Vector Magnitude (3GPP Test Signals)

EVM Long-term evolution (LTE) 20 MHz downlink, 5 dB RF attenuation

700 MHz LO −45 dB 2600 MHz LO −39 dB 3500 MHz LO −38.5 dB 5500 MHz LO −37.5 dB

Output Impedance 50 Ω Differential RECEIVERS (Rx)

Center Frequency 300 6000 MHz Gain Range 0 30 dB Analog Gain Step 0.5 dB BW Ripple ±0.5 dB 100 MHz BW, compensated

by programmable FIR filter ±0.2 dB Any 20 MHz span,

compensated by programmable FIR filter

Rx Bandwidth 8 100 MHz Analog low-pass filter (LPF) BW is 20 MHz minimum, programmable FIR BW configurable over the entire range

Rx Alias Band Rejection 75 dB Due to digital filters Maximum Recommended Input

Power8 −14 dBm Input is a CW7 signal at a 0 dB

attenuation setting; this level increases decibel for decibel with attenuation

Noise Figure NF Maximum Rx gain, at Rx port, matching losses de-embedded

700 MHz LO 12 dB 2600 MHz LO 13.5 dB 3500 MHz LO 14 dB 5500 MHz LO 18 dB

Input Third-Order Intercept Point IIP3 Maximum Rx gain, third-order intermodulation (IM3) 1 MHz offset from LO


Input Second-Order Intercept Point

IIP2 Maximum Rx gain, second-order intermodulation (IM2) 1 MHz offset from LO


Data Sheet AD9371


Parameter Symbol Min Typ Max Unit Test Conditions/Comments Image Rejection QEC3 active, within Rx BW


Input Impedance 200 Ω Differential Tx1 to Rx1 Signal Isolation and

Tx2 to Rx2 Signal Isolation


Tx1 to Rx2 Signal Isolation and Tx2 to Rx1 Signal Isolation


Rx1 to Rx2 Signal Isolation 700 MHz LO 60 dB 2600 MHz LO 60 dB 3500 MHz LO 60 dB 5500 MHz LO 60 dB

Rx Band Spurs Referenced to RF Input at Maximum Gain

−95 dBm No more than one spur at this level per 10 MHz of Rx BW; excludes harmonics of the reference clock

Rx LO Leakage at Rx Input at Maximum Gain

Leakage decreases decibel for decibel with attenuation for first 12 dB

700 MHz LO −65 dBm 2600 MHz LO −65 dBm 3500 MHz LO −62 dBm 5500 MHz LO −62 dBm

OBSERVATION RECEIVER (ORx) Center Frequency 300 6000 MHz Gain Range 0 18 dB Analog Gain Step 1 dB BW Ripple ±0.5 dB 250 MHz RF BW, compensated

by programmable FIR filter Deviation from Linear Phase 10 Degrees 250 MHz RF BW ORx Bandwidth 250 MHz ORx Alias Band Rejection 60 dB Due to digital filters Maximum Recommended Input

Power8 −13 dBm Input is a CW7 signal at 0 dB

attenuation setting; this level increases decibel for decibel with attenuation

Signal-to-Noise Ratio9 SNR Maximum gain at ORx port 700 MHz LO 60 dB 2600 MHz LO 60 dB 3500 MHz LO 60 dB 5500 MHz LO 59 dB 200 MHz BW, 245.76 MSPS

AD9371 Data Sheet


Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Third-Order Intercept Point IIP3 Maximum ORx gain,

IM3 1 MHz offset from LO 700 MHz LO 22 dBm 2600 MHz LO 22 dBm 3500 MHz LO 18 dBm 5500 MHz LO 18 dBm

Input Second-Order Intercept Point

IIP2 Maximum ORx gain, IM2 1 MHz offset from LO


Image Rejection After online tone calibration 700 MHz LO 65 dB 2600 MHz LO 65 dB 3500 MHz LO 65 dB 5500 MHz LO 65 dB

Input Impedance 200 Ω Differential Tx1 to ORx1 Signal and Tx2 to

ORx2 Signal Isolation


Tx1 to ORx2 Signal and Tx2 to ORx1 Signal Isolation


SNIFFER RECEIVER (SnRx) Center Frequency 300 4000 MHz Gain Range 0 52 dB Analog Gain Step 1 dB BW Ripple ±0.5 dB 20 MHz RF BW, compensated

by programmable FIR filter Rx Bandwidth 20 MHz Rx Alias Band Rejection 60 dB Due to digital filters Maximum Recommended Input

Power8 −26 dBm Input is a CW7 signal at 0 dB

attenuation setting Noise Figure NF Maximum gain at

SnRx port, matching losses de-embedded, gain control limited to the first 20 steps

700 MHz LO 5 dB 2600 MHz LO 5 dB 3500 MHz LO 7 dB

Input Third-Order Intercept Point IIP3 Maximum gain, IM3 1 MHz offset from LO, gain control limited to the first 20 steps

700 MHz LO 1 dBm 2600 MHz LO 1 dBm 3500 MHz LO 1 dBm

Data Sheet AD9371


Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Second-Order Intercept

Point IIP2 Maximum gain, IM2 1 MHz

offset from LO, gain control limited to the first 20 steps

700 MHz LO 45 dBm 2600 MHz LO 45 dBm 3500 MHz LO 45 dBm

Image Rejection After online tone calibration 700 MHz LO 75 dB 2600 MHz LO 75 dB 3500 MHz LO 75 dB

Input Impedance 400 Ω Differential Tx1 to SnRx Signal and Tx2 to

SnRx Signal Isolation Applies to each SnRx input

700 MHz LO 60 dB 2600 MHz LO 60 dB 3500 MHz LO 60 dB

LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 3 GHz, 76.8 MHz

phase frequency detector (PFD) frequency

LO Spectral Purity −80 dBc Excludes integer boundary spurs 1 kHz to 100 MHz

Spot Phase Noise 700 MHz LO

10 kHz −104 dBc 100 kHz −107 dBc 1 MHz −133 dBc

2600 MHz LO 10 kHz −93 dBc 100 kHz −97 dBc 1 MHz −123 dBc



Integrated Phase Noise Integrated from 1 kHz to 100 MHz

700 MHz LO 0.20 °rms 2600 MHz LO 0.49 °rms 3500 MHz LO 0.55 °rms 5500 MHz LO 0.75 °rms

EXTERNAL LO INPUT Input Frequency fEXTLO 600 8000 MHz Input frequency must be 2×

the desired LO frequency Input Signal Power 0 3 6 dBm 50 Ω matching at the source

AD9371 Data Sheet


Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFERENCE CLOCK (DEV_CLK_IN

SIGNAL)

Frequency Range 10 320 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode

voltage (VCM) = 618 mV; for best spurious performance, use a <1 V p-p input clock

AUXILIARY CONVERTERS ADC

ADC Resolution 12 Bits Input Voltage

Minimum 0.25 V Maximum 3.05 V

DAC DAC Resolution 10 Bits Includes four offset levels Output Voltage

Minimum 0.5 V Reference voltage (VREF) = 1 V Maximum 3.0 V VREF = 2.5 V

Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS),

GPIO_x, RX1_ENABLE, RX2_ENABLE, TX1_ENABLE, TX2 ENABLE, SYNCINBx+, SYNCOUTB0+, GP_INTERRUPT, SDIO, SDO, SCLK, CSB, RESET

Logic Inputs Input Voltage

High Level VDD_IF × 0.8

VDD_IF V

Low Level 0 VDD_IF × 0.2

V

Input Current High Level −10 +10 μA Low Level −10 +10 μA

Logic Outputs Output Voltage

High Level VDD_IF × 0.8

V

Low Level VDD_IF × 0.2

V

Drive Capability 3 mA DIGITAL SPECIFICATIONS (LVDS),

SYSREF_INx, SYNCOUTB0±, SYNCINBx PAIRS

Logic Inputs Input Voltage Range 825 1675 mV Each differential input in the

pair Input Differential Voltage

Threshold −100 +100 mV

Receiver Differential Input Impedance

100 Ω Internal termination enabled

Data Sheet AD9371


Parameter Symbol Min Typ Max Unit Test Conditions/Comments Logic Outputs

Output Voltage High 1375 mV Low 1025 mV Differential 225 mV Offset 1200 mV

DIGITAL SPECIFICATIONS (CMOS), GPIO_3P3_x SIGNALS

Logic Inputs Input Voltage

High Level VDDA_3P3 × 0.8

VDDA_3P3 V

Low Level 0 VDDA_3P3 × 0.2

V

Input Current High Level −10 +10 μA Low Level −10 +10 μA

Logic Outputs Output Voltage

High Level VDDA_3P3 × 0.8

V

Low Level VDDA_3P3 × 0.2

V

Drive Capability 4 mA 1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,

VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. 2 Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation. 3 Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal. 4 Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal. 5 Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel. 6 dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting. 7 Continuous wave (CW) is a single frequency signal. 8 Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard

clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level. 9 Signal-to-noise ratio is limited by the baseband quantization noise.

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2. Parameter Min Typ Max Unit Test Conditions / Comments SUPPLY CHARACTERISTICS

VDDA_1P3 Analog Supplies1 1.267 1.3 1.33 V VDIG Supply 1.267 1.3 1.33 V VDDA_1P8 Supply 1.71 1.8 1.89 V VDD_IF Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range VDDA_3P3 Supply 3.135 3.3 3.465 V VDDA_SER, VDDA_DES,

JESD_VTT_DES Supplies 1.14 1.3 1.365 V

POSITIVE SUPPLY CURRENT (Rx MODE) Two Rx channels enabled, Tx upconverter disabled, 100 MHz Rx BW, 122.88 MSPS data rate

VDDA_1P3 Analog Supplies1 1055 mA VDIG Supply 625 mA Rx QEC2 enabled, QEC2 engine active VDD_IF Supply (CMOS and LVDS) 8 mA VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the

auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA VDDA_SER, VDDA_DES,

JESD_VTT_DES Supplies 375 mA

Total Power Dissipation 2.70 W

AD9371 Data Sheet


Parameter Min Typ Max Unit Test Conditions / Comments POSITIVE SUPPLY CURRENT (Tx MODE) Two Tx channels enabled, Rx downconverter disabled, 200 MHz

Tx BW, 245.76 MSPS data rate (ORx disabled) VDDA_1P3 Analog Supplies1 1000 mA VDIG Supply 410 mA Tx QEC2 active VDDA_1P8 Supply Full-scale CW3 405 mA Tx RF attenuation = 0 dB, 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 1 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the



Total Power Dissipation Typical supply voltages, Tx QEC2 active 3.70 W Tx RF attenuation = 0 dB 3.11 W Tx RF attenuation = 15 dB POSITIVE SUPPLY CURRENT (FDD MODE),

2× Rx, 2× Tx, ORx ACTIVE 100 MHz Rx BW, 122.88 MSPS data rate; 200 MHz Tx BW,

245.76 MSPS data rate; 200 MHz ORx BW, 245.76 MSPS data rate VDDA_1P3 Analog Supplies1 1700 mA VDIG Supply 1080 mA Tx QEC2 active VDDA_1P8 Supply Full-scale CW3 405 mA Tx RF attenuation = 0 dB 80 mA Tx RF attenuation = 15 dB VDD_IF Supply 8 mA VDDA_3P3 Supply 2 mA No auxiliary DACs or auxiliary ADCs enabled; if enabled, the



Total Power Dissipation Typical supply voltages, Tx QEC2 active 4.86 W Tx RF attenuation = 0 dB 4.27 W Tx RF attenuation = 15 dB MAXIMUM OPERATING JUNCTION

TEMPERATURE 110 °C Device designed for 10-year lifetime when operating at

maximum junction temperature 1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,

VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO. 2 QEC is the system for minimizing quadrature images of a desired signal. 3 Continuous wave (CW) is a single frequency signal.

TIMING SPECIFICATIONS Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SERIAL PERIPHERAL INTERFACE (SPI) TIMING

SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CSB Setup to First SCLK Rising Edge tSC 3 ns Last SCLK Falling Edge to CSB Hold tHC 0 ns SDIO Data Input Setup to SCLK tS 2 ns SDIO Data Input Hold to SCLK tH 0 ns SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode) tCO 3 8 ns Bus Turnaround Time After Baseband Processor (BBP) Drives

Last Address Bit tHZM tH tCO ns

Bus Turnaround Time After AD9371 Drives Last Address Bit tHZS 0 tCO ns DIGITAL TIMING

TXx_ENABLE Pulse Width 10 μs RXx_ENABLE Pulse Width 10 μs


Data Sheet AD9371


JESD204B DATA OUTPUT TIMING Unit Interval UI 162.76 1627.6 ps Data Rate per Channel (Nonreturn to Zero (NRZ)) 614.4 6144 Mbps Rise Time tR 24 35 ps 20% to 80% in 100 Ω load Fall Time tF 24 35 ps 20% to 80% in 100 Ω load Output Common-Mode Voltage VCM 0 1.8 V AC-coupled Termination Voltage (VTT) = 1.2 V 735 1135 mV DC-coupled Differential Output Voltage VDIFF 360 466 770 mV Short-Circuit Current IDSHORT −100 +100 mA Differential Termination Impedance ZRDIFF 80 100 120 Ω Total Jitter 17 48.8 ps Bit error rate (BER) = 10−15 Uncorrelated Bounded High Probability Jitter UBHPJ 1.2 24.4 ps Duty-Cycle Distortion DCD 3 8.1 ps SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal tS 2.5 ns See Figure 2 and Figure 3 SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal tH −1.5 ns See Figure 2 and Figure 3

JESD204B DATA INPUT TIMING Unit Interval UI 162.76 1627.6 ps Data Rate per Channel (NRZ) 614.4 6144 Mbps Input Common-Mode Voltage VCM 0.05 1.85 V AC-coupled VTT = 1.2 V 720 1200 mV DC-coupled Differential Input Voltage VDIFF 125 750 mV VTT Source Impedance ZTT 1.2 30 Ω Differential Termination Impedance ZRDIFF 80 106 120 Ω VTT

AC-Coupled 1.27 1.33 V DC-Coupled 1.14 1.26 V

Timing Diagrams

AT DEVICE PINS

DEV_CLK_IN

tH = –1.5nstS = +2.5ns

t'H = +0.5nst'S = +0.5ns

AT DIGITAL CORE

tH

tS

tH

tS t'Ht'St'H

DEV_CLK_IN DELAYIN REFERENCE TO SYSREF

CLK DELAY = 2ns 1465

1-00

2

Figure 2. SYSREF_IN Signal Setup and Hold Timing

DEV_CLK_IN

SYSREF_IN

VALID SYSREF_INtH = –1.5nstS = +2.5ns

tH

tS

tH

tS

tH

tS

tH

tS

INVALID SYSREF_IN

1465

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3

Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal

AD9371 Data Sheet


ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDDA_1P31 to VSSA −0.3 V to +1.4 V VDDA_SER, VDDA_DES, and

JESD_VTT_DES to VSSA −0.3 V to +1.4 V

VDIG to VSSD −0.3 V to +1.4 V VDDA_1P8 to VSSA −0.3 V to +2.0 V VDD_IF to VSSA −0.3 V to +3.0 V VDDA_3P3 to VSSA −0.3 V to +3.9 V Logic Inputs and Outputs to VSSD −0.3 V to VDD_IF + 0.3 V JESD204B Logic Outputs to VSSA −0.3 V to VDDA_SER JESD204B Logic Inputs to VSSA −0.3 V to VDDA_DES Input Current to Any Pin Except

Supplies ±10 mA

Maximum Input Power into RF Ports (Excluding Sniffer Receiver Inputs)

23 dBm (peak)

Maximum Input Power into SNRXA±, SNRXB±, and SNRXC±

2 dBm (peak)

Maximum Junction Temperature (TJ MAX) 110°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

1 VDDA_1P3 refers to all analog 1.3 V supplies: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_RXRF, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

REFLOW PROFILE The AD9371 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C.

THERMAL RESISTANCE Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required.

Table 5. Thermal Resistance

Package Airflow Velocity1 (m/sec) θJA

2, 3 (°C/W) θJC2, 4 (°C/W)

BC-196-12 JEDEC5 0.0 20.5 0.05

1.0 18.5 N/A6 2.5 17.2 N/A6

10-Layer PCB 0.0 14.1 0.05 1.0 12.4 N/A6 2.5 11.6 N/A6

1 Power dissipation is 3.0 W for all test cases. 2 Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board. 3 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 4 Per MIL-STD 883, Method 1012.1. 5 JEDEC entries refer to the JEDEC JESD51-9 (high K thermal test board). 6 N/A means not applicable.

ESD CAUTION


Data Sheet AD9371


PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VSSA

VSSA VSSA VSSA VSSA

VSSA

VSSA

VSSA VSSA

VSSA VSSA

VSSA

VSSA VSSAVSSA

VSSA

VSSA VSSAVSSA

VSSA VSSA VSSA VSSA

VSSA VSSA VSSA

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA

VSSA VSSA VSSA VSSAVSSA

VSSAVSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA

VSSAVSSA

VSSA

VSSAVSSA

VSSA

VSSAVSSA

VSSAVSSA

VSSA

VSSA

VSSAVSSAVSSA

VSSA

VSSAVSSA

VSSAVSSA

VSSA

VSSD

VSSA

VSSD

VSSA

VSSA

ORX2+ ORX2– RX2+ RX2– RX1+ RX1– ORX1+ ORX1–

RX_EXTLO– RX_EXTLO+

AUXADC_1 AUXADC_2

AUXADC_3

RBIAS

AUXADC_0TX_EXTLO– TX_EXTLO+DEV_CLK_IN+

DEV_CLK_IN–SNRXA+

SNRXA–

SNRXB+

SNRXB–

SNRXC+

SNRXC–

TX2+

TX2–

TX1–

TX1+

SYSREF_IN+ SYSREF_IN–

VDDA_RXRF

VSNRX_VCO_LDO

VDDA_SNRXVCO VDDA_RXLO VRX_

VCO_LDOVDDA_RXVCO

VDDA_3P3

VDDA_1P8

VDDA_BB

VDDA_RXTX

VDDA_CALPLL

VDDA_CLKSYNTH

VDDA_SNRXSYNTH

VDDA_TXSYNTH

VDD_IF

VDDA_RXSYNTH

VDDA_TXVCO VDDA_TXLO VTX_

VCO_LDO

VDIGVDIG

VCLK_VCO_LDO

VDDA_CLK VDDA_SER

VDDA_SER

VDDA_DES

JESD_VTT_DES SERDIN1+SERDIN1–SERDIN0+SERDIN0–

SERDIN3+SERDIN3–SERDIN2+SERDIN2–

SERDOUT0+SERDOUT0–SERDOUT1+SERDOUT1–

SERDOUT2+SERDOUT2–SERDOUT3+SERDOUT3–

SYNCINB0+SYNCINB0–

SYNCINB1+SYNCINB1–

SYNCOUTB0–SYNCOUTB0+GPIO_17 GPIO_16

GPIO_15 GPIO_8

GPIO_9GPIO_14

GPIO_10

GPIO_11

GPIO_13

GPIO_12

GPIO_0

GPIO_1

GPIO_3

GPIO_2

GPIO_4

GPIO_7

GPIO_5

GPIO_6

SDIO

SCLK

SDO

CSB

GPIO_18 RESET GP_INTERRUPT TEST

RX1_ENABLE

TX1_ENABLE

RX2_ENABLE

TX2_ENABLE

GPIO_3P3_5

GPIO_3P3_0 GPIO_3P3_1

GPIO_3P3_3

GPIO_3P3_4

GPIO_3P3_2

GPIO_3P3_10

GPIO_3P3_6

GPIO_3P3_11

GPIO_3P3_9

GPIO_3P3_8GPIO_3P3_7

1 4 7 8 11 142 3 5 6 9 10 12 13

A

G

K

L

P

J

H

B

M

N

C

D

E

F

ANALOGINPUT/OUTPUT

DIGITALINPUT/OUTPUT DC POWER GROUND

AD9371TOP VIEW

(Not to Scale)

1465

1-00

4

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions Pin No. Type1 Mnemonic Description A1, A4, A7, A8, A11, A14, B2 to B6, B9 to B13, C5, C9, C10, D6 to D9, E6, E9, E10, F3 to F10, G1 to G3, G5, G10 to G14, H2 to H10, H13, J2, J13, K1, K2, K13, K14, L1, L2, L13, L14, M2, M9, N2, N7, N14, P1, P2, P3, P10

I VSSA Analog ground.

A2, A3 I ORX2+, ORX2− Differential Input for Observation Receiver 2. Do not connect if these pins are unused.

A5, A6 I RX2+, RX2− Differential Input for Receiver 2. Do not connect if these pins are unused.

A9, A10 I RX1+, RX1− Differential Input for Receiver 1. Do not connect if these pins are unused.

AD9371 Data Sheet


Pin No. Type1 Mnemonic Description A12, A13 I ORX1+, ORX1− Differential Input for Observation Receiver 1. Do not

connect if these pins are unused. B1 I VDDA_RXRF 1.3 V Supply Input. B7, B8 I/O RX_EXTLO−, RX_EXTLO+ Differential Rx External LO Input/Output. If used for

external LO, the input frequency must be 2× the desired carrier frequency. Do not connect if these pins are unused.

B14 I VDDA_3P3 Supply Voltage for GPIO_3P3_x. C1, C2, C13, D1, D5, D12 to D14, E1, E14, F1, F14

I/O GPIO_3P3_0 to GPIO_3P3_11 General-Purpose Inputs and Outputs Referenced to 3.3 V Supply. See Figure 4 to match the ball location to the GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also function as auxiliary DAC outputs.

C3 O VSNRX_VCO_LDO Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 μF capacitor.

C4 I VDDA_SNRXVCO 1.3 V Supply Input for Sniffer VCO Low Dropout (LDO) Regulator.

C6 I VDDA_RXLO 1.3 V Supply for the Rx Synthesizer LO Generator. This pin is sensitive to aggressors.

C7 I VDDA_RXVCO 1.3 V Supply Input for Receiver VCO LDO Regulator. C8 O VRX_VCO_LDO Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 μF

capacitor. C11 I AUXADC_1 Auxiliary ADC 1 Input Pin. C12 I AUXADC_2 Auxiliary ADC 2 Input Pin. C14 N/A RBIAS Bias Resistor Connection. This pin generates an internal

current based on an external 1% resistor. Connect a 14.3 kΩ resistor between this pin and ground (VSSA).

D2, E2 I SNRXC−, SNRXC+ Differential Input for Sniffer Receiver Input C. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor.

D3, E3 I SNRXB−, SNRXB+ Differential Input for Sniffer Receiver Input B. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor.

D4, E4 I SNRXA−, SNRXA+ Differential Input for Sniffer Receiver Input A. If these pins are unused, connect to VSSA with a short or with a 1 kΩ resistor.

D10 I VDDA_1P8 1.8 V Tx Supply. D11 I AUXADC_3 Auxiliary ADC 3 Input Pin. E5 I VDDA_BB 1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs. E7, E8 I DEV_CLK_IN+, DEV_CLK_IN− Device Clock Differential Input. E11, E12 I/O TX_EXTLO−, TX_EXTLO+ Differential Tx External LO Input/Output. If these pins are

used for the external LO, the input frequency must be 2× the desired carrier frequency. Do not connect if these pins are unused.

E13 I AUXADC_0 Auxiliary ADC 0 Input Pin. F2 I VDDA_RXTX 1.3 V Supply Input for Tx/Rx Baseband Circuits,

Transimpedance Amplifier (TIA), Tx Transconductance (Gm), Baseband Filters, and Auxiliary DACs.

F11 I VDDA_TXVCO 1.3 V Supply Input for Transmitter VCO LDO Regulator. F12 I VDDA_TXLO 1.3 V Supply for the Tx Synthesizer LO Generator. This pin is

sensitive to aggressors. F13 O VTX_VCO_LDO Transmitter VCO LDO 1.1 V Output. Bypass this pin with a

1 μF capacitor. G4 I VDDA_CALPLL 1.3 V Supply Input for Calibration PLL Circuits. Use a

separate trace on the PCB back to a common supply point. G6 I VDDA_CLKSYNTH 1.3 V Clock Synthesizer Supply Input. This pin is sensitive

to aggressors. G7 I VDDA_SNRXSYNTH 1.3 V Sniffer Rx Synthesizer Supply Input. This pin is

sensitive to aggressors. G8 I VDDA_TXSYNTH 1.3 V Tx Synthesizer Supply Input. This pin is sensitive to

aggressors. G9 I VDDA_RXSYNTH 1.3 V Rx Synthesizer Supply Input. This pin is sensitive to

aggressors.

Data Sheet AD9371


Pin No. Type1 Mnemonic Description H1, J1 O TX2−, TX2+ Differential Output for Transmitter 2. H11, H12, J3, J7, J8, J11, J12, K5 to K8, K11, K12, L5, L6, L11, L12, M10, M11

I/O GPIO_0 to GPIO_18 General-Purpose Inputs and Outputs Referenced to VDD_IF. See Figure 4 to match the ball location to the GPIO_x signal name.

H14, J14 O TX1+, TX1− Differential Output for Transmitter 1. J4 I RESET Active Low Chip Reset.

J5 O GP_INTERRUPT General-Purpose Interrupt Signal. J6 I TEST Test Pin Used for JTAG Boundary Scan. Ground this pin if

unused. J9 I/O SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire

Mode. J10 O SDO Serial Data Output. K3, K4 I SYSREF_IN+, SYSREF_IN− LVDS SYSREF Clock Inputs for the JESD204B Interface. K9 I SCLK Serial Data Bus Clock. K10 I CSB Serial Data Bus Chip Select. Active low. L3, L4 I SYNCINB1−, SYNCINB1+ LVDS Sync Signal Associated with ORx/Sniffer Channel

Data on the JESD204B Interface. Alternatively, these pins can be set to a CMOS input using SYNCINB1+ as the input and connecting SYNCINB1− with a 1 kΩ resistor to GND.

L7, L10 I VSSD Digital Ground. L8, L9 I VDIG 1.3 V Digital Core Supply. Use a separate trace on the PCB

back to a common supply point. M1 O VCLK_VCO_LDO Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 μF

capacitor. M3, M4 I SYNCINB0−, SYNCINB0+ LVDS Sync Signal Associated with Rx Channel Data on the

JESD204B Interface. Alternatively, these pins can be set to a CMOS input using SYNCINB0+ as the input and connecting SYNCINB0− with a 1 kΩ resistor to GND.

M5 I RX1_ENABLE Enables Rx Channel 1 Signal Path. M6 I TX1_ENABLE Enables Tx Channel 1 Signal Path. M7 I RX2_ENABLE Enables Rx Channel 2 Signal Path. M8 I TX2_ENABLE Enables Tx Channel 2 Signal Path. M12 I VDD_IF CMOS/LVDS Interface Supply. M13, M14 O SYNCOUTB0+, SYNCOUTB0− LVDS Sync Signal Associated with Transmitter Channel

Data on the JESD Interface. Alternatively, these pins can be set to a CMOS output using SYNCOUTB0+ as the output while leaving SYNCOUTB0− floating.

N1 I VDDA_CLK 1.3 V Clock Supply Input. N3, N4 O SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. This

JESD204B lane can be used by the receiver data or by the sniffer/observation receiver data.

N5, N6 O SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. This JESD204B lane can be used by the receiver data or by the sniffer/observation receiver data.

N8, P8 I VDDA_SER JESD204B 1.3 V Serializer Supply Input. N9 I VDDA_DES JESD204B 1.3 V Deserializer Supply Input. N10, N11 I SERDIN2−, SERDIN2+ RF CML Differential Input 2. N12, N13 I SERDIN3−, SERDIN3+ RF CML Differential Input 3. P4, P5 O SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. This JESD204B lane can be

used by receiver data or by sniffer/observation receiver data. P6, P7 O SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. This JESD204B lane can be

used by receiver data or by sniffer/observation receiver data. P9 I JESD_VTT_DES JESD204B Deserializer Termination Supply Input. P11, P12 I SERDIN0−, SERDIN0+ RF CML Differential Input 0. P13, P14 I SERDIN1−, SERDIN1+ RF CML Differential Input 1. 1 I is input, O is output, I/O is input/output, and N/A is not applicable.

AD9371 Data Sheet


TYPICAL PERFORMANCE CHARACTERISTICS 700 MHz BAND Temperature settings refer to the die temperature. The die temperature is 40°C for single trace plots.

–30

–110

–100

–90

–80

–70

–60

–50

–40

300 400 500 600 700 800 900 1000

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

RECEIVER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-30

5

Figure 5. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

45

0

5

10

15

20

25

30

35

40

0 3 6 9 12 15

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-30

6

Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 700 MHz LO, 20 MHz Bandwidth, 30.72 MSPS Sample Rate, 20 MHz Integration Bandwidth

(Includes 1 dB Matching Circuit Loss)

30

0

5

10

15

20

25

300 400 500 600 700 800 900 1000

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+40°C–40°C

1465

1-30

7

Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, 20 MHz

Integration Bandwidth (Includes 1 dB Matching Circuit Loss)

100

0

10

20

30

40

50

60

70

80

90

0 3 6 9 12 15

REC

EIVE

R II

P2 (d

Bm

)

f1 OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-30

8

Figure 8. Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, f2 = f1 + 1 MHz, 30.72 MSPS Sample Rate

100

0

10

20

30

40

50

60

70

80

90

4 6 8 10 12

REC

EIVE

R II

P2 (d

Bm

)

INTERMODULATION FREQUENCY (MHz)

f2 – f1, +110°Cf2 – f1, +40°Cf2 – f1, –40°Cf2 + f1, +110°Cf2 + f1, +40°Cf2 + f1, –40°C

1465

1-30

9

Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 900 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

40

0

5

10

15

20

25

30

35

0 3 6 9 12 15

REC

EIVE

R II

P3 (d

Bm

)


+110°C+40°C–40°C

1465

1-31

0

Figure 10. Receiver IIP3 vs. F1 Offset Frequency, 900 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,

30.72 MSPS Sample Rate

Data Sheet AD9371


40

0

5

10

15

20

25

30

35

4 6 8 10 12

REC

EIVE

R II

P3 (d

Bm

)


f2 – 2f1, +110°Cf2 – 2f1, +40°Cf2 – 2f1, –40°Cf2 + 2f1, +110°Cf2 + 2f1, +40°Cf2 + 2f1, –40°C

1465

1-31

1


0

–110

–100

–90

–80

–70

–60

–50

–40

–20

–30

–10

0 5 10 15 20 25 30

REC

EIVE

R IM

AG

E (d

Bc)


+110°C+40°C–40°C

1465

1-31

2

Figure 12. Receiver Image vs. Receiver Attenuation, 800 MHz LO, Continuous Wave (CW) Signal 3 MHz Offset, 20 MHz RF Bandwidth, Background

Tracking Calibration (BTC) Active, 30.72 MSPS Sample Rate

25

–15

–10

–5

0

5

15

10

20

0 5 10 15 20 25 30

REC

EIVE

R G

AIN

(dB

)


+110°C+40°C–40°C

1465

1-31

3

Figure 13. Receiver Gain vs. Receiver Attenuation, 800 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

–40

–110

–100

–90

–80

–70

–60

–50

0 5 10 15 20 25 30

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

1465

1-31

4

Figure 14. Receiver DC Offset vs. Receiver Attenuation, 800 MHz LO, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

–40

–110

–100

–90

–80

–70

–60

–50

0 5 10 15 20 25 30

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-31

5

Figure 15. Receiver HD2 vs. Receiver Attenuation, 800 MHz LO, CW Signal 3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

–40

–110

–100

–90

–80

–70

–60

–50

0 5 10 15 20 25 30

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-31

6


AD9371 Data Sheet


0

–60

–50

–40

–30

–20

–10

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0

REC

EIVE

R E

VM (d

B)

RECEIVER INPUT POWER (dBm)

+110°C+40°C–40°C

1465

1-31

7Figure 17. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,

900 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active, 30.72 MSPS Sample Rate

–20

–120

–100

–80

–110

–90

–70

–60

–50

–40

–30

300 400 500 600 700 800 900 1000

Rx2

TO

Rx1

CR

OSS

TALK

(dB

)

RECEIVER LO FREQUENCY (MHz) 1465

1-31

8

Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO

30

0

5

10

15

20

25

–50 –45 –40 –35 –30 –25 –20

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

CLOSE-IN INTERFERER SIGNAL POWER (dBm)

+110°C+40°C–40°C

1465

1-31

9

Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power, 703 MHz LO, 709 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz,

20 MHz RF Bandwidth

30

0

5

10

15

20

25

–35 –30 –25 –20 –10 0–15 –5 5 10

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)

+110°C+40°C–40°C

1465

1-32

0

Figure 20. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power, 703 MHz LO, 901 MHz CW Interferer, NF Integrated Over 7 MHz to 10 MHz,

20 MHz RF Bandwidth

0

–100

–90

–80

–70

–60

–50

–40

–20

–30

–10

0 5 10 15 30

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-32

1

Figure 21. Transmitter Image vs. RF Attenuation, 20 MHz RF Bandwidth, 900 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run with

Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW 10 MHz Offset from LO, 3 dB Digital Backoff, 122.88 MSPS Sample Rate

0

–100

–90

–80

–70

–60

–50

–40

–20

–30

–10

–10 –5 0 5 10

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

DESIRED OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-32

2

Figure 22. Transmitter Image vs. Desired Offset Frequency, 20 MHz RF Bandwidth, 900 MHz LO, 0 dB RF Attenuation, Transmitter

QEC Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW Signal, 3 dB Digital Backoff, 122.88 MSPS Sample Rate

Data Sheet AD9371


10

–10

–8

–6

–4

–2

0

2

6

4

8

300 400 600 800500 700 900 1000

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-32

3

Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage Tracking Active, 10 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,


–60

–100

–95

–90

–85

–80

–75

–70

–65

0 5 10 15 20

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-32

4

Figure 24. Transmitter LO Leakage vs. RF Attenuation, 900 MHz LO, Transmitter QEC and External LO Leakage Tracking Active, CW Signal 5 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input Power to ORx Channel Is Not Held Constant, Performance Degrades As Shown in This Plot)

–60

–100

–95

–90

–85

–80

–75

–70

–65

–10 –5 0 5 10

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

OFFSET FREQUENCY (MHz)

900MHz, +110°C900MHz, +40°C900MHz, –40°C600MHz, +110°C600MHz, +40°C600MHz, –40°C300MHz, +110°C300MHz, +40°C300MHz, –40°C

1465

1-32

5

Figure 25. Transmitter LO Leakage vs. Offset Frequency, Transmitter QEC and External LO Leakage Tracking Active,

5 dB Digital Backoff, 1 MHz Measurement Bandwidth

–20

–120

–100

–80

–110

–90

–70

–60

–50

–40

–30

300 400 500 600 700 800 900 1000

Tx1

TO R

x1 C

RO

SSTA

LK (d

B)


1-32

6

Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 20 MHz Receiver RF Bandwidth, 20 MHz Transmitter RF Bandwidth,

CW Signal 3 MHz Offset from LO

–20

–120

–100

–80

–110

–90

–70

–60

–50

–40

–30

300 400 500 600 700 800 900 1000

Tx2

TO R

x2 C

RO

SSTA

LK (d

B)


1-32

7

Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 20 MHz Receiver RF Bandwidth, 20 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO

–20

–120

–100

–80

–110

–90

–70

–60

–50

–40

–30

300 400 500 600 700 800 900 1000

Tx2

TO T

x1 C

RO

SSTA

LK (d

B)

TRANSMITTER LO FREQUENCY (MHz) 1465

1-32

8

Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency, 20 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO

AD9371 Data Sheet


–80

–180

–160

–140

–170

–150

–130

–120

–110

–100

–90

0 5 10 15 20

TRA

NSM

ITTE

R N

OIS

E (d

Bm

/Hz)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-32

9Figure 29. Transmitter Noise vs. RF Attenuation, 800 MHz LO,

20 MHz Offset Frequency

–40

–80

–75

0 4 8 12 16 20

Tx A

DJA

CEN

T C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

Bc)

RF ATTENUATION (dB)

+110°C LOWER+40°C LOWER–40°C LOWER+110°C UPPER+40°C UPPER–40°C UPPER

–70

–65

–60

–55

–50

–45

1465

1-33

0

Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 900 MHz LO, 20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, Transmitter

QEC and LO Leakage Tracking Active

–40

–80

–75

0 4 8 12 16 20

Tx A

LTER

NA

TE C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

Bc)

RF ATTENUATION (dB)


–70

–65

–60

–55

–50

–45

1465

1-33

1

Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation, 900 MHz LO, 20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active

–60

–150

–130

–140

100 1k 10k 100k 1M 10M

LO P

HA

SE N

OIS

E (d

Bc)

OFFSET FREQUENCY (Hz)

–120

–110

–100

–90

–80

–70

1465

1-33

2

Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff, 710 MHz LO

1.0

0

0.2

0.4

0.1

0.3

0.5

0.6

0.7

0.8

0.9

300 400 500 600 700 800 900 1000

Tx IN

TEG

RA

TED

PH

ASE

NO

ISE

(Deg

rees

)

TRANSMITTER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-33

3

Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency, 20 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff

35

0

5

10

15

20

25

30

0 6 12 184 10 162 8 14 20

TRA

NSM

ITTE

R O

IP3

(dB

m)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-33

4

Figure 34. Transmitter OIP3 vs. RF Attenuation, 800 MHz LO, 20 MHz RF Bandwidth, f1 = 10 MHz, f2 = 11 MHz, 3 dB Digital Backoff,


Data Sheet AD9371


0

–100

–80

–60

–90

–70

–50

–40

–30

–20

–10

700 725 750 775 800 825 850 875 900

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz) 1465

1-33

5

Figure 35. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, 20 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,

LTE 10 MHz Signal, 800 MHz LO, 1 MHz Resolution Bandwidth, 122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded

0

–100

–80

–60

–90

–70

–50

–40

–30

–20

–10

300 400 500 600 700 800 900 11001000 1200 1300

Tx O

UTP

UT

(dB

m)


1-33

6



–20

–50

–45

–40

–35

–30

–25

0 4 8 12 16 20

TRA

NSM

ITTE

R E

VM (d

B)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-33

7

Figure 37. Transmitter EVM vs. RF Attenuation, 900 MHz LO, Transmitter LO Leakage and Transmitter QEC Tracking Active, 20 MHz RF

Bandwidth, LTE 20 MHz Downlink Signal, 122.88 MSPS Sample Rate

0

–100

–80

–60

–90

–70

–50

–40

–30

–20

–10

0 5 10 15 20 25 30

TRA

NSM

ITTE

R H

D2

(dB

c)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-33

8

Figure 38. Transmitter HD2 vs. RF Attenuation, 800 MHz LO, 810 MHz CW Desired Signal, 20 MHz RF Bandwidth,


0

–80

–60

–70

–50

–40

–30

–20

–10

0 5 10 15 20

TRA

NSM

ITTE

R H

D3

(dB

c)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-33

9



10

–20

–15

–10

–5

0

5

0 5 10 15 20

TRA

NSM

ITTE

R O

UTP

UT

POW

ER (d

Bm

)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-34

0

Figure 40. Transmitter Output Power vs. RF Attenuation, 800 MHz LO, 810 MHz CW Desired Signal, 20 MHz RF Bandwidth,


AD9371 Data Sheet


0.10

–0.10

–0.06

–0.02

–0.08

–0.04

0

0.02

0.04

0.06

0.08

0 5 10 15 20 25 30

Tx A

TTEN

UA

TIO

N S

TEP

ERR

OR

(dB

)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-34

1Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 800 MHz LO,

810 MHz CW Desired Signal, 20 MHz RF Bandwidth, 122.88 MSPS Sample Rate

0.5

–0.5

–0.3

–0.1

–0.4

–0.2

0

0.1

0.2

0.3

0.4

–50 –40 –20 0 20–30 –10 10 30 40 50

DEV

IATI

ON

FR

OM

FLA

TNES

S (d

B)

FREQUENCY OFFSET FROM LO (MHz) 1465

1-34

2

Figure 42. Transmitter Frequency Response Deviation from Flatness vs. Frequency Offset from LO, 800 MHz LO, 20 MHz RF Bandwidth,

6 dB Digital Backoff, 122.88 MSPS Sample Rate

–40

–100

–90

–80

–70

–60

–50

300 400 500 600 700 800 900 1000

OB

SER

VATI

ON

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

OBSERVATION RECEIVER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-34

3

Figure 43. Observation Receiver LO Leakage vs. Observation Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth,


30

0

5

10

15

20

25

300 400 500 600 700 800 900 1000

OB

SER

VATI

ON

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+40°C–40°C

1465

1-34

4

Figure 44. Observation Receiver Noise Figure vs. Observation Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth,

122.88 MSPS Sample Rate, 100 MHz Integration Bandwidth

80

0

10

20

30

40

50

60

70

0 30 60 90 10020 50 8010 40 70 110

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)


+110°C+40°C–40°C

1465

1-34

5

Figure 45. Observation Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,


80

0

10

20

30

40

50

60

70

0 20 35 50 5515 30 4510 25 40 60

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)


+110°C+40°C–40°C

1465

1-34

6

Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1), 900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,


Data Sheet AD9371


40

0

5

10

15

20

25

30

35

0 30 60 90 10020 50 8010 40 70 110

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)


+110°C+40°C–40°C

1465

1-34

7

Figure 47. Observation Receiver IIP3 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,


5 20 35 50 5515 30 4510 25 40 60INTERMODULATION FREQUENCY (MHz)

+110°C+40°C–40°C

40

0

5

10

15

20

25

30

35

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)

1465

1-34

8

Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency (2f2 − f1), 900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,


0

–120

–100

–80

–40

–60

–20

0 3 6 9 12 15 18

OB

SER

VATI

ON

REC

EIVE

R IM

AG

E (d

Bc)

OBSERVATION RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-34

9

Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation, 800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth, BTC Active,


25

–15

–10

–5

10

0

20

5

15

0 3 6 9 12 15 18

OB

SER

VATI

ON

REC

EIVE

R G

AIN

(dB

)


+110°C+40°C–40°C

1465

1-35

0

Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation, 800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth,


–40

–120

–110

–100

–90

–80

–70

–60

–50

0 3 6 9 12 15 18

OB

SER

VATI

ON

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

1465

1-35

1

Figure 51. Observation Receiver DC Offset vs. Observation Receiver Attenuation, 800 MHz LO, 100 MHz RF Bandwidth,


0

–120

–100

–80

–60

–40

–20

0 3 6 9 12 15 18

OB

SER

VATI

ON

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-35

2

Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation, 800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation,

Input Power Increasing Decibel for Decibel with Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate

AD9371 Data Sheet


0

–100

–90

–80

–70

–60

–50

–40

–20

–30

–10

0 3 6 9 12 15 18

OB

SER

VATI

ON

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-35

3Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation,

800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for Decibel with Attenuation,

100 MHz RF Bandwidth, 122.88 MSPS Sample Rate

–50

–130

–120

–110

–100

–90

–70

–80

–60

300 400 500 600 700

SNIF

FER

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

SNIFFER RECEIVER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-35

4

Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency, 0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

300 400 500 600 700

30

0

5

10

20

15

25

SNIF

FER

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+40°C–40°C

1465

1-35

5

Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency, 0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate,

20 MHz Integration Bandwidth

90

0

10

20

50

30

70

60

40

80

3 6 9 12 15

SNIF

FER

REC

EIVE

R II

P2 (d

Bm

)


+110°C+40°C–40°C

1465

1-35

6

Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1), 600 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

20

15

10

5

0

–5

–103 151296

SNIF

FER

REC

EIVE

R II

P3 (d

Bm

)


+110°C+40°C–40°C

1465

1-35

7

Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 600 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

0 5 10 15 20

SNIF

FER

REC

EIVE

R IM

AG

E (d

Bc)

SNIFFER RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

0

–100

–80

–60

–90

–70

–50

–40

–30

–20

–10

1465

1-35

8

Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,


Data Sheet AD9371


0 5 10 15 20

SNIF

FER

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

–40

–110

–100

–80

–60

–90

–70

–50

1465

1-35

9

Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, 600 MHz LO, CS Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation,


0 5 10 15 20

SNIF

FER

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

0

–100

–80

–60

–90

–70

–50

–40

–30

–20

–10

1465

1-36

0

Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 600 MHz LO, CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power Increasing

Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

0 5 10 15 20

SNIF

FER

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

0

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

1465

1-36

1

Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 600 MHz LO, CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power

Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

0

–60

–50

–40

–30

–20

–10

–70 –55 –50–65 –60 –45 –40 –35 –30 –25

SNIF

FER

REC

EIVE

R E

VM (d

B)

SNIFFER RECEIVER INPUT POWER (dBm)

+110°C+40°C–40°C

1465

1-36

2

Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,


40

–40

–30

–20

–10

0

20

10

30

0 12 164 8 20 24 28 32 36 40 4844 52

SNIF

FER

REC

EIVE

R G

AIN

(dB

)


+110°C+40°C–40°C

1465

1-36

3

Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation, 600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,


AD9371 Data Sheet


2.6 GHz BAND –30

–40

–50

–60

–70

–80

–90

–100

–110

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


+110°C+40°C–40°C

1465

1-00

5

Figure 64. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 40 MHz RF Bandwidth,


45

0

10

5

15

20

25

30

35

40

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

0 3 6 9 12 15RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-00

6

Figure 65. Receiver Noise Figure vs. Receiver Attenuation, 2600 MHz LO, 40 MHz Bandwidth, 122.88 MSPS Sample Rate, 20 MHz Integration

Bandwidth (Includes 1.4 dB Matching Circuit Loss)

30

0

5

10

15

20

25

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+40°C–40°C

1465

1-00

7

Figure 66. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate,

20 MHz Integration Bandwidth (Includes 1.4 dB Matching Circuit Loss)

100

0

30

20

10

40

50

60

70

80

90

REC

EIVE

R II

P2 (d

Bm

)

0 5 10 15 20 25 30f1 OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-00

8

Figure 67. Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO, 0 dB Attenuation, 40 MHz RF Bandwidth, f2 = f1 + 1 MHz,


100

0

30

20

10

40

50

60

70

80

90R

ECEI

VER

IIP2

(dB

m)


5 10 15 20 25 30INTERMODULATION FREQUENCY (MHz) 14

651-

009


40

0

15

10

5

20

25

30

35

REC

EIVE

R II

P3 (d

Bm

)

0 5 10 15 20 25 30f1 OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-01

0

Figure 69. Receiver IIP3 vs. f1 Offset Frequency, 2600 MHz LO, 0 dB Attenuation, 40 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz,


Data Sheet AD9371


40

0

15

10

5

20

25

30

35

REC

EIVE

R II

P3 (d

Bm

)

5 10 15 20 25 30INTERMODULATION FREQUENCY (MHz)

f2 – 2f1, +110°Cf2 – 2f1, +40°Cf2 – 2f1, –40°Cf2 + 2f1, +110°Cf2 + 2f1, +40°Cf2 + 2f1, –40°C

1465

1-01

1


–40

–100

–90

–80

–70

–60

–50

REC

EIVE

R IM

AG

E (d

Bc)

0 5 10 15 20 25 30RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-01

2

Figure 71. Receiver Image vs. Receiver Attenuation, 2600 MHz LO, Continuous Wave (CW) Signal 5 MHz Offset, 40 MHz RF Bandwidth,

Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate

25

–15

–10

0

10

20

–5

5

15

REC

EIVE

R G

AIN

(dB

)


+110°C+40°C–40°C

1465

1-01

3


–40

–120

–80

–60

–90

–100

–110

–70

–50

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

1465

1-01

4


–40

–110

–100

–80

–60

–90

–70

–50

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-01

5


–40

–110

–100

–80

–60

–90

–70

–50

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-01

6

Figure 75. Receiver HD3 vs. Receiver Attenuation, 2600 MHz LO, CW Signal 5 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for

Decibel with Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate

AD9371 Data Sheet


0

–45

–35

–20

–10

–25

–40

–30

–15

–5

REC

EIVE

R E

VM (d

B)

–60 –50 –40 –30 –20 –10 0–55 –45 –35 –25 –15 –5RECEIVER INPUT POWER (dBm)

+110°C+40°C–40°C

1465

1-01



0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Rx2

TO

Rx1

CR

OSS

TALK

(dB

)


1-01

8


30

0

5

10

15

20

25

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

–50 –45 –40 –35 –30 –25 –20CLOSE-IN INTERFERER SIGNAL POWER (dBm)

+110°C+40°C–40°C

1465

1-01

9

Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power, 2614 MHz LO, 2625 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz, 40 MHz RF Bandwidth

30

0

5

10

15

20

25

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

–40 –35 –30 –25 –20 –15 –10 –5 0OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)

+110°C+40°C–40°C

1465

1-02

0

Figure 79. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power, 2614 MHz LO, 2435 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz

0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

0 15105 20RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-02

1

Figure 80. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth, 2600 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run

with Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW 10 MHz Offset from LO, 3 dB Digital Backoff, 245.76 MSPS Sample Rate

0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

–20 100–10 205–5–15 15DESIRED OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-02

2

Figure 81. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF Bandwidth, 2300 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with

CW Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate

Data Sheet AD9371


10

6

8

4

–10

–8

–6

–4

–2

0

2

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-02

3

Figure 82. Tx Output Power, Transmitter QEC, and External LO Leakage Active, 5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,


–60

–100

–95

–85

–80

–70

–90

–75

–65

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

0 5 10 15 20RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-02

4

Figure 83. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO, External Transmitter QEC and LO Leakage Tracking Active, CW Signal 10 MHz

Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input Power to the ORx Channel Is Not Held Constant, Device Performance Degrades as Shown in This Figure)

–60

–100

–95

–85

–80

–70

–90

–75

–65

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

1.8GHz, +110°C1.8GHz, +40°C1.8GHz, –40°C2.3GHz, +110°C2.3GHz, +40°C2.3GHz, –40°C2.8GHz, +110°C2.8GHz, +40°C2.8GHz, –40°C

–30 –10 10–20 0 20 30OFFSET FREQUENCY (MHz) 14

651-

025

Figure 84. Transmitter LO Leakage vs. Offset Frequency, External Transmitter QEC and LO Leakage Tracking Active, 6 dB Digital Backoff,

1 MHz Measurement Bandwidth

0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Tx1

TO R

x1 C

RO

SSTA

LK (d

B)


1-02

6



0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Tx2

TO R

x2 C

RO

SSTA

LK (d

B)


1-02

7



0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Tx2

TO T

x1 C

RO

SSTA

LK (d

B)

TRANSMITTER LO FREQUENCY (MHz) 1465

1-02

8


AD9371 Data Sheet


–80

–180

–160

–130

–120

–100

–140

–170

–150

–110

–90

TRA

NSM

ITTE

R N

OIS

E (d

Bm

/Hz)


+110°C+40°C–40°C

1465

1-02


10 MHz Offset Frequency

–40

–80

–65

–70

–75

–60

–55

–50

–45

Tx A

DJA

CEN

T C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)

0 4 8 12 16 20RF ATTENUATION (dB)

+110°C UPPER+40°C UPPER–40°C UPPER+110°C LOWER+40°C LOWER–40°C LOWER

1465

1-03

0

Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,

Transmitter QEC and LO Leakage Tracking Active

–40

–80

–65

–70

–75

–60

–55

–50

–45

Tx A

LTER

NA

TE C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)



1465

1-03

1



LO P

HA

SE N

OIS

E (d

Bc)


–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

100 1k 10k 100k 1M 10M

1465

1-03

2

Figure 91. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff, 2600 MHz

1.0

0

0.2

0.3

0.1

0.4

0.5

0.6

0.7

0.8

0.9

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900

Tx IN

TEG

RA

TED

PH

ASE

NO

ISE

(Deg

rees

)


+110°C+40°C–40°C

1465

1-03

3

Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency, 40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,

3 dB Digital Backoff

35

0

5

10

15

20

25

30

TRA

NSM

ITTE

R O

IP3

(dB

m)

0 4 8 12 16 202 6 10 14 18RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-03

4



Data Sheet AD9371


0

–100

–90

–80

–70

–50

–30

–10

–60

–40

–20

Tx O

UTP

UT

(dB

m)

2500 2550 2600 2650 27002525 2575 2625 2675FREQUENCY (MHz) 14

651-

035

Figure 94. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, 40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active, LTE 10 MHz

Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth, 245.76 MSPS Sample Rate

0

–100

–90

–80

–70

–50

–30

–10

–60

–40

–20

Tx O

UTP

UT

(dB

m)

2100

2300

2500

2800

3100

2200

2400

2600

3000

2750

2900


1-03

6

Figure 95. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff, 40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,

LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth, 245.76 MSPS Sample Rate

–20

–50

–45

–40

–35

–30

–25

TRA

NSM

ITTE

R E

VM (d

B)


+110°C+40°C–40°C

1465

1-03

7

Figure 96. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter LO Leakage and Transmitter QEC Tracking Active, 200 MHz RF Bandwidth,

LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate

0

–20

–10

–30

–100

–90

–80

–70

–60

–50

–40

TRA

NSM

ITTE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-03

8



0

–20

–10

–30

–80

–70

–60

–50

–40

TRA

NSM

ITTE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-03

9



10

0

5

–5

–20

–15

–10

TRA

NSM

ITTE

R O

UTP

UT

POW

ER (d

Bm

)


+110°C+40°C–40°C

1465

1-04

0

Figure 99. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO, 2605MHz CW Desired Signal, 40 MHz RF Bandwidth,


AD9371 Data Sheet


0.10

0.04

0.08

0

–0.10

–0.08

–0.04

0.02

0.06

–0.02

–0.06

Tx A

TTEN

UA

TIO

N S

TEP

ERR

OR

(dB

)


+110°C+40°C–40°C

1465

1-04

1

Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO, 2610 MHz CW Desired Signal, 40 MHz RF Bandwidth,


0.5

–0.5

–0.4

–0.3

–0.2

0

0.2

0.4

–0.1

0.1

0.3

DEV

IATI

ON

FR

OM

FLA

TNES

S (d

B)

–100 –60 –20 40 100–80 –40 0 8020 60FREQUENCY OFFSET FROM LO (MHz) 14

651-

042



–40

–80

–75

–65

–60

–70

–50

–45

–55

OB

SER

VATI

ON

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900


+110°C+40°C–40°C

1465

1-04

3



30

0

5

10

20

25

15

OB

SER

VATI

ON

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

2900


+110°C+40°C–40°C

1465

1-04

4



80

0

10

20

30

40

60

50

70

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)

0 20 40 60 80 11010 30 50 70 90 100f1 OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-04

5



80

0

10

20

30

40

60

50

70

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)

5 25 45 65 85 11515 35 55 75 95 105INTERMODULATION FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-04

6



Data Sheet AD9371


40

0

5

10

15

20

30

25

35

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)

0 20 40 60 80 11010 30 50 70 90 100f1 OFFSET FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-04

7

Figure 106. Observation Receiver IIP3 vs. f1 Offset Frequency, 2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,

f2 = 2f1 + 1 MHz, 245.76 MSPS Sample Rate

40

0

5

10

15

20

30

25

35

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)

5 25 45 65 85 11515 35 55 75 95 105INTERMODULATION FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-04

8

Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,


0

–120

–100

–80

–60

–40

–20

OB

SER

VATI

ON

REC

EIVE

R IM

AG

E (d

Bc)

0 6 12 183 9 15OBSERVATION RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-04

9



25

–15

–10

–5

0

5

15

10

20

OB

SER

VATI

ON

REC

EIVE

R G

AIN

(dB

)


+110°C+40°C–40°C

1465

1-05

0

Figure 109. Observation Receiver Gain vs. Observation Receiver Attenuation, 2600 MHz LO, CW Signal 25 MHz Offset,


–40

–100

–90

–80

–70

–60

–50

OB

SER

VATI

ON

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

1465

1-05

1

Figure 110. Observation Receiver DC Offset vs. Observation Receiver Attenuation, 2600 MHz LO, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

0

–120

–100

–80

–60

–40

–20

OB

SER

VATI

ON

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-05

2



AD9371 Data Sheet


0

–120

–100

–80

–60

–40

–20

OB

SER

VATI

ON

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-05




–40

–120

–110

–100

–90

–80

–60

–70

–50

SNIF

FER

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

2300 2500 2700 28002400 2600SNIFFER RECEIVER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-05

4


30

0

5

10

20

15

25

SNIF

FER

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

2300 2500 2700 28002400 2600SNIFFER RECEIVER LO FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-05

5



90

0

10

20

60

40

80

50

30

70

SNIF

FER

REC

EIVE

R II

P2 (d

Bm

)

3 9 126INTERMODULATION FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-05

6


20

–10

5

–5

15

0

10

SNIF

FER

REC

EIVE

R II

P3 (d

Bm

)

0 8 124 6 102INTERMODULATION FREQUENCY (MHz)

+110°C+40°C–40°C

1465

1-05

7


0

–100

–90

–70

–40

–80

–50

–20

–60

–30

–10

SNIF

FER

REC

EIVE

R IM

AG

E (d

Bc)

0 2010 155SNIFFER RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-05

8

Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 2600 MHz LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate

Data Sheet AD9371


–40

–110

–100

–80

–90

–70

–50

–60

SNIF

FER

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

1465

1-05

9

Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, 2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,


0

–100

–90

–70

–80

–60

–20

–40

–50

–10

–30

SNIF

FER

REC

EIVE

R H

D2

(dB

c)


+110°C+40°C–40°C

1465

1-06

0

Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,


0

–120

–100

–40

–80

–20

–60

SNIF

FER

REC

EIVE

R H

D3

(dB

c)


+110°C+40°C–40°C

1465

1-06

1

Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,


0

–50

–45

–40

–15

–35

–5

–25

–20

–10

–30

SNIF

FER

REC

EIVE

R E

VM (d

B)

–70 –25–40–55 –45 –30–60 –50 –35–65SNIFFER RECEIVER INPUT POWER (dBm)

+110°C+40°C–40°C

1465

1-06

2

Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

BTC Active, 30.72 MSPS Sample Rate

40

–40

–30

0

–10

20

–20

10

30

SNIF

FER

REC

EIVE

R G

AIN

(dB

)

0 5236 4820 32 4412 28 404 24168SNIFFER RECEIVER ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-06

3



AD9371 Data Sheet


3.5 GHz BAND

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


–80

–75

–70

–65

–60

–55

–50

–45

–40

–35

–30

3300 3400 3500 3600 3700 3800

+110°C+40°C–40°C

1465

1-06

4

Figure 123. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


0

5

10

15

20

25

30

35

40

45+110°C+40°C–40°C

1465

1-06

5

Figure 124. Receiver Noise Figure vs. Receiver Attenuation, 3500 MHz LO, 100 MHz Bandwidth, 153.6 MSPS Sample Rate, 50 MHz Integration Bandwidth

(Includes 1 dB Matching Circuit Loss)

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


0

5

10

15

20

25

30

3300 3400 3500 3600 3700 3800

+110°C+40°C–40°C

1465

1-06

6

Figure 125. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate,

50 MHz Integration Bandwidth (Includes 1 dB Matching Circuit Loss)

REC

EIVE

R II

P2 (d

Bm

)


0

10

20

30

40

50

60

70

80

90

5 10 15 20 25 30 35 40 45 50 55 60

+110°C+40°C–40°C

1465

1-06

7



REC

EIVE

R II

P2 (d

Bm

)


0

10

20

30

40

50

60

70

80

90

100

5 10 15 20 25 30 35 40 45 50 55 60


1465

1-06

8


REC

EIVE

R II

P3 (d

Bm

)

f1 OFFSET FREQUENCY (MHz)5 10 15 20 25 30 35 40 45 50 55 60

0

5

10

15

20

25

30

35

40+110°C+40°C–40°C

1465

1-06

9

Figure 128. Receiver IIP3 vs. f1 Offset Frequency, 3500 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,


Data Sheet AD9371


REC

EIVE

R II

P3 (d

Bm

)

INTERMODULATION FREQUENCY (MHz)5 10 15 20 25 30 35 40 45 50 55 60

0

5

10

15

20

25

30

35

40f2 – f1, +110°Cf2 – f1, +40°Cf2 – f1, –40°Cf2 + f1, +110°Cf2 + f1, +40°Cf2 + f1, –40°C

1465

1-07

0


REC

EIVE

R IM

AG

E (d

Bc)


–110

–100

–90

–80

–70

–60

–50

–40+110°C+40°C–40°C

1465

1-07

1



REC

EIVE

R G

AIN

(dB

)


–15

–10

–5

0

5

10

15

20

25+110°C+40°C–40°C

1465

1-07

2

Figure 131. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO, CW Signal 17 MHz Offset, 100 MHz RF Bandwidth, De-Embedded to Receiver Port,


REC

EIVE

R D

C O

FFSE

T (d

BFS

)

RECEIVER ATTENUATION (dB)0 5 10 15 20 25 30

–120

–110

–100

–90

–80

–70

–60

–50

–40+110°C+40°C–40°C

1465

1-07

3


REC

EIVE

R H

D2

(dB

c)


–110

–100

–90

–80

–70

–60

–50

–40+110°C+40°C–40°C

1465

1-07

4


REC

EIVE

R H

D3

(dB

c)


–110

–100

–90

–80

–70

–60

–50

–40+110°C+40°C–40°C

1465

1-07

5

Figure 134. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO, CW Signal 17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel

for Decibel with Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate

AD9371 Data Sheet


REC

EIVE

R E

VM (d

B)


–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0

+110°C+40°C–40°C

1465

1-07



Rx2

TO

Rx1

CR

OSS

TALK

(dB

)


–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

3300 3400 3500 3600 3700 3800

1465

1-07

7


REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

CLOSE-IN INTERFERER SIGNAL POWER (dBm)

10

12

14

16

18

20

22

24

26

28

30

–50 –45 –40 –35 –30 –25 –20

1465

1-07

8

+110°C+40°C–40°C

Figure 137. Receiver Noise Figure vs. Close-In Interferer Signal Power, 3614 MHz LO, 3625 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz, 100 MHz RF Bandwidth

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


0

5

10

15

20

25

30

–30 –25 –20 –15 –10 –5 0

1465

1-07

9

+110°C+40°C–40°C

Figure 138. Receiver Noise Figure vs. Out of Band Interferer Signal Power, 3614 MHz LO, 3665 MHz CW Interferer, Noise Figure Integrated over

7 MHz to 10 MHz

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-08

0

Figure 139. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth, 3550 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run

with Two 20 MHz, LTE Downlink Carriers, Then Image Measured with CW 10 MHz Offset from LO, 6 dB Digital Backoff, 307.2 MSPS Sample Rate

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

DESIRED OFFSET FREQUENCY (MHz)–50 –40 –30 –20 –10 0 10 20 30 40 50

+110°C+40°C–40°C

1465

1-08

1



Data Sheet AD9371


Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

–10

–8

–6

–4

–2

0

2

4

6

8

10

3300 3400 3500 3600 3700 3800

+110°C+40°C–40°C

1465

1-08

2

Figure 141. Tx Output Power, Transmitter QEC and External LO Leakage Active, 5 MHz CW Offset Signal,

1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate

0 5 10 15 20

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

RF ATTENUATION (dB)

–95

–90

–85

–80

–75

–70

–65

–60

–100

+110°C+40°C–40°C

1465

1-08

3

Figure 142. Transmitter LO Leakage vs. RF Attenuation, 3550 MHz LO, Transmitter QEC and External LO Leakage Tracking Active, CW Signal 10 MHz

Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input Power to ORx Channel Is Not Held Constant,

Performance Degrades as Shown in This Plot)

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)


3.3GHz, +110°C3.3GHz, +40°C3.3GHz, –40°C3.55GHz, +110°C3.55GHz, +40°C3.55GHz, –40°C3.8GHz, +110°C3.8GHz, +40°C3.8GHz, –40°C

–30 –20 –10 0 10 20 30

1465

1-08

4

Figure 143. Transmitter LO Leakage vs. Offset Frequency, Transmitter QEC and External LO Leakage Tracking Active,


Tx1

TOR

x1C

RO

SSTA

LK(d

B)


–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

3300 3400 3500 3600 3700 3800

1465

1-08

5



0

–1003300 3400 3500 3600 3700 3800

Tx2

TO R

x2 C

RO

SSTA

LK (d

B)


–90

–80

–70

–60

–50

–40

–30

–20

–10

1465

1-08

6



0

–1003300 3800

Tx2

TO T

x1 C

RO

SSTA

LK (d

B)

TRANSMITTER LO FREQUENCY (MHz)3400 3500 3600 3700

–90

–80

–70

–60

–50

–40

–30

–20

–10

1465

1-08

7


AD9371 Data Sheet


–80

–180

TRA

NSM

ITTE

R N

OIS

E (d

Bm

/Hz)

–170

–160

–150

–140

–130

–120

–110

–100

–90

0 205 10 15RF ATTENUATION (dB)

+110°C+40°C–40°C

1465

1-08


100 MHz Offset Frequency, Zeros Input Data

0 205 10 15

–40

–80

Tx A

DJA

CEN

T C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)

RF ATTENUATION (dB)

–75

–70

–65

–60

–55

–50

–45


1465

1-08

9

Figure 148. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,


–40

–800 20

Tx A

LTER

NA

TE C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)

RF ATTENUATION (dB)

–75

–70

–65

–60

–55

–50

–45

5 10 15


1465

1-09

0



–60

–150100 10M

LO P

HA

SE N

OIS

E (d

Bc)


–140

–130

–120

–110

–100

–90

–80

–70

1k 10k 100k 1M

1465

1-09

1


1.0

03300 3800

Tx IN

TEG

RA

TED

PH

ASE

NO

ISE

(Deg

rees

)


0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

3400 3500 3600 3700

+110°C+40°C–40°C

1465

1-09

2


35

00 20

TRA

NSM

ITTE

R O

IP3

(dB

m)

RF ATTENUATION (dB)

5

10

15

20

25

30

2 4 6 8 10 12 14 16 18

+110°C+40°C–40°C

1465

1-09

3



Data Sheet AD9371


3400 3600FREQUENCY (MHz)

0

–100

Tx O

UTP

UT

(dB

m)

–90

–80

–70

–60

–50

–40

–30

–20

–10

3425 3450 3475 3500 3525 3550 3575

1465

1-09

4


LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate

0

–1003000 4000

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

–90

–80

–70

–60

–50

–40

–30

–20

–10

3100 3200 3300 3400 3500 3600 3700 3800 3900

1465

1-09

5


LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate (Noise Floor Includes Test Equipment Response)

–20

–500 20

TRA

NSM

ITTE

R E

VM (d

B)

RF ATTENUATION (dB)

–45

–40

–35

–30

–25

5 10 15

+110°C+40°C–40°C

1465

1-09

6

Figure 155. Transmitter EVM vs. RF Attenuation, 3500 MHz LO, Transmitter LO Leakage, and Transmitter QEC Tracking Active,

100 MHz RF Bandwidth, LTE 20 MHz Downlink Signal, 307.2 MSPS Sample Rate

0

–1000 20

TRA

NSM

ITTE

R H

D2

(dB

c)

RF ATTENUATION (dB)

–90

–80

–70

–60

–50

–40

–30

–20

–10

5 10 15

+110°C+40°C–40°C

1465

1-09

7



0

–800 20

TRA

NSM

ITTE

R H

D3

(dB

c)

RF ATTENUATION (dB)

–70

–60

–50

–40

–30

–20

–10

5 10 15

+110°C+40°C–40°C

1465

1-09

8



10

–250 20

TRA

NSM

ITTE

R O

UTP

UT

POW

ER (d

Bm

)

RF ATTENUATION (dB)

–20

–15

–10

–5

0

5

5 10 15

+110°C+40°C–40°C

1465

1-09

9



AD9371 Data Sheet


0.10

–0.100 20

Tx A

TTEN

UA

TIO

N S

TEP

ERR

OR

(dB

)

RF ATTENUATION (dB)

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

2 4 6 8 10 12 14 16 18

+110°C+40°C–40°C

1465

1-10

0

Figure 159. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO, 3510 MHz CW Desired Signal, 100 MHz RF Bandwidth,

De-Embedded to Transmitter Port, 307.2 MSPS Sample Rate

1.0

–1.0–100 100

DEV

IATI

ON

FR

OM

FLA

TNES

S (d

B)

FREQUENCY OFFSET FROM LO (MHz)

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

–80 –60 –40 –20 0 20 40 60 80

1465

1-10

1



–40

–803300 3800

OB

SER

VATI

ON

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


–75

–70

–65

–60

–55

–50

–45

3400 3500 3600 3700

+110°C+40°C–40°C

1465

1-10

2



30

03300 3800

OB

SER

VATI

ON

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


5

10

15

20

25

3400 3500 3600 3700

+110°C+40°C–40°C

1465

1-10

3



80

00 110

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)


10

20

30

40

50

60

70

10 20 30 40 50 60 70 80 90 100

+110°C+40°C–40°C

1465

1-10

4



80

05 115

OB

SER

VATI

ON

REC

EIVE

R II

P2 (d

Bm

)

INTERMODULATION FREQUENCY (MHz)15 25 35 45 55 65 75 85 95 105

10

20

30

40

50

60

70

+110°C+40°C–40°C

1465

1-10

5



Data Sheet AD9371


40

00 110

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)


5

10

15

20

25

30

35

10 20 30 40 50 60 70 80 90 100

+110°C+40°C–40°C

1465

1-10

6

Figure 165. Observation Receiver IIP3 vs. f1 Offset Frequency, 3600 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,


40

05 115

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)


5

10

15

20

25

30

35

15 25 35 45 55 65 75 85 95 105

+110°C+40°C–40°C

1465

1-10

7



0

–1000 18

OB

SER

VATI

ON

REC

EIVE

R IM

AG

E (d

Bc)


–90

–80

–70

–60

–50

–40

–30

–20

–10

3 6 9 12 15

+110°C+40°C–40°C

1465

1-10

8



25

–150 18

OB

SER

VATI

ON

REC

EIVE

R G

AIN

(dB

)


–10

–5

0

5

10

15

20

3 6 9 12 15

+110°C+40°C–40°C

1465

1-10

9

Figure 168. Observation Receiver Gain vs. Observation Receiver Attenuation, 3500 MHz LO, CW Signal 25 MHz Offset, 240 MHz RF Bandwidth,

De-Embedded to Receiver Port, 307.2 MSPS Sample Rate

–40

–1100 18

OB

SER

VATI

ON

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


–100

–90

–80

–70

–60

–50

3 6 9 12 15

+110°C+40°C–40°C

1465

1-11

0

Figure 169. Observation Receiver DC Offset vs. Observation Receiver Attenuation, 3500 MHz LO, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate

0

–1200 18

OB

SER

VATI

ON

REC

EIVE

R H

D2

(dB

c)


–100

–80

–60

–40

–20

3 6 9 12 15

+110°C+40°C–40°C

1465

1-11

1



AD9371 Data Sheet


0

–1000 18

OB

SER

VATI

ON

REC

EIVE

R H

D3

(dB

c)


–90

–80

–70

–60

–50

–40

–30

–20

–10

3 6 9 12 15

+110°C+40°C–40°C

1465

1-11




–40

–120

SNIF

FER

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


–110

–100

–90

–80

–70

–60

–50

3300 38003400 3500 3600 3700

+110°C+40°C–40°C

1465

1-11

3


20

03300 3800

SNIF

FER

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

SNIFFER RECEIVER LO FREQUENCY (MHz)3400 3500 3600 3700

2

4

6

8

10

12

14

16

18+110°C+40°C–40°C

1465

1-11

4



90

02 18

SNIF

FER

REC

EIVE

R II

P2 (d

Bm

)


10

20

30

40

50

60

70

80

6 10 14

+110°C+40°C–40°C

1465

1-11

5


20

–100 12

SNIF

FER

REC

EIVE

R II

P3 (d

Bm

)


–5

0

5

10

15

2 4 6 8 10

+110°C+40°C–40°C

1465

1-11

6


0

–1000 50

SNIF

FER

REC

EIVE

R IM

AG

E (d

Bc)


–90

–80

–70

–60

–50

–40

–30

–20

–10

5 10 15 20 25 30 35 40 45

+110°C+40°C–40°C

1465

1-11

7

Figure 176. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 3500 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,


Data Sheet AD9371


–40

–1100 20

SNIF

FER

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


–100

–90

–80

–70

–60

–50

5 10 15

+110°C+40°C–40°C

1465

1-11

8

Figure 177. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation, 3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,


0

–1000 20

SNIF

FER

REC

EIVE

R H

D2

(dB

c)


–90

–80

–70

–60

–50

–40

–30

–20

–10

5 10 15

+110°C+40°C–40°C

1465

1-11

9



0

–100

–90

–80

–70

–60

–50

–40

–30

–20

0 20

SNIF

FER

REC

EIVE

R H

D3

(dB

c)


–10

5 10 15

+110°C+40°C–40°C

1465

1-12

0



0

–45–70 –30

SNIF

FER

REC

EIVE

R E

VM (d

B)

SNIFFER RECEIVER INPUT POWER (dBm)

–40

–35

–30

–25

–20

–15

–10

–5

–65 –60 –55 –50 –45 –40 –35

+110°C+40°C–40°C

1465

1-12

1

Figure 180. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,

BTC Active, 38.4 MSPS Sample Rate

35

–350 55

SNIF

FER

REC

EIVE

R G

AIN

(dB

)


–25

–15

–5

5

15

25

5 10 15 20 25 30 35 40 45 50

+110°C+40°C–40°C

1465

1-12

2


De-Embedded to Receiver Port, 38.4 MSPS Sample Rate

AD9371 Data Sheet


5.5 GHz BAND –30

–1005300 5900

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


–90

–80

–70

–60

–50

–40

5400 5500 5600 5700 5800

+110°C+40°C–40°C

1465

1-22

3Figure 182. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate

45

00 15

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


5

10

15

20

25

35

30

40

3 6 9 12

+110°C+40°C–40°C

1465

1-22

4

Figure 183. Receiver Noise Figure vs. Receiver Attenuation, 5600 MHz LO, 100 MHz Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Integration

Bandwidth (Includes 1.2 dB Matching Circuit Loss)

30

05300 5900

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


5

10

15

20

25

5400 5500 5600 5700 5800

+110°C+40°C–40°C

1465

1-22

5

Figure 184. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 50 MHz

Integration Bandwidth (Includes 1.2 dB Matching Circuit Loss)

100

90

80

70

60

50

40

30

20

10

00 60

REC

EIVE

R II

P2 (d

Bm

)

f1 OFFSET FREQUENCY (MHz)20 4010 30 50

+110°C+40°C–40°C

1465

1-18

5



100

015 45

REC

EIVE

R II

P2 (d

Bm

)


10

30

50

70

90

20

40

60

80

20 25 30 35 40

f2 + f1, +110°Cf2 + f1, +40°Cf2 + f1, –40°Cf2 – f1, +110°Cf2 – f1, +40°Cf2 – f1, –40°C

1465

1-22

6


40

35

30

25

20

15

10

5

00 60

REC

EIVE

R II

P3 (d

Bm

)

f1 OFFSET FREQUENCY (MHz)20 4010 30 50

+110°C+40°C–40°C

1465

1-18

7

Figure 187. Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz, 122.88 MSPS Sample Rate

Data Sheet AD9371


40

010 15 35

REC

EIVE

R II

P3 (d

Bm

)


10

20

5

15

25

30

35

20 25 30

+110°C+40°C–40°C

1465

1-22

7


–40

–1000 30

REC

EIVE

R IM

AG

E (d

Bc)


–80

–90

–70

–60

–50

5 15 2510 20

+110°C+40°C–40°C

1465

1-22

8



20

–200 30

REC

EIVE

R G

AIN

(dB

)


–10

–15

–5

5

15

0

10

5 15 2510 20

+110°C+40°C–40°C

1465

1-22

9


–40

–1100 30

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


–90

–100

–80

–60

–70

–50

5 15 2510 20

+110°C+40°C–40°C

1465

1-23

0


–40

–1100 30

REC

EIVE

R H

D2

(dB

c)


–90

–100

–80

–60

–70

–50

5 15 2510 20

+110°C+40°C–40°C

1465

1-23

1

Figure 192. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO, CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,


–40

–1100 30

REC

EIVE

R H

D3

(dB

c)


–90

–100

–80

–60

–70

–50

5 15 2510 20

+110°C+40°C–40°C

1465

1-23

2

Figure 193. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO, CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power

Increasing Decibel for Decibel with Attenuation,100 MHz RF Bandwidth, 122.88 MSPS Sample Rate

AD9371 Data Sheet


0

–45–55 0

REC

EIVE

R E

VM (d

B)


–35

–40

–30

–15

–25

–5

–20

–10

–45 –25 –5–35 –15–50 –30 –10–40 –20

+110°C+40°C–40°C

1465

1-23


5600 MHz LO, 100 MHz RF Bandwidth LTE, 20 MHz Uplink Centered at DC, BTC Active, 122.88 MSPS Sample Rate

0

–1005300 5900

Rx2

TO

Rx1

CR

OSS

TALK

(dB

)


–70

–80

–90

–60

–30

–50

–10

–40

–20

5500 57005400 58005600

1465

1-23

4


30

0–40 0

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


15

5

25

10

20

–25 –5–35 –15–30 –10–20

+110°C+40°C–40°C

1465

1-23

5

Figure 196. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power, 5400 MHz LO, 5600 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz

0

–1000 20

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

RF ATTENUATION (dB)

–70

–80

–90

–60

–30

–50

–10

–40

–20

105 15

+110°C+40°C–40°C

1465

1-23

6

Figure 197. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth, 5600 MHz LO, 0 dB RF Attenuation, Transmitter Quadrature Error Correction

(QEC) Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW 10 MHz Offset from LO, 3 dB Digital Backoff,


0

–100–40 40

TRA

NSM

ITTE

R IM

AG

E (d

Bc)

DESIRED OFFSET FREQUENCY (MHz)

–70

–80

–90

–60

–30

–50

–10

–40

–20

0–20 20 30–10–30 10

+110°C+40°C–40°C

1465

1-23

7



10

–105300 5900

Tx O

UTP

UT

(dB

m)


–8

–4

0

4

8

–6

–2

2

6

5400 5500 5600 5700 5800

+110°C+40°C–40°C

1465

1-23

8

Figure 199. Tx Output Power, Transmitter QEC, and External LO Leakage Active, 5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,


Data Sheet AD9371


–40

–1000 20

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)

RF ATTENUATION (dB)

–90

–70

–80

–60

–50

5 10 15

+110°C+40°C–40°C

1465

1-23

9

Figure 200. Transmitter LO Leakage vs. RF Attenuation, 5600 MHz LO, External Transmitter QEC, and LO Leakage Tracking Active, CW Signal

10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth

–60

–100–40 40

TRA

NSM

ITTE

R L

O L

EAK

AG

E (d

BFS

)


–90

–75

–80

–95

–85

–70

–65

–20 0 20 30–30 –10 10

5.9GHz, +110°C5.9GHz, +40°C5.9GHz, –40°C5.6GHz, +110°C5.6GHz, +40°C5.6GHz, –40°C

5.3GHz, +110°C5.3GHz, +40°C5.3GHz, –40°C

1465

1-24

0

Figure 201. Transmitter LO Leakage vs. Offset Frequency, External Transmitter QEC and LO Leakage Tracking Active,


0

–1005300 5900

Tx1

TO R

x1 C

RO

SSTA

LK (d

B)


–90

–70

–50

–30

–10

–80

–60

–40

–20

5400 5500 5600 5700 5800

1465

1-24

1

Figure 202. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver RF Bandwidth, 75 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO

0

–1005300 5900

Tx2

TO R

x2 C

RO

SSTA

LK (d

B)


–90

–70

–50

–30

–10

–80

–60

–40

–20

5400 5500 5600 5700 5800

1465

1-24

2



–110

–100

5300 5900

Tx2

TO T

x1 C

RO

SSTA

LK (d

B)


–90

–70

–50

–30

–10

–80

–60

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5400 5500 5600 5700 5800

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NSM

ITTE

R N

OIS

E (d

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RF ATTENUATION (dB)

–170

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–90

5 10 15

+110°C+40°C–40°C

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Figure 205. Transmitter Noise vs. RF Attenuation, 5600 MHz LO, 1 MHz Offset Frequency

AD9371 Data Sheet


–40

–800 20

TxA

DJA

CEN

T C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)

RF ATTENUATION (dB)

–70

–60

–50

–65

–75

–55

–45

5 10 15


1465

1-24

5Figure 206. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,

5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, Transmitter QEC and LO Leakage Tracking Active

–40

–800 20

TxA

LTER

NA

TE C

HA

NN

EL L

EAK

AG

E R

ATI

O (d

B)

RF ATTENUATION (dB)

–70

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–50

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–55

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5 10 15


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–60

–150100 10M

LO P

HA

SE N

OIS

E (d

Bc)


–120

–100

–80

–110

–140

–130

–90

–70

1k 100k10k 1M

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1-24

7


1.0

05300 5900

Tx IN

TEG

RA

TED

PH

ASE

NO

ISE

(Deg

rees

)


0.1

0.3

0.5

0.7

0.9

0.2

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5400 5500 5600 5700 5800

+110°C+40°C–40°C

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30

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TRA

NSM

ITTE

R O

IP3

(dB

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RF ATTENUATION (dB)

10

20

5

15

25

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+110°C+40°C–40°C

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9



0

–1005750 5950

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

–90

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5775 5800 5825 5850 59005875 5925

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Data Sheet AD9371


0

–1005350 6350

Tx O

UTP

UT

(dB

m)

FREQUENCY (MHz)

–90

–70

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–10

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5450 5550 5650 5750 59505850 61506050 6250

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TRA

NSM

ITTE

R E

VM (d

B)

RF ATTENUATION (dB)

–45

–35

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–30

–25

5 10 15

+110°C+40°C–40°C

1465

1-25

2

Figure 213. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter LO Leakage, and Transmitter QEC Tracking Active, 75 MHz RF Bandwidth,

LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate

0

–1000 20

TRA

NSM

ITTE

R H

D2

(dB

c)

RF ATTENUATION (dB)

–70

–80

–90

–60

–30

–50

–10

–40

–20

105 15

+110°C+40°C–40°C

1465

1-25

3

Figure 214. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO, 5855 MHz CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate

0

–800 20

TRA

NSM

ITTE

R H

D3

(dB

c)

RF ATTENUATION (dB)

–70

–60

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–50

–10

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105 15

+110°C+40°C–40°C

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1-25

4



10

–200 2520

TRA

NSM

ITTE

R O

UTP

UT

POW

ER (d

Bm

)

RF ATTENUATION (dB)

–5

–15

5

–10

0

105 15

+110°C+40°C–40°C

1465

1-25

5



0.10

–0.100 20

Tx A

TTEN

UA

TIO

N S

TEP

ERR

OR

(dB

)

RF ATTENUATION (dB)

–0.02

–0.04

–0.08

0.08

–0.06

0.02

0.06

0.04

0

105 15

+110°C+40°C–40°C

1465

1-25

6

Figure 217. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO, 5855 MHz CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate

AD9371 Data Sheet


0.5

–0.5–100 100

DEV

IATI

ON

FR

OM

FLA

TNES

S (d

B)

FREQUENCY OFFSET FROM LO (MHz)

–0.1

–0.2

–0.4

0.4

–0.3

0.1

0.3

0.2

0

20–40 800–60 60–20–80 40

1465

1-25

7Figure 218. Transmitter Frequency Response Deviation from Flatness vs. Frequency Offset from LO, 5850 MHz LO, 200 MHz Synthesis Bandwidth,


–40

–805300 5900

OB

SER

VATI

ON

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


–75

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5400 5500 5600 5700 5800

+110°C+40°C–40°C

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8



30

05300 5900

OB

SER

VATI

ON

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


5

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20

5400 5500 5600 5700 5800

+110°C+40°C–40°C

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00 10 110

OB

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ON

REC

EIVE

R II

P2 (d

Bm

)


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REC

EIVE

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P2 (d

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)


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2

40

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25

20

15

10

5

00 110100908070605040302010

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)


+110°C+40°C–40°C

Figure 223. Observation Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,


Data Sheet AD9371


40

05 115

OB

SER

VATI

ON

REC

EIVE

R II

P3 (d

Bm

)


5

15

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+110°C+40°C–40°C

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ON

REC

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AG

E (d

Bc)


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63 129 15

+110°C+40°C–40°C

1465

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Figure 225. Observation Receiver Image vs. Observation Receiver Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset,

200 MHz RF Bandwidth, BTC Active, 245.76 MSPS Sample Rate

25

–150 18

OB

SER

VATI

ON

REC

EIVE

R G

AIN

(dB

c)


–10

–5

10

0

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5

15

63 129 15

+110°C+40°C–40°C

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Figure 226. Observation Receiver Gain vs. Observation Receiver Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset,


–40

–50

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–80

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–10

–1100 181512963

OB

SER

VATI

ON

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


+110°C+40°C–40°C

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4

Figure 227. Observation Receiver DC Offset vs. Observation Receiver Attenuation, 5850 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input,


0

–1000 18

OB

SER

VATI

ON

REC

EIVE

R H

D2

(dB

c)


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63 129 15

+110°C+40°C–40°C

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5

Figure 228. Observation Receiver HD2 vs. Observation Receiver Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power


0

–120

–100

0 18

OB

SER

VATI

ON

REC

EIVE

R H

D3

(dB

c)


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63 129 15

+110°C+40°C–40°C

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6

Figure 229. Observation Receiver HD3 vs. Observation Receiver Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power


AD9371 Data Sheet


THEORY OF OPERATION The AD9371 is a highly integrated RF transceiver that can be configured for a wide range of applications. The device integrates all the RF, mixed-signal, and digital blocks necessary to provide transmit and receive functions in a single device. Programmability allows the two receiver channels and two transmitter channels to be used in TDD and FDD systems for 3G and 4G cellular standards.

The observation receiver channel has two inputs for use in monitoring the transmitter outputs. This channel has a wide channel bandwidth that receives the entire transmit band and feeds it back to the digital section for error correction purposes. In addition, three sniffer receiver inputs can monitor different radio frequency bands (one at a time). These channels share the baseband ADC and digital processing with the two ORx inputs.

The AD9371 contains four high speed serial interface links for the transmit chain and four high speed serial interface links shared by the Rx, ORx, and SnRx channels (JESD204B, Subclass 1 compliant), providing a low pin count and reliable data interface to a field-programmable gate array (FPGA) or other custom integrated baseband solutions.

The AD9371 also provides self calibration for dc offset, LO leakage, and quadrature error correction using an integrated microcontroller core to maintain a high performance level under varying temperatures and input signal conditions. Firmware is supplied with the device to schedule all calibrations with no user interaction. The device includes test modes that allows system designers to debug designs during prototyping and optimize radio configurations.

TRANSMITTER (Tx) The AD9371 employs a direct conversion transmitter architecture consisting of two identical and independently controlled channels that provide all the digital processing, mixed signal, and RF blocks necessary to implement a direct conversion system. Both channels share a common frequency synthesizer.

The digital data from the JESD204B lanes pass through a fully programmable 96-tap FIR filter with optional interpolation. The FIR output is sent to a series of conversion filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each DAC has an adjustable sample rate and is linear up to full scale.

When converted to baseband analog signals, the in-phase (I) and quadrature (Q) signals are filtered to remove sampling artifacts, and then the signals are fed to the upconversion mixers. At the mixer stage, the I and Q signals are recombined and modulated onto the carrier frequency for transmission to the output stage. Each transmit chain provides a wide attenuation adjustment range with fine granularity to help designers optimize SNR.

RECEIVER (Rx) The AD9371 contains dual receiver channels. Each Rx channel is a direct conversion system that contains a programmable attenuator stage, followed by matched I and Q mixers that downconvert received signals to baseband for digitization.

To achieve gain control, a programmed gain index map is implemented. This gain map distributes attenuation among the various Rx blocks for optimal performance at each power level. In addition, support is available for both automatic and manual gain control modes.

The receiver includes Σ-Δ ADCs and adjustable sample rates that produce data streams from the received signals. The signals can be conditioned further by a series of decimation filters and a fully programmable 72-tap FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing the decimation factors to produce the desired output data rate.

OBSERVATION RECEIVER (ORx) The ORx operates in a similar manner to the main receivers. Each input is differential and uses a dedicated mixer. The ORx inputs share a baseband ADC and baseband section; therefore, only one can be active at any time. The mixed-signal and digital section is identical in design and operation to the main receiver channels. This channel can monitor the Tx channels and implement error correction functions. It can also be used as a general-purpose receiver.

SNIFFER RECEIVER (SnRx) The sniffer receiver provides three differential inputs that can monitor different frequency bands. Each input has a low noise amplifier (LNA) that is multiplexed to feed a single mixer. The output of this mixer stage is multiplexed with the ORx receiver mixers to feed the same baseband section. The SnRx bandwidth is limited to 20 MHz. This receiver can also be used as a general-purpose receiver if the bandwidth and RF performance are acceptable for a given application. The sniffer channel has limited operation from 400 MHz to 4000 MHz. Performance cannot be guaranteed for LO settings above 4000 MHz.

These receiver inputs also provide an LNA bypass mode that removes the gain of the LNA when large signals are present. Note that no requirements for the LNA bypass mode are included in Table 1; performance specifications are only relative to the scenario in which the LNA is enabled.

CLOCK INPUT The AD9371 requires a differential clock connected to the DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the clock input must be between 10 MHz and 320 MHz, and it must have very low phase noise because this signal generates the RF local oscillator and internal sampling clocks.







Data Sheet AD9371


SYNTHESIZERS RF PLL

The AD9371 contains three fractional-N PLLs to generate the RF LOs used by the transmitter, receiver, and observation receiver. The PLL incorporates an internal VCO and loop filter that require no external components. The internal VCO LDO regulators eliminate the need for additional external power supplies for the PLLs. These regulators only require an external bypass capacitor for each supply.

Clock PLL

The AD9371 contains a PLL synthesizer that generates all of the baseband related clock signals and SERDES clocks. This PLL is programmed based on the data rate and sample rate requirements of the system.

External LO Inputs

The AD9371 provides two external LO inputs to allow an external synthesizer to be used with the device. These inputs must be 2× the desired LO frequency. Note that operation for the external LO option is limited to a maximum of 4000 MHz. One input pair is dedicated to the receiver LO generation circuit and the other input provides the input to the transmitter and observation receiver LO generation blocks. Note that the observation receiver can obtain the LO from either the Tx LO generator block or its own dedicated PLL. When the sniffer channel is enabled, the LO for this block can only come from the dedicated internal observation channel PLL.

SERIAL PERIPHERAL INTERFACE (SPI) INTERFACE The AD9371 uses a SPI to communicate with the baseband processor (BBP). This interface can be configured as a 4-wire interface with dedicated receive and transmit ports, or it can be configured as a 3-wire interface with a bidirectional data communications port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first bit sets the bus direction of the bus transfer. The next 15 bits set the address where data is written. The final eight bits are the data being transferred to the specific register address.

Read commands follow a similar format with the exception that the first 16 bits are transferred on the SDIO pin, and the final eight bits are read from the AD9371, either on the SDO pin in 4-wire mode or on the SDIO pin in 3-wire mode.

GPIO_x AND GPIO_3P3_x PINS The AD9371 general-purpose input/output signals referenced to the VDD_IF supply can be configured for numerous functions. Some of these pins, when configured as outputs, are used by the BBP as real-time signals to provide a number of internal settings and measurements. This configuration allows the BBP to monitor receiver performance in different situations. A pointer register selects what information is output to these pins. Signals used for

manual gain mode, calibration flags, state machine states, and various receiver parameters are among the outputs that can be monitored on these pins. In addition, certain pins can be configured as inputs and used in various functions such as setting the receiver gain in real time.

The GPIO_3P3_x pins referenced to the VDDA_3P3 supply are also included in the device and can provide control signals to the external components such as VGAs or attenuators in the RF section that typically use a higher reference voltage.

AUXILIARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x)

The AD9371 contains an auxiliary ADC that is multiplexed to four input pins (AUXADC_0 through AUXADC_3). This block can monitor system voltages without adding additional components. The auxiliary ADC is 12 bits with an input voltage range of 0.05 V to VDDA_3P3 − 0.25 V. When enabled, the auxiliary ADC is free running. Software reads of the output value provide the last value latched at the ADC output.

Auxiliary DACs (AUXDAC_x)

The AD9371 contains 10 identical auxiliary DACs (AUXDAC_0 to AUXDAC_9) that can supply bias voltages, analog control voltages, or other system functionality. The inputs of these auxiliary DACs (AUXDAC_0 to AUXDAC_9) are multiplexed with the GPIO_3P3_x pins according to Table 7. The auxiliary DACs are 10 bits and have an output voltage range of approximately 0.5 V to VDDA_3P3 − 0.3 V and have a current drive of 10 mA.

Table 7. AUXDAC Input Pin Assignments GPIO_3P3 Pin AUXDAC Output GPIO_3P3_9 AUXDAC_0 GPIO_3P3_7 AUXDAC_1 GPIO_3P3_6 AUXDAC_2 GPIO_3P3_10 AUXDAC_3 GPIO_3P3_0 AUXDAC_4 GPIO_3P3_1 AUXDAC_5 GPIO_3P3_3 AUXDAC_6 GPIO_3P3_4 AUXDAC_7 GPIO_3P3_5 AUXDAC_8 GPIO_3P3_8 AUXDAC_9

JESD204B DATA INTERFACE The digital data interface for the AD9371 uses JEDEC Standard JESD204B Subclass 1. The serial interface operates at speeds of up to 6144 Mbps. The benefits of the JESD204B interface include a reduction in required board area for data interface routing and smaller package options due to the need for fewer pins. Digital filtering is included in all receiver and transmitter paths to provide proper signal conditioning and sampling rates to meet the JESD204B data requirements. Examples of the digital filtering configurations for the Tx and Rx paths are shown in Figure 230 and Figure 231, respectively.










AD9371 Data Sheet


Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates) Tx/Tx Synthesis/ Rx Bandwidth (MHz)

Tx Input Rate (MSPS)

Rx Output Rate (MSPS)

JESD204B Lane Rate (Mbps), Two Tx/Two Rx

JESD204B (No. of Lanes) Tx/Rx Reference Clock Options (MHz)

100/250/100 307.2 153.6 6144 4/2 122.88, 153.6, 245.76, 307.2 75/200/100 245.76 122.88 4915.2 4/2 122.88, 245.76 20/100/40 122.88 61.44 2457.6 4/2 122.88, 245.76 20/100/20 122.88 30.72 2457.6 4/1 122.88, 245.76

I/Q DACTRANSMITTER

HALF-BANDFILTER 2

TRANSMITTER FIR(INTERPOLATION

1, 2, 4)

QUADRATUREERROR

CORRECTIONDIGITAL

GAIN JESD204BTRANSMITTER

HALF-BANDFILTER 1

1465

1-12

5

Figure 230. Example Tx Data Path Filter Implementation

ADC JESD204BRECEIVER

HALF-BANDFILTER 3

RFIR(DECIMATION

1, 2, 4)

QECCORRECTION

FILTER

DCCORRECTION

DIGITALGAIN

DEC5

RECEIVERHALF-BAND

FILTER 2

RECEIVERHALF-BAND

FILTER 1

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6

Figure 231. Data Rx Data Path Filter Implementation

POWER SUPPLY SEQUENCE The AD9371 requires a specific power-up sequence to avoid undesired power-up currents. The optimal power-on sequence starts the process by powering up the VDIG and the VDDA_1P3 (analog) supplies simultaneously. If they cannot power up simultaneously, the VDIG supply must power up first. The VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies must then power up after the VDIG and VDDA_1P3 supplies. Note that the VDD_IF supply can power up at any time. It is also recommended to toggle the RESET signal after power has stabilized prior to configuration. Follow the reverse order of the power-up sequence to power-down.

Note that VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.

JTAG BOUNDARY SCAN The AD9371 provides support for a JTAG boundary scan. There are five dual-function pins associated with the JTAG interface. These pins, listed in Table 9, are used to access the on-chip test access port. To enable the JTAG functionality, set the GPIO_0 through GPIO_3 pins according to Table 10 depending on how the desired JESD204B sync pin (that is, SYNCINB0+, SYNCINB0−, SYNCINB1+, SYNCINB1−, SYNCBOUTB0+, or SYNCBOUTB0−) is configured in the software (LVDS or CMOS mode). Pull the TEST pin high to enable the JTAG mode.

Table 9. Dual-Function Boundary Scan Test Pins Mnemonic JTAG Mnemonic Description GPIO_4 TRST Test access port reset

GPIO_5 TDO Test data output GPIO_6 TDI Test data input GPIO_7 TMS Test access port mode select GPIO_18 TCK Test clock

Table 10. JTAG Modes Test Pin Level GPIO_0 to GPIO_3 Description 0 XXXX1 Normal operation 1 1001 JTAG mode with LVDS

JESD204B sync signals 1 1011 JTAG mode with CMOS

JESD204B sync signals

1 X means don’t care.



Data Sheet AD9371


OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1. 03-0

2-20

15-A

0.80

0.80 REF

0.44 REF

ABCDEFG

91011121314 8 7 56 4 23 1

BOTTOM VIEW

10.40 SQ

HJKLMNP

DETAIL A

TOP VIEW

DETAIL A

COPLANARITY0.12

0.500.450.40

BALL DIAMETER

SEATINGPLANE

12.1012.00 SQ11.90

A1 BALLPAD CORNER

1.271.181.09

7.755 REF

8.165 REF

0.910.840.77

0.390.340.29

PKG

-004

569

A1 BALLCORNER

PIN A1INDICATOR

Figure 232. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-12) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9371BBCZ −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-12 AD9371BBCZ-REEL −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-12 ADRV9371-N/PCBZ Evaluation Board, 2600 MHz Matching Circuits ADRV9371-W/PCBZ Evaluation Board, 300 MHz to 6000 MHz Matching Circuits 1 Z = RoHS Compliant Part.

©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14651-0-3/17(B)

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Integrated, Dual RF Transceiver with Observation Path Data ...RadioVerse™ Technology and Design Ecosystem Technical Articles •A Review of Wideband RF Receiver Architecture Options