Interrupts Chapter 6. Interrupts 68HC12 Interrupts 68HC11 Interrupts Interrupt Vector Jump Tables Writing WHYP Interrupt Service Routines Real-Time Interrupts

Interrupts

Chapter 6

Interrupts

• 68HC12 Interrupts


• Interrupt Vector Jump Tables

• Writing WHYP Interrupt Service Routines

• Real-Time Interrupts

• Writing Assembly Language Interrupt Service Routines

68HC12 Interrupts

Table 6.1 68HC12 Non-Maskable InterruptsVector Address Interrupt Source$FFFE-$FFFF Reset$FFFC-$FFFD COP Clock Monitor Fail Reset$FFFA-$FFFB COP Failure Reset$FFF8-$FFF9 Unimplemented Instruction Trap$FFF6-$FFF7 SWI$FFF4-$FFF5 XIRQ

Register Stacking for Interrupts

Ret Addr H

YL

YH

XL

XH

ACCA

ACCB

CCR

SP before interrupt

SP after interrupt

Ret Addr L

68HC12 InterruptsTable 6.2 68HC812A4 Maskable Interrupts

Vector Address Interrupt Source$FFF2-$FFF3 IRQ or Key Wake Up D$FFF0-$FFF1 Real-Time Interrupt$FFEE-$FFEF Timer Channel 0$FFEC-$FFED Timer Channel 1$FFEA-$FFEB Timer Channel 2$FFE8-$FFE9 Timer Channel 3$FFE6-$FFE7 Timer Channel 4$FFE4-$FFE5 Timer Channel 5$FFE2-$FFE3 Timer Channel 6$FFE0-$FFE1 Timer Channel 7$FFDE-$FFDF Timer Overflow$FFDC-$FFDD Pulse Accumulator Overflow$FFDA-$FFDB Pulse Accumulator Input Edge$FFD8-$FFD9 SPI Serial Transfer Complete$FFD6-$FFD7 SCI 0$FFD4-$FFD5 SCI 1$FFD2-$FFD3 ATD$FFD0-$FFD1 Key Wakeup J (stop wakeup)$FFCE-$FFCF Key Wakeup H (stop wakeup)

68HC12 InterruptsTable 6.3 68HC912B32 Maskable Interrupts

Vector Address Interrupt Source$FFF2-$FFF3 IRQ$FFF0-$FFF1 Real-Time Interrupt$FFEE-$FFEF Timer Channel 0$FFEC-$FFED Timer Channel 1$FFEA-$FFEB Timer Channel 2$FFE8-$FFE9 Timer Channel 3$FFE6-$FFE7 Timer Channel 4$FFE4-$FFE5 Timer Channel 5$FFE2-$FFE3 Timer Channel 6$FFE0-$FFE1 Timer Channel 7$FFDE-$FFDF Timer Overflow$FFDC-$FFDD Pulse Accumulator Overflow$FFDA-$FFDB Pulse Accumulator Input Edge$FFD8-$FFD9 SPI Serial Transfer Complete$FFD6-$FFD7 SCI 0$FFD4-$FFD5 Reserved$FFD2-$FFD3 ATD$FFD0-$FFD1 BDLC

Interrupt Control Register7 6 5 4 3 2 1 0

$001E IRQE IRQEN DLY 0 0 0 0 0 INTCR

IRQE: IRQ Select Edge Sensitive Only (read anytime, write once)0 – IRQ responds to low-level on pin PE1 (default)1 – IRQ responds only to falling edges on pin PE1

IRQEN: External IRQ Enable (read and write anytime)0 – Pin PE1 not connected to IRQ interrupt logic1 – Pin PE1 connected to IRQ interrupt logic (default)

DLY: Enable Oscillator Start-Up Delay on Exit from STOP (read anytime, write once)0 – No stabilization delay imposed on exit from STOP1 – Stabilization delay is imposed on exit from STOP (default)

Highest Priority I Interrupt Register

7 6 5 4 3 2 1 0$001F 1 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 HPRIO

PSEL[5:1]: Priority select bits to form low byte of vector address of maskable interruptwith highest priority (default is F2: IRQ)

Interrupts







68HC11 InterruptsTable 6.4 68HC711E9 Interrupts

Vector Address Interrupt Source$FFFE-$FFFF Reset$FFFC-$FFFD COP Clock Monitor Fail Reset$FFFA-$FFFB COP Failure Reset$FFF8-$FFF9 Illegal Opcode Trap$FFF6-$FFF7 SWI$FFF4-$FFF5 XIRQ$FFF2-$FFF3 IRQ$FFF0-$FFF1 Real-Time Interrupt$FFEE-$FFEF Timer Input Capture 1$FFEC-$FFED Timer Input Capture 2$FFEA-$FFEB Timer Input Capture 3$FFE8-$FFE9 Timer Output Compare 1$FFE6-$FFE7 Timer Output Compare 2$FFE4-$FFE5 Timer Output Compare 3$FFE2-$FFE3 Timer Output Compare 4$FFE0-$FFE1 Timer Input Capture 4/Output Compare 5$FFDE-$FFDF Timer Overflow$FFDC-$FFDD Pulse Accumulator Overflow$FFDA-$FFDB Pulse Accumulator Input Edge$FFD8-$FFD9 SPI Serial Transfer Complete$FFD6-$FFD7 SCI Serial System

Interrupts







68HC711E9Listing 6.1 INTVECE9.LST File for Interrupt Vectors0001 e000 ROMBS EQU $D0000002 e000 WHYP EQU $D00000030004 00c4 ORG $00C40005 *** Vector jump table ***0006 00c4 JSCI RMB 30007 00c7 JSPI RMB 30008 00ca JPAIE RMB 30009 00cd JPAO RMB 30010 00d0 JTOF RMB 30011 00d3 JTOC5 RMB 30012 00d6 JTOC4 RMB 30013 00d9 JTOC3 RMB 30014 00dc JTOC2 RMB 30015 00df JTOC1 RMB 30016 00e2 JTIC3 RMB 30017 00e5 JTIC2 RMB 30018 00e8 JTIC1 RMB 30019 00eb JRTI RMB 30020 00ee JIRQ RMB 30021 00f1 JXIRQ RMB 30022 00f4 JSWI RMB 30023 00f7 JILLOP RMB 30024 00fa JCOP RMB 30025 00fd JCLM RMB 30026

00260027 ffd6 ORG ROMBS+$2FD60028 *** Vectors ***0029 ffd6 00 c4 VSCI FDB JSCI0030 ffd8 00 c7 VSPI FDB JSPI0031 ffda 00 ca VPAIE FDB JPAIE0032 ffdc 00 cd VPAO FDB JPAO0033 ffde 00 d0 VTOF FDB JTOF0034 ffe0 00 d3 VTOC5 FDB JTOC50035 ffe2 00 d6 VTOC4 FDB JTOC40036 ffe4 00 d9 VTOC3 FDB JTOC30037 ffe6 00 dc VTOC2 FDB JTOC20038 ffe8 00 df VTOC1 FDB JTOC10039 ffea 00 e2 VTIC3 FDB JTIC30040 ffec 00 e5 VTIC2 FDB JTIC20041 ffee 00 e8 VTIC1 FDB JTIC10042 fff0 00 eb VRTI FDB JRTI0043 fff2 00 ee VIRQ FDB JIRQ0044 fff4 00 f1 VXIRQ FDB JXIRQ0045 fff6 00 f4 VSWI FDB JSWI0046 fff8 00 f7 VILLOP FDB JILLOP0047 fffa 00 fa VCOP FDB JCOP0048 fffc 00 fd VCLM FDB JCLM0049 fffe d0 00 VRST FDB WHYP

D-Bug12

Table 6.5 68HC12 Non-Maskable User InterruptsVector Address Interrupt Source User Vector Address$FFFE-$FFFF Reset *$FFFC-$FFFD COP Clock Monitor Fail Reset *$FFFA-$FFFB COP Failure Reset *$FFF8-$FFF9 Unimplemented Instruction Trap $0B38-$0B39$FFF6-$FFF7 SWI $0B36-$0B37$FFF4-$FFF5 XIRQ $0B34-$0B35

D-Bug12Table 6.6 68HC812A4 Maskable User Interrupt Vectors

Vector Address Interrupt Source User Vector Address$FFF2-$FFF3 IRQ or Key Wake Up D $0B32-$0B33$FFF0-$FFF1 Real-Time Interrupt $0B30-$0B31$FFEE-$FFEF Timer Channel 0 $0B2E-$0B2F$FFEC-$FFED Timer Channel 1 $0B2C-$0B2D$FFEA-$FFEB Timer Channel 2 $0B2A-$0B2B$FFE8-$FFE9 Timer Channel 3 $0B28-$0B29$FFE6-$FFE7 Timer Channel 4 $0B26-$0B27$FFE4-$FFE5 Timer Channel 5 $0B24-$0B25$FFE2-$FFE3 Timer Channel 6 $0B22-$0B23$FFE0-$FFE1 Timer Channel 7 $0B20-$0B21$FFDE-$FFDF Timer Overflow $0B1E-$0B1F$FFDC-$FFDD Pulse Accumulator Overflow $0B1C-$0B1D$FFDA-$FFDB Pulse Accumulator Input Edge $0B1A-$0B1B$FFD8-$FFD9 SPI Serial Transfer Complete $0B18-$0B19$FFD6-$FFD7 SCI 0 $0B16-$0B17$FFD4-$FFD5 SCI 1 $0B14-$0B15$FFD2-$FFD3 ATD $0B12-$0B13$FFD0-$FFD1 Key Wakeup J (stop wakeup) $0B10-$0B11$FFCE-$FFCF Key Wakeup H (stop wakeup) $0B0E-$0B0F

D-Bug12Table 6.7 68HC912B32 Maskable User Interrupt Vectors

Vector Address Interrupt Source User Vector Address$FFF2-$FFF3 IRQ $0B32-$0B33$FFF0-$FFF1 Real-Time Interrupt $0B30-$0B31$FFEE-$FFEF Timer Channel 0 $0B2E-$0B2F$FFEC-$FFED Timer Channel 1 $0B2C-$0B2D$FFEA-$FFEB Timer Channel 2 $0B2A-$0B2B$FFE8-$FFE9 Timer Channel 3 $0B28-$0B29$FFE6-$FFE7 Timer Channel 4 $0B26-$0B27$FFE4-$FFE5 Timer Channel 5 $0B24-$0B25$FFE2-$FFE3 Timer Channel 6 $0B22-$0B23$FFE0-$FFE1 Timer Channel 7 $0B20-$0B21$FFDE-$FFDF Timer Overflow $0B1E-$0B1F$FFDC-$FFDD Pulse Accumulator Overflow $0B1C-$0B1D$FFDA-$FFDB Pulse Accumulator Input Edge $0B1A-$0B1B$FFD8-$FFD9 SPI Serial Transfer Complete $0B18-$0B19$FFD6-$FFD7 SCI 0 $0B16-$0B17$FFD4-$FFD5 Reserved $0B14-$0B15$FFD2-$FFD3 ATD $0B12-$0B13$FFD0-$FFD1 BDLC $0B10-$0B11

Interrupts







WHYP Interrupt Words

// SEIvoid sei()

{if(compile) dict12.tcomma(0x1410); // compile SEI 1410else cout << "SEI must be in colon definition ";}

// CLIvoid cli()

{if(compile) dict12.tcomma(0x10ef); // compile CLI 10EFelse cout << "CLI must be in colon definition ";}

WHYP Interrupt Words

// INT:void int_colon()

{int int_stack;int_stack = RAMBASE + 0x30;colon(); // make headerdict12.tccomma(0xce); // LDX #(RAMBASE+$30)dict12.tcomma(int_stack);}

// RTI;void rti_semis()

{compile = false;dict12.tccomma(0x0b); // compile RTIdict12.fix_size();}

Interrupts







Real-Time Interrupt Registers

Real-Time Interrupt Registers7 6 5 4 3 2 1 0

$0014 RTIE RSWAI RSBCK 0 RTBYP RTR2 RTR1 RTR0 RTICTL

RTIE: Real Time Interrupt Enable0 – RTIF interrupts disabled1 – RTIF interrupts enabled

RSWAI: RTI and COP Stop While in Wait0 – RTI and COP continue running in wait1 – RTI and COP disabled when in wait

RSBCK: RTI and COP Stop While in Background Debug Mode0 – RTI and COP continue running in background mode1 – RTI and COP disabled when in background mode

RTBYP: Real Time Interrupt Divider Chain Bypass0 – Divider chain functions normally1 – Divider chain bypassed

RTR[2:0]: RTI Interrupt Rate SelectRTR[2:0] Time-Out Period

M = 8.0 MHz0 0 0 OFF0 0 1 1.024 ms0 1 0 2.048 ms0 1 1 4.096 ms1 0 0 8.196 ms1 0 1 16.384 ms1 1 0 32.768 ms1 1 1 65.536 ms

7 6 5 4 3 2 1 0$0015 RTIF 0 0 0 0 0 0 0 RTIFLG

RTIF: Real Time Interrupt Flag0 – Cleared by writing a 1 to bit position 71 – Set to 1 when timeout occurs (causes interrupt if RTIE set in RTICTL)

Listing 6.2 Real-time Interrupt\ Real-time Interrupt File: RTI.WHP

VARIABLE TICKS

HEX0B30 CONSTANT RTI.IVEC0014 CONSTANT RTICTL0015 CONSTANT RTIFLG

( Use real-time interrupt for delay )

: RTIF.CLR ( -- ) \ clear RT1 flag 80 RTIFLG C! ;

: RTI.SET32 ( -- ) 06 RTICTL C! ; \ set RTI rate to 32.77 msec

: RTI.INT.ENABLE ( -- ) 7 RTICTL HI ;

: RTI.INT.DISABLE ( -- ) 7 RTICTL LO ;

INT: RTI.INTSER ( -- ) \ increment TICKS 1 TICKS +! RTIF.CLRRTI;

: SET.RTI.INTVEC ( -- ) [ ' RTI.INTSER ] LITERAL RTI.IVEC ! ;

DECIMAL

: TICK.DELAY ( n -- ) \ delay n ticks >R TICKS @ \ ticks0 BEGIN TICKS @ OVER - \ ticks0 elapsed R@ U>= UNTIL R> 2DROP ;

: RTI.OFF ( -- ) SEI RTI.INT.DISABLE ;

: RTI.ON ( -- ) SEI RTI.SET32 SET.RTI.INTVEC RTI.INT.ENABLE CLI ;

DECIMAL

Real-Time Interrupt on a 68HC117 6 5 4 3 2 1 0

$1024 TOI RTII PAOVI PAII 0 0 PR1 PR0 TMSK2

RTII: Real Time Interrupt Enable0 – RTIF interrupts disabled1 – RTIF interrupts enabled

7 6 5 4 3 2 1 0$1025 TOF RTIF PAOVF PAIF 0 0 0 0 TFLG2

RTIF: Real Time (Periodic) Interrupt Flag0 – Cleared by writing a 1 to bit position 61 – Set to 1 when timeout occurs (causes interrupt if RTII set in TMSK2)

7 6 5 4 3 2 1 0$1026 DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0 PACTL

RTR[1:0]: RTI Interrupt Rate SelectRTR[1:0] periodic rate

0 0 4.096 ms0 1 11.192 ms1 0 16.384 ms1 1 32.768 ms

Table 6.8 68HC711E9 Interrupt Jump TableVector Address Interrupt Source User Jump Table$FFFE-$FFFF Reset main$FFFC-$FFFD COP Clock Monitor Fail Reset $00FD$FFFA-$FFFB COP Failure Reset $00FA$FFF8-$FFF9 Illegal Opcode Trap $00F7$FFF6-$FFF7 SWI $00F4$FFF4-$FFF5 XIRQ $00F1$FFF2-$FFF3 IRQ $00EE$FFF0-$FFF1 Real-Time Interrupt $00EB$FFEE-$FFEF Timer Input Capture 1 $00E8$FFEC-$FFED Timer Input Capture 2 $00E5$FFEA-$FFEB Timer Input Capture 3 $00E2$FFE8-$FFE9 Timer Output Compare 1 $00DF$FFE6-$FFE7 Timer Output Compare 2 $00DC$FFE4-$FFE5 Timer Output Compare 3 $00D9$FFE2-$FFE3 Timer Output Compare 4 $00D6$FFE0-$FFE1 Timer Input Capture 4/Output Compare 5 $00D3$FFDE-$FFDF Timer Overflow $00D0$FFDC-$FFDD Pulse Accumulator Overflow $00CD$FFDA-$FFDB Pulse Accumulator Input Edge $00CA$FFD8-$FFD9 SPI Serial Transfer Complete $00C7$FFD6-$FFD7 SCI Serial System $00C4

68HC11 SET.INTVECHEX00EB CONSTANT RTI.IVEC

\ set interrupt vector in EVB jump table: SET.INTVEC ( intser.addr jmp.tbl.addr -- )

7E OVER C! \ JMP opcode1+ ! ;

: SET.RTI.INTVEC ( -- ) [ ' RTI.INTSER ] LITERAL RTI.IVEC SET.INTVEC ;

Interrupts







Computing Execution Time

INT: RTI.INTSER ( -- ) \ increment TICKS 1 TICKS +! RTIF.CLRRTI;

#clock cycles CE 09 30 LDX #$0930 2 16 45 1B 00 01 JSR (LIT) 0001 4+17 = 21 16 50 00 JSR TICKS 4+22 = 26 16 44 AE JSR +! 4+17 = 21 16 50 18 JSR RTIF.CLR 4+66 = 70 0B RTI 8 148

148/8 = 18.5 s

RTI_INTSER in Assembly Language

* Real-time Interrupt File: RTI.ASM

RTIFLG EQU $0015

ORG $0810TICKS DW 0

ORG $4C00RTI_INTSER #clock cycles LDY TICKS 3 INY 1 STY TICKS 3 LDAA #$80 1 STAA RTIFLG 3 RTI 8

19

19/8 = 2.4 s

For example, to use the interrupt service routine in Figure 6.8 instead of the one inFigure 6.7 in the program in Listing 6.2 you only need to do the following:

1. Delete the interrupt service routine (from INT: to RTI;) in Listing 6.2.2. Delete the statement VARIABLE TICKS at the beginning of Listing 6.2 and

add the statement 0810 CONSTANT TICKS following the word HEX. Thiswill give the variable TICKS the same address assigned in Figure 6.8.

3. Add the line RTI.INTSER C00 at the beginning of the file WHYP12.HED.When WHYP12 is run this will put RTI.INTSER in the dictionary with anaddress of $4C00 (assuming you are using the 'A4 board with TORG =$4000).

4. Assemble the file RTI.ASM shown in Figure 6.8 and download the resultingfile, RTI.S19, to the 68HC12 using HOST.

5. Execute WHYP on the 68HC12, run WHYP12 on the PC, and load themodified file, RTI.WHP, shown in Listing 11.2. Typing RTI.ON will turn onthe real-time interrupts using the assembly language interrupt service routineshown in Figure 6.8.

Box 6.1 WHYP Words Introduced in this Chapter

[ ( -- ) ("left-bracket") Turns off the compiler within a colon definition.

] ( -- ) ("right-bracket") Turns on the compiler within a colon definition.

LITERAL ( n -- ) Compile n as a literal within a colon definition. Compiles JSR (LIT)followed by n.

CLI ( -- )Compiles the opcode for CLI ($10EF) inline within a colon definition.

SEI ( -- )Compiles the opcode for SEI ($1410) inline within a colon definition.

INT: ( -- )Used in place of : to define a high-level WHYP word that is an interruptservice routine.

RTI; ( -- )Used to end a high-level WHYP word defined using INT:. Compiles theopcode for the RTI instruction ($0B) inline.

Documents

Interrupts Chapter 6. Interrupts 68HC12 Interrupts 68HC11 Interrupts Interrupt Vector Jump Tables Writing WHYP Interrupt Service Routines Real-Time Interrupts