Intro to Electronics BJT 2015 (2)

Mrinal K Mandal [email protected] Department of E & ECE I.I.T. Kharagpur. 721302. www.ecdept.iitkgp.ernet.in

Introduction to Electronics

Part - II

1

Bipolar Junction Transistor (BJT)

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur [email protected] 2 The first transistors.

• One of the most important inventions (John Bardeen, Walter Brattain and William Shockley at AT & T Bells lab, got Nobel in 1956).

• It has three layers (npn or pnp): two pn junctions. • A three terminal device: emitter, base and collector. • Main applications: amplifiers, oscillators, switches, logic gates.

Shockley

Bardeen

Brattain p n p

Emitter Collector

Base

n p n p

BJT

E C

B

Bipolar Junction Transistor (BJT)

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur [email protected] 3 Different types of transistors.

E

E

BJT with a heat sink

Analogy with a water tap point.

p n p E C

B (base)

n p n E C

B

pnp- transistor

C

E

B Conventional current flow direction

npn- transistor

C

E

B

(emitter) (collector)

Base

emitter collector

BJT

Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur [email protected] 4

• Two pn junctions: barrier voltages are negative on the p-side and positive on the n-side.

• Bipolar device: two types of charge carrier are involved in the current flow. • The base region (mid-layer) is thin and lightly doped. • The emitter emits electron in npn, holes in pnp and collector collects them. • In normal operation, the emitter-base junction is forward-biased: carrier

injection. • The collector-base junction is reverse-biased, its depletion region penetrates

deep into the base.

pnp- transistor

C

E

B p n

E C p

emitter collector base

+ + + +

- - - - VEB VBC

pnp- transistor biasing

Holes are the majority charge carriers in an pnp device.

BJT Operation


npn- transistor

C

E

B n

E C p

emitter collector base

+ + + +

- - - - VBE VCB

n

npn- transistor biasing

• Forward bias base-emitter junction works as a diode: majority carriers electron in n-type emitter drift into p-type base.

• Holes also drift from base into emitter small because the base is thin and lightly doped.

• The electrons diffused into the collector-base depletion region they are drawn across the collector-base junction collected at the collector terminals (~96-99.5%).

• In the bas region, a small percentage of the injected electrons recombines with holes base current.

Electrons are the majority charge carriers in an npn device.

BJT Voltages and Currents


npn-transistor biasing: common emitter (CE) configuration.

pnp-transistor biasing: common emitter (CE) configuration.

Applying KCL, E C BI I I= +

Common emitter current gain: .dc C BI Iβ =

npn-transistor biasing: common base (CB) configuration.

RC RB VEE

+

-

IE

VCC

+

- IB

IC

Common base current gain: .dc C EI Iα =

( ) .

1.

1

1B

C C B C

C B

II I I I

I I α β

αα

ββ

α

β αα

= + ⇒

= =−

−

⇒ ⇒+

=

=

RC

E

B

RB

C

VBB +

- IB

VCC

+

-

IE

IC

VEB

VEC

+ -

-

+

RC

E

B

RB

C

VBB

+

-

IB VCC

+

- IE

IC

VBE

VCE

+

-

Different Configurations


Common emitter (CE) configuration. Common base (CB) configuration.

RC RB VEE

+

-

IE

VCC

+

- IB

IC RC

E

B

RB

C

VBB

+

-

IB VCC

+

- IE

IC

VBE

VCE

+

-

Common collector (CC) configuration.

RC E B

RB C

VBB

+

-

IB VCC

+

- IC

IE

VBE

VCE

+

-

BJT Characteristics: Input Characteristics


VBE(V)

0 0.3 0.6 0.9 0

10

20

30

IB (μA)

VBE(V)

0 -0.3 -0.6 -0.9 0

10

20

30

IB (μA)

RC RB

VBB

+

-

IB VCC

+

- IE

IC

VBE

VCE

+

-

A

V

A

A

V +

- Input characteristics of a npn-transistor in CE configuration.

Input characteristics of a pnp-transistor in CE configuration.

npn-transistor in common emitter (CE) configuration.

• Input parameters:

• Output parameters:

,B BEI V,C CEI V

0 exp BEB B

T

VI IV

=

• Base current:

BJT Characteristics: Output Characteristics


VCC /RC

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA

0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

DC load line

Saturation region

Cut-off region

Active region

Output characteristics for a npn transistor in CE configuration.

Input loop: Applying KVL,

Output loop:

BB B B BEV I R V= +

Applying KVL,

.

CC C C CE

CE CCC

C C

V I R VV VIR R

= +

⇒ = − +

At 0, and

at 0, .

C CE CC

CCCE C

C

I V VVV IR

= =

= =

load line

• Active region: base-emitter junction is in FB but base-collector junction is in RB., Saturation region: both junctions are in FB, Cut-off region: both are in RB.

• A saturation current component IC = ICBO flows even for IB = 0. • Consider VCE|sat = 0.2 V, if the transistor in saturation.

[ ]C E CBOI I Iα= +

Some Important Characteristics


• In active region, collector current IC is almost independent of VCE: constant current source.

• IC can be tuned by IB (linear model, function of VBE): voltage controlled current source.

• IC is mostly due to the flow of charges injected from a high-concentration emitter into the base where there are minority carriers that diffuse toward the collector: a minority-carrier device.

• When using as an amplifier, the DC source supplies the energy required to amplify a signal: fix the dc operating point (Q-point) first.

• Linear approximation (output is an exact replica of the input signal) is valid only for small signal amplitudes.

Non-linear device: Does not have a linear relationship between current and voltage.

Examples: diode, transistors.

( )0 exp .TI I V V=

Voltage Amplification


• A BJT works as an amplifier only in active region and under proper biasing condition.

• In a class A amplifier, Q-point is so selected that a BJT always remains in the active region.

• Slope of the load line and hence voltage amplification depends on RC.

• In CE configuration, when the input voltage (vbe) increases, the output voltage (vce) decreases.

VCC /RC

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA

0

5

10

15

0 4 8 12 VCE (V)

IC (mA)

Saturation region

Cut-off region

Active region

Output characteristics for a npn transistor in CE configuration.

t (mS)

ib ic

vce

t (mS)

• Maximum possible variation in VCE = VCC - 0.2 V

Why Need Biasing?


In the following circuit, IB changes by ±10 μA because of a VBE change by ±20 mV. Calculate the change in VCE. Given that β = 100.

RC = 6 kΩ

VBB = 0.7 V

VCC = 20 V

IE

IC

VBE

VCE

20sin mVbv tω=

100 20 2 .2 6

12 .

β µ∆ = ∆ = × =∆ = ∆ = ×

=

C B

CE C C

I I A mAV I R

V

Solutions:

• Biasing: to set the dc operating point.

• IC = βIB, only in active region.

In lab. experiment, don’t forget to switch on the dc power supply.

VBE(V)

0.7 0

40

IB (μA)

Input characteristics of the BJT.

Linear approximation

BJT in Saturation


In the previous example, recalculate the change in VCE if RC is changed to 12 kΩ.

RC = 12 kΩ

VBB = 0.7 V

VCC = 20 V

IE

IC

VBE

VCE

20sin mVbv tω=

100 20 2 .

(2 12

24 ) .

β µ∆ = ∆ = × =∆ = ∆ = ×

>= →C

C B

C C

C

E C

I I A mAV I R

V V wrong

Solutions:

High IB drives the BJT in saturation. Considering maximum possible variation,

max 0.219.8

∆ = −=

CE CCV VV Neglecting the contribution of ICBO.

BJT In Saturation


RC

E

B

RB

C

VBB

+

-

IB VCC

+

- IE

IC

VBE

VCE

+

-

RC

RB

+VBB

IB

+VCC

IE

IC

VBE

VCE

+

-

npn-transistor in CE configuration.

Calculate IB and IC. Given that β = 100, RB = 10 kΩ, RC = 1 kΩ, VBB = 5 V and VCC = 12 V.

Solutions: Applying KVL in the input loop,

5 0.7 0.43 .10

BB B B BE

BB BEB

B

V I R VV VI mA

R k

= +− −

⇒ = = =

wr43

.12 3

ong4 31 ?

C B

CE CC C C

I I mA

V V I R V

β∴ = =

⇒ = − = − = −

Applying KVL in the output loop,

12 10 1.8 ..21

CC CEC

C

V VI mAR k− −

= = =

So, the transistor is in saturation.

BJT Biasing


• Biasing: setting up the dc operating point (quiescent point). • Minimize number of dc sources, increase stability of the circuit (eg. VBE and ICBO

depend on temperature, β varies widely from transistor to transistor). • Three popular biasing schemes:

1. Base bias 2. Collector-to-base bias 3. Voltage divider bias.

Analysis objectives: • Draw the dc load line (apply KVL for the input and output loops, assume

suitable VBE value) • Identify Q-point (IBQ, ICQ, VCEQ) • Estimate the maximum variation of the output voltage.

1. Base Bias


RC

+VCC

IE

IC

VBE

VCE

RB

IB

vout

vin

+

+

- -

Base bias configuration (npn-BJT).

Input loop: = −

−⇒ = .

B B CC BE

CC BEB

B

R I V VV VI

RIn forward active region:

β==

,0.7 V( Si), 0.3 V( Ge) .

C B

BE

I IV

Output loop: = −

−⇒ =

⇒ = − .

C C CC CE

CC CECQ

C

CEQ CC C C

R I V VV VI

RV V R I

= =

= =

0,

0, .

C CE CC

CCCE C

C

At I V VVV IR

VCC /RC

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

DC load line

Load line:

= − + .CE CCC

C C

V VIR R

Base Bias


Calculate the Q-point values (β = 100).

2.2 kΩ

+18 V

IE

IC

VBE

VCE

470 kΩ

IB

+

+

- -

Solutions:

µ

− −= =

×=

3018

470 103 .

.7

6.8

CC BEBQ

B

V VIR

A

β= = 3.68 .CQ BQI I mA

Assuming active condition.

18 3.68 2.V

2. .9 9

CEQ CC C CV V R I= − = − ×=

Assumption is correct.

Recalculate the Q-point values for β = 50.

β= = 1.84mA.CQ BQI I13.95 V.CEQ CC C CV V R I= − =

VCEQ changes by 41% when β changes by 50%.

A BJT with the same number may have wide variation of β (high manufacturing tolerance)

Base Bias


2.2 kΩ

-18 V

IE

IC

VEB

VEC

470 kΩ

IB

-

-

+ + 2.2 kΩ

+18 V

IE

IC

VEB VEC

470 kΩ

IB

+ +

- -

pnp transistor in base bias configuration.

In the above circuit, Vcc is changed to 12 V. Calculate the new Q-point (β = 100).

3012

470 107

2 .

.

4

CC BE B B

CC BEBQ

B

V V R IV VI

RAµ

= +− −

⇒ = =×

=

12 2.4 2.26.72 V.

CEQ CC C CV V R I= − = − ×=

2.4mA.CQ BQI Iβ= =

The transistor is working in the forward active region.

Base Bias Circuit Design


RC

+VCC

IE

IC

VBE

VCE

RB

IB

vout

vin

+

+

- -

Base bias configuration (npn-BJT).

Input loop:

put .

B BQ CC BE

CQCC BEB BQ

BQ

R I V VIV VR I

I β

= −

−⇒ = =

In forward active region:

0.7 V( Si), 0.3 V( Ge) .BEV =

Output loop:

.CC CEQC CQ CC CEQ C

CQ

V VR I V V RI−

= − ⇒ =

Determine the resistor values for the specified Q-value.

Design a base bias circuit using a Si transistor with β = 100 to set the Q-point at ICQ = 5 mA and VCEQ = 6 V. Use VCC = 12 V.

Solution: 50 μA. 0.7 V. 226 k and 1.2 k .CQ

B BE B CII V R Rβ

∴ = = = = Ω = Ω

2. Collector-To-Base Bias


npn transistor in collector-to-base bias configuration.

RC

+VCC

IE

(IC+IB)

VBE

VCE

RB

IB

vout

vin

+

+

- -

Output loop:

( )

( )( )

1 11 1 .

CC C B CEC

CC CECQ

C

CEQ CC C C

V R I I VV VI

RV V R I

β

β

= + +

−⇒ =

+

⇒ = − +

( )

0,

0, .1 1

C CE CC

CC CCCE C

C C

At I V VV VV I

R Rβ

= =

= = ≈+

load line

VCC /RC

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

DC load line

Input loop:

( )

( ).

1

CC C C B B B BE

CC BEB

B C

V R I I R I VV VI

R R β

= + + +

−⇒ =

+ +where .C BI Iβ=

Applying KVL,

Collector-To-Base Bias



RC

+VCC

IE

(IC+IB)

VBE

VCE

RB

IB

vout

vin

+

+

- -

The change in resistor position improves bias stability.

VCC /RC

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

DC load line

Negative feedback effect: • IF IC increases above the design level, VCE decreases. • The reduced VCE level causes IB to be lower than the design value. • Because IC = βIB, IC tends to decrease.



Solutions:


2.2 kΩ

+18 V

IE

(IC+IB)

VBE

VCE

IB

vout

vin

+

+

- -

270 kΩ

Calculate the Q-point values for β = 100. Calculate the new values if β is changed to 50.

( )

( )

135.1 μA.

3.51 mA.

V10.2 .

CC BEB

B C

CQ B

CEQ CC C C B

V VIR R

I IV V R I I

β

β

−=

+ +

=∴ = =

= − +

=

( )

( )

145.3 μA.

2.31 mA.

12.82 V.

CC BEB

B C

CQ B

CEQ CC C C B

V VIR R

I IV V R I I

β

β

−=

+ +

=∴ = =

= − +

=

For β = 100: For β = 50:

• Observe that the change in Q-point values in comparison to base-bias case is much smaller.

• In this case IB is also a function of β.



Solutions:

( )

( )

123 μA.

2.3 mA.

6.89 V.

CC BEB

B C

CQ B

CEQ CC C C B

V VIR R

I IV V R I I

β

β

−=

+ +

=∴ = =

= − +

=

pnp transistor in collector-to-base bias configuration.

2.2 kΩ

+12 V IE

(IC+IB)

VBE

VEC

IB

vout

vin

+ +

-

- 270 kΩ

In the above circuit, Vcc is changed to 12 V. Calculate the new Q-point values (β = 100).

Collector-To-Base Bias Circuit Design


put , 0.7 V for Si,.

0.3 V for Ge

.

B BQ CEQ BEQ

CQBQ BECEQ BEQ

BBQ

CC CEQC

BQ CQ

R I V VII VV VR

I

V VRI I

β

= −

= =− ⇒ =

−=

+

Design a collector-to-base bias circuit using a Si transistor with β = 100 to fix the Q-point at ICQ = 5 mA and VCEQ = 6 V. Use VCC = 15 V.

Solution:

50 μA. 0.7 V.106 k and 1.78 k .

CQB BE

B C

II V

R Rβ

∴ = = =

= Ω = Ω


RC

+VCC

IE

(IC+IB)

VBE

VCE

RB

IB

vout

vin

+

+

- -

3. Voltage Divider Bias


1 2 21 2

1 2 1 2

|| and .Th Th CCR R RR R R V V

R R R R∴ = = =

+ +

• Most stable biasing scheme among the three.

• R1 and R2 form a voltage divider. • I2 >>IB VB remains almost constant.

RC

+VCC

IE

IC

VBE

VCE

RE

IB

VB

+

+

- -

R1

R2

I1

I2

npn transistor in voltage divider bias configuration.

+VCC

VB

R1

R2

I1

I2 RTh

VTh

The voltage divider and its Thevenin equivalent.

I1 = I2

Voltage Divider Bias: Analysis


Voltage divider bias using the Thevenin equivalent.

RC

+VCC

IE

IC

VBE

VCE

RE

IB +

+

- - RTh

VTh

Input loop: ( )

( ).

1

Th Th B BE E B C

Th BEB

Th E

V R I V R I IV VI

R R β

= + + +

−⇒ =

+ +where .C BI Iβ=

Output loop: ( )

( )( )

1 1.

CC C C CE E B C

CC CE CC CECQ

C E C E

CEQ CC C E C E B

V R I V R I IV V V VI

R R R RV V R R I R I

β

= + + +

− −⇒ = ≈

+ + +

⇒ = − + −

( )

0,

0, .1 1

C CE CC

CC CCCE C

E C E C

At I V VV VV I

R R R Rβ

= =

= = ≈+ + +

load line

Voltage Divider Bias


Load line and the Q-point on the output characteristics.

VCC /(RC+RE)

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

DC load line

Voltage Divider Bias


+18 V

IE

IC

VBE

VCE

IB +

+

- 1 kΩ


12 kΩ

33 kΩ 1.2 kΩ

Calculate the Q-point values for β = 100. Recalculate the values for β = 50. A Si transistor has been used.

Solution:

21 2

1 2

|| 8.8 k Ω

and =4 8 VTh Th CC

RR R R V VR R

∴ = = =+

( )37.3 μA.1

3.73 mA.

Th BEB

Th E

C

V VIR R

Iβ

−= =

+ +

∴ =

( ) 9.76 V.CEQ CC C E C E BV V R R I R I= − + − =

For β = 100:

For β = 50:

68.6 μA 3 43 mAB CI I= ∴ =

10.39 V.CEQV =

Introduction of an emitter resistor RE greatly improves the biasing stability.

.

remains almost constant.

B BE BEC E C E

E E

B

V V VI I I IR R

V

− ∆≈ ≈ ⇒ ∆ ≈ ∆ =

Voltage Divider Bias Design


RC

+VCC

IE

IC

VBE

VCE

RE

IB

VB

+

+

- -

R1

R2

I1

I2


VC

VE

• VB should be stable I2>>IB. • Avoid low input impedance choose low I2 (because R1||R2 w.r.t. the input

terminals). • VE>VBE.

RC

RE

IB

R1

R2

Equivalent circuit as seen by any AC source.

Voltage Divider Bias Design


Approximations:

2 CC

1 2

1. 10 3. 3 V for V 5 V2. 5 V otherwise.

C EI I VI I= = == = RC

+VCC

IE

IC

VBE

VCE

RE

IB

VB

+

+

- -

R1

R2

I1

I2


VC

VE

( )

( )

22

12

,

,

10 ,

10 .

EE

EQ

CC CEQ EC

EQ

BEQ EBQ

CQ

CC BEQ ECC BQ

CQ

VRI

V V VRI

V VVRI I

V V VV VRI I

∴ =

− −=

+= =

− +−= =

Design a voltage divider bias circuit using a Si BJT with β = 100. Fix the Q-point at ICQ = 5 mA and VCEQ = 5 V. VCC = 15 V. Answers:

2 1

1 , 1 ,11.4 , 18.6 .

E CR k R kR k R k∴ = Ω = Ω

= Ω = Ω

Choose nearest available values of resistors.

Bias Stability


VBE(V)

0 0.3 0.6 0.9 0

10

20

30

IB (μA)

500C 00C

250C

RC

+VCC

VBE

VCE

RE

ICBO

+

+

- -

R1

R2

• VBE decreases by 1.8 mV (Si) and 2.02 mV (Ge) for 10C rise in temperature.

• ICBO doubles for every 100C rise in temperature

• β (hFE) widely varies from transistor to transistor.

Thermal runway:

If ICBO increases, IC increases increases temperature of the device cumulative effect can permanently damage the device (burn out). • Rule of thumb: take Δvcemax < VCC/2.

Effects:

C E CBOI I Iα= +

1. Q-point is changed. 2. Thermal runway.

Thermal Stability


Stability factor: RC

+VCC

IE

IC

VBE

VCE

RE

IB

VB

+

+

- -

R1

R2

I1

I2


VC

VE

• Change in ICBO can permanently damage the device ICBO is the most important parameter.

C

CBO

ISI∆

=∆

( )

( )1 2

1

11

11 ||

C C B

E E

S

SR R R

SR R R R

β

ββ

ββ

= +

+=

+ +

+=

+ +

• Base bias:

• Collector-to-base bias:

• Voltage divider bias:

• S depends on the circuit configuration and the bias resistors.

• S should be as small as possible.

Thermal Stability


+18 V

VBE

VCE

+

+

- 1 kΩ

voltage divider bias configuration.

12 kΩ

33 kΩ 1.2 kΩ

collector-to-base bias configuration.

2.2 kΩ

+18 V

VBE

VCE

+

+

- -

270 kΩ

2.2 kΩ

+18 V

VBE

VCE

470 kΩ +

+

- -

Base bias configuration.

Calculate the stability factor for the three biasing schemes. In each case, the same Si transistor with β = 100 has been used.

• Base bias: S = 101 • Collector-to-base bias: S = 56 • Voltage divider bias: S = 9.

Diode Compensation


VBE

VCE

+

+

-

voltage divider bias configuration with diode

compensation.

R1

- - R2

RC

RE

VD

+

VCC The diode can compensate for the changes in VBE.

2

2

2 .

B R D

BE E

R D BEC E

E

R

E

V V VV V

V V VI IR

VR

= += +

+ −∴ ≈ =

≈ [If the two junctions have similar characteristics]

AC Analysis of BJT Circuits


Signal source incorrectly direct-coupled to the

circuit.

RC

+VCC

VBE

RE

IB

+

-

R1

R2

vs

Rs

+VCC

R1

R2

vs

Rs

VB C1

RC

+VCC

VBE

RE

IB

+

-

R1

R2

vs

Rs

VB is changed by the direct-coupled signal

source.

Signal source capacitor-coupled to the circuit.

Direct-coupled:

2

1 2

|| .||

SB CC

S

R RV VR R R

=+

• Signal source changes the Q-point.

Capacitor-coupled:

2

1 2

.B CCRV V

R R=

+

• Always use a coupling capacitor C1 to avoid the change in Q-point by the signal source.

(DC condition)

AC Analysis of BJT Circuits


Load is incorrectly direct-coupled to the circuit.

VC is changed by the direct-coupled load.

Load capacitor-coupled to the circuit.

Direct-coupled:

.LC CC

C L

RV VR R

=+

• Direct-coupled load changes the Q-point.

RC

+VCC

RE

R1

R2

vs

Rs

C1

RL

RC

+VCC

RE

VC

RL vs

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL

Capacitor-coupled:

.C CC C CV V I R= −

• Always use a coupling capacitor C2 to avoid the change in Q-point by the load.

RC

+VCC

RB /2 RB /2

CB

Negative Feedback and AC Degeneration


If IC increases above the design level, VCE decreases.

The reduced VCE level causes IB to be lower than the design value.

Because IC = βIB, IC tends to decrease. So, voltage change at the collector is fed back

to the base, where it tends to partially cancel the signal.

For collector-to-base bias RB and for voltage divider bias RE are the feedback resistors.

The above effect produces good bias stability.

• The same reaction occurs when an ac signal is applied to the circuit for amplification.

very low voltage gain. • AC bypass capacitors are connected to avoid

the above effect.

CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL

Corrected circuits.

AC and DC Equivalent Circuits


R1||R2 Rs

RC||RL

vs

RC

+VCC

RE

R1

R2

CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL vs

The amplifier circuit. AC equivalent circuit of the amplifier.

DC equivalent circuit of the

amplifier.

• AC equivalent circuit: replace all the capacitors by short circuits (assume the capacitance to be high).

• DC equivalent circuit: replace all the capacitors by open circuits (capacitors block dc signal).

• RC acts as a load in the ac equivalent circuit when external load RL is absent. • Draw a new load line for the ac source: ac load line.

AC Load Line


• DC load line remains the same as before.

Consider extreme scenario:

Q-point is fixed for the AC as well as DC load lines.

[ ]When changes to zero,

consider .0 .

CQ

CE CQ C L

c ceQ CEQ CQ C

IV I R RAt i v V I R

∆ = = ∞

∴ = ⇒ = +

DC and AC load lines on the output characteristics.

VCC /(RC+RE)

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

5

10

15

0 4 8 12 VCE (V)

IC (mA) Q-point

AC load line DC load line

VCEQ + ICQRC

AC Load Line


+18 V

VBE

VCE

+

+

- 1 kΩ


12 kΩ

33 kΩ 1.2 kΩ

Draw the DC and AC load line for the following amplifier (Si BJT with β = 100).

Solutions: DC load line:

( )1 1CC CE CC CE

CQC E C E

V V V VIR R R Rβ

− −= ≈

+ + +

0, 18 V180, 8.18 mA.

1 1.2

C CE CC

CCCE C

E C

At I V VVV I

R R

= = =

= = = =+ +

AC load line: Calculate the Q-point values first. From slide 26: 3.73 , 9.76 V.CQ CEQI mA and V= =

[ ]0, 0 .9.76 3.73 1.214.24 V.

c ce CEQ CQ C LAt i V V I R RV

∴ = = + =

= + ×=

AC Load Line (cont...)


DC and AC load lines on the output characteristics.

8.18

18

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA

= 0 μA 0

3.73

0 9.76 VCE (V)

IC (mA) Q-point

AC load line DC load line

14.24

• Note that under any condition IC cannot be more than 8.18 mA (assuming biasing circuit remains unaltered).

The amplifier circuit.

CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL vs

vs (mV)

vB (mV)

vE (mV)

vC (V) vo

(V)

Small Signal Hybrid-π Model


BJT as a two-port device.

vbe

vce

+

+

- -

ib

ic

ie

Small signal parameters: 1. Input resistance rπ (Ω), 2. Current gain β (dimension less), 3. Output resistance r0 (Ω), 4. Transconductance gm (Ω-1).

1. Input resistance rπ:

Q-point

Q-point

Q-point

change in input voltagechange in input current

1

1 .

B

BE

b

be

r

ir v

ir v

π

π

π

=

∂=∂

=

: DC value,: total instantaneous value,: instantaneous AC value.

BE

BE

be

Vvv

• Input parameters: ib, vbe. • Output parameters: ic, vce.

• Assume linear device: only for small signal Valid only in forward active region.


Department of Electronics & Electrical Communication Engineering, I.I.T. Kharagpur [email protected]

43

VBE(V)

0 0.3 0.6 0

10

20

30

IB (μA)

IBQ

VBEQ

1/rπ Q-point

, is the thermal voltage,

, called the emitter resistance.

TbeT

b CQ

Te e

CQ

Vvr Vi I

Vr rI

πβ

β

∴ = =

= =

• rπ is also called the diffusion resistance. • It is a function of the Q-point. Calculation of rπ from the

input characteristics. 2. Current gain β:

Q-point

Q-point

Q-point

change in output currentchange in input current

.

C

B

c

b

ii

ii

β =

∂=∂

=Calculation of β.

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA = 0 μA

0

5

10

15

0 4 8 12 VCE (V)

Q-point IC (mA)



3. Output resistance r0:

0Q-point

Q-point

Q-point

change in output voltagechange in output current

where is the Early voltage.

CE

C

ce

c

AA

CQ

r

vi

vi

V VI

=

∂=

∂

=

=

Calculation of r0.

VCC

IB = 40 μA

= 30 μA

= 20 μA

= 10 μA = 0 μA

0

5

10

15

0 4 8 12 VCE (V)

Q-point IC (mA)

• Consider r0 as infinite if unspecified.



4. Transconductance gm:

Q-point

Q-point

Q-point

change in output currentchange in input voltage

where is the thermal voltage

1 .

m

C

BE

c

be

CQT

T

e

g

iv

ivI VV

r

=

∂=∂

=

=

=

• Three parameters are required.

Now, .

.

CQTm

Q T

m

C

IVr g

rI V

g

π

πβ

β β

=

= × =

∴

VBE(V)

0 0.3 0.6 0

10

20

30

IB (μA)

IBQ

VBEQ

1/rπ

Calculation of rπ and hence gm from the input characteristics.

Frequency variation of β.

1

10

100

1000

0 Freq. (kHz)

|β(jω)|

500 1000 fT fβ

βdc

0.707βdc




vbe

vce

+

+

- -

ib

ic

ie

Small signal hybrid model of a npn transistor in CE configuration.

βib= gmvπ rπ vbe

+

-

r0 vπ gmvπ

vce

+

-

B C

E

ib ic


vbe

vce

-

-

+ +

ib

ic

ie

Small signal hybrid model of a pnp transistor in CE configuration.

rπ vbe

-

+

r0 vπ

vce

-

+

B C

E

ib ic

gmvπ

Calculation of Voltage Gain


AC equivalent circuit using the small signal hybrid-π.

BJT amplifier.

vi

+VCC

RC

RB

Analysis steps: • Draw the AC equivalent circuit. • Replace the BJT by its small signal equivalent model. • Calculate the input impedance, output impedance and voltage gain of the

circuit.

rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E

RB

RC

Calculation of Voltage Gain



( )0 0

0

0

0

0

0

0

.

||

.

for .

iB

m C

Cm i

C B

vi

Cm

C B

m CB

rv vr R

v g v r Rr R rg v

r R r RvAv

r R rgr R r R

rg R rr R

ππ

π

π

π

π

π

π

π

π

=+

= −

= − ×+ +

∴ =

= − ×+ +

= − × → ∞+

rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E

RB

RC

• Parallel combination: 5 k||200 k = 4.87 kΩ.



Draw the small-signal hybrid-π equivalence of the following circuit (Si BJT with β = 100 and VA = 500 V). Solutions:

0

1

3.73mA( calculated previously).26100 134k .

3.73

697 . 143.5 .

CQ

T A

CQ CQ

CQm

T

IV Vr rI I

Ig mV

π β

−

=

∴ = = × = = Ω

= Ω = = Ω


+18 V

1 kΩ


12 kΩ

33 kΩ 1.2 kΩ

rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E

RB

RC R1||R2

Small Signal Analysis of CE Amplifier


CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL vs


R1||R2 Rs

RC||RL

vs

AC equivalent circuit of the amplifier.

AC equivalent circuit using the small signal hybrid-π model.

rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E RC||RL R1||R2

RS



( )

( )

1 2

1 2

0 0

1 20

1 2

|| || .|| ||

|| |||| |||| || .

|| ||

ss

m C L

m C L ss

R R rv vR R r R

v g v r R RR R rg r R R v

R R r R

ππ

π

π

π

π

=+

= −

= − ×+


rπ vs

+

-

r0 vπ gmvπ v0

+

-

B C

E RC||RL R1||R2

RS

( )

( )

( ) ( )

0

1 20

1 2

0

|| |||| |||

|

| |||| for 0 an ,

.|

d

||

VLs

m C Ls

m C L s

CC L

eL

vAv

R R rg r R RR R r R

R Rr

g R R R r

R Rr

π

π

π

β

∴ =

= − ×+

=

−

− → →∞

= − =

• Voltage gain without RL:

( ) 1 20 0

1 2

|| |||| .|| ||

Cv m C m C C

s e

R R rA g r R g R RR R r rR

Rr

π

π π

β−= − × ≈ − = − =

+



( )

( ) [ ]

1 2

1 2

.

|| ||

, where || .||

oi

i

b i

i b BB

iAi

R R ri irri i R R R

R r

π

π

π

π

=

=

⇒ = =

( )

( )

( )( )

0

0

|| ||Now,

|| || ||

.

C Lo m

L

C L Bi m

L b

C B

C L B

r R Ri g vR

r R R R rA g vR i r

R RR R R r

π

ππ

π

π

β

=

∴ = ×

=+ +

• Power gain: .p v iA A A= ×


Current gain:

rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E RC R1||R2

RS ic iL

RL

ib ii




rπ vi

+

-

r0 vπ gmvπ v0

+

-

B C

E RC R1||R2

RS

Ro Ri

1 2

0

Input resistance || || .Output resistance || .

i

o C C

R R R rR r R R

π== ≈

• Input resistance is the resistance seen by the AC source. • Output resistance is the resistance seen by the load.

• Voltage gain mainly depends on RC and RL. We may end with attenuation instead of amplification if RL is too small.



100 μF

3.9 kΩ

12V

4.7 kΩ

68 kΩ

56 kΩ

82 kΩ

100 μF

47 μF


Calculate the input and output impedances and the small signal voltage gain of the amplifier (Si BJT with rπ = 2.1 kΩ, β = 75, ro = 1 MΩ).

Solutions: • If unspecified, the small signal equivalent

parameters are to be calculated from the DC biasing condition.

1 2

0

Input resistance || || 1.97k .Output resistance || 3.9k .

i

o C

R R R rR r R

π= = Ω= ≈ Ω

( )|| 133.VL C LA R Rrπβ

= − = −

139.3.V CA Rrπβ

= − = −Voltage gain without the load:

Voltage gain with the load:

Recalculate the gain if the load is changed to 8 Ω (e.g. a sound box speaker). Answer: Voltage gain with the load: ( ) 0.29 ( attenuation).VL LA r Rπβ≈ − = −

CE Amplifier With an Emitter Resistor


CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL vs


R1||R2 Rs

RC||RL

vs

AC equivalent circuit of the amplifier.

RE

Equivalent small signal hybrid-π model.

rπ vs

+

-

r0 vπ gmvπ v0

+

-

B C

E RC||RL R1||R2

RS

RE βib+ib

ib

ic



( )

( )

( )

1 2

Applying KVL,

1 .

Emitter resistance is multiplied by a factor 1 .

|| || , and|| .

i b b b E

iib E

b

i ib

o C o C

v i r i i RvR r Ri

R R R RR R r R

π

π

β

β

β

= + +

∴ = = + +

∴ +

∴ == ≈ Output resistance remains almost

unchanged but input resistance increases.


rπ vs

+

-

r0 vπ gmvπ v0

+

-

B C

E RC R1||R2

RS

RE βib+ib

ib

ic

Ri Rib

RL

Ro

vi

+

-



( )

( )

( )( )

00

.

For , put || instead of

11

for 0 and 1 ,1

.

ii s

i s

b C iv VL C L C

s i i s

b i iC C

i i s E i s

Cs E

E

C

E

Rv vR R

v i R RA A R R Rv v R R

i R RR Rv R R r R R RR R R r

RRR

π

π

β

β ββ

β ββ

=+

∴ = = − × +

≈ − × = − ×+ + + +

≈ − → + >>+

≈ − Voltage gain decreases.


rπ vs

+

-

r0 vπ gmvπ v0

+

-

B C

E RC R1||R2

RS

RE βib+ib

ib ic

Ri Rib

RL

Ro

vi

+

-



100 μF

3.9 kΩ

12V

4.7 kΩ

68 kΩ

56 kΩ

82 kΩ

100 μF


Calculate the input and output impedances and the small signal voltage gain of the amplifier (Si BJT with rπ = 2.1 kΩ, β = 75, ro = 1 MΩ).

Solutions: ( )

1 2

0

1 359.3 k .Input resistance || || 28.3k .Output resistance || 3.9k .

ib E

i ib

o C

R r RR R R R

R r R

π β= + + = Ω

= = Ω= ≈ Ω

( )0.82.

1C

VE

RAR

ββ

= − = −+

Voltage gain without the load:

Small Signal h-Parameter Model



vbe

vce

+

+

- -

ib

ic

ie

Small signal hybrid model of a npn transistor in CE configuration and approximate

relationship with rπ parameters.

(rπ)

vbe

+

- (r0)

hfeib vce

+

-

B C

E

ib ic

+ - (gmib) 1/hoe

hie

hrevce

be ie b re ce

c fe b oe ce

v h i h vi h i h v

= += +

• Input voltage and output current are expressed in terms of input current and output voltage.

Small Signal h-Parameter Model


0

0

-3

0

0

, small signal input resistance( ~k Ω

) .

, small signal current gain.

reverse transverse ratio or voltage feedback ratio( ~10 ) .

1 , small signal output conductanc

ce

ce

b

b

beie

b v

cfe

b v

bere

ce i

coe o

ce i

vh ri

ihi

vhv

ih rv

π

β

=

=

=

=

= ≈

= ≈

=

= ≈ -6e( ~10 ) .

be ie b re ce

c fe b oe ce

v h i h vi h i h v

= += +

Amplifier


Representation of an amplifier.

Ri vo (V)

vi (mV)

Ro

ii (pi)

io (po)

[ ]

[ ]

p 10

2

10 2

10

10

Power gain( dB) ,

A 10log

10log

20log only when ,

20log only when .

o

i

o L

i i

oi L

i

oi L

i

p dBp

v R dBv Rv dB R Rvi dB R Ri

=

=

= =

= =

Half-power points: ( )

( )

10

10

when 2 . . 2 ,

210log

10log 1 23.01 3 dB.

o i o i

ip

i

p p i e v v

pAp

= =

=

=

= − ≈ −

Frequency Response of an Amplifier


Frequency response of an amplifier.

0

10

20

30

0 100 Freq. (kHz)

Ap (dB)

200 300 400

3 dB

fc1 fc2

Half-power bandwidth

• fc1 and fc2 corresponds to the half-power points and known as the lower and higher cut-off frequencies, respectively.

• The output voltage vo = 0.707vi at the cut-off frequencies.

• The difference (fc1 - fc2) is known as the half-power bandwidth of the amplifier.

• f0 = (fc1 - fc2)/2 is called the mid-band frequency or center frequency of the amplifier.

Frequency variation of β.

1

10

100

1000

0 Freq. (kHz)

|β(jω)|

500 1000 fT fβ

βdc

0.707βdc

High Frequency Limitation of BJT


High frequency small signal equivalent circuit of a npn transistor in CE configuration.

High frequency limitations: 1. Junction capacitances: base-emitter and collector-base junctions are associated with junction capacitances. 2. Transit time: charge carriers take finite transit time.

rπ vbe

+

-

r0 Cbe gmvπ vce

+

-

B C

E

ib ic Cbc

• Limitation is represented by a cutoff frequency fα where voltage gain falls to 0.707 of the mid-band value.

• Common-emitter cutoff frequency: β falls to 0.707 of the mid-band value at fαe (sometimes fβ).

• Common-base cutoff frequency: α falls to 0.707 of the mid-band value at fαb (sometimes fα).

• Cbc: capacitance of the reverse-biased C-B junction.

• Cbe: capacitance of the forward-biased B-E junction.

.b ef fα αβ=

High Frequency Limitation of BJT


Unity gain frequency:

fT : in CE configuration, where short-circuited current gain is unity.

gain×bandwidth .T bf fα= ≈

• For a given device, the gain-bandwidth product is a constant term that cannot be changed.

• Cbe and Cbc are in pF range and their values depend on the Q-point values.

Representation of the junction capacitances.

Cbe

VCC

RC

Cbc

6.1 .Ebe

T

ICf

≈

Miller effect: • If there is any capacitance (Cio) between the input and output terminals of an

inverting voltage amplifier (-Av), then the equivalent input capacitance (CM) increases.

( )1 .M io vC C A≈ +

Miller Effect


Miller effect.

Cbe

VCC

RC

Cbc

Cbe

VCC

RC

CM

( )

( )

Change in output voltage because of a change in input voltage ,.

Total collector-base voltage reduction,1 .

Now, charge change in voltage.Charge supplied to the input.

1

o i

o v i

CB i v i i v

bc v i

V VV A V

V V A V V AQ C

Q C A VC

∆ ∆∆ = − ∆

∴

∆ = ∆ + ∆ = ∆ +

= ×∴

= × + ∆

= .M iV∆

In CE configuration, total input capacitance is ( )1in be v bcC C A C= + +

Frequency Response of a CE Amplifier


CE

C2

C1

RC

+VCC

RE

R1

R2 Rs

RL vs

BJT in CE configuration.

• The coupling capacitors (C1 and C2) block low frequency signal: highpass filtering.

• For the input side, the corresponding cutoff frequency:

• The input capacitance Cin + stray capacitance (a few hundred pF together) bypasses high frequency components: lowpass filtering.

• Miller effect does not occur in common-base configuration: operates to a much higher frequency.

11

12c

inf

R Cπ=

C1

Rin Rs

vs vin

+

-

RC highpass filter.

Cs RL Ro

Avvi vo

+

-

RC lowpass filter.

Noise in BJT Circuit


Thermal noise: because of random thermal motion of electrons in a metal.

[ ]34

23

4 4 Volt, for <<exp( ) 1

where 6.626 10 J-S is Planck's const.1.37 10 J/K is Boltzmann's const.temperature( K)bandwidth, - center frequency( Hz)resistance( Ω

)

nh f BRe kTBR hf kThf kt

hkTB fR

−

−

= ≈−

− ×

− ×−−−

• Resistors are the main source of noise • rms value of this noise voltage is

• Some other noises: Shot noise (independent of f and T), Flicker noise (1/f), Transit-time noise (at high frequencies) etc.

Noise figure 1( also expressed in dB)in in

out out

S NFS N

= ≥

Power Dissipation


Power dissipation at an ambient temperature, .D C CEP I V=

• When designing a circuit, consider maximum possible values of the current and voltage.

max maxD C CEP I V∴ =

2.2 kΩ

VCC

IE

IC

VBE

VCE

470 kΩ

IB

+

+

- -

The amplifier shown in the figure uses a 2N3904 BJT (PD = 625 mW at 250C). Calculate the maximum value of VCC that can be applied without damaging the device.

37 .D CC CC C

CC

P V V RV V

∴ = ×⇒ =

Transfer Characteristics


470 kΩ

Vi

IB

+12 V

IE

IC

Vo

10 kΩ

Draw the transfer characteristic of the following amplifier with β = 100.

Solution: OFF state:

0.2

12

0.7 4.85 Vi (V)

Vo (V)

ON state: Vi>0.7 (forward active region) 0.7

470k0.712 10 12 100 10k

470k

iC

io C

VI

VV I k

β −=

−= − × = − × ×

0.712 0.2 12 100 10k470k

4.85 V

i

i

V

V

−− = − × ×

⇒ =

When BJT is in saturation Vo= 0.2 V

Vi <0.7 (cutoff condition) Vo= 12 V.

Switching Circuit


• OFF state (Vout = VCE ≈ VCC): Vi is low/ negative IB ≈ 0 the BJT is in cutoff, IC = ICBO.

VCC /RC

VCC = 12

IB = 40 μA

= 30

= 20

= 10

= 0 0

4

8

12

0 3 6 VCE (V)

IC (mA) RC = 1 kΩ

= 3 kΩ

Design equations:

[ ]

( )

min

maxmax

maxmax

max max

Off state: check cut-in voltage.

On state: choose = 1mA if unspecified

,

11 . Choose 12

i

CCC C

C

CC i CCB C

B C

i iB C B C

CC CC

VVR II

V V VNow I IR R

V VR R R R

V V

β β

β β

⟨

=

−⟩ ⇒ ⟩

⟨ − = −

VBE

VCE

RB

+

+

- -

Capacitor-coupled switching circuit.

RC

VCC

vs • ON state (Vout = VCE ≈ 0.2 V): Vi is high IB = IBmax the BJT is in saturation, IC ≈ VCC /RC.

Switching Circuit


Design a capacitor-coupled stitching circuit using base-bias configuration. IC should not exceed 1 mA. The input is a positive square wave of amplitude 5 V with a PRF = 10 kHz, VCC = 6 V, a Si-BJT with β = 100 is to be used.

Solutions:

max

6 .

5100 6 16

100 .Take 50 .

CCC

C

B

B

B

VR kI

R

R kR k

= = Ω

⟨ × × −

⇒ ⟨ Ω= Ω

VBE

VCE

RB

+

+

- -

Capacitor-coupled switching circuit.

RC

VCC

C

Direct-coupled switching circuit.

VBE

VCE

50 kΩ

+

+

- -

+6 V

6 kΩ

vs

Problems on BJT -1


2.2 kΩ

+12 V

IE

IC

VEC

470 kΩ

IB

+

- Solution:

12 0.7 24.04470k3.6126 7.2 .3.61

B

C

e

I A

I mAmVrmA

µ−= =

∴ =

∴ = = Ω

Small signal equivalent circuit.

βre vπ gmvπ

B C

470 kΩ 2.2 kΩ

ib ic

470k || 1080 10772.2 k

Now, , and .2.2 305.5.7.2

i

o

o b c i b e

Cv

e

RR

v i R v i rkRA

r

β β

= = Ω= Ω

= = −

∴ = − = − = −

P1. In the following circuit, a Si BJT with β = 150 is used to design an amplifier. Calculate the emitter resistance re, Ri, Ro and the small signal voltage gain of the amplifier.

Problems on BJT -2



+18 V

2.2 kΩ

100 kΩ 100 kΩ

Solution: ( )

( )

12 1 2.2k 200k18 0.7 40.98 μA.200k 101 2.2k

4.1 mA.26 6.34 .4.1 mA100k || 100 6.34 630100 || 2.2 k =2.15 .

B B

B

C

e

i

o

I I

I

ImVr

RR k

β= + × + ×

−⇒ = =

+ ×∴ =

∴ = = Ω

∴ = × = Ω

∴ = Ω

AC equivalent circuit.

100 kΩ

100 kΩ 2.2 kΩ

Now, , and .2.2 || 100 339.

6.34

o b o i b e

v

v i R v i rk kA

β β= − =

∴ = − = −

Problems on BJT



Solution: ( )

( )

18 1 1k 330k18 0.7 40.14 μA.330k 101 1k

4.01 mA.26 6.48 .4.01 mA330k || 100 6.48 646.72.2 k .

B B

B

C

e

i

o

I I

I

ImVr

RR

β= + × + ×

−⇒ = =

+ ×∴ =

∴ = = Ω

∴ = × = Ω

∴ ≈ Ω

Now, , and .2.2k 339.5.6.48

o b o i b e

Cv

e

v i R v i rRAr

β β= − =

∴ = − = − = −

47 μF

2.2 kΩ

18V

1 kΩ

330 kΩ

47 μF

10 μF

Small signal equivalent circuit.

βre vπ gmvπ

B C

330 kΩ 2.2 kΩ

ib ic

Questions


100 μF

4.7 kΩ

12V

3.3 kΩ

33 kΩ

22 kΩ

100 kΩ

100 μF

47 μF


Q1. In the following circuit, a Si BJT with β = 100 is used to design an amplifier. Calculate the change in no-load voltage gain if β is changed to 200.

Q2. Design a collector-to-base bias circuit using a 12 V DC source and a pnp type Si BJT with β = 150 and fix the Q-point at (5V, 1 mA). Draw the load line. Redraw the load line if β is changed to 200.

RC

RB

+VBB

IB

+VCC

IE

IC

VBE

VCE

+

-

[email protected] Ph. – +91-3222-283550 (o) Department of E. & E.C.E. I.I.T. Kharagpur, 721302.

Thank you

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Documents

Intro to Electronics BJT 2015 (2)