Introduction to Xilinx Design Constraints (XDC)gongterr.co.kr/down/session7_Intro_XDC_Henry.pdf · Introduction to Xilinx Design Constraints ... get_timing_paths Timing path objects,

Xilinx Confidential – Internal

Software Applications

Introduction to Xilinx

Design Constraints (XDC)

Page 1

Xilinx Confidential – Internal • Unpublished Work © Copyright 2011 Xilinx

Topics

Xilinx Design Constraints (XDC)

Netlist object querying

Timing assertions

Timing exceptions

Physical constraints

Demo

Lab


Xilinx Design Constraints (XDC)

Version 9


Journal and Log Files

Journal and Log Files

– Linux – directory where planAhead is invoked

– Windows via icon - %APPDATA%\Xilinx\PlanAHead

C:\Users\<user_name>\AppData\Roaming\Xilinx\PlanAhead

– Windows via command line – in directory where planAhead is invoked

– From the GUI you can access via:

• File -> Open Log File

• File -> Open Journal File

Page 4


XDC & Rodin Tcl Defined

SDC - Synopsys Design Constraints

XDC - Xilinx Design Constraints

– Tcl Equivalent to UCF/PCF/XCF/BCD

Rodin Tcl

– SDC + XDC

– Xilinx commands

• Project, compilation, report,…

– Xilinx objects

• Netlist, device, timing, project,…

– General Tcl (8.5)

• List-related commands are overloaded to support primary objects,

unlike Synopsys and Altera

• Primary objects can directly be used with general commands, unlike

Synopsys and Altera

=> Improved Ease-Of-Use!

Page 5

Rodin Tcl

XDC

SDC


Benefits of XDC and Rodin Tcl – Why you should care

Future constraint language from Synthesis to P&R

– Rodin-only for sign-off static timing analysis (STA)

Powerful debug and analysis

– Fast custom timing reports

– What-if Analysis with incremental STA

– Extendable

Industry standard Tool Control

– Altera, Synplify, Precision, and all ASIC Synthesis/P&R

– 3rd Party EDA Tools Use Same Interface - EOU

Cross-platform Scripting (Linux and Windows)

– Just beware those DOS backslashes! “\”

• Use “/” or {}

Page 6


Tcl limitations within XDC files

Cannot do looping in an XDC file (foreach, while, etc)

Limited to doing simple Tcl commands

– Full list documented in the getting started guide

Can write Tcl scripts to do more complex work if needed

– Execute via “source <name>.tcl”

Page 7


General Differences between UCF/ISE and

XDC/Rodin

Constraint vs Command

– UCF: A constraint

– XDC: Tcl command (i.e. defines path(s) requirement)

Path Resolution/Constraint Intersection

– ISE: Complicated

– Rodin: Simple; XDC follows specific priority to defining a path’s requirement

Multiple Constraints for same path (i.e. Clock Mux)

– ISE: Requires 2 UCF

– Rodin: Simple; A path can be covered by different clock periods

Page 8


Rodin Tcl – Documentation & Help

Documentation in the Lounge and Wiki

– http://testlinx/member/rodin_beta/

– http://xsjrdodin/twiki/bin/view/Main/Documentation

Help from Tcl prompt

% help - list categories (see next slide for details)

% help * - list all commands with brief description

% help get_cells - gives details of “get_cells” command

% help get_* - lists all commands starting with “get_” with

a brief description

Help for Specific Commands:

% <command_name> -help

Page 9

http://testlinx/member/rodin_beta/

http://xsjrdodin/twiki/bin/view/Main/Documentation


PlanAhead – help categories

Help categories

– To aid in organizing the many commands available, they are grouped

by functionality

% help

% help –category <name> - gives list and brief description of

commands in that category

Page 10


PlanAhead Command Categories Examples

Project - Project Management

– create_project

– add_files

– import_files

– import_ip

Object - Object Access

– get_cells

– get_property

– set_property

Report

– report_timing

– report_power

– report_drc

Project - Runs, Synthesis and

Implementation Control

– create_run

– launch_runs

– wait_on_run

FileIO

– read_verilog

– read_xdc

– read_csv

– write_verilog

GUIControl

– start_gui

– stop_gui

Page 11


XDC Objects - Design

Page 12

net

cell

pin port

clock

First Class Objects

– Not just strings!!

Properties

– Query and filter with “get_” commands

% get_cells –hier * -filter {LIB_CELL == FD}

% filter [get_cells –hier *] {LIB_CELL == FD}

– Set value with “set_property” (or reset_property)

– Get value with “get_property”

Related objects with “-of_object”

% get_nets -of [get_pins -of [get_cells]]

% get_clocks -of [get_nets core_clock]

Special support in General Tcl

– Simplified scripting syntax, unlike Altera & Synopsys

% llength [get_cells A/B/*/C]


Filtering

Can use the -filter <args> option with get_* commands

Filter the results list with the specified expression

For example, the -filter argument filters the list of objects returned

by get_cells based on property values on the cells.

You can find out what properties are on an object with the

report_property or list_property commands

The specific operators that can be used in the filter expression are:

==, !=, and =~, as well as && and || between filter patterns

Example:

get_ports -filter {DIRECTION == in && NAME =~ *clk*}

Page 13


What to filter on?

Use the list_property command to help you identify properties

to filter on:

% list_property -class cell

BEL CLASS DONT_TOUCH FILE_NAME IOB IODELAY_GROUP

IS_BEL_FIXED IS_BLACKBOX IS_LOC_FIXED IS_PARTITION…

The list_property_value command will list the valid property

values of an object:

% list_property_value –class cell <enum_property_name>

This command currently only works on enum properties

– Eventually will extend to the design context

Page 14


Hierarchy Separators and Wildcards

work differently than UCF

Speed tradeoff with large netlists and Native SDC

– UCF style searches cannot handle 2 million+ instances

Possible confusion between “/” and “/”

– Synthesis replaces hierarchy separator with pseudo-hierarchy

separator when flattening the netlist

– Default is the same for both: “/”. This can be modified in Rodin.

UCF Command:

– INST “oneInst/twoInst/myInst/*” AREA_GROUP=ag;

Native SDC:

– get_cells oneInst/twoInst/myInst/*

– Wildcard characters don’t match names across hierarchy, but they do

match pseudo-hierarchy separator

UCF-style in SDC – equivalent but not optimal

get_cells * -hier -filter {name =~ oneInst/twoInst/myInst/*}

Page 15


Netlist object queries


Helper Commands: get_*, all_*

Lots of helper commands to query the design database

Useful for netlist traversal and project exploration

Can be used in conjunction with timing constraint commands

Do not return a string, return an object

Page 17


Object query commands

Command Description

get_cells Cell objects based on name/hierarchy or connectivity

get_pins Pin objects based name/hierarchy or connectivity

get_nets Net objects by name/hierarchy or connectivity

get_ports Top-level netlist ports by name or connectivty

get_clocks Clock objects by name or object traversed

get_generated_clocks Clock objects (generated only)

get_path_groups Path group objects

get_timing_paths Timing path objects, equivalent to report_timing printout

get_iobanks IO Bank objects, needed for constraining

…

Page 18


get_cells

Page 19

get_cells - 3 use models

– Global Expression: get_cells *Reg*

– Regular Expression: get_cells -regexp -nocase .*reg.*

– Object: get_cells -of_objects <pin or net object>

Hierarchical search:

get_cells –hier xReg_*


Convenience/helper commands

Page 20

Topic Description

all_clocks Get a list of all clocks in the current design (timing)

all_dsps Get a list of dsp cells in the current design

all_fanin Get a list of pins or cells in fanin of specified sinks (timing)

all_fanout Get a list of pins or cells in fanout of specified sources (timing)

all_hsios Get a list of hsio cells in the current design

all_inputs Get a list of all input ports in the current design

all_outputs Get a list of all output ports in the current design

all_rams Get a list of ram cells in the current design

all_registers Get a list of register cells in the current design (timing)


get_nets, get_pins, get_ports

get_nets: return net object(s)

– get_nets -of_objects [get_cells arnd2/ct0/xReg_reg[0]]

get_pins: return pin object(s)

– get_pins -of_objects [get_cells i_747]

get_ports: return port object(s)

– get_ports -of_objects [get_nets n_123]

Tons more get_* commands

– help get_*

Page 21


Pins and Ports

Once instanced, ports of a module become pins of a cell

get_ports returns only top level IO ports of the design

Page 22

top

module

Ports Ports

Pins Pins


Timing Assertions


Timing Assertion Definitions

Assertion => Fundamental Period and IO Commands

Exception => Multicycle, False Paths, Min/Max delays

Start-Point => Input/Bi-Dir Port and/or Synchronous Element

End-Point => Synchronous Element and/or Output/Bi-Dir Port

Input Pad => Input Port

Output Pad => Output Port

Recovery => Assertion of the asynchronous clear/preset

Removal => De-assertion of the asynchronous clear/preset

Pulse-width Check => Component Switching Limit Check

Page 24


UCF to XDC Conversion Basic Timing Constraints and Exceptions

UCF XDC

TIMESPEC PERIOD create_clock

OFFSET IN set_input_delay

OFFSET OUT set_output_delay

TIG set_false_path

FROM/THRU/TO set_multicycle_path

set_max_delay/set_min_delay

TNM create_path_group

INST “X” LOC= set_property LOC

Page 25

Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx Page 26

OK

?

Yes

check_timing -verbose -override_defaults no_clock

No

No

set_input_delay

Create Clocks create_clock

create_generate_clock

Check for missing clocks

Set input delays

check_timing -verbose -override_defaults no_input_delay

Check for missing input delays

set_output_delay

Set output delays

check_timing -verbose -override_defaults unconstrained_endpoints

Check for missing output delays

No

Yes

Yes

Verify clocks

report_clocks

OK

?

OK

?

OK

?

No

set_false_path set_clock_group

OK

?

Implement

No

report_timing [with filters]

Check Timing

Check for async clock boundaries

report_clock_interaction

Yes

Add Exception

set_multicyle_path

set_max_delay

set_min_delay

set_case_analysis

Add Design Exceptions

Yes

No


Assertion Path Types

Input Pads to Synchronous Element

Synchronous Element to Synchronous Element

Synchronous Element to Output Pad

Input Pad to Output Pad

Page 27


Clock Definition

Clock characteristics

– Period

– Waveform (duty cycle)

• Even number of edges

• First value = first rising edge time

– Latency

• source: latency outside the design

• network: latency inside the design – computed by Rodin

– Jitter

• User specified: set_input_jitter, set_system_jitter

• Final value computed by Rodin (includes phase error)

– Uncertainty (additional margin)

Report constrained clocks

– get_clocks / all_clocks

– report_clock/report_clock_interaction

Page 28


Clock creation: UCF/XDC Examples

UCF:

– NET clock_input TNM_NET = clk_grp;

– TIMESPEC TS_clk = PERIOD clk_grp 4 ns;

XDC:

– create_clock –name clock_input –period 4 [get_ports clock_input]

UCF:

– NET clock_input TNM_NET = clk_grp;

– TIMESPEC TS_clk = PERIOD clk_grp 4 ns HIGH 40% INPUT_JITTER 200 ps;

XDC:

– create_clock –name clock_input –period 4 -waveform {0.0 1.6} [get_ports clock_input]

– set_input_jitter 0.2 [get_clocks clock_input]

Page 29


Generated Clocks

Derived from master/primary clock

– Frequency multiplication/division

– Phase shift / duty cycle change

– PLL/MMCM/BUFR create generated clocks

• Automatically constrained by Rodin if not already done by the user

• Predictable clock name: <master_clock_name>:<CMB_inst>:<input_pin>:<output_pin>

Edges propagation from master to derived

– Edges start from master clock ones, propagate through cells on the tree

– Insertion delay = master clock network + derived clock network

Example – create_generated_clock -name CLK1 –source REGA/C –divide_by 2 REGA/Q

– create_generated_clock -name CLK1 –source REGA/C –edges {1 3 5} REGA/Q

Page 30

CLK1

CLK0

REGA

D Q

CE

BUFG0

CLK0

CLK1

(edge#) 1 2 3 4 5 6 7 8 9 10 11 12


Generated clock: UCF/XDC Examples

UCF: – NET clk2 TNM = clk_div_grp;

– TIMESPEC TS_clk_div = PERIOD clk_div_grp TS_clk / 2 INPUT_JITTER 350 ps;

XDC: – create_generated_clock –name CLK2 –source [get_ports CKP1] –divide_by 2 [get_pins FF1/Q]

– set_input_jitter 0.35 CLK2

create_clock –name CLK0 –period 8 [get_ports CLK0]

create_generated_clock –name CLK1 –source CMB/CLKIN –edges {1 2 3} –edge_shift {0 -1.0 -2.0} CMB/CLKOUT

OR (simultaneous use of multiply_by & divide_by – Xilinx enhancment)

create_generated_clock –name CLK1 –source CMB/CLKIN –multiply_by 4 –divide_by 3 CMB/CLKOUT

Page 31

CLK1

CLK0 CMB

CLKIN CLKOUT CLK0 CLK1

(edge#) 1 2 3 4 5 6

(time) 0ns 4ns 8ns

(time) 0ns 3ns 6ns


Input Delay

Model external input delays, off chip delay values

Defines a relationship of data arriving at input port after clock

arrival

– set_input_delay

Recommend associate with a real clock via –clock option

By default, in Rodin XDC flow, the unconstrained input ports

are constrained WRT a virtual clock (input port clock). To

disable this default clock:

– config_timing_analysis –enable_input_delay_default_clock false

Page 32

REGA

D Q

CE

CLK0

REGI

D Q

CE

DIN

FPGA DEVICE

BUFG0

Input Delay

Internal Delay

Port Clock


UCF OFFSET IN SDC Example

UCF: (assume Period = 5 ns)

– OFFSET = IN 1.5 ns BEFORE clock_input;

• Requirement = PERIOD – (Board Trace Delay +

Upstream Clk2Out)

XDC:

– set_input_delay –max 3.5 –clock clock_input [all_inputs]

• Requirement = Board Trace Delay + Upstream Clk2Out

• Or Requirement = UCF PERIOD – UCF OFFSET


– INST “input_data*” TNM = input_pad_grp;

– TIMEGRP input_pad_grp OFFSET = IN 1.5 ns

VALID 4 ns BEFORE clock_input;

XDC:

– set_input_delay –max 3.5 –clock clock_input [get_ports input_data*]

– set_input_delay –min 2.5 –clock clock_input [get_ports input_data*]

Page 33


Output Delay

Model external output delays

– Downstream Setup (max)

– Downstream Hold (min)

– Downstream Board delay

Path delays beyond the FPGA Boundaries

Defines a relationship of the data departing at the output port before

the clock arrival

set_output_delay

Page 34


OFFSET OUT XDC Example


– OFFSET = OUT 3.5 ns AFTER clock_input;

• Requirement = PERIOD – (Board Trace Delay +

Downstream Setup)

XDC:

– set_output_delay 1.5 –clock clock_input [all_outputs]

• Max Requirement = Board Trace Delay + Downstream Setup

• Min Requirement = Board Trace Delay + Downstream Hold

• Or Requirement = UCF PERIOD – UCF OFFSET


– INST “output_data*” TNM = output_pad_grp;

– TIMEGRP output_pad_grp OFFSET = OUT 3.5 ns

AFTER clock_input;

XDC:

– set_output_delay –max 1.5 –clock clock_input [get_ports output_data*]

Page 35


Timing Exceptions


Timing Exceptions – Overriding Constraints

False Path

Exclusive/Asynchronous Clock Groups

Multicycle Paths

Maximum and Minimum Delay Paths

Case analysis

Page 37


False Paths

Invalid timing paths:

– Cross clock domains (or paths groups) when the clocks are unrelated

set_false_path –from [get_clocks CLK0] –to [get_clocks CLK1]

– Static signals driven by configuration registers or input ports

set_false_path –through [get_pins MUX/S]

Removing such timing paths can be beneficial

– Reduce stress on timing-driven implementation tools

– Focus on and report real critical paths

UCF equivalent

– TIMESPEC “TS_false” = FROM “REGA/Q” TIG;

Page 38

REGA

REGB

Static signal

S


Asynchronous/Exclusive Clock Groups

Efficiently constrain exclusive clocks

– Example: clock MUX

CLK0 and CLK1 are 2

exclusive clocks

set_clock_groups -physically_exclusive -group CLK0 -group CLK1

Efficiently constrain unrelated clocks

– Default: all clocks are related

– Equivalent to false path constraint, for both directions and without edge

filters (CLK0 => CLK1 & CLK1 => CLK0)

set_clock_groups -asynchronous

-group CLKA

-group CLKB

Page 39

CLK0

REGA

CE

D Q

REGB

CE

D Q

CLK1

CLKA

REGA

CE

D Q

REGB0

CE

D Q

CLKB

REGB1

CE

D Q


Asynchronous/Exclusive Clock Groups

Auto derived clocks

Timing engine creates generated clocks on Clock Modifying

Block Output Pins (if not manually specified)

– Generated Clocks characteristics are based on Master Clock definition

and CMB parameters

– SDC standard behavior:

• all clocks are related => derived clocks are related too !!

• Master clocks are unrelated ≠ auto derived clocks are unrelated !!

set_clock_groups -asynchronous -group [get_clocks CLKB]

-group [get_clocks {CLKA CLKA:MMCM_inst:CLKIN1:CLKOUT0}]

CLKA

REGA

CE

D Q

REGB0

CE

D Q

CLKB

REGB1

CE

D Q MMCM_inst

CLKIN1

CLKFBIN CLKFBOUT

CLKOUT0


Multicycle Paths – Setup and Hold checks (1/2)

Some logic paths need more than 1 clock cycle to propagate

to the next sequential cell, which can be controlled by design

Adding such constraints can be beneficial

– Reduce stress on timing-driven implementation tools

– Focus on and report real critical paths

Hold check clock edge refers to setup check clock edge

Consequence of multicycle path on setup/hold checks

– Setup check is performed N clock cycles after the launch clock edge

– Hold check is performed N-1 clock cycles after the launch clock edge

(default)

– Hold check can be moved separately (-hold option)

• set_multicycle_path –hold <N-1-Value> xxx

UCF equivalent:

– TIMESPEC TS_A = FROM “MG_FD” TO “MG_FD” TS_CLK*2;

Page 41


Multicycle Paths – Setup and Hold checks (2/2)

Page 42

REGA

CE

D Q

REGB

CE

D Q

Multicycle Path = 2T

CLK

REGA/CLK

REGB/CLK

REGB/D

REGA/CLK

REGB/CLK

REGB/D

REGA/CLK

REGB/CLK

REGB/D

> create_clock –name CLK –period 10 CLK

> set_multicycle_path –from REGA/CLK

–to REGB/D 2


–to REGB/D

2


–to REGB/D

-hold 1

SETUP HOLD

SETUP HOLD

Violation!!

Violation!!

SETUP HOLD


Min/Max Path Delays

Specify a timing path requirement without defining a clock

– Feed-through paths

• Example between input and output ports

– Paths across asynchronous timing groups

– Override existing timing requirement defined by a clock period

between 2 sequential cells

Max delay timing check (setup/recovery): set_max_delay

Min delay timing check (hold/removal): set_min_delay

No support for “DATAPATHONLY” (for now)

– Clock skew is always considered

UCF equivalent:

– TIMESPEC TSname=FROM “group1” TO “group2” value [DATAPATHONLY];

Page 43

portA portB

REGA

D Q

REGB

D Q

CLKA CLKB


Case Analysis

Specifies that a port or pin is at a constant logic value 1 or 0,

or is considered with a rising or falling transition

Propagates the following through the design

– Constant (1 or 0)

– Transition (rising or falling)

Propagate constant causes timing paths to be disabled

Propagate transition causes certain timing paths to be limited

to that transition

– set_case_analysis <value> {port_or_pin_list}

Report the case analysis elements

– report_case_analysis

Page 44


Case Analysis Example

2:1 Mux – Select is set to 1 causes the timing paths to be

disabled from I0 input

– set_case_analysis 1 SEL

Page 45

Output In0 (I0)

In1 (I1)

Sel


Physical Constraints


Physical Constraints

Majority of ISE Physical Constraints are supported in Rodin

In general, SDC uses set_property command

– UCF: INST "XCOUNTER/BU5" LOC=SLICE_X32Y49;

– XDC: set_property LOC SLICE_X32Y49 [get_cells XCOUNTER/BU5]

IO Properties will not be supported on NETs:

– Will generate an error:

XDC: set_property LOC H18 [get_nets RESET]

Page 47


Location Constraints

Area Groups

– Rodin uses Pblocks

– Ranges include CLOCKREGION, SLICE, DSP48 and RAMB

• No Pblock ranges on IOBs

– Existing ISE AG attributes will not be supported in Rodin

• Any required for HD will be added when HD is supported

LOC Constraints

– XDC does not support multiple locs; XDC will use pblocks with ranges

– BANK constraints – Not Supported

– T,L,R,B and LB, RB, LT, RT, BR, TR, BL,TL – Not Supported

– NET LOC – Not Supported

Page 48


IOB Register Packing

IOB

– XDC support is on the instance or port object, not on nets

– Values supported are TRUE/FALSE/AUTO

• TRUE - will generate an error if FF can’t be packed into IOB

• AUTO - always pack into the slice for Rodin Beta, based on timing in the

future

• FORCE – not supported in Rodin

• FALSE – packed in the slice

Page 49


IO Constraints

IO Constraints

– XDC support is the same using set_property on port objects, no

support for nets

• IOSTANDARD

• FAST/SLOW – converted to SLEW FAST/SLOW in UCF2SDC

• SLEW

• DRIVE

• PULLUP/PULLDOWN

• IOBDELAY

• IN_TERM

• OUT_TERM

• KEEPER

Page 50


Configuration Properties

CONFIG

– IO Bank Properties will be properties on the IO Bank object

• INTERNAL_VREF; DCI_CASCADE; PROHIBIT on a bank

– Prohibit is a property on the package pins

– The rest become properties on the Design Objects

– S3 and older config values will not be supported

ENABLE_SUSPEND;POST_CRC;

DEFAULT

– Not supported

• KEEPER;PULLDOWN;PULLUP;IOSTANDARD

• Not fully supported in ISE

Page 51


Packing Constraints

BEL

– XDC support is the same using set_property

LUTNM/HLUTNM

– XDC support is the same using set_property

LOCK_PINS

– XDC support is on the instance objects

– ALL is not supported, pins have to specifically named

Page 52


RPM Support

Page 53

Planned Support

– RLOC, U_SET, H_SET, HU_SET, RLOC_ORIGIN, RPM_GRID

– HDL, UCF, but not XDC

– Available in RB3

• Currently only works with batch mode commands (opt_design, place_design, etc)

• May fail to build RPM_GRID RPMs

– Set this parameter before open_netlist_design:

set_param placedata.supportRLOCShapes yes

Not planning to support

– RLOC_RANGE dropped in favor of Pblocks

– USE_RLOC dropped: RLOCs can be deleted using Tcl

– No planned support of RLOCs at multiple hierarchical levels within same RPM

• Cumulative RLOCs for “multi-dimensional” RPMs


RPMs in Rodin

Simple Verilog example


RPM alternatives

Net with weight property – device independent

– Causes net sources and destinations to be placed closer together

– The higher the number, the tighter the placement

– Use instead of hetergeneous (mixed-site) RPMs

XDC Group paths with weight property – device independent

– Causes the placer to work harder on these paths

Weighted range-less pblocks (planned for Rodin 2012.1)

– Replaces floating RPMs

– Weight corresponds to degree of area compression

– Use instead of RPMs when exact relative locations are less important

Page 55


Directed Routing (DIRT) Support

Page 56

Pre-routing through Tcl scripts – device specific

– Route critical nets before full routing

– Pre-routed nets remain fixed during routing of remaining nets

– DIRT alternative to reduce dependency on complex DIRT constraints

DIRT support

– Tcl commands to specify routing resources for a logical net

– Identical usage to ISE DIRT strings

Available in advanced Tcl batch flow


Thanks

Page 57

Documents

Introduction to Xilinx Design Constraints (XDC)gongterr.co.kr/down/session7_Intro_XDC_Henry.pdf · Introduction to Xilinx Design Constraints ... get_timing_paths Timing path objects,