ISL81601 FN9299 60V Bidirectional 4-Switch Synchronous ... · 60V Bidirectional 4-Switch Synchronous Buck-Boost Controller DATASHEET The ISL81601 is a true bidirectional 4-switch

FN9299 Rev.3.00 Page 1 of 54Nov 21, 2018

FN9299Rev.3.00

Nov 21, 2018

ISL8160160V Bidirectional 4-Switch Synchronous Buck-Boost Controller

DATASHEET

The ISL81601 is a true bidirectional 4-switch synchronous buck-boost controller with peak and average current sensing and monitoring at both ends. Its wide input and output voltage ranges make it suitable for industrial, telecommunication, and after-market automotive applications.

The ISL81601 uses the proprietary buck-boost control algorithm with valley current modulation for Boost mode and peak current modulation for Buck mode control.

The ISL81601 has four independent control loops for input and output voltages and currents. Inherent peak current sensing at both ends and cycle-by-cycle current limit of this family of products ensures high operational reliability by providing instant current limit in fast transient conditions at either ends and in both directions. It also has two current monitoring pins at both input and output to facilitate Constant Current (CC) limit and other system management functions. CC operation down to low voltages avoids any runaway condition at over load or short-circuit conditions. In addition to multilayer overcurrent protection, it also provides full protection features such as OVP, UVP, OTP, and average and peak current limit on both input and output to ensure high reliability in both unidirectional and bidirectional operation. The IC is packaged in a space conscious 32 Ld 5mm x5mm QFN package or easy to assemble 4.4mmx9.7mm 38 Ld HTSSOP package. Both packages use an EPAD to improve thermal dissipation and noise immunity. Low pin count, fewer external components, and default internal values make the ISL81601 an ideal solution for quick to market simple power supply designs. The unique DE/Burst mode at light-load dramatically lowers standby power consumption with consistent output ripple over different load levels.

Related LiteratureFor a full list of related documents, visit our website:

• ISL81601 device page

Features• Single inductor 4-switch buck-boost controller

• On-the-fly bidirectional operation with independent control of voltage and current on both ends

• Proprietary algorithm for smoothest mode transition

• MOSFET drivers with adaptive shoot-through protection

• Wide input voltage range: 4.5V to 60V

• Wide output voltage range: 0.8V to 60V

• Supports pre-biased output with SR soft-start

• Programmable frequency: 100kHz to 600kHz

• Supports parallel operation current sharing with cascade phase interleaving

• External sync with clock out or frequency dithering

• External bias for higher efficiency supports 8V - 36V input

• Output and input current monitor

• Selectable PWM mode operation between PWM/DE/Burst modes

• Accurate EN/UVLO and PGOOD indicator

• Low shutdown current: 2.7µA

• Complete protection: OCP, SCP, OVP, OTP, and UVP

• Dual-level OCP protection with average current and pulse-by-pulse peak current limit

• Selectable OCP response with either hiccup or constant current mode

• Negative pulse-by-pulse peak current limit

Applications• Battery backup

• UPS/storage systems

• Battery powered industrial applications

• Renewable energy

• Aftermarket automotive

• Redundant power supplies

• Robot and drones

• Medical equipment

• Building and industrial automation

• Security surveillance Figure 1. Buck-Boost Power Train Topology

Q1

Q3

VIN VOUT

Q2

Q4

Rs_in Rs_out

LUG1

LG1

UG2

LG2

PH1 PH2

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FN9299 Rev.3.00 Page 2 of 54Nov 21, 2018

ISL81601

Figure 2. Typical Application Diagram

Figure 3. Efficiency (VOUT = 12V, DE Mode)

ISL81601 QFN

EX

TB

IAS

VDD

SS/TRK

RT/SYNC

FB_OUT

PGND

VIN

OV

EN

/UV

LO

SGND

VCC5V

COMP

ISE

N-

ISE

N+

CS

-

CS

+

PHASE2

LG1/

PWM_MODE

PHASE1

UG1

BOOT1

UG2

BOOT2

LG2/

OC_MODE

VDD

VDD

PLL_COMP

VIN

VOUTFB_IN

CL

KO

UT

/

DIT

HE

R

IMON_IN

IMON_OUT

PG

OO

D

CL

KE

N

BS

TE

N

30

40

50

60

70

80

90

100

0 2 4 6 8 10

Eff

icie

nc

y (

%)

Output Current (A)

Vin = 9V Vin = 12V

Vin = 24V Vin = 36V

Vin = 48V Vin = 60V

FN9299 Rev.3.00 Page 3 of 54Nov 21, 2018

ISL81601

Contents

1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.2 Internal 8V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 Enable (EN/UVLO) and Soft-Start Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 Tracking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.5 Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.6 Buck-Boost Conversion Topology and Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.7 Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.8 Prebiased Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.9 Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.10 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.11 Frequency Synchronization and Dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.12 Parallel Operation Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.13 Gate Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.14 Power-Good Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5. Protection Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.1 Input Undervoltage Lockout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2 VCC5V Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3 Overcurrent Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.5 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6. Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2 General EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FN9299 Rev.3.00 Page 4 of 54Nov 21, 2018

ISL81601

7. Component Selection Guideline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.1 MOSFET Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.3 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.4 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9. Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

FN

929

9R

ev.3

.00

Pag

e 5 of 5

4N

ov 2

1, 2

018

ISL

816

011. O

verview1. Overview

1.1 Typical Application Schematics

Figure 4. ISL81601EVAL1Z (VIN = 9V to 60V, VOUT = 12V, IOUT = 10A) Evaluation Board Schematic

VIN VOUT

VOUT

EN

EN

C7 10u

C14

220pC1810n

Q2NMOS

Q4NMOS

C42200u/16v

Q3NMOS

R8 169k

R9 2.7k

R12

3.48k

D4

C9 820p

R515k

C1220u/100v

D2

100v

D34V7

C131n

C1647n

R1110k

U1

ISL81601

BSTEN1

FB_IN2

VCC5V3

NC4

RT/SYNC5

PLL_COMP6

CLKOUT/DITHER7

SS/TRK8

CO

MP

9

FB_O

UT

10

IMO

N_O

UT

11

OV

12

ISEN

-13

ISEN

+14

PGO

OD

15

UG

216

PHASE217

BOOT218

LG2/OC_MODE19

VDD20

PGND21

LG1/PWM_MODE22

BOOT123

PHASE124

UG

125

EXTB

IAS

26

VIN

27

CS+

28

CS-

29

EN_U

VLO

30

IMO

N_I

N31

CLK

EN32

EPAD

_SG

ND

33

R2110

R437.4K

D1

100v

C12

22n

R17

1

C1710n

R620k

C21

10n

L1

5.6uH

R13

48.7k

D54V7

C8 10n

C20

10n

C10 33n

R720k

R23200k

C11 0.47u

C1910uR19

1R3154k

R22820k

C6 10u

R1044.2k

R155.1k

C2247n

R181 C23

0.1uR20 5.1k

R141k

C21n

R1 4m

C15

220p

R16

1

C50.47u

R2 3m

Q1NMOS

FN

929

9R

ev.3

.00

Pag

e 6 of 5

4N

ov 2

1, 2

018

ISL

816

011. O

verview


VIN VOUT

R2562k

Q2NMOS

C1810n

C14220p

C7 10u

R241Meg

C4470uF/100V

Q4NMOS

R12

3.48k

R9 2.7k

R8 169k

Q3NMOS

C9 820p

D2100v

C1220u/100v

R53.48k

C16

47nC13

1n

D34V7

R2110

R11

10k

R441.2K

C1710n

R17

1

C12

22n

D1100v

R620k

R13

205k

L1

22uH

C21

10n

R720k

C10 33n

C20

10n

C8 10n

R3154k

R191

C190.1u

C11

0.47u

R181

U1

ISL81601

BSTEN8

FB_IN9

VCC5V10

SGND11

RT/SYNC12

PLL_COMP13

CLKOUT/DITHER14

SS/TRK15

COMP16

FB_OUT17

IMON_OUT18

OV19

ISEN-20

ISEN+21

PGOOD23

UG225

PHASE226

BOOT227

LG2/OC_MODE29

VDD30

PGND31

LG1/PWM_MODE32

BOOT134

PHASE135

UG136

EXTBIAS38

VIN1

CS+2

CS-3

EN_UVLO5

IMON_IN6

CLKEN7

EPAD

_SG

ND

39

NC14

NC222

NC324

NC428

NC533

NC637

C22

47n

R15

5.1k

R10 44.2k

C6 10u

C2

1n

R141k

R20 5.1k

C15

470p

R23

0

R1 6m

D44V7

Q1NMOS

R2 6m

C5 0.47u

R16

1

R222.2

FN9299 Rev.3.00 Page 7 of 54Nov 21, 2018

ISL81601 1. Overview

1.2 Block Diagram

Figure 6. Block Diagram

POREnable

Bias Supplies

Reference

Fault LatchOVP

HICCUPOCP

FB_OUT

PGOOD EN/UVLO VIN VDD EXTBIAS

FB_OUT

SS/TRK

CS+

2µA

SS/TRK

SS/TRK

+

_

+

_0.8VREF

Slope-Comp RampGenerator

Clock

RTSYNC

EPAD

ZCD

PWM

VOUTVIN

IMON_OUT

VCC5V

LDOLDO

LDO

VDD

BOOT1

UG1

PHASE1

LG1PWM_MODE

PGND

Adaptive Dead TimeBoot Refresh

Logic

VDD

BOOT2

UG2

PHASE2

LG2OC_MODE

PGND


Logic

GM1

COMP

CS-

A1Slope

Compensation

Buck-Boost LogicPWM Logic

DEM Burst Logic

PWMComparator

+

_

COMP

COMP

ISEN+

ISEN-

A2+

_

VOUT

+_

PWMBuck

PWMBoost

FB_IN

CLKOUTDITHER

+

_

+

_0.8VREF

GM2

1.2V

GM3 GM4

IMON_INPLL_COMP

SGND

OV

OV

BSTEN CLKEN

BSTEN CLKEN

BSTEN CLKEN OV

Pulse-by-PulseNegative Peak Current Limit

PGND

+_

Pulse-by-PulsePeak Current Limit

1.2V

FN9299 Rev.3.00 Page 8 of 54Nov 21, 2018


1.3 Ordering Information

Part Number(Notes 2, 3) Part Marking Temp. Range (°C)

Tape and Reel (Units)(Note 1)

Package(RoHS Compliant) Pkg. Dwg. #

ISL81601FRZ 81601 FRZ -40 to +125 - 32 Ld 5x5 QFN L32.5x5B

ISL81601FRZ-T 81601 FRZ -40 to +125 6k 32 Ld 5x5 QFN L32.5x5B

ISL81601FRZ-T7A 81601 FRZ -40 to +125 250 32 Ld 5x5 QFN L32.5x5B

ISL81601FVEZ 81601 FVEZ -40 to +125 - 38 Ld HTSSOP M38.173C

ISL81601FVEZ-T 81601 FVEZ -40 to +125 2.5k 38 Ld HTSSOP M38.173C

ISL81601FVEZ-T7A 81601 FVEZ -40 to +125 250 38 Ld HTSSOP M38.173C

ISL81601EVAL1Z Evaluation Board for QFN

ISL81601EVAL2Z Evaluation Board for HTSSOP

Notes:1. See TB347 for details about reel specifications.2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the ISL81601 device page. For more information about MSL, see TB363.

Table 1. Key Differences Between Family of Parts

Part Number VIN Op/Max (V) VDD (V)

Current Control Parallelable Dithering Removed Pins Pin 12

ISL81601 60/70 8 Bidirectional Yes Yes None OV

ISL81401 40/45 5.3 Bidirectional Yes Yes BSTEN, CLKEN MODE

ISL81401A 40/45 5.3 Unidirectional No No BSTEN, CLKEN, FIB_IN, CLKOUT

MODE

https://www.renesas.com/www/doc/tech-brief/tb347.pdf

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FN9299 Rev.3.00 Page 9 of 54Nov 21, 2018


1.4 Pin Configurations32 Ld 5x5 QFN

Top View38 Ld HTSSOP

Top View

VIN

VDDRT/SYNC

FB

_O

UT

PG

OO

D

PHASE2

PGND

LG1/

PWM_MODE

PHASE1

UG

1

BOOT1

CS

+

CO

MP

EPAD

SGND

VCC5V

PLL_COMP

ISE

N-

ISE

N+

CS

-

EN

/UV

LO

UG

2

BOOT2

LG2/

OC_MODE

28 27 26 25

24

22

23

15 16

17

18

19

20

21

1

2

3

4

5

6

7

8

9 10 11 12 13 14

FB_IN

IMO

N_

OU

T

CLKOUT/

DITHER

CL

KE

N

BSTEN

29303132

EX

TB

IAS

SS/TRK

IMO

N_

IN

NC

OV

EXTBIAS

VDD

NC

RT/SYNC

FB_OUT

PGOOD

PHASE2

PGND

LG1/PWM_MODE

PHASE1

UG1

BOOT1

VIN

COMP

EPADVCC5V

PLL_COMP

ISEN-

ISEN+

CS1-

CS1+

UG2

BOOT2

LG2/OC_MODE

31

32

33

34

35

1

2

3

4

5

6

7

8

FB_IN

IMON_OUT

CLKOUT/DITHER

EN/UVLO

IMON_IN

OV

SS/TRK

NC

SGND

9

10

11

12

13

14

15

16 23

24

25

26

27

30

28

29

36

37

38

17

18

19 20

21

22

CLKEN

BSTEN

NC

NC

NC

NC

SGND

FN9299 Rev.3.00 Page 10 of 54Nov 21, 2018


1.5 Pin Descriptions

Pin #(QFN)

Pin #(HTSSOP)

PinName Function

1 8 BSTEN DE Burst mode enable signal. The pin is pulled up to 5V by an internal 250k resistor in PWM and DE mode. It is pulled low in Burst mode. The pull-down MOSFET rDS(ON) resistance is about 4.5k. Connect this pin together in the multi-chip parallel operation application to sync all the chips together for Burst mode operation.

2 9 FB_IN Input voltage feedback pin for reverse direction operation. Use a resistor divider to feed the input voltage back to this pin. When the input voltage drops to the pin voltage below 0.8V, the internal control loop reduces the duty cycle to sink in current from output to input to keep the pin voltage regulated at 0.8V.Keep the pin voltage below 0.3V to disable the reverse direction operation.When the reverse operation function is not used, tie this pin to VCC5V or SGND to set up the phase shift for the interleaving parallel operation.

3 10 VCC5V Output of the internal 5V linear regulator. This output supplies bias for the IC. The VCC5V pin must always be decoupled to SGND with a minimum of 4.7µF ceramic capacitor placed very close to the pin.

4 4, 22, 24,28, 33, 37

NC No connection pin.

5 12 RT/SYNC A resistor from this pin to ground adjusts the default switching frequency from 100kHz to 600kHz. The default switching frequency of the PWM controller is determined by the resistor RT as shown in Equation 1.

where fSW is the switching frequency in MHz.When this pin is open or tied to VCC5V, the fSW is set to 120kHz. When this pin is tied to GND, the fSW is set to 575kHz. When an external clock signal is applied to this pin, the internal frequency is synchronized to the external clock frequency.

6 13 PLL_COMP Compensation pin for the internal PLL circuit. A compensation network shown in the Figure 52 on page 37 is required. RPLL(2.7kΩ), CPLL1 (10nF), and CPLL2 (820pF) are recommended.

7 14 CLKOUT/DITHER

Dual function pin. When there is no capacitor connected to this pin, it provides a clock signal to synchronize the other ISL81601(s). The phase shift of the clock signal is set by the FB_IN and IMON_IN pin voltages.When a capacitor is connected to this pin, the clock out function is disabled and the frequency dither function is enabled before the soft-start. The capacitor is charged and discharged by internal current sources. As the voltage on the pin ramps up and down, the oscillator frequency is modulated between –15% and +15% of the nominal frequency set by the RT resistor. The frequency dither function is disabled in the external Sync mode or if the RT pin is open or shorted.

8 15 SS/TRK Dual function pin. When used for soft-starting control, a soft-start capacitor is connected from this pin to ground. A regulated 2μA soft-starting current charges up the soft-start capacitor. the value of the soft-start capacitor sets the output voltage ramp.When used for tracking control, an external supply rail is configured as the master and the output voltage of the master supply is applied to this pin using a resistor divider. The output voltage tracks the master supply voltage.

9 16 COMP Voltage error GM amplifier output. It sets the reference of the inner current loop. The feedback compensation network is connected between the COMP and SGND pins. When the COMP pin is pulled below 1V, the PWM duty cycle reduces to 0%.

10 17 FB_OUT Output voltage feedback input. Connect FB_OUT to a resistive voltage divider between the output and SGND to adjust the output voltage. FB_OUT pin voltage is regulated to the internal 0.8V reference.

RT34.7fSW----------- 4.78– k=(EQ. 1)

FN9299 Rev.3.00 Page 11 of 54Nov 21, 2018


11 18 IMON_OUT Output current monitor. The current from this pin is proportional to the differential voltage between the ISEN+ and ISEN- pins. Connect a resistor and capacitor network between the pin and SGND to make the pin voltage proportional to the average output current. When the pin voltage reaches 1.2V, the internal average current limit loop reduces the output voltage to keep the output current constant when constant current OCP mode is set or the converter shuts down when hiccup OCP mode is set.In DE Burst mode, when this pin voltage is less than 850mV, the controller runs in Burst mode. When this pin voltage is higher than 880mV, the controller exits Burst mode. When a higher resistance on this pin is used to set its voltage higher than 880mV at no load condition, the controller runs in DE mode with no burst operation.

12 19 OV OVP comparator output signal. The pin is pulled low to GND by an internal 250k resistor in normal operation. It is pulled high when output OVP trips. The pull-up MOSFET rDS(ON) resistance is about 4.5k. Connect this pin together in multi-chip parallel operation application to sync all the chips together for the OVP reaction.

13 20 ISEN- Output current sense signal negative input pin.

14 21 ISEN+ Output current sense signal positive input pin.

15 23 PGOOD Open-drain logic output used to indicate the status of output voltage. This pin is pulled low when the output is not within ±10% of the nominal voltage or the EN pin is pulled LOW.

16 25 UG2 High-side MOSFET gate driver output controlled by the boost PWM signal.

17 26 PHASE2 Phase node connection of the boost converter. This pin is connected to the junction of the upper MOSFET’s source, filter inductor, and lower MOSFET’s drain of the boost converter.

18 27 BOOT2 Bootstrap pin to provide bias for the boost high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. Connect a bootstrap diode between this pin and VDD to create the bias for the high-side driver. The BOOT2 to PHASE2 voltage is monitored internally. When the voltage drops to 5.95V at no switching condition, a minimum off-time pulse is issued to turn off UG2 and turn on LG2 to refresh the bootstrap capacitor and maintain the high-side driver bias voltage.

19 29 LG2/OC_MODE

Low-side MOSFET gate driver output controlled by the boost PWM signal and OCP mode set pin. The OCP mode is set by a resistor connected between the pin and ground during the initiation stage before soft-start. During the initiation stage, the pin sources out 10µA current to set the voltage on the pin. If the pin voltage is less than 0.3V, the OCP is set to constant current mode. If the pin voltage is higher than 0.3V, the OCP is set to Hiccup mode.

20 30 VDD Output of the internal 8V linear regulator supplied by either VIN or EXTBIAS. This output supplies bias for the IC low-side drivers and the boot circuitries for the high-side drivers. The VDD pin must always be decoupled to PGND pin with a minimum of 4.7µF ceramic capacitor placed very close to the pin.

21 31 PGND Power ground connection. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the VDD decoupling capacitors.

22 32 LG1/PWM_MODE

Low-side MOSFET gate driver output controlled by the buck PWM signal and PWM mode set pin. The PWM mode is set by a resistor connected between the pin and ground during the initiation stage before soft-start. During the initiation stage, the pin sources out 10µA current to set the voltage on the pin. If the pin voltage is less than 0.3V, the converter is set to forced PWM mode. If the pin voltage is higher than 0.3V, the converter is set to DE mode.

23 34 BOOT1 Bootstrap pin to provide bias for the buck high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. Connect a bootstrap diode between this pin and VDD to create the bias for the high-side driver. The BOOT1 to PHASE1 voltage is monitored internally. When the voltage drops to 5.95V at no switching condition, a minimum off-time pulse is issued to turn off UG1 and turn on LG1 to refresh the bootstrap capacitor and maintain the high-side driver bias voltage.

24 35 PHASE1 Phase node connection of the buck converter. This pin is connected to the junction of the upper MOSFET’s source, filter inductor, and lower MOSFET’s drain of the buck converter.

25 36 UG1 High-side MOSFET gate driver output controlled by the buck PWM signal.

26 38 EXTBIAS External bias input for the optional VDD LDO. There is an internal switch to disconnect the VIN LDO when EXTBIAS voltage is higher than 7.5V. Decouple this pin to ground with a 10µF ceramic capacitor when it is in use, otherwise tie this pin to ground. DO NOT float this pin.

Pin #(QFN)

Pin #(HTSSOP)

PinName Function

FN9299 Rev.3.00 Page 12 of 54Nov 21, 2018


27 1 VIN Tie this pin to the input rail using a 5-10Ω resistor. It provides power to the internal LDO for VDD. Decouple this pin with a small ceramic capacitor (10nF to 1µF) to ground.

28 2 CS+ Input current sense signal positive input pin.

29 3 CS- Input current sense signal negative input pin.

30 5 EN/UVLO

This pin provides enable/disable and accurate UVLO functions. The output is disabled when the pin is pulled to ground. When the voltage on the pin reaches 1.3V, the VDD and VCC5V LDOs become active. When the voltage on the pin reaches 1.8V, the PWM modulator is enabled. When the pin is floating, it is enabled in default by internal pull-up.

31 6 IMON_IN Input current monitor. The current from this pin is proportional to the differential voltage between the CS+ and CS- pins. Connect a resistor and capacitor network between the pin and SGND to make the pin voltage proportional to the average input current. When the pin voltage reaches 1.2V, the internal average current limit loop reduces the output voltage to keep the input current constant when constant current OCP mode is set or the converter shuts down when hiccup OCP mode is set.When the input current monitor function is not used, tie this pin to VCC5V or SGND to set up the phase shift for interleaving parallel operation.

32 7 CLKEN DE mode burst operation off state enable signal. The pin is pulled up to 5V by an internal 250k resistor in PWM and DE modes and burst mode on state. It is pulled low in Burst mode off state. The pull-down MOSFET rDS(ON) resistance is about 4.5k. Connect this pin together in multi-chip parallel operation application to sync all the chips together for the burst operation.

- 11 SGNDEPAD

Small-signal ground common to all control circuitries. Route this pin separately from the high current ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around the chip. All voltage levels are measured with respect to this pin. EPAD at ground potential. EPAD is connected to SGND internally. However, it is highly recommended to solder it directly to the ground plane for better thermal performance and noise immunity.

Pin #(QFN)

Pin #(HTSSOP)

PinName Function

FN9299 Rev.3.00 Page 13 of 54Nov 21, 2018

ISL81601 2. Specifications

2. Specifications

2.1 Absolute Maximum Ratings

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions canadversely impact product reliability and result in failures not covered by warranty.

2.2 Thermal Information

Notes:4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”

features. See TB379.5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Parameter Minimum Maximum Unit

VCC5V, EN/UVLO, FB_IN to GND -0.3 +5.9 V

VDD to GND -0.3 +9 V

EXTBIAS to GND -0.3 +40 V

VIN, CS+, CS-, ISEN+, ISEN- to GND -0.3 +70 V

BOOT1, 2/UG1, 2 to PHASE1, 2 -0.3 VDD + 0.3 V

PHASE1, 2 to GND -5 (<20ns)/-0.3 (DC)

+70 V

FB_OUT, SS/TRK, COMP, RT/SYNC, PLL_COMP, CLKOUT/DITHER, BSTEN, CLKEN, OV, PGOOD, IMON_IN, IMON_OUT to GND

-0.3 VCC5V + 0.3 V

LG1/PWM_MODE, LG2/OC_MODE to GND -0.3 VDD + 0.3 V

CS+ to CS- and ISEN+ to ISEN- -0.3 +0.3 V

VCC5V, VDD Short-Circuit to GND Duration 1 s

ESD Ratings Value Unit

Human Body Model (Tested per JS-001-2017) 2 kV

Machine Model (Tested per JESD22-A115C) 150 V

Charge Device Model (Tested per JS-002-2014) 1.5 kV

Latch-Up (Tested per JESD78E; Class II, Level A, +125°C (TJ)) 100 mA

Thermal Resistance (Typical) JA (°C/W) JC (°C/W)

32 Ld QFN Package (Notes 4, 5) 29 1.2

38 Ld HTSSOP Package (Notes 4, 5) 29 2


Junction Temperature -55 +150 °C

Operating Temperature -40 +125 °C

Storage Temperature Range -65 +150 °C

Pb-Free Reflow Profile see TB493



FN9299 Rev.3.00 Page 14 of 54Nov 21, 2018


2.3 Recommended Operating Conditions

2.4 Electrical Specifications


Temperature -40 +125 °C

VIN to GND 4.5 60 V

VCC5V, EN/UVLO, FB_IN to GND 0 5.25 V

VDD to GND 0 8.3 V

EXTBIAS to GND 0 36 V

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 7 and “Typical Application Schematics” on page 5. VIN = 4.5V to 60V, or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C.

Parameter Symbol Test ConditionsMin

(Note 6) TypMax

(Note 6) Unit

VIN Supply

Input Voltage Range VIN 4.5 60.0 V

VIN Supply Current

Shutdown Current (Note 7) IVINQ EN = 0V, PGOOD is floating 2.7 6.0 µA

Operating Current (Note 8) IVINOP PGOOD is floating 4.7 6.0 mA

VCC5V Supply

Internal LDO Output Voltage VCC5V VIN = 8V, IL = 0mA 4.70 5.10 5.25 V

VIN = 60V, IL = 0mA 4.70 5.10 5.25 V

VIN = 4.5V, IL = 5mA 4.00 4.25 V

VIN > 5.6V, IL = 10mA 4.65 5.00 V

Maximum Supply Current of Internal LDO

IVCC_MAX VVCC5V = 0V, VIN = 8V 120 mA

VDD Supply

Internal LDO Output Voltage VDD VIN = 12V, EXTBIAS = 0V, IL = 0mA 7.5 8.0 8.3 V

VIN = 60V, EXTBIAS = 0V, IL = 0mA 7.5 8.0 8.3 V

VIN = 4.5V, EXTBIAS = 12V, IL = 0mA 7.5 8.0 8.3 V

VIN = 60V, EXTBIAS = 12V, IL = 0mA 7.6 8.0 8.3 V

VIN = 4.5V, EXTBIAS = 0V, IL = 30mA 3.9 4.3 V

VIN = 4.5V, EXTBIAS = 7.8V, IL = 30mA 7.4 7.6 V

VIN > 8.6V, EXTBIAS = 0V, IL = 75mA 7.30 7.85 V

VIN = 4.5V, EXTBIAS > 9.0V, IL = 75mA 7.30 7.85 V


IVDD_MAX VVDD = 0V, EXTBIAS = 0V, VIN = 12V 120 mA

VVDD= 4.5V, EXTBIAS = 12V, VIN = 4.5V 160 mA

EXTBIAS Supply

Switch Over Threshold Voltage, Rising

VEXT_THR EXTBIAS voltage 7.10 7.38 7.55 V

Switch Over Threshold Voltage, Falling

VEXT_THF EXTBIAS voltage 6.60 6.85 7.10 V

FN9299 Rev.3.00 Page 15 of 54Nov 21, 2018


VIN UVLO

VIN Rising UVLO Threshold (Note 10) VUVLOTHR VIN voltage, 0mA on VCC5V and VDD 3.20 3.50 3.85 V

VIN Falling UVLO Threshold VUVLOTHF VIN voltage, 0mA on VCC5V and VDD 3.0 3.2 3.4 V

VCC5V Power-On Reset

VCC5V Rising POR Threshold VPORTHR VCC5V voltage, 0mA on VCC5V and VDD 3.7 4.0 4.3 V

VCC5V Falling POR Threshold VPORTHF VCC5V voltage, 0mA on VCC5V and VDD 3.30 3.55 3.75 V

EN/UVLO Threshold

EN Rise Threshold VENSS_THR VIN > 5.6V 0.75 1.05 1.30 V

EN Fall Threshold VENSS_THF VIN > 5.6V 0.60 0.90 1.10 V

EN Hysteresis VENSS_HYST VIN > 5.6V 70 150 300 mV

UVLO Rise Threshold VUVLO_THR VIN > 5.6V 1.77 1.80 1.83 V

UVLO Hysteresis Current IUVLO_HYST VIN = 12V, EN/UVLO = 1.815V 2.5 4.2 5.5 µA

Soft-Start Current

SS/TRK Soft-Start Charge Current ISS SS/TRK = 0V 2.00 µA

Default Internal Minimum Soft-Starting

Default Internal Output Ramping Time tSS_MIN SS/TRK open 1.7 ms

Power-Good Monitors

PGOOD Upper Threshold VPGOV 107 109 112 %

PGOOD Lower Threshold VPGUV 87 90 92 %

PGOOD Low Level Voltage VPGLOW I_SINK = 2mA 0.35 V

PGOOD Leakage Current IPGLKG PGOOD = 5V 0 150 nA

PGOOD Timing

VOUT Rising Threshold to PGOOD Rising (Note 9)

tPGR 1.1 5 ms

VOUT Falling Threshold to PGOOD Falling

tPGF 80 µs

Reference Section

Internal Voltage Loop Reference Voltage

VREFV 0.800 V

Reference Voltage Accuracy TA = 0°C to +85°C -0.75 +0.75 %

TA = -40°C to +125°C -1.00 +1.00 %

Internal Current Loop Reference Voltage

VREFI 1.200 V


TA = -40°C to +125°C -1.00 +1.00 %

PWM Controller Error Amplifiers

FB_OUT Pin Bias Current IFBOUTLKG -50 0 +50 nA

FB_OUT Error Amp GM Gm1 1.75 mS

FB_OUT Error Amp Voltage Gain AV1 82 dB

FB_OUT Error Amp Gain-BW Product GBW1 8 MHz

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 7 and “Typical Application Schematics” on page 5. VIN = 4.5V to 60V, or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)


(Note 6) TypMax

(Note 6) Unit

FN9299 Rev.3.00 Page 16 of 54Nov 21, 2018


FB_OUT Error Amp Output Current Capability

±310 µA

COMP Max High Voltage VCOMP_HIGH FB_OUT = 0V 3.8 V

COMP Min Low Voltage VCOMP_LOW FB_OUT = 1V 0.01 V

FB_IN Pin Bias Current IFBINLKG -50 0 +50 nA

FB_IN Error Amp GM Gm2 12 µS

FB_IN Error Amp Voltage Gain AV2 72 dB

FB_IN Error Amp Gain-BW Product GBW2 5 MHz

FB_IN Active Range (Note 10) VFB_IN_ACT VCC5V = 5V 0 4.3 V

FB_IN Logic Low Threshold (Note 10) VFB_IN_L 0.2 V

FB_IN Logic High Threshold (Note 10) VFB_IN_H VCC5V = 5V 4.7 V

PWM Regulator

Buck Mode Minimum Off-Time tOFF_MIN1 220 ns

Buck Mode Minimum On-Time tON_MIN1 100 ns

Boost Mode Minimum Off-Time tOFF_MIN2 180 ns

Boost Mode Minimum On-Time tON_MIN2 140 ns

Buck Mode Peak-to-Peak Sawtooth Amplitude

DVRAMP1 VIN = VOUT = 12V, fSW = 300kHz 1.0 V

Boost Mode Peak-to-Peak Sawtooth Amplitude


Buck Mode Ramp Offset VROFFSET1 0.88 0.95 1.11 V

Boost Mode Ramp Offset VROFFSET2 2.84 3.15 3.7 V

Current Sense, Current Monitors, and Average Current Loop

Input Current Sense Differential Voltage Range

VCS+ - VCS- -80 +150 mV

Input Current Sense Common-Mode Voltage Range

CMIRCS 0 60 V

IMON_IN Offset Current ICSOFFSET CS+ = CS- = 12V 15.5 19.5 22.5 µA

Input Current Sense Voltage to IMON_IN Current Source Gain

GmCS 12V common-mode voltage applied to CS+/- pins, 0 to 40mV differential voltage

170 200 220 µS

IMON_IN Error Amp GM Gm3 12 µS

IMON_IN Error Amp Voltage Gain AV3 72 dB

IMON_IN Active Range (Note 10) VIMON_IN_ACT VCC5V = 5V 0 4.3 V

IMON_IN Logic High Threshold (Note 10)

VIMON_IN_H VCC5V = 5V 4.7 V

IMON_IN Error Amp Gain-BW Product

GBW3 5 MHz

Output Current Sense Differential Voltage Range

VISEN+ - VISEN- -80 +150 mV

Output Current Sense Common-Mode Voltage Range

CMIRISEN 0 60 V

IMON_OUT Offset Current IISENOFFSET ISEN+ = ISEN- = 12V 17.5 20 22 µA



(Note 6) TypMax

(Note 6) Unit

FN9299 Rev.3.00 Page 17 of 54Nov 21, 2018


IMON_OUT Current ISEN+ = 12V. ISEN- = 11.96V 25 27.8 29.5 µA

Output Current Sense Voltage to IMON_OUT Current Source Gain

GmISEN 12V common-mode voltage applied to ISEN+/- pins, 0mV to 40mV differential voltage

170 200 220 µS

IMON_OUT Error Amp GM Gm4 12 µS

IMON_OUT Error Amp Voltage Gain AV4 72 dB

IMON_OUT Error Amp Gain-BW Product

GBW4 5 MHz

Switching Frequency and Synchronization

Switching Frequency fSW RT = 144kΩ 220 245 265 kHz

RT = 72kΩ 420 450 485 kHz

RT Open or to VCC5V 90 120 145 kHz

RT = 0V 470 575 650 kHz

RT Voltage VRT RT = 72kΩ 580 mV

SYNC Synchronization Range fSYNC 140 600 kHz

SYNC Input Logic High VSYNCH 3.2 V

SYNC Input Logic Low VSYNCL 0.5 V

Clock Output and Frequency Dither

CLKOUT Output High VCLKH ISOURCE = 1mA, VCC5V = 5V 4.55 V

CLKOUT Output Low VCLKL ISINK = 1mA 0.3 V

CLKOUT Frequency fCLK RT = 72kΩ 420 450 485 kHz

Dither Mode Setting Current Source IDITHER_MODE_SO 10 µA

Dither Mode Setting Threshold Low VDITHER_MODE_L 0.26 V

Dither Mode Setting Threshold High VDITHER_MODE_H 0.34 V

Dither Source Current IDITHERSO 8 µA

Dither Sink Current IDITHERSI 10 µA

Dither High Threshold Voltage VDITHERH 2.2 V

Dither Low Threshold Voltage VDITHERL 1.05 V

Diode Emulation Mode Detection

LG1/PWM_MODE Current Source IMODELG1 7.5 10 12.5 µA

LG1/PWM_MODE Threshold Low VMODETHL 0.26 V

LG1/PWM_MODE Threshold High VMODETHH 0.34 V

Buck Mode Diode Emulation Phase Threshold (Note 11)

VCROSS1 VIN = 12V 2 mV

Boost Mode Diode Emulation Shunt Threshold (Note 12)

VCROSS2 VIN = 12V -2 mV

Diode Emulation Burst Mode

Burst Mode Enter Threshold VIMONOUTBSTEN IMON_OUT pin voltage 0.81 0.85 0.89 V

Burst Mode Exit Threshold VMONOUTBSTEX IMON_OUT pin voltage 0.83 0.88 0.92 V

Burst Mode Peak Current Limit Input Shunt Set Point

VBST-CS VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins

16 27 39 mV



(Note 6) TypMax

(Note 6) Unit

FN9299 Rev.3.00 Page 18 of 54Nov 21, 2018


Burst Mode Peak FB Voltage Limit Set Point

VBST-VFB-UTH 0.82 V

Burst Mode Exit FB Voltage Set Point VBST-VFB-LTH 0.78 V

BSTEN Output Logic High VBSTEN-OH No load, VCC5V = 5V 4.9 V

BSTEN Output Logic Low VBSTEN-OL Pull-up resistance 100kΩ 0.07 V

BSTEN Input Logic High VBSTEN-IH 3.2 V

BSTEN Input Logic Low VBSTEN-IL 1 V

CLKEN Output Logic High VCLKEN-OH No load, VCC5V = 5V 4.9 V

CLKEN Output Logic Low VCLKEN-OL Pull-up resistance 100kΩ 0.07 V

CLKEN Input Logic High VCLKEN-IH 3.2 V

CLKEN Input Logic Low VCLKEN-IL 1 V

PWM Gate Drivers

Driver 1, 2 BOOT Refresh Trip Voltage

VBOOTRF1,2 BOOT voltage - PHASE voltage 5.4 5.95 6.65 V

Driver 1, 2 Source and Upper Sink Current

IGSRC1,2 2000 mA

Driver 1, 2 Lower Sink Current IGSNK1,2 3000 mA

Driver 1, 2 Upper Drive Pull-Up RUG_UP1,2 2.2 Ω

Driver 1, 2 Upper Drive Pull-Down RUG_DN1,2 1.7 Ω

Driver 1, 2 Lower Drive Pull-Up RLG_UP1,2 3 Ω

Driver 1, 2 Lower Drive Pull-Down RLG_DN 2 Ω

Driver 1, 2 Upper Drive Rise Time tGR_UP COUT = 1000pF 10 ns

Driver 1, 2 Upper Drive Fall Time tGF_UP COUT = 1000pF 10 ns

Driver 1, 2 Lower Drive Rise Time tGR_DN COUT = 1000pF 10 ns

Driver 1, 2 Lower Drive Fall Time tGF_DN COUT = 1000pF 10 ns

Overvoltage Protection

Output OVP Threshold VOVTH_OUT 112 114 116 %

OV Pin Output Logic High VOV-OH Load resistance 100k, VCC5V = 5V 4.9 V

OV Pin Output Logic Low VOV-OL No load 0 V

OV Pin Input Logic High VOV-IH 3.2 V

OV Pin Input Logic Low VOV-IL 1 V

Overcurrent Protection

LG2/OC_MODE Current Source IMODELG2 7.5 10 12.5 µA

LG2/OC_MODE Threshold Low VMODETHLOC 0.26 V

LG2/OC_MODE Threshold High VMODETHHOC 0.34 V

Pulse-by-Pulse Peak Current Limit Input Shunt Set Point

VOCSET-CS VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins

68 82 96 mV

Hiccup Peak Current Limit Input Shunt Set Point

VOCSET-CS-HIC VCS+ - VCS- 100 mV

Pulse-by-Pulse Negative Peak Current Limit Output Shunt Set Point

VOCSET-ISEN VISEN+ - VISEN-, 12V common-mode voltage applied to ISEN+/- pins

-72 -59 -48 mV



(Note 6) TypMax

(Note 6) Unit

FN9299 Rev.3.00 Page 19 of 54Nov 21, 2018


Input Constant and Hiccup Current Limit Set Point

VIMONINCC IMON_IN Pin Voltage 1.18 1.2 1.22 V

Input Constant and Hiccup Current Limit Set Point at CS+/- Input

VAVOCP_CS VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +125°C

35 52 74 mV

VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +85°C

35 52 71 mV

Output Constant and Hiccup Current Limit Set Point

VIMONOUTCC IMON_OUT Pin Voltage 1.18 1.2 1.22 V

Output Constant and Hiccup Current Limit Set Point at ISEN+/- Input

VAVOCP_ISEN VISEN+ - VISEN-, 12V common-modeapplied to ISEN+/- pins,RIMON_OUT = 40.2k, TJ = -40°C to +125°C

41 50 64 mV

VISEN+ - VISEN-, 12V common-mode applied to ISEN+/- pins, RIMON_OUT = 40.2k, TJ = -40°C to +85°C

41 50 61 mV

Hiccup OCP Off-Time tHICC_OFF 50 ms

Over-Temperature

Over-Temperature Shutdown TOT-TH 160 °C

Over-Temperature Hysteresis TOT-HYS 15 °C

Notes:6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.7. This is the total shutdown current with VIN = 5.6V and 60V.8. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive

current.9. When soft-start time is less than 4.5ms, tPGR increases. With internal soft-start (the fastest soft-start time), tPGR increases close

to its max limit 5ms.10. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.11. Threshold voltage at the PHASE1 pin for turning off the buck bottom MOSFET during DE mode.12. Threshold voltage between the CS+ and CS- pins for turning off the boost top MOSFET during DE mode.



(Note 6) TypMax

(Note 6) Unit

FN9299 Rev.3.00 Page 20 of 54Nov 21, 2018

ISL81601 3. Typical Performance Curves

3. Typical Performance CurvesOscilloscope plots are taken using the ISL81601EVAL1Z evaluation board, VIN = 9V to 60V, VOUT = 12V, IOUT = 10A unless otherwise noted.

Figure 7. Shutdown Current vs Temperature Figure 8. Quiescent Current vs Temperature

Figure 9. VDD Load Regulation at 12V Input Figure 10. VDD Line Regulation at 20mA Load

Figure 11. VCC5V Load Regulation at 12VIN Figure 12. VCC5V Line Regulation at 20mA Load

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-50 0 50 100 150

Sh

utd

ow

n C

urr

en

t (�

A)

Temperature (oC)

Vin = 4.5 Vin = 5.6

Vin = 12V Vin = 60V3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

-50 0 50 100 150

Qu

iescen

t C

urr

en

t (m

A)

Temperature (oC)

Vin = 4.5 Vin = 5.6

Vin = 12V Vin = 60V

0

1

2

3

4

5

6

7

8

9

0 20 40 60 80 100 120 140 160

VD

D(V

)

IOUT (mA)

Vin = 12V, Vextbias = 0V

Vextbias = 12V, Vin = 4.5V

3

4

5

6

7

8

9

0 10 20 30 40 50 60 70

VD

D(V

)

VIN, VEXTBIAS (V)

VDD vs Vin

VDD vs Vextbias

0

1

2

3

4

5

6

0 20 40 60 80 100 120 140

VC

C5V

(V

)

Load Current (mA)

4.4

4.5

4.6

4.7

4.8

4.9

5.0

4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

VC

C5V

(V

)

VDD (V)

FN9299 Rev.3.00 Page 21 of 54Nov 21, 2018


Figure 13. Switching Frequency vs Temperature Figure 14. Switching Frequency vs VIN, RT = 144k

Figure 15. 0.8V Reference Voltage vs Temperature Figure 16. 1.2V Reference Voltage vs Temperature

Figure 17. Normalized Output Voltage vs Voltage on Soft-Start Pin

Figure 18. Input Current IIN (DC) vs IMON_IN Pin Voltage,RS_IN = 4mΩ, RIM_IN = 36k

Oscilloscope plots are taken using the ISL81601EVAL1Z evaluation board, VIN = 9V to 60V, VOUT = 12V, IOUT = 10A unless otherwise noted. (Continued)

200

250

300

350

400

450

500

-50 0 50 100 150

Sw

itch

ing

Fre

qu

en

cy (

kH

z)

Temperature (oC)

RT = 72kΩ

RT = 144kΩ

231

232

233

234

235

236

237

238

239

240

241

0 10 20 30 40 50 60 70

f SW

(kH

z)

VIN (V)

0.792

0.794

0.796

0.798

0.800

0.802

0.804

0.806

0.808

-50 0 50 100 150

0.8

V R

efe

ren

ce V

olt

ag

e (

V)

Temperature (oC)

1.195

1.196

1.197

1.198

1.199

1.200

1.201

1.202

1.203

1.204

1.205

-50 0 50 100 150

1.2

V R

efe

ren

ce V

olt

ag

e (

V)

Temperature (oC)

0

20

40

60

80

100

120

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

No

rmalized

Ou

tpu

t V

olt

ag

e (

%)

Soft-Start Pin Voltage (V)

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

0 2 4 6 8 10

IMO

N_IN

(V)

IIN (A)

+25C +125C

-40C

FN9299 Rev.3.00 Page 22 of 54Nov 21, 2018


Figure 19. Output Current IOUT (DC) vs IMON_OUT Pin Voltage, RS_OUT = 4mΩ, RIM_OUT = 40.2k

Figure 20. CCM Mode Efficiency

Figure 21. DE Mode Efficiency Figure 22. CCM Load Regulation at +25°C

Figure 23. CCM Line Regulation at 10A Load +25°C Figure 24. Boost Mode Waveforms, VIN = 9V, IOUT = 10A, CCM Mode


0.6

0.7

0.8

0.9

1.0

1.1

1.2

0 2 4 6 8 10

IMO

N_O

UT

(V

)

IOUT (A)

+25C +125C

-40C30

40

50

60

70

80

90

100

0 2 4 6 8 10

Eff

icie

nc

y (

%)

IOUT (A)

Vin=9V Vin=12V Vin=24V

Vin=36V Vin=48V Vin=60V

30

40

50

60

70

80

90

100

0 2 4 6 8 10

Eff

icie

nc

y (

%)

IOUT (A)

Vin = 9V Vin = 12V

Vin = 24V Vin = 36V

Vin = 48V Vin = 60V

11.90

11.92

11.94

11.96

11.98

12.00

12.02

12.04

12.06

12.08

12.10

0 2 4 6 8 10

VO

UT

(V)

IOUT (A)

Vin=9V Vin=12V

Vin=24V Vin=36V

Vin=48V Vin=60V

11.90

11.92

11.94

11.96

11.98

12.00

12.02

12.04

12.06

12.08

12.10

0 10 20 30 40 50 60

VO

UT

(V)

VIN (V) 4µs/Div

PHASE1 10V/Div

PHASE2 20V/Div

VOUT 100mV/Div

IL 10A/Div

BOOT Refresh

FN9299 Rev.3.00 Page 23 of 54Nov 21, 2018


Figure 25. Buck-Boost Mode Waveforms,VIN = 12V, IOUT = 10A, CCM Mode

Figure 26. Buck Mode Waveforms, VIN = 60V, IOUT = 10A,CCM Mode

Figure 27. DE Mode Waveforms, VIN = 60V, IOUT = 0.2A Figure 28. Burst Mode Waveforms, VIN = 9V, IOUT = 0.1A

Figure 29. Burst Mode Waveforms, VIN = 12V, IOUT = 0.1A Figure 30. Burst Mode Waveforms, VIN = 60V, IOUT = 0.1A


4µs/Div

PHASE1 10V/Div

PHASE2 20V/Div

VOUT 50mV/Div

IL 10A/Div

4µs/Div

PHASE1 50V/Div

PHASE2 20V/Div

VOUT 50mV/Div

IL 10A/Div

BOOT Refresh

4µs/Div

PHASE1 50V/Div

VOUT 100mV/Div

IL 2A/Div

PHASE2 10V/Div

2ms/Div

PHASE1 5V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

2ms/Div

PHASE1 10V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

PHASE1 50V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

2ms/Div

FN9299 Rev.3.00 Page 24 of 54Nov 21, 2018


Figure 31. Load Transient, VIN = 9V, IOUT = 0A to 10A, 2.5A/µs, CCM


Figure 33. Load Transient, VIN = 60V IOUT = 0A to 10A, 2.5A/µs, CCM

Figure 34. Line Transient, VIN = 9V-60V, 1V/ms, IOUT = 0A

Figure 35. Line Transient, VIN = 60V-9V, 1V/ms, IOUT = 0A Figure 36. Start-Up Waveform, VIN = 9V IO = 10A CCM


VOUT 200mV/Div

IOUT 5A/Div

2ms/Div

VOUT 200mV/Div

IOUT 5A/Div

2ms/Div

2ms/Div

VOUT 200mV/Div

IOUT 5A/Div

VOUT 200mV/Div

IL 10A/Div

VIN 20V/Div

10ms/Div

VOUT 200mV/Div

IL 10A/Div

VIN 20V/Div

10ms/Div 4ms/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

FN9299 Rev.3.00 Page 25 of 54Nov 21, 2018


Figure 37. Start-Up Waveform, VIN = 12V IO = 10A, CCM Figure 38. Start-Up Waveform, VIN = 60V IO = 10A, CCM

Figure 39. OCP Response, Output Short-Circuited from No Load to Ground and Released, CCM Mode, VIN = 12V

Figure 40. Constant Voltage (CV) andConstant Current (CC) Operation

Figure 41. Bidirectional OperationVIN = 18V, VIN Regulation at 9V, Remove VIN DC Source with 1A Load Applied on Input Terminals


4ms/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

4ms/Div

PHASE1 50V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

40ms/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 10V/Div

IL 20A/Div

0

2

4

6

8

10

12

14

0 2 4 6 8 10 12 14

VO

UT

(V)

IOUT (A)

Vin = 9V

Vin = 12V

Vin = 60V

Hold CCDown to 0.1V

VIN 5V/Div

VOUT 5V/Div

4ms/Div

IL 10A/Div

Remove DCSource on VIN

On-the-Fly Reverse Direction

FN9299 Rev.3.00 Page 26 of 54Nov 21, 2018

ISL81601 4. Functional Description

4. Functional Description

4.1 General DescriptionThe ISL81601 implements a complete buck-boost switching control with a PWM controller, internal drivers, references, protection circuitry, current and voltage control inputs, and monitor outputs. Refer to Figure 6 on page 7.

The ISL81601 is a current-mode controller. It uses a proprietary control algorithm to automatically switch between Buck and Boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads. The controller integrates four control loops to regulate not only VOUT, but also average IOUT and IIN for constant current control and VIN for reverse direction control.

The driver and protection circuits are also integrated to simplify the end design.

The part has an independent enable/disable control line, which provides a flexible power-up sequencing and a simple VIN UVP implementation. The soft-start time is programmable by adjusting the soft-start capacitor connected from SS/TRK.

4.2 Internal 8V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V)

The ISL81601 provides two input pins, VIN and EXTBIAS, and two internal LDOs for VDD gate driver supply. A third LDO generates VCC5V from VDD. VCC5V provides power to all internal functional circuits other than the gate drivers. Bypass the linear regulator’s outputs (VDD) with a 10µF capacitor to the power ground. Also bypass the third linear regulator output (VCC5V) with a 10µF capacitor to the signal ground. VCC5V is monitored by a power-on-reset circuit, which disables all regulators when VCC5V falls below 3.5V.

Both LDOs from VIN and EXTBIAS can source over 75mA for VDD to power the buck and boost gate drivers. When driving large FETs at high switching frequency, little or no regulator current may be available for external loads. The LDO from VDD to VCC5V can also source over 75mA to supply the IC internal circuit. Although the current consumed by the internal circuit is low, the current supplied by VCC5V to the external loads is limited by VDD. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).

Also, at higher input voltages with larger FETs, the power dissipation across the internal 8V LDO increases. Excessive power dissipation across this regulator must be avoided to prevent junction temperature rise. Thermal protection may be triggered if die temperature increases above +160°C due to excessive power dissipation.

When large MOSFETs or high input voltages are used, an external 8V bias voltage can be applied to the EXTBIAS pin to alleviate excessive power dissipation. When the voltage at the EXTBIAS pin is higher than typical 7.38V, the LDO from EXTBIAS activates and the LDO from VIN is disconnected. The recommended maximum voltage at the EXTBIAS pin is 36V. For applications with VOUT significantly lower than VIN, EXTBIAS is usually back biased by VOUT to reduce the LDO power loss. EXTBIAS is allowed to activate only after soft-start is finished to avoid early activation during the VOUT rising stage. An external UVLO circuit might be necessary to ensure smooth soft-starting. Renesas recommends adding a 10µF capacitor on the EXTBIAS pin and using a diode to connect the EXTBIAS pin to VOUT to avoid the EXTBIAS pin voltage being pulled low at the VOUT short-circuit condition.

The two VDD LDOs have an overcurrent limit for short-circuit protection. The VIN to VDD LDO current limit is set to typical 120mA. The EXTBIAS to VDD LDO current limit is set to typical 160mA.

4.3 Enable (EN/UVLO) and Soft-Start OperationPulling the EN/UVLO pin high or low can enable or disable the controller. When the EN/UVLO pin voltage is higher than 1.3V, the three LDOs are enabled. After the VCC5V reaches the POR threshold, the controller is powered up to initialize its internal circuit. When EN/UVLO is higher than the 1.8V accurate UVLO threshold, the ISL81601 soft-start circuitry becomes active. The internal 2µA charge current begins charging up the soft-start

FN9299 Rev.3.00 Page 27 of 54Nov 21, 2018


capacitor connected from the SS/TRK pin to GND. The voltage error amplifier reference voltage is clamped to the voltage on the SS/TRK pin. The output voltage thus rises from 0V to regulation as SS/TRK rises from 0V to 0.8V. Charging of the soft-start capacitor continues until the voltage on the SS/TRK pin reaches 3V.

Typical applications for ISL81601 use programmable analog soft-start or the SS/TRK pin for tracking. The soft-start time can be set by the value of the soft-start capacitor connected from SS/TRK to GND. Inrush current during start-up can be alleviated by adjusting the soft-starting time.

The typical soft-start time is set according to Equation 2:

When the soft-starting time set by external CSS or tracking is less than 1.7ms, an internal soft-start circuit of 1.7ms takes over the soft-start.

PGOOD toggles to high when the output voltage is in regulation.

Pulling the EN/UVLO lower than the EN falling threshold VENSS_THF typical 0.9V, disables the PWM output and internal LDOs to achieve low standby current. The SS/TRK pin is also discharged to GND by an internal MOSFET with 70Ω rDS(ON). For applications with a larger than 1µF capacitor on the SS/TRK pin, Renesas recommends adding a 100Ω to 1kΩ resistor in series with the capacitor to share the power loss at the discharge.

With use of the accurate UVLO threshold, an accurate VIN Undervoltage Protection (UVP) feature can be implemented by feeding the VIN into the EN/UVLO pin using a voltage divider, RUV1 and RUV2, shown in Figure 42.

Figure 42. VIN Undervoltage Protection

The VIN UVP rising threshold can be calculated by Equation 3.

where VUVLO_THR is the EN/UVLO pin UVLO rising threshold, typically 1.8V.

The VIN UVP falling threshold can be calculated by Equation 4.

where IUVLO_HYST is the UVLO hysteresis current, typically 4.2µA.

tSS 0.8VCSS2A----------- =(EQ. 2)

EN/UVLO

VIN

RUV1

RUV2

ISL81601

VUVRISE

VUVLO_THR RUV1 RUV2+ 1.1x10 6–– RUV1RUV2RUV2

--------------------------------------------------------------------------------------------------------------------------------------------=(EQ. 3)

VUVFALL

VUVLO_THR RUV1 RUV2+ IUVLO_HYST – RUV1RUV2RUV2

--------------------------------------------------------------------------------------------------------------------------------------------------------=(EQ. 4)

FN9299 Rev.3.00 Page 28 of 54Nov 21, 2018


4.4 Tracking OperationThe ISL81601 can track an external supply. To implement tracking, connect a resistive divider between the external supply output and ground. Connect the center point of the divider to the SS/TRK pin of the ISL81601. The resistive divider ratio sets the ramping ratio between the two voltage rails. To implement coincident tracking, set the tracking resistive divider ratio exactly the same as the ISL81601 output resistive divider given by Equation 5 on page 29. Make sure that the voltage at SS/TRK is greater than 0.8V when the master rail reaches regulation.

To minimize the impact of the 2µA soft-start current on the tracking function, Renesas recommends using resistors less than 10kΩ for the tracking resistive divider.

When the SS/TRK pin voltage is pulled down to less than 0.3V by the external tracking source, the prebias startup DE mode function is enabled again. The output voltage may not be able to be pull down if the load current is not high enough.

When Overcurrent Protection (OCP) is triggered, the internal minimum soft-start circuit determines the 50ms OCP soft-start hiccup off-time.

4.5 Control LoopsThe ISL81601 is a current-mode controller that can provide an output voltage above, equal to, or below the input voltage. Referring to Figure 2 on page 2 (Typical Application circuit) and Figure 6 on page 7 (Block Diagram), the Renesas proprietary control architecture uses a current sense resistor in series with the buck upper FET to sense the inductor current in Buck or Boost mode. The inductor current is controlled by the voltage on the COMP pin, which is the lowest output of the error amplifiers Gm1 - Gm4. As the simplest example, when the output is regulated to a constant voltage, the FB_OUT pin receives the output feedback signal, which is compared to the internal reference by Gm1. Lower output voltage creates higher COMP voltage which leads to higher PWM duty cycle to push more current to the output. Conversely, higher output voltage creates lower COMP voltage which leads to lower PWM duty cycle to reduce the current to the output.

The ISL81601 has four error amplifiers (Gm1-4) which can control output voltage (Gm1), input voltage (Gm2), input current (Gm3), and output current (Gm4). In a typical application, the output voltage is regulated by Gm1, and the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. In other applications, such as a battery charger, the output current regulator (Gm4) implements constant current charging until a predetermined voltage is reached, at which point the output voltage regulator (Gm1) takes control.

FN9299 Rev.3.00 Page 29 of 54Nov 21, 2018


4.5.1 Output Voltage Regulation LoopThe ISL81601 provides a precision 0.8V internal reference voltage to set the output voltage. Based on this internal reference, the output voltage can be set from 0.8V up to a level determined by the feedback voltage divider, as shown in Figure 43.

A resistive divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT pin. The output voltage value is determined by Equation 5.

where RFBO1 is the top resistor of the feedback divider network and RFBO2 is the bottom resistor connected from FB_OUT to ground, shown in Figure 43.

Figure 43. Output Voltage Regulator

As shown in Figure 43, the RCOMP, CCOMP1, and CCOMP2 network connected on the Gm1 regulator output COMP pin is needed to compensate the loop for stable operation. The loop stability can be affected by many different factors such as VIN, VOUT, load current, switching frequency, inductor value, output capacitance and the compensation network on COMP pin. For most applications 22nF is a good value for CCOMP1. A larger CCOMP1 makes the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. CCOMP2 is typically 1/10th to 1/30th of CCOMP1 to filter high frequency noise. A good starting value for RCOMP is 10k. Lower RCOMP improves stability but slows the loop response. Optimize the final compensation network with a bench test.

4.5.2 Input Voltage Regulation LoopAs shown in Figure 44 on page 30, the input voltage VIN can be sensed by the FB_IN pin using a resistor divider RFBIN1/RFBIN2 and regulated by Gm2. When the FB_IN pin voltage falls below the 0.8V reference voltage, the COMP pin voltage is pulled low to reduce the PWM duty cycle and thus the input current. For applications with a high input source impedance, such as a solar panel, the input voltage regulation loop can prevent the input voltage from being pulled too low in high output load conditions. For applications with a low input source impedance, such as batteries, the VIN feedback loop can prevent the battery from being over-discharged. For applications with loads on the VIN supply, such as a DC back up system, the input voltage regulation loop can reduce the input current to negative area to reverse power conversion direction to discharge the backup battery or super capacitor to supply a regulated VIN for the loads. The regulated input voltage value is determined by Equation 6.

VOUT 0.8VRFBO1 RFBO2+

RFBO2---------------------------------------------

=(EQ. 5)

COMPFB_OUT

+

_

+

_0.8VREF

GM1

VOUT

RFBO1

RFBO2RCOMP

CCOMP1

CCOMP2

VIN 0.8VRFBIN1 RFBIN2+

RFBIN2------------------------------------------------

=(EQ. 6)

FN9299 Rev.3.00 Page 30 of 54Nov 21, 2018


Figure 44. VIN Feedback Loop

FB_IN is a dual-function pin. It also sets the phase angle of the clock output signal on the CLKOUT/DITHER pin, shown in Table 2 on page 38. The VIN feedback loop is disabled when the FB_IN pin voltage is below 0.3V or above 4.7V. The VIN feedback loop is also disabled in DE mode and during soft-start.

4.5.3 Input and Output Average Current Monitoring and Regulation LoopsAs shown in Figure 45 on page 31, the ISL81601 has two current sense operational amplifiers (op amps), A1 and A2, which monitor both input and output current. The voltage signals on the input and output current sense resistor RS_IN and RS_OUT are sent to the differential inputs of CS+/CS- and ISEN+/ISEN-, respectively, after the RC filters RS_IN1/CS_IN1, RS_IN2/CS_IN2, RS_OUT1/CS_OUT1, and RS_OUT2/CS_OUT2. Renesas recommends using a 1Ω value for RS_IN1, RS_IN2, RS_OUT1, and RS_OUT2, and a 10nF value for CS_IN1, CS_IN2, CS_OUT1, and CS_OUT2 to effectively damp the switching noise without delaying the current signal too much and introducing too much error by the op amp bias current. The Gm op amps A1 and A2 then transfer the current sense voltage signals to current signals ICS and IISEN.

where

• IIN is the input current in Q1 drain

• VCSOFFSET is the A1 input offset voltage

• GmCS is the gain of A1, typical 200µS

• VCSOFFSET GmCS = ICSOFFSET.

The typical value of ICSOFFSET is 19.5µA.

where

• IOUT is the output current in Q4 drain

• VISENOFFSET is the A2 input offset voltage

• GmISEN is the gain of A2, typical 200µS

• VISENOFFSET GmISEN = IISENOFFSET.

The typical value of IISENOFFSET is 20µA.

COMPFB_IN

+

_

+

_0.8VREF

GM2

VIN

RFBIN1

RFBIN2

ICS IIN RS_IN VCSOFFSET+ GmCS=(EQ. 7)

IISEN IOUT RS_OUT VISENOFFSET+ GmISEN=(EQ. 8)

FN9299 Rev.3.00 Page 31 of 54Nov 21, 2018


Figure 45. Input and Output Average Current Monitoring and Regulation Loops

By connecting resistor RIM_IN and RIM_OUT on the IMON_IN and IMON_OUT pins, the ICS and IISEN current signals are transferred to voltage signals. The RC networks on the IMON_IN and IMON_OUT pins RIM_IN1/CIM_IN1/CIM_IN2 and RIM_OUT1/CIM_OUT1/CIM_OUT2 are needed to remove the AC content in the ICS and IISEN signals and ensure stable loop operation. The average voltages at the IMON_IN and IMON_OUT pins are regulated to 1.2V by Gm3 and Gm4 for constant input and output current control.

The input constant current loop set point IINCC is calculated by Equation 9. Refer to VAVOCP_CS on page 19 in the Electrical Specifications table to estimate the set point tolerance.

The output constant current loop set point IOUTCC is calculated by Equation 10. Refer to VAVOCP_ISEN on page 19 in the Electrical Specifications table on to estimate the set point tolerance.

Similar to the voltage control loops, the average current loop stability can be affected by many different factors such as VIN, VOUT, switching frequency, inductor value, output and input capacitance, and the RC network on the IMON_IN or IMON_OUT pin. Due to the high AC content in ICS and IISEN, large CIM_IN1 and CIM_OUT1 are needed. Larger CIM_IN1 and CIM_OUT1 can also make the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. For most applications 47nF is a good value for CIM_IN1 and CIM_OUT1. CIM_IN2 and CIM_OUT2 are typically 1/10th to 1/30th of CIM_IN1 and CIM_OUT1 to filter high frequency noise. RIM_IN1 and RIM_OUT1 are needed to boost the phase margin. A good starting value for RIM_IN1 and RIM_OUT1 is 5k. Optimize the final compensation network with iSim simulation and bench testing.

CS+

IMON_OUT

CS-

A1

+_

COMP

ISEN+ ISEN-

+_1.2V

Gm3 Gm4

IMON_IN

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

L

UG1

LG1

UG2

LG2

PH1 PH2

A2

1.2V

RIM_INRIM_OUT

RIM_IN1

CIM_IN1CIM_IN2 CIM_OUT2

CIM_OUT1

RIM_OUT1

RS_IN1 RS_IN2

CS_IN1 CS_IN2 CS_OUT1 CS_OUT2

RS_OUT1RS_OUT2

VCS_OFFSETVISEN_OFFSET

IcsIISEN

IINCC

1.2 ICSOFFSET– xRIM_INRIM_INxR

S_INxGm

CS

----------------------------------------------------------------------=(EQ. 9)

IOUTCC

1.2 IISENOFFSET– xRIM_OUTRIM_OUTxR

S_OUTxGm

ISEN

---------------------------------------------------------------------------------=(EQ. 10)

FN9299 Rev.3.00 Page 32 of 54Nov 21, 2018


4.6 Buck-Boost Conversion Topology and Control AlgorithmThe ISL81601 uses the Renesas proprietary buck-boost control algorithm to achieve optimized power conversion performance. The buck-boost topology is shown in Figure 46. The ISL81601 controls the four power switches Q1, Q2, Q3, and Q4 to work in either Buck or Boost mode. When VIN is far lower than VOUT, the converter works in Boost mode. When VIN is far higher than VOUT, the converter works in Buck mode. When VIN is equal or close to VOUT, the converter alternates between Buck and Boost mode as necessary to provide a regulated output voltage, which is called Buck-Boost mode. Figure 47 shows the relationship between the operation modes and VOUT - VIN.

RS_IN is a current sense resistor to sense the inductor current during Q1 on-time. As shown in the “Block Diagram” on page 7, the sensed signal is fed into the CS+ and CS- pins and used for peak or valley current-mode control, DE mode control, input average current monitor, constant current control, and protections.

RS_OUT is a current sense resistor to sense the inductor current during Q4 on-time. As shown in the Block Diagram, the sensed signal is fed into the ISEN+ and ISEN- pins and used for negative peak inductor current limit, output average current monitor, constant current control, and protections.

4.6.1 Buck Mode Operation (VIN > VOUT)In Buck mode, Q4 is always on and Q3 is always off unless boot refresh or inductor negative peak current limit is tripped. Q1 and Q2 runs in a normal peak current controlled sync buck operation mode. Q1 turns on by the clock. During Q1 on-time, op amp A1 senses the inductor current by the voltage on RS_IN. Q1 turns off when the sensed signal combined with the slope compensation ramp is higher than the COMP pin voltage which is the error signal from the upper voltage or current regulator. The equivalent circuit and operation waveforms are shown in Figure 48 on page 33.

Figure 46. Buck-Boost Topology Figure 47. Operation Modes vs VOUT - VIN

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

L

UG1

LG1

UG2

LG2

PH1 PH2

0

Boost Mode

Buck/Boost Mode

Buck Mode

VO

UT -

VIN

Q1 On, Q2 Off

Q3, Q4 PWM Switching

Q4 On, Q3 Off


4-Switch PWM

Q3 Max Duty

Q3 Min Duty

Q2 Min Duty

Q2 Max Duty

FN9299 Rev.3.00 Page 33 of 54Nov 21, 2018


In Buck mode, the Q1 duty cycle is given by:

DQ1 = VOUT / VIN x 100%

As VIN decreases to close to VOUT, DQ1 increases to close to its maximum value decided by its minimum off-time. When DQ1 reaches its maximum value, the converter moves to Buck-Boost mode.

When VIN is much higher than VOUT, DQ1 decreases to close to its minimum duty cycle decided by its minimum on-time. To allow stable loop operation and avoid duty cycle jitter, Renesas recommends keeping the Q1 on-time always two to three times higher than the minimum on-time.

4.6.2 Boost Mode Operation (VIN < VOUT)In Boost mode, the converter Q1 is always on and Q2 is always off unless boot refresh or inductor negative peak current limit is tripped. Q3 and Q4 run in a normal valley current controlled sync boost operation mode. Q3 turns off by the clock. During Q3 off-time, op amp A1 senses the inductor current by the voltage on RS_IN. Q3 turns on when the sensed signal combined with the slope compensation ramp is lower than the COMP pin voltage which is the error signal from the upper voltage or current regulator. The equivalent circuit and operation waveforms are shown in Figure 49 on page 34.

Figure 48. Buck Mode Equivalent Circuit and Operation Waveforms

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

0V

8V

Q1

VIN VOUT

Q2

RS_IN RS_OUT

LUG1

LG1

PH1 PH2

FN9299 Rev.3.00 Page 34 of 54Nov 21, 2018


Figure 49. Boost Mode Equivalent Circuit and Operation Waveforms

In Boost mode, the Q3 duty cycle is given by:

DQ3 = (1 - VIN / VOUT) x 100%

As VIN increases close to VOUT, DQ3 decreases close to its minimum value decided by its minimum on-time. When DQ3 reaches its minimum value, the converter moves to Buck-Boost mode.

When VIN is much lower than VOUT, DQ3 increases close to its maximum duty cycle decided by its minimum off-time. To allow stable loop operation and avoid duty cycle jitter, Renesas recommends keeping the Q3 off-time always two to three times higher than the minimum off-time.

4.6.3 Buck-Boost Mode Operation (VIN ≈ VOUT)In Buck-Boost mode, the converter runs in one cycle of Buck mode followed by one cycle of Boost mode operation mode. It takes two clock cycles to finish a full buck-boost period.

When VIN is higher than VOUT, Q3 runs in minimum duty in the Boost mode cycle. Q1 duty cycle DQ1 is modulated in the buck cycle to keep VOUT in regulation. As VIN increases, DQ1 decreases. When DQ1 decreases to less than 66.7% of the clock period, the converter moves to Buck mode.

When VIN is lower than VOUT, Q1 runs in maximum duty in the Buck mode cycle. Q3 duty cycle DQ3 is modulated in the Boost mode cycle to keep VOUT in regulation. As VIN decreases, DQ3 increases. When DQ3 increases to more than 33.3% of the clock period, the converter moves to Boost mode.

Q3

VIN VOUT

Q4

RS_IN RS_OUT

LUG2

LG2

PH1 PH2

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

0V

8V

FN9299 Rev.3.00 Page 35 of 54Nov 21, 2018


Figure 50. Buck-Boost Mode Equivalent Circuit and Operation Waveforms

4.7 Light-Load Efficiency EnhancementThe ISL81601 can be set to DE and Burst mode to improve light load efficiency. The dual functional LG1/PWM_MODE pin sets the DE or PWM mode operation in the initiation stage before soft-start. During the initiation stage, a typical 10µA current source IMODELG1 from the LG1/PWM_MODE pin creates a voltage drop on the resistor RLG1 connected between the LG1/PWM_MODE pin and GND. When the voltage is lower than typical 0.3V, PWM mode is set. Otherwise, DE mode is set.

To set for DE mode operation, select RLG1 to meet:

When DE mode is set, the buck sync FET driven by LG1 and the boost sync FET driven by UG2 are all running in DE mode. The inductor current is not allowed to reverse (discontinuous operation) depending on the zero cross detection reference level VCROSS1 for buck sync FET and VCROSS2 for boost sync FET. At light load conditions, the converter goes into diode emulation. When the load current is less than the level set by VIMONOUTBSTEN typical 0.85V on the IMON_OUT pin, the part enters Burst mode. Equation 12 sets the Burst mode operation enter condition.

where (refer to Figure 45 on page 31):

ISENOFFSET is the output current sense op amp internal offset current, typical 20µA

GmISEN is the output current sense op amp Gm, typical 200µS.

The part exits Burst mode when the output current increases to higher than the level set by VIMONOUTBSTEX typical 0.88V on the IMON_OUT pin. Equation 13 sets the Burst mode operation exit condition.

When the part enters Burst mode, the BSTEN pin goes low. To fully avoid any enter/exit chattering, a 4-10MΩ resistor can be added between the BSTEN and IMON_OUT pins to further expand the hysteresis.

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

LUG1

LG1

UG2

LG2

PH1 PH2

RLG1xIMODELG1 0.34V(EQ. 11)

RIM_OUTx ISENOFFSET IOUTxRS_OUTxGmISEN+ VIMONOUTBSTEN(EQ. 12)

RIM_OUTx ISENOFFSET IOUTxRS_OUTxGmISEN+ vIMONOUTBSTEX(EQ. 13)

FN9299 Rev.3.00 Page 36 of 54Nov 21, 2018


In Burst mode, an internal window comparator takes control of the output voltage. The comparator monitors the FB_OUT pin voltage. When the FB_OUT pin voltage is higher than 0.82V, the controller enters Low Power Off mode. Some of the unnecessary internal circuitries are powered off. When the FB_OUT pin voltage drops to 0.8V, the controller wakes up and runs in a fixed level peak current controlled D/(1-D) Buck-Boost mode when VIN - VOUT < 2V and Buck mode when VIN -VOUT > 2V. In the D/(1-D) Buck-Boost mode, Q1 and Q3 conduct in D*T period, where D is the duty cycle and T is the switching period. Q2 and Q4 complimentarily conduct in (1-D)*T period. Q1 and Q3 are turned on by the clock signal and turned off when inductor current rises to the level that the input current sense op amp input voltage reaches VBST-CS, typical 27mV. After Q1 and Q3 are turned off, Q2 and Q4 are turned on to pass the energy stored in the inductor to the output until next cycle begins. The output voltage increases in the wake up period. When the output reaches 0.82V again, the controller enters into Low Power Off mode again. When the load current increases, the Low Power Off mode period decreases. When the off mode period disappears and the load current further increases but still does not meet the Equation 13 exit condition, the output voltage drops. When the FB_OUT pin voltage drops to 0.78V, the controller exits Burst mode and runs in normal DE PWM mode. The voltage error amplifier takes control of the output voltage regulation.

In Low Power Off mode, the CLKEN pin goes low. By connecting the BSTEN and CLKEN pins together in a multiple chip parallel system, the Burst mode enter/exit and burst on/off control are all synchronized.

Because the VOUT is controlled by a window comparator in Burst mode, higher than normal low frequency voltage ripples appears on the VOUT, which can generate audible noise if the inductor and output capacitors are not chosen properly. Also, the efficiency in D/(1-D) Buck-Boost mode is low. To avoid these drawbacks, the Burst mode can be disabled by choosing a bigger RIM_OUT to set the IMON_OUT pin voltage higher than 0.88V at no load condition, shown in Equation 14. The part runs in DE mode only. Pulse Skipping mode can also be implemented to lower the light load power loss with much lower output voltage ripple as the VOUT is always controlled by the regulator Gm1.

4.8 Prebiased Power-UpThe ISL81601 can soft-start with a prebiased output by running in forced DE mode during soft-start. The output voltage is not pulled down during prebiased start-up. The PWM mode is not active until the soft-start ramp reaches 90% of the output voltage times the resistive divider ratio. Forced DE mode is set again when the SS/TRK pin voltage is pulled to less than 0.3V by either internal or external circuit.

The overvoltage protection function is still alive during soft-start of the DE mode operation.

RIM_OUTxISENOFFSET vIMONOUTBSTEX(EQ. 14)

FN9299 Rev.3.00 Page 37 of 54Nov 21, 2018


4.9 Frequency Selection Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency improves efficiency by reducing MOSFET switching loss. To meet the output ripple and load transient requirements, operation at a low switching frequency requires larger inductance and output capacitance. The switching frequency of the ISL81601 is set by a resistor connected from the RT/SYNC pin to GND according to Equation 1 on page 10.

The frequency setting curve shown in Figure 51 assists in selecting the correct value for RT.

Figure 51. RT vs Switching Frequency fSW

4.10 Phase Lock Loop (PLL)The ISL81601 integrates a high performance PLL. The PLL ensures the wide range of accurate clock frequency and phase setting. It also makes the internal clock easily synchronized to an external clock with the frequency either lower or higher than the internal setting.

As shown in Figure 52, an external compensation network of RPLL, CPLL1, and CPLL2 is needed to connect to the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩ for RPLL, 10nF for CPLL1, and 820pF for CPLL2. With the recommended compensation network, the PLL stability is ensured in the full clock frequency range of 100kHz to 600kHz.

Figure 52. PLL Compensation Network

0

500

1,000

1,500

2,000

2,500

3,000

0 50 100 150 200 250

f SW

(kH

z)

RT (k�)

PLL_COMP

CPLL1

RPLL

CPLL2

ISL81601

FN9299 Rev.3.00 Page 38 of 54Nov 21, 2018


4.11 Frequency Synchronization and DitheringThe RT/SYNC pin can synchronize the ISL81601 to an external clock or the CLKOUT/DITHER pin of another ISL81601. When the RT/SYNC pin is connected to the CLKOUT/DITHER pin of another ISL81601, the two controllers operate in cascade synchronization with phase interleaving.

When the RT/SYNC pin is connected to an external clock, the ISL81601 synchronizes to this external clock frequency. The frequency set by the RT resistor can be either lower or higher than, or equal to the external clock frequency.

The CLKOUT/DITHER pin outputs a clock signal with approximately 300ns pulse width. The signal frequency is the same as the frequency set by the resistor from the RT pin to ground or the external sync clock. The signal rising edge phase angle to the rising edge of the internal clock or the external clock to the RT/SYNC pin can be set by the voltage applied to the FB_IN and IMON_IN pins. The phase interleaving can be implemented by the cascade connecting of the upper chip CLKOUT/DITHER pin to the lower chip RT/SYNC pin in a parallel system. Table 2 on page 38 shows the CLKOUT/DITHER phase settings with different FB_IN and IMON_IN pin voltages.

When the FB_IN is connected to 5V, the VIN feedback control loop is disabled. When IMON_IN is connected to 5V, the average input current control loop and input current hiccup OCP are disabled.

In multi-chip cascade parallel operation, the CLKOUT pin of the upstream chip is connected to the RT/SYNC pin of the downstream chip. The BSTEN, FB_IN, SS/TRK, COMP, FB_OUT, IMON_OUT, OV, EN/UVLO, IMON_IN, and CLKEN pins of all the paralleled chips should be tied together.

The CLKOUT/DITHER pin provides a dual function option. When a capacitor CDITHER is connected on CLKOUT/DITHER pin, the internal circuit disables the CLKOUT function and enables the DITHER function. When the CLKOUT/DITHER pin voltage is lower than 1.05V, a typical 8µA current source IDITHERSO charges the capacitor on the pin. When the capacitor voltage is charged to more than 2.2V, a typical 10µA current source IDITHERSI discharges the capacitor on the pin. A sawtooth voltage waveform shown in Figure 53 on page 39 is generated on the CLKOUT/DITHER pin. The internal clock frequency is modulated by the sawtooth voltage on the CLKOUT/DITHER pin. The clock frequency dither range is set to typically ±15% of the frequency set by the resistor on RT/SYNC pin. The dither function is lost when the chip is synchronized to an external clock.

Table 2. CLKOUT Phase Shift vs FB_IN and IMON_IN Voltage

CLKOUT Phase Shift 120° 90° 60° 180°

FB_IN Voltage Active 1 1 Active

IMON_IN Voltage 1 Active 1 Active

Note: “1” means logic high 4.7V to 5V. “Active” means logic low 0V to 4.3V.

FN9299 Rev.3.00 Page 39 of 54Nov 21, 2018


Figure 53. Frequency Dithering Operation

The dither frequency FDITHER can be calculated by Equation 15. Renesas recommends setting CDITHER between 10nF and 1µF. With a too low CDITHER the part may not be able to set to Dither mode. With a higher CDITHER, the discharge power loss at disable or power off is higher, leading to a higher thermal stress to the internal discharge circuit.

4.12 Parallel Operation Current SharingMultiple ISL81601 controlled buck-boost DC/DC converters can be paralleled to each other in cascade as described in “Frequency Synchronization and Dithering” on page 38. The currents in the paralleled converters can be shared by feeding the same connected COMP pin voltage signal to the reference of the current control loops in each IC. However, the current sharing accuracy is not ideal due to the loose tolerance in RAMP and current sense circuit settings. To achieve an acceptable current sharing accuracy, an external active current sharing circuit is recommended, as shown in Figure 54 on page 40.

CLKOUT/DITHER

CDITHER

ISL81601

FDITHER

1

2.2V

1.05V

a. Frequency Dithering Operation

b. CLKOUT/DITHER Pin Voltage Waveform in Dither Operation

FDITHER3.865x10e 6–

CDITHER-----------------------------------------=(EQ. 15)

FN9299 Rev.3.00 Page 40 of 54Nov 21, 2018


Figure 54 shows the connections between the two paralleled converters. Two external operational amplifiers (op amps) are added for active current sharing in each converter. The first op amp, U2B in Converter 1 or U4B in Converter 2, is a buffer to send the local output current signal from the IMON_OUT pin to the current sharing circuit. The buffer output is connected to the iSh bus using R28 in Converter 1 and R61 in Converter 2 to create the reference signal. The voltage on the iSh bus, ViSh, can be calculated using Equation 16.

where VIMON_OUT1 is the Converter 1 IMON_OUT pin voltage and VIMON_OUT2 is the Converter 2 IMON_OUT pin voltage.

The second op amp, U2A in Converter 1 or U4A in Converter 2 is a differential op amp to feed the current error signal to the IC FB_OUT pin. The differential input signal is equal to VIMON_OUT1 - ViSh for U2A and

Figure 54. ISL81601DEMO1Z Current Sharing Circuit

VIN

GND

VOUT

GND

C3910u

R1143.2k

C41820p

C291n

R64

1M

R47196k

R3110k

R30

100k

J3

1234

C24

220u

U4AISL28213

21

84

3

R31M

C4010n

C26

47n

R1 1.5m

C35

10u

C27100p

C37 10u

R19100k

C111n

Q5

R4343.2k

R50499k

C21

100nR29

1M

R541

R201

R5810k

C14820p

R561M

D3S110FA

D5S110FA

R643.2k

C16 0.47u

C47

10n

J41234

D2S110FA

R37 1.5m

C48

10n

C747n

C50

100n

R6210k

C52

47n

R492.2

R59

48.7

k

R46

15k

R60

5.1k

C22

1n

C381n

C360.47u

C23

220u

Q3

R10 43.2k

R558.45k

L215u

R57

10k

C49

1n

C5

100n

Q2

R482.7k

C1

10u

C25

220u

R3943.2k

R462k

R15196k

Q4

R411

R228.45k

D14V7

D6S110FA

C31 10

n

U2BISL28213

6

57

C3447n

C51100p

R401

C6

1n

R26

5.1k

R385.1k

C1210u

R18499k

R1315k

R75.1k

D44V7

R91

C33

1n

L115u

Q6

C4522n

Q7

Q1

C18

220p

R42 43.2k

R122.2

R81

R51100k

R3410

Q8

J1

1234

C3

10n

R65

100kR631M

C1722n

R210

R2710k

C21n

R531

C1310n

C1533n

R351M

U4BISL28213

6

57

R14

15k

R6110k

C46

220p

R231M

C10 10u

R24

10k

U2AISL28213

21

84

3

U3ISL81601

BSTEN1

FB_IN2

VCC5V3

NC4

RT/SYNC5

PLL_COMP6

CLKOUT/DITHER7

SS/TRK8

CO

MP

9

FB

_OU

T10

IMO

N_O

UT

11

OV

12

ISE

N-

13

ISE

N+

14

PG

OO

D15

UG

216

PHASE217

BOOT218

LG2/OC_MODE19

VCC8V20

PGND21

LG1/PWM_MODE22

BOOT123

PHASE124

UG

125

EX

TB

IAS

26

VIN

27

CS

+28

CS

-29

EN

_UV

LO30

IMO

N_I

N31

CLK

EN

32

EP

AD

33

C8

10u

C32

100n

J2

1234

C20

10n

R4515k

C19

10n

R211

R25

48.7

k

C43 0.47u

C90.47u

R172.2

C30 10

n

R2810k

C28

10u

R442.2

U1ISL81601

BSTEN1

FB_IN2

VCC5V3

NC4

RT/SYNC5

PLL_COMP6

CLKOUT/DITHER7

SS/TRK8

CO

MP

9

FB

_OU

T10

IMO

N_O

UT

11

OV

12

ISE

N-

13

ISE

N+

14

PG

OO

D15

UG

216

PHASE217

BOOT218

LG2/OC_MODE19

VCC8V20

PGND21

LG1/PWM_MODE22

BOOT123

PHASE124

UG

125

EX

TB

IAS

26

VIN

27

CS

+28

CS

-29

EN

_UV

LO30

IMO

N_I

N31

CLK

EN

32

EP

AD

33

R5 1.5m

R3662k

C4233n

R162.7k

R321M

R33 1.5m

C4

10n

vcc8-1

vcc8-1

vcc5-1

vcc5-1

comp

vcc8-1

VCC5-1

iSh

iSh

vcc8-2

vcc8-2

vcc5-2

VOUT

VCC5-2

VIN

en

vcc8-2

VIN

VOUT

bsten

vcc5-2

vcc5-1

clken

clken

besten

clk

ss

ss

en

en

clk

ov

ov

vcc5-2

(EQ. 16) ViSh VIMON_OUT1 VIMON_OUT2+ 2=

FN9299 Rev.3.00 Page 41 of 54Nov 21, 2018


VIMON_OUT2 - ViSh for U4A. The differential op amp gain and the value of the resistor between the op amp output and the FB_OUT pin can be defined based on the current sharing accuracy and the allowed max output voltage change caused by the current sharing loop, assuming the current sense circuit tolerance can be ignored.

The maximum allowed current sharing error can be represented by the max allowed differential op amp input. The differential op amp outputs a maximum voltage of 5V at its maximum differential input, assuming a rail-to-rail op amp is used. The differential op amp gain Ksh can be calculated by Equation 17.

where ΔVsh is the maximum allowed differential op amp input voltage, which is proportional to the output current sharing error ΔIsh = |IOUT1 – IOUT2| / 2. IOUT1 and IOUT2 are the output currents of Converter 1 and 2, respectively. ΔVsh = ΔIsh x RIM_OUT x RS_OUT x GmISEN, referring to the descriptions in “Input and Output Average Current Monitoring and Regulation Loops” on page 30.

As shown in Figure 54 on page 40, Ksh = R23/R27 for Converter 1 and Ksh = R56/R58 for Converter 2.

The value Rsh of the resistor between the differential op amp output and the FB_OUT pin can be calculated using Equation 18.

where ΔVOUT is the maximum allowed output voltage change caused by the current sharing loop, which is limited by the VOUT regulation tolerance.

RFBO1 is the resistance of the upper resistor of the VOUT voltage sense divider shown in Figure 43 on page 29. As shown in Figure 54, Rsh = R29 + R30 for Converter 1 and Rsh = R64 + R65 for Converter 2. RFBO1 = R18 for Converter 1 and RFBO1 = R50 for Converter 2.

4.13 Gate DriversThe ISL81601 integrates two almost identical high voltage driver pairs to drive both buck and boost MOSFET pairs. Each driver pair consists of a gate control logic circuit, a low-side driver, a level shifter, and a high-side driver.

The ISL81601 incorporates an adaptive dead time algorithm that optimizes operation with varying MOSFET conditions. This algorithm provides approximately 16ns dead time between the switching of the upper and lower MOSFETs. This dead time is adaptive and allows operation with different MOSFETs without having to externally adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead time circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. When the upper MOSFET gate-to-source voltage drops below a threshold of 1V, the LGATE is allowed to rise. Renesas recommends not using a resistor between the driver outputs and the respective MOSFET gates, because it can interfere with the dead time circuitry.

The low-side gate driver is supplied from VDD and provides a 3A peak sink and 2A peak source current. The high-side gate driver can also deliver peak 3A sink and 2A source current. Gate-drive voltage for the upper N-channel MOSFET is generated by a flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high-side MOSFET driver. As shown in Figure 55 on page 42, the boot capacitor is charged up to VDD by an external Schottky diode during low-side MOSFET on-time (phase node low). To limit the peak current in the Schottky diode, an external resistor can be placed between the BOOT pin and the boot capacitor. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance.

At start-up, the low-side MOSFET turns on first and forces PHASE to ground to charge the BOOT capacitor to 8V if the diode voltage drop is ignored. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn

(EQ. 17) Ksh5

Vsh--------------=

(EQ. 18) Rsh5 RFBO1

VOUT-----------------------------=

FN9299 Rev.3.00 Page 42 of 54Nov 21, 2018


on the upper MOSFET, an action that boosts the 8V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 8V regulator supplied from either VIN or EXTBIAS pin.

The BOOT to PHASE voltage is monitored internally. When the voltage drops to 5.95V at no switching condition, a minimum off-time pulse is issued to turn off the upper MOSFET and turn on the low-side MOSFET to refresh the bootstrap capacitor and maintain the upper driver bias voltage.

To optimize EMI performance or reduce phase node ringing, a small resistor can be placed between the BOOT pin to the positive terminal of the bootstrap capacitor.

Figure 55. Upper Gate Driver Circuit

4.14 Power-Good IndicatorThe power-good pin can monitor the status of the output voltage. PGOOD is true (open drain) 1.1ms after the FB_OUT pin is within ±10% of the reference voltage.

There is no extra delay when the PGOOD pin is pulled LOW.

BOOT

UGATE

PHASE

VDDVIN

ISL81601

CB

RBOOT

ExternalSchottky

FN9299 Rev.3.00 Page 43 of 54Nov 21, 2018

ISL81601 5. Protection Circuits

5. Protection CircuitsThe converter output and input are monitored and protected against overload, overvoltage, and undervoltage conditions.

5.1 Input Undervoltage Lockout The ISL81601 includes input UVLO protection, which keeps the device in a reset condition until a proper operating voltage is applied. UVLO protection shuts down the ISL81601 if the input voltage drops below 3.2V. The controller is disabled when UVLO is asserted. When UVLO is asserted, PGOOD is valid and is deasserted. If the input voltage rises above 3.5V, UVLO is deasserted to allow the start-up operation.

5.2 VCC5V Power-On Reset (POR)The ISL81601 sets its VCC5V POR rising threshold at 4V and falling threshold at 3.5V when supplied by VIN. EXTBIAS can kick in only after VCC5V reaches its POR rising threshold.

5.3 Overcurrent Protection (OCP)

5.3.1 Input and Output Average Overcurrent ProtectionAs described in “Input and Output Average Current Monitoring and Regulation Loops” on page 30, the ISL81601 can regulate both input and output current with close loop control. This provides a constant current type of overcurrent protection for both input and output average current. It can be set to a hiccup type of protection by selecting a different value of the resistor connected between LG2/OC_MODE and GND.

The input and output constant or hiccup average OCP set points IINCC and IOUTCC can be calculated by Equations 9 and 10 in Input and Output Average Current Monitoring and Regulation Loops.

The average OCP mode is set by a resistor connected from the LG2/OC_MODE pin to ground during the initiation stage before soft-start. During the initiation stage, the LG2/OC_MODE pin sources out typical 10µA current IMODELG2 to set the voltage on the pin. If the pin voltage is less than typical 0.3V, the OCP is set to Constant Current-mode. Otherwise, the OCP is set to hiccup mode.

In hiccup OCP mode, after the average current is higher than the set point for 32 consecutive switching cycles the converter turns off for 50ms before a restart-up is issued.

5.3.2 First Level Pulse-by-Pulse Peak Current LimitAs shown in Figure 45 on page 31 in Input and Output Average Current Monitoring and Regulation Loops, the inductor peak current is sensed by the shunt resistor RS_IN and op amp A1. When the voltage drop on RS_IN reaches the set point VOCSET-CS typical 82mV, Q1 is turned off in Buck mode or Q3 is turned off in Boost mode. The first level peak current limit set point IOCPP1 can be calculated by Equation 19.

IOCPP1

VOCSET CS–RS_IN

----------------------------------=(EQ. 19)

FN9299 Rev.3.00 Page 44 of 54Nov 21, 2018

ISL81601 5. Protection Circuits

5.3.3 Second Level Hiccup Peak Current ProtectionTo avoid any false trip in peak current-mode operation, a minimum on or blanking time is set to the PWM signal. The first level pulse-by-pulse current limit circuit cannot further reduce the PWM duty cycle in the minimum on-time. In output dead short condition especially at high VIN, the inductor current runs away with the minimum on PWM duty. The ISL81601 integrates a second level hiccup type of peak current protection. When the voltage drop on RS_IN reaches the set point VOCSET-CS-HIC (typical 100mV), the converter turns off by turning off all four switches Q1, Q2, Q3, and Q4 for 50ms before a re-start up is issued. The second level peak current protection set point IOCPP2 can be calculated by Equation 20.

5.3.4 Pulse-by-Pulse Negative Peak Current LimitIn cases of reverse direction operation and OVP protection, the inductor current goes to negative. The negative current is sensed by the shunt resistor RS_OUT and op amp A2 shown in Figure 45. When the voltage drop on RS_OUT reaches the set point VOCSET-ISEN (typical -59mV), Q2 and Q4 are turned off and Q1 and Q3 are turned on. The negative peak current limit set point IOCPPN can be calculated by Equation 21.

The device can be damaged in negative peak current limit conditions. In these conditions, the energy flows from output to input. If the impedance of the input source or devices is not low enough, the VIN voltage increases. When VIN increases to higher than its maximum limit, the IC can be damaged.

5.4 Overvoltage ProtectionThe overvoltage set point is set at 114% of the nominal output voltage set by the feedback resistors. In the case of an overvoltage event, the IC attempts to bring the output voltage back into regulation by keeping Q1 and Q3 turned off and Q2 and Q4 turned on. If the OV condition continues, the inductor current goes negative to trip the negative peak current limit. The converter reverses direction to transfer energy from the output end to the input end. Input voltage is pushed high if the input source impedance is not low enough. The IC can be damaged if the input voltage goes to higher than its maximum limit. If the overvoltage condition is corrected and the output voltage drops to the nominal voltage, the controller resumes work in normal PWM switching. The OV pin is pulled high when output OVP trips.

5.5 Over-Temperature ProtectionThe ISL81601 incorporates an over-temperature protection circuit that shuts the IC down when a die temperature of +160°C is reached. Normal operation resumes when the die temperature drops below +145°C through the initiation of a full soft-start cycle. During OTP shutdown, the IC consumes only 100µA current. When the controller is disabled, thermal protection is inactive. This helps achieve a very low shutdown current of 5µA.

IOCPP2

VOCSET-CS-HICRS_IN

--------------------------------------------=(EQ. 20)

IOCPPN

VOCSET-ISENRS_OUT

--------------------------------------=(EQ. 21)

FN9299 Rev.3.00 Page 45 of 54Nov 21, 2018

ISL81601 6. Layout Guidelines

6. Layout GuidelinesCareful attention to layout requirements is necessary for successful implementation of an ISL81601 based DC/DC converter. The ISL81601 switches at a very high frequency, so the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in an extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and ringing. Careful component selection and proper Printed Circuit Board (PCB) layout minimize the magnitude of these voltage spikes.

The three sets of critical components in a DC/DC converter using the ISL81601 are the following:

• the controller

• the switching power components

• the small signal components

The switching power components are the most critical from a layout point of view because they switch a large amount of energy, which tends to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.

6.1 Layout Considerations(1) The input capacitors, buck FETs, inductor, boost FETs, and output capacitor should be placed first. Isolate

these power components on dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output high frequency decoupling ceramic capacitors very close to the MOSFETs.

(2) If signal components and the IC are placed in a separate area to the power train, use full ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise, use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND together close to the IC. DO NOT connect them together anywhere else.

(3) Keep the loop formed by the input capacitor, the buck top FET, and the buck bottom FET as small as possible. Also, keep the loop formed by the output capacitor, the boost top FET, and the boost bottom FET as small as possible.

(4) Ensure the current paths from the input capacitor to the buck FETs, the power inductor, the boost FETs, and the output capacitor are as short as possible with maximum allowable trace widths.

(5) Place the PWM controller IC close to the lower FETs. The low-side FETs gate drive connections should be short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.

(6) Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND pin. Connect the PGND pin to the ground plane by a via. Do not directly connect the PGND pin to the SGND EPAD.

(7) Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.

(8) Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output capacitors to load to avoid inductance and resistances.

(9) Use copper filled polygons or wide short traces to connect the junction of the buck or boost upper FET, buck or boost lower FET, and output inductor. Also keep the buck and boost PHASE nodes connection to the IC short. DO NOT oversize the copper islands for the PHASE nodes. Because the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.

(10) Route all high speed switching nodes away from the control circuitry.

(11) Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths including feedback resistors, current monitoring resistors and capacitors, soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors should be connected to this SGND plane.

FN9299 Rev.3.00 Page 46 of 54Nov 21, 2018

ISL81601 6. Layout Guidelines

(12) Use a pair of traces with minimum loop for the input or output current sensing connection.

(13) Ensure the feedback connection to the output capacitor is short and direct.

6.2 General EPAD Design ConsiderationsFigure 56 illustrates how to use vias to remove heat from the IC.

Figure 56. PCB Via Pattern

Fill the thermal pad area with vias. A typical via array fills the thermal pad footprint so that their centers are three times the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow.

Connect all vias to the ground plane. The vias must have a low thermal resistance for efficient heat transfer. Ensure a complete connection of the plated through hole to each plane.

FN9299 Rev.3.00 Page 47 of 54Nov 21, 2018

ISL81601 7. Component Selection Guideline

7. Component Selection Guideline

7.1 MOSFET ConsiderationsThe MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirement. Select these MOSFETs based upon rDS(ON), gate supply requirements, and thermal management considerations.

The buck MOSFETs’ maximum operation voltage is decided by the maximum VIN voltage, and the boost MOSFETs’ maximum operation voltage is decided by the maximum VOUT voltage. Choose the buck or boost MOSFETs based on their maximum operation voltage with sufficient margin for safe operation.

The MOSFETs’ power dissipation is based on: conduction loss and switching loss. In Buck mode, the power loss of the buck upper and lower MOSFETs are calculated by Equations 22 and 23. The conduction losses are the main source of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the lower MOSFET’s body diode.

In Boost mode, there is only conduction loss on the buck upper MOSFET calculated by Equation 24.

In Boost mode, the boost upper and lower MOSFETs’ power loss are calculated by Equations 25 and 26. The conduction losses are the main component of power dissipation for the upper MOSFET. Only the lower MOSFET has significant switching losses, because the upper device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the upper MOSFET’s body diode.

In Buck mode, the conduction loss exists on the boost upper MOSFET calculated by Equation 27.

A large gate-charge increases the switching time, tSW, which increases the switching losses of the buck upper and boost lower MOSFETs. Ensure that all four MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications.

PUPPERBUCK

IOUT2 rDS ON VOUT

VIN-----------------------------------------------------------------------

IOUT VIN tSW fSW

2-----------------------------------------------------------------+=(EQ. 22)

PLOWERBUCK

IOUT2 rDS ON VIN VOUT–

VIN---------------------------------------------------------------------------------------=(EQ. 23)

PUPPERBUCK

IOUT2 VOUT

2

VIN2

---------------------------------------------- rDS ON =(EQ. 24)

PLOWERBOOST

IOUT2 VOUT

2

VIN2

----------------------------------------------VOUT VIN– rDS ON

VOUT-----------------------------------------------------------------

IOUT VOUT2 tSW fSW

2 VIN ---------------------------------------------------------------------------+=(EQ. 25)

PUPPERBOOST

IOUT2 rDS ON VOUT

VIN-----------------------------------------------------------------------=

(EQ. 26)

PUPPERBOOST IOUT2 rDS ON =(EQ. 27)

FN9299 Rev.3.00 Page 48 of 54Nov 21, 2018


7.2 Inductor SelectionThe inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and the output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 28 for Buck mode and Equation 29 for Boost mode.

The ripple current ratio is usually 30% to 70% of the inductor average current at the full output load condition.

7.3 Output Capacitor SelectionIn general, select the output capacitors to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the inductor, so some inductor analysis is required to select the output capacitors.

One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to its new level. The ISL81601 provides either 0% or maximum duty cycle in response to a load transient.

The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). The output capacitance can be minimized if faster loop compensation is used. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor.

The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown in Equation 30 for Buck mode and Equation 31 for Boost mode:

where COUT is the output capacitor(s) required, L is the inductor, ITRAN is the transient load current step, VIN is the input voltage, VOUT is output voltage, and DVOUT is the drop in output voltage allowed during the load transient.

High frequency capacitors initially supply the transient current and slow the load rate of change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the Equivalent Series Resistance (ESR) and voltage rating requirements as well as actual capacitance requirements.

In Buck mode, the output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 32:

where ILBuck is calculated in Equation 28.

ILBuck

VIN VOUT– VOUT

fSW L VIN ----------------------------------------------------------=(EQ. 28)

ILBoost

VOUT VIN– VIN

fSW L VOUT ----------------------------------------------------=(EQ. 29)

COUTBuck

L ITRAN 2

2 VIN VOUT– DVOUT ------------------------------------------------------------------=(EQ. 30)

COUTBoost

L VOUT ITRAN 2

2 VIN2 DVOUT

-------------------------------------------------------=(EQ. 31)

VRIPPLE ILBuck ESR =(EQ. 32)

FN9299 Rev.3.00 Page 49 of 54Nov 21, 2018


In Boost mode, the current to the output capacitor is not continuous. The output voltage ripple is much higher as defined by Equation 33:

where ILBoost is calculated in Equation 29 on page 48.

Place high frequency decoupling capacitors as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements.

Use only specialized low-ESR capacitors intended for switching regulator applications for the bulk capacitors. In most cases, multiple small case electrolytic capacitors perform better than a single large case capacitor.

The stability requirement on the selection of the output capacitor is that the ESR zero (fZ) is between 2kHz and 60kHz. The ESR zero can help increase phase margin of the control loop.

This requirement is shown in Equation 34:

In conclusion, the output capacitors must meet the following criteria:

• They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient.

• The ESR must be sufficiently low to meet the desired output voltage ripple due to the supplied ripple current.

• The ESR zero should be placed in a large range to provide additional phase margin.

7.4 Input Capacitor Selection The important parameters for the input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. In Buck mode the AC RMS input current varies with the load giving in Equation 35:

where DC is duty cycle.

The maximum RMS current supplied by the input capacitance occurs at VIN = 2 X VOUT, DC = 50% as shown in Equation 36:

In Boost mode, the input current is continuous. The RMS current supplied by the input capacitance is much smaller.

Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the MOSFETs to suppress the voltage induced in the parasitic circuit impedances.

Solid tantalum capacitors can be used, but use caution with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up.

VRIPPLE

IOUT VOUT

VIN----------------------------------------

ILBoost2

------------------------+

ESR =(EQ. 33)

COUT1

2 ESR fZ ------------------------------------=(EQ. 34)

IRMS DC DC2

– IOUT=(EQ. 35)

IRMS12--- IOUT=(EQ. 36)

FN9299 Rev.3.00 Page 50 of 54Nov 21, 2018

ISL81601 8. Revision History

8. Revision History

Rev. Date Description

3.00 Nov 21, 2018 Updated RT/SYNC and PLL_COMP pin descriptions.Updated label on Figure 33 on page 24.Changed 150 to 160 and updated the first sentence of the 4th paragraph in “Internal 8V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V)” on page 26.Updated 1.5ms to 1.7ms in the sentence after Equation 2 on page 27.Updated the 5th paragraph in “Frequency Synchronization and Dithering” on page 38.Updated the 3rd paragraph in “Gate Drivers” on page 41.Updated the 3rd paragraph in “Output Capacitor Selection” on page 48.

2.00 Sep 19, 2018 Updated page 1 description and Features bullets.Added Figure 1.Updated Figure 6.Added HTSSOP information throughout document.Updated Table 1. Updated the following specifications in the Recommended Operating Conditions table:-VCC5V, EN/UVLO, FB_IN to GND from 5 to 5.25.-VDD to GND from 8 to 8.3.Updated the following specifications in the Electrical specification table: -Operation Voltage (VIN = 60V, EXTBIAS = 12V, IL = 0mA) maximum specification from 8.2 to 8.3.-EN Rise Threshold minimum specification from 0.80 to 0.75.-EN Fall Threshold minimum specification from 0.65 to 0.60.-PGOOD Leakage Current typical specification from 20 to 0.-COMP Min Low Voltage from 0.3 to 0.01.-FB_IN Error Amp Gain-BW Product typical specification from 2 to 5.-Buck Mode Ramp Offset specifications minimum from 0.91 to 0.88, typical from 1.01 to 0.95, and -maximum from 1.13 to 1.11.-Boost Mode Ramp Offset specifications typical from 2.95 to 3.15 and maximum from 3.03 to 3.7.-IMON_IN Error Amp Gain-BW Product typical specification from 2 to 5.-IMON_OUT Error Amp Gain-BW Product typical specification from 2 to 5.-Switching Frequency (RT = 72kΩ)specifications minimum from 425 to 420 and maximum from 475 to 485.-Changed “SYNC Input High Threshold” to “SYNC Input Logic High” and added a minimum specification of 3.2 and removed the maximum specification.-Changed “SYNC Input Low Threshold” to “SYNC Input Logic Low” and added a maximum specification of 0.5 and removed the minimum specification.-CLKOUT Output High minimum specification from 4.65 to 4.55.-CLKOUT Frequency specifications minimum from 425 to 420 and maximum from 475 to 485.-Buck Mode Diode Emulation Phase Threshold typical specification from 0 to 2.-Boost Mode Diode Emulation Shunt Threshold typical specification from -8 to -2.-BSTEN Input Logic High removed maximum specification and added minimum specification of 3.2.-BSTEN Input Logic Low removed minimum specification and added maximum specification of 1.-CLKEN Input Logic High removed maximum specification and added minimum specification of 3.2.-CLKEN Input Logic Low removed minimum specification and added maximum specification of 1.-OV Pin Input Logic High removed maximum specification and added minimum specification of 3.2.-OV Pin Input Logic Low removed minimum specification and added maximum specification of 1.-Changed Parameter name from “Hiccup and Current Input Constant Limit Set Point” to “Input Constant and Hiccup Current Limit Set Point”.Updated Enable (EN/UVLO) and Soft-Start Operation section on page 27 by removing the last paragraph.Added “Parallel Operation Current Sharing” section on page 39.Added last sentence to “Overvoltage Protection” on page 44.

FN9299 Rev.3.00 Page 51 of 54Nov 21, 2018

ISL81601 8. Revision History

1.00 May 3, 2018 Removed references to M38.173C package (38 Ld HTSSOP) and all parts that support it (ISL81601FVEZ, ISL81601FVEZ-T, ISL81601FVEZ-T7A, and ISL81601EVAL2Z).Updated the following specifications on page 16:-BSTEN Output Logic High: changed Test Conditions from “Load Resistance 100kΩ” to “No load, VCC5V = 5” and Typical value from 4 to 4.9-BSTEN Output Logic Low: changed Typical value from 0.3 to 0.07-CLKEN Output Logic High: changed Test Conditions from “Load Resistance 100kΩ” to “No load, VCC5V = 5” and Typical value from 4 to 4.9-CLKEN Output Logic Low: changed Typical value from 0.3 to 0.07-OV PIN Output Logic High from 4 to 4.9: changed Test Conditions from “Load Resistance 100kΩ” to “No load, VCC5V = 5” and Typical value from 4 to 4.9-OV PIN Output Logic Low: changed Test Conditions from “Pull-up Resistance 100kΩ” to “No load” and Typical value from 0.3 to 0

0.00 Apr 11, 2018 Initial release.


FN9299 Rev.3.00 Page 52 of 54Nov 21, 2018

ISL81601 9. Package Outline Drawings

9. Package Outline DrawingsL32.5x5B32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGERev 3, 5/10

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

6.

either a mold or mark feature.

3.

5.

4.

2.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

5.00 A

5.0

0

B

INDEX AREAPIN 1

6

(4X) 0.15

32X 0.40 ± 0.10 4

A

32X 0.23

M0.10 C B16 9

4X

0.5028X

3.5

6PIN #1 INDEX AREA

3 .30 ± 0 . 15

0 . 90 ± 0.1BASE PLANE

SEE DETAIL "X"

SEATING PLANE

0.10 CC

0.08 C

0 . 2 REFC

0 . 05 MAX.0 . 00 MIN.

5

( 3. 30 )

( 4. 80 TYP )( 28X 0 . 5 )

(32X 0 . 23 )

( 32X 0 . 60)

+ 0.07

- 0.05

17

25

24

8

1

32

For the most recent package outline drawing, see L32.5x5B.

https://www.renesas.com/package-image/pdf/outdrawing/l32.5x5b.pdf

FN9299 Rev.3.00 Page 53 of 54Nov 21, 2018

ISL81601 9. Package Outline Drawings

M38.173C38 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE (HTSSOP)Rev 0, 4/10

NOTES:

EXPOSED PAD VIEW

DETAIL "A"SIDE VIEW


TOP VIEW

9.70±0.10

1.10 MAX

0.50

0.09-0.20

0.05/0.15

38

PIN 1 ID

4

0.90±0.05

SEATINGPLANE

123

SEEDETAIL "A"

0.10

DA-BC0.20

CL

CM0.08 A-B 5

0.05

3

B

A

D

C

4.4±0.10

6.4

D

C

C

0.17-0.27

4

2X N/2 TIPS

0.25

H

0.6±0.10

LINEPARTING

(1.00)

1 2 3

3.20±0.10

4.6±0.10

(0-8°)

(1.30)

(5.80)

(36X 0.50) (38X 0.28)

(3.20)

(4.60)

SCALE: 30/1(VIEW ROTATED 90°C.W.)

END VIEW

1. Die thickness allowable is 0.279±0.0127 (0.0110±0.0005 inches).

2. Dimensioning & tolerances per ASME. Y14.5m-1994.

3. Datum plane H located at mold parting line and coincident with lead where lead exits plastic body at bottom of parting line.

4. At reference datum and does not include mold flash or protrusions, and is measured at the bottom parting line. Mold flash or protrusions shall not exceed 0.15mm on the package ends and 0.25mm between

5. The lead width dimension does not include dambar protrusion.

Allowable dambar protrusion shall be 0.07mm total in excess of

6. This part is compliant with JEDEC specification MO-153 variation BDT-1

the leads.

the lead width dimension at maximum material condition. Dambar

cannot be located on the lower radius or the foot. Minimum space

between protrusions and an adjacent lead should be 0.08mm.

(14°) TYP

For the most recent package outline drawing, see M38.173C.

https://www.renesas.com/package-image/pdf/outdrawing/m38.173c.pdf

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FN9310 Rev.0.00 Page 1 of 47Sep 11, 2018

FN9310Rev.0.00

Sep 11, 2018

ISL81401, ISL81401A40V 4-Switch Synchronous Buck-Boost Controller

DATASHEET

The ISL81401 and ISL81401A are 4-switch synchronous buck-boost controller with peak and average current sensing and monitoring at both ends. The ISL81401 is a bidirectional device that can conduct current in both directions while the ISL81401A is an unidirectional device.

The ISL81401 and ISL81401A use the proprietary buck-boost control algorithm with valley current modulation for Boost mode and peak current modulation for Buck mode control.

The ISL81401 and ISL81401A have four independent control loops for input and output voltages and currents. Inherent peak current sensing at both ends and cycle-by-cycle current limit of this family of products ensures high operational reliability by providing instant current limit in fast transient conditions at either ends and in both directions. It also has two current monitoring pins at both input and output to facilitate Constant Current (CC) limit and other system management functions. CC operation down to low voltages avoids any runaway condition at over load or short-circuit conditions. In addition to multilayer overcurrent protection, it also provides full protection features such as OVP, UVP, OTP, and average and peak current limit on both input and output to ensure high reliability in both unidirectional and bidirectional operation.

The IC is packaged in a space conscious 32 Ld 5mmx5mm QFN package to improve thermal dissipation and noise immunity. The unique DE/Burst mode at light-load dramatically lowers standby power consumption with consistent output ripple over different load levels.

Related LiteratureFor a full list of related documents, visit our website:

• ISL81401 and ISL81401A product pages

Features• Single inductor 4-switch buck-boost controller

• On-the-fly bidirectional operation with independent control of voltage and current on both ends

• Proprietary algorithm for smoothest mode transition

• MOSFET drivers with adaptive shoot-through protection

• Wide input voltage range: 4.5V to 40V

• Wide output voltage range: 0.8V to 40V

• Supports pre-biased output with SR soft-start

• Programmable frequency: 100kHz to 600kHz

• Supports parallel operation current sharing with cascade phase interleaving

• External sync with clock out or frequency dithering

• External bias for higher efficiency supports 5V - 36V input

• Output and input current monitor

• Selectable PWM mode operation between PWM/DE/Burst modes

• Accurate EN/UVLO and PGOOD indicator

• Low shut down current: 2.7µA

• Complete protection: OCP, SCP, OVP, OTP, and UVP

• Dual-level OCP protection with average current and pulse-by-pulse peak current limit

• Selectable OCP response with either hiccup or constant current mode

• Negative pulse-by-pulse peak current limit

Applications• Battery backup

• Type-C power supply and chargers

• Battery powered industrial applications

• Aftermarket automotive

• Redundant power supplies

• Robot and drones

• Medical equipment

• Security surveillance

Figure 1. Buck-Boost Power Train Topology

Q1

Q3

VIN VOUT

Q2

Q4

Rs_in Rs_out

LUG1

LG1

UG2

LG2

PH1 PH2

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FN9310 Rev.0.00 Page 2 of 47Sep 11, 2018

ISL81401, ISL81401A

Figure 2. Typical Application Diagram

Figure 3. Efficiency (VOUT = 12V, CCM)

82

84

86

88

90

92

94

96

98

100

0 1 2 3 4 5 6 7 8 9

Eff

icie

nc

y (

%)

IOUT(A)

VIN = 6V VIN = 9V

VIN = 12V VIN = 24V

VIN = 36V

FN9310 Rev.0.00 Page 3 of 47Sep 11, 2018

ISL81401, ISL81401A

Contents

1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Internal 5.3V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Enable (EN/UVLO) and Soft-Start Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 Tracking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5 Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6 Buck-Boost Conversion Topology and Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.7 Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.8 Prebiased Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.9 Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.10 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.11 Frequency Synchronization and Dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.12 Gate Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.13 Power-Good Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5. Protection Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.1 Input Undervoltage Lockout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2 VCC5V Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3 Overcurrent Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.4 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.5 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6. Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.2 General EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

FN9310 Rev.0.00 Page 4 of 47Sep 11, 2018

ISL81401, ISL81401A

7. Component Selection Guideline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1 MOSFET Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.4 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FN

931

0R

ev.0

.00

Pag

e 5 of 4

7S

ep 11

, 201

8

ISL

814

01, IS

L81

401

A1. O

verview1. Overview

1.1 Typical Application Schematics


FN

931

0R

ev.0

.00

Pag

e 6 of 4

7S

ep 11

, 201

8

ISL

814

01, IS

L81

401

A1. O

verview1.2 Block Diagram

Figure 5. Block Diagram

OVP

HICCUPOCPFB_OUT

PGOOD EN/UVLO VIN VDD EXTBIAS

FB_OUT

SS/TRK

CS+

2µA

SS/TRK

SS/TRK

+

_

+_

0.8VREF

Slope-Comp Ramp Generator Clock

RTSYNC

EPAD

ZCD

PWM

VOUTVIN

IMON_OUT

VCC5V

LDOLDO

LDO

VDD

BOOT1

UG1

PHASE1

LG1

PGND


Logic

VDD

BOOT2

UG2

PHASE2

LG2OC_MODE

PGND


Logic

GM1

COMP

CS-A1

SlopeCompensation

Buck-Boost LogicPWM Logic

DEM Burst Logic

PWMComparator

+_

COMP

COMP

ISEN+

ISEN-A2

+_

VOUT

Pulse-by-Pulse Peak Current Limit

+_

PWMBuck

PWMBoost

FB_IN

CLKOUTDITHER

+

_

+_

0.8VREF

GM2

1.2V

GM3 GM4

IMON_INPLL_COMP

SGND

MODE

MODE

Pulse-by-Pulse Negative Peak Current Limit

PGND

+_

Enable PORBias Supplies

ReferenceFault Latch

FN9310 Rev.0.00 Page 7 of 47Sep 11, 2018

ISL81401, ISL81401A 1. Overview

1.3 Ordering Information

Part Number(Notes 2, 3) Part Marking Temp. Range (°C)

Tape and Reel(Units) (Note 1)

Package(RoHS Compliant) Pkg. Dwg. #

ISL81401FRZ 81401 FRZ -40 to +125 - 32 Ld 5x5 QFN L32.5x5B

ISL81401FRZ-T 81401 FRZ -40 to +125 6k 32 Ld 5x5 QFN L32.5x5B

ISL81401FRZ-T7A 81401 FRZ -40 to +125 250 32 Ld 5x5 QFN L32.5x5B

ISL81401AFRZ 81401A FRZ -40 to +125 - 32 Ld 5x5 QFN L32.5x5B

ISL81401AFRZ-T 81401A FRZ -40 to +125 6k 32 Ld 5x5 QFN L32.5x5B

ISL81401AFRZ-T7A 81401A FRZ -40 to +125 250 32 Ld 5x5 QFN L32.5x5B

ISL81401EVAL1Z ISL81401 Evaluation Board

ISL81401AEVAL1Z ISL81401A Evaluation Board

Notes:1. Refer to TB347 for details about reel specifications.2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), refer to the ISL81401 and ISL81401A product information pages. For more information about MSL, see TB363.

Table 1. Summary of Key Differences

Device

VIN Op/Maximum

(V) VDD (V)Current

Direction Parallelable Dithering Removed Pins Pin 12

ISL81401 40/45 5.3 Bidirectional Yes Yes BSTEN, CLKEN MODE

ISL81401A 40/45 5.3 Unidirectional No No BSTEN, CLKEN, FIB_IN, CLKOUT

MODE

ISL81601 60/70 8 Bidirectional Yes Yes None OV



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FN9310 Rev.0.00 Page 8 of 47Sep 11, 2018


1.4 Pin ConfigurationsISL81401

32 Ld 5x5 QFNTop View

EX

TB

IAS

VDDRT/SYNC

FB

_O

UT

PG

OO

D

PHASE2

PGND

LG1

PHASE1

UG

1

BOOT1

VIN

CO

MP

EPAD

VCC5V

PLL_COMP

ISE

N-

ISE

N+

CS

+

CS

-

UG

2

BOOT2

LG2/OC_MODE

24

22

23

15 16

17

18

19

20

21

1

2

3

4

5

6

7

8

9 10 11 12 13 14

FB_IN

IMO

N_O

UT

CLKOUT/DITHER

EN

/UV

LO

IMO

N_IN

29303132

SS/TRK

NC

SGND

MO

DE

NC

NC

FN9310 Rev.0.00 Page 9 of 47Sep 11, 2018


1.5 Pin Descriptions

ISL81401A32 Ld 5x5 QFN

Top View

Pin Number

Pin Name(ISL81401)

Pin Name(ISL81401A) Function

1 NC NC No connection pin.

2 FB_IN NC Input voltage feedback pin for reverse direction operation. Use a resistor divider to feed the input voltage back to this pin. When the input voltage drops to the pin voltage below 0.8V, the internal control loop reduces the duty cycle to sink in current from output to input to keep the pin voltage regulated at 0.8V.Keep the pin voltage below 0.3V to disable the reverse direction operation.When the reverse operation function is not used, tie this pin to VCC5V or SGND to set up the phase shift for the interleaving parallel operation.

3 VCC5V VCC5V Output of the internal 5V linear regulator. This output supplies bias for the IC. The VCC5V pin must always be decoupled to SGND with a minimum of 4.7µF ceramic capacitor placed very close to the pin.


EX

TB

IAS

VDDRT/SYNC

FB

_O

UT

PG

OO

D

PHASE2

PGND

LG1

PHASE1

UG

1

BOOT1

VIN

CO

MP

EPAD

VCC5V

PLL_COMPIS

EN

-

ISE

N+

CS

+

CS

-

UG

2

BOOT2

LG2/OC_MODE

24

22

23

15 16

17

18

19

20

21

1

2

3

4

5

6

7

8

9 10 11 12 13 14

NC

IMO

N_O

UT

NC

EN

/UV

LO

IMO

N_IN

32

SS/TRK

NC

SGNDM

OD

E

NC

NC

FN9310 Rev.0.00 Page 10 of 47Sep 11, 2018


5 RT/SYNC RT/SYNC A resistor from this pin to ground adjusts the default switching frequency from 100kHz to 600kHz. The default switching frequency of the PWM controller is determined by the resistor RT as shown in Equation 1.

where fSW is the switching frequency in MHz.When this pin is open or tied to VCC5V, the fSW is set to 100kHz. When this pin is tied to GND, the fSW is set to 550kHz. When an external clock signal is applied to this pin, the internal frequency is synchronized to the external clock frequency.

6 PLL_COMP PLL_COMP Compensation pin for the internal PLL circuit. A compensation network shown in the “Typical Application Diagram” on page 2 is required. RPLL(2.7kΩ), CPLL1 (10nF), and CPLL2 (820pF) are recommended.

7 CLKOUT/DITHER

NC Dual function pin. When a capacitor is not connected to this pin, it provides a clock signal to synchronize the other ISL81401. The phase shift of the clock signal is set by the FB_IN and IMON_IN pin voltages.When a capacitor is connected to this pin, the clock out function is disabled and the frequency dither function is enabled before the soft-start. The capacitor is charged and discharged by internal current sources. As the voltage on the pin ramps up and down, the oscillator frequency is modulated between –15% and +15% of the nominal frequency set by the RT resistor. The frequency dither function is disabled in the external Sync mode or if the RT pin is open or shorted.

8 SS/TRK SS/TRK Dual function pin. When used for soft-starting control, a soft-start capacitor is connected from this pin to ground. A regulated 2µA soft-starting current charges up the soft-start capacitor and ramps up the pin voltage. The pin voltage sets the reference of the output voltage control loop during soft-start. The value of the soft-start capacitor sets the output voltage ramp up slope.When used for tracking control, an external supply rail is configured as the master and the output voltage of the master supply is applied to this pin using a resistor divider. The output voltage tracks the master supply voltage.

9 COMP COMP Voltage error GM amplifier output. It sets the reference of the inner current loop. The feedback compensation network is connected between the COMP and SGND pins. When the COMP pin is pulled below 1V, the PWM duty cycle reduces to 0%.

10 FB_OUT FB_OUT Output voltage feedback input. Connect FB_OUT to a resistive voltage divider between the output and SGND to adjust the output voltage. The FB_OUT pin voltage is regulated to the internal 0.8V reference.

11 IMON_OUT IMON_OUT Output current monitor. The current from this pin is proportional to the differential voltage between the ISEN+ and ISEN- pins. Connect a resistor and capacitor network between the pin and SGND to make the pin voltage proportional to the average output current. When the pin voltage reaches 1.2V, the internal average current limit loop reduces the output voltage to keep the output current constant when constant current OCP mode is set or the converter shuts down when hiccup OCP mode is set.In DEM Burst mode, when this pin voltage is less than 840mV, the controller runs in Burst mode. When this pin voltage is higher than 880mV, the controller exits Burst mode. When a higher resistance on this pin is used to set its voltage higher than 880mV at no load condition, the controller runs in DEM mode with no burst operation.

12 MODE MODE Input pin. Forces CCM when low or floating and allows DEM when high.

13 ISEN- ISEN- Output current sense signal negative input pin.

14 ISEN+ ISEN+ Output current sense signal positive input pin.

15 PGOOD PGOOD Open-drain logic output used to indicate the status of output voltage. This pin is pulled low when the output is not within ±10% of the nominal voltage or the EN pin is pulled low.

16 UG2 UG2 High-side MOSFET gate driver output controlled by the boost PWM signal.

17 PHASE2 PHASE2 Phase node connection of the boost converter. This pin is connected to the junction of the upper MOSFET’s source, filter inductor, and lower MOSFET’s drain of the boost converter.

Pin Number

Pin Name(ISL81401)


RT34.7fSW----------- 4.78– k=(EQ. 1)

FN9310 Rev.0.00 Page 11 of 47Sep 11, 2018


18 BOOT2 BOOT2 Bootstrap pin to provide bias for the boost high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. Connect a bootstrap diode between this pin and VDD to create the bias for the high-side driver. The BOOT2 to PHASE2 voltage is monitored internally. When the voltage drops to 3.9V at no switching condition, a minimum off-time pulse is issued to turn off UG2 and turn on LG2 to refresh the bootstrap capacitor and maintain the high-side driver bias voltage.

19 LG2/OC_MODE

LG2/OC_MODE

Low-side MOSFET gate driver output controlled by the boost PWM signal and OCP mode set pin. The OCP mode is set by a resistor connected between the pin and ground during the initiation stage before soft-start. During the initiation stage, the pin sources out 10µA current to set the voltage on the pin. If the pin voltage is less than 0.3V, the OCP is set to constant current mode. If the pin voltage is higher than 0.3V, the OCP is set to Hiccup mode.

20 VDD VDD Output of the internal 5.3V linear regulator supplied by either VIN or EXTBIAS. This output supplies bias for the IC low-side drivers and the boot circuitries for the high-side drivers. The VDD pin must always be decoupled to the PGND pin with a minimum 4.7µF ceramic capacitor placed very close to the pin.

21 PGND PGND Power ground connection. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the VDD decoupling capacitors.

22 LG1 LG1 Low-side MOSFET gate driver output controlled by the PWM Buck signal.

23 BOOT1 BOOT1 Bootstrap pin to provide bias for the buck high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. Connect a bootstrap diode between this pin and VDD to create the bias for the high-side driver. The BOOT1 to PHASE1 voltage is monitored internally. When the voltage drops to 3.9V at no switching condition, a minimum off-time pulse is issued to turn off UG1 and turn on LG1 to refresh the bootstrap capacitor and maintain the high-side driver bias voltage.

24 PHASE1 PHASE1 Phase node connection of the buck converter. This pin is connected to the junction of the upper MOSFET’s source, filter inductor, and lower MOSFET’s drain of the buck converter.

25 UG1 UG1 High-side MOSFET gate driver output controlled by the buck PWM signal.

26 EXTBIAS EXTBIAS External bias input for the optional VDD LDO. There is an internal switch to disconnect the VIN LDO when EXTBIAS voltage is higher than typical 4.8V. Decouple this pin to ground with a 10µF ceramic capacitor when it is in use, otherwise tie this pin to ground. DO NOT float this pin.

27 VIN VIN Tie this pin to the input rail using a 5Ω to 10Ω resistor. It provides power to the internal LDO for VDD. Decouple this pin with a small ceramic capacitor (10nF to 1µF) to ground.

28 CS+ CS+ Input current sense signal positive input pin.

29 CS- CS- Input current sense signal negative input pin.

30 EN/UVLO

EN/UVLO

This pin provides enable/disable and accurate UVLO functions. The output is disabled when the pin is pulled to ground. When the voltage on the pin reaches 1.3V, the VDD and VCC5V LDOs become active. When the voltage on the pin reaches 1.8V, the PWM modulator is enabled. When the pin is floating, it is enabled in default by internal pull-up.

31 IMON_IN IMON_IN Input current monitor. The current from this pin is proportional to the differential voltage between the CS+ and CS- pins. Connect a resistor and capacitor network between the pin and SGND to make the pin voltage proportional to the average input current. When the pin voltage reaches 1.2V, the internal average current limit loop reduces the output voltage to keep the input current constant when constant current OCP mode is set or the converter shuts down when hiccup OCP mode is set.When the input current monitor function is not used, tie this pin to VCC5V or SGND to set up the phase shift for interleaving parallel operation.


- SGNDEPAD

SGNDEPAD

Small-signal ground common to all control circuitry. Route this pin separately from the high current ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around the chip. All voltage levels are measured with respect to this pin. EPAD at ground potential. EPAD is connected to SGND internally. However, it is highly recommended to solder it directly to the ground plane for better thermal performance and noise immunity.

Pin Number

Pin Name(ISL81401)


FN9310 Rev.0.00 Page 12 of 47Sep 11, 2018

ISL81401, ISL81401A 2. Specifications

2. Specifications

2.1 Absolute Maximum Ratings

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions canadversely impact product reliability and result in failures not covered by warranty.

2.2 Thermal Information

Notes:4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”

features. See TB379.5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.


VCC5V, EN/UVLO, FB_IN to GND -0.3 +5.9 V

VDD to GND -0.3 +9 V

EXTBIAS to GND -0.3 +40 V

VIN, CS+, CS-, ISEN+, ISEN- to GND -0.3 +45 V

BOOT1, 2/UG1, 2 to PHASE1, 2 -0.3 VDD + 0.3 V

PHASE1, 2 to GND -5 (<20ns)/-0.3 (DC)

+45 V

MODE, FB_OUT, SS/TRK, COMP, RT/SYNC, PLL_COMP, CLKOUT/DITHER, PGOOD, IMON_IN, IMON_OUT to GND

-0.3 VCC5V + 0.3 V

LG1, LG2/OC_MODE to GND -0.3 VDD + 0.3 V

CS+ to CS- and ISEN+ to ISEN- -0.3 +0.3 V

VCC5V, VDD Short-Circuit to GND Duration 1 s

ESD Ratings Value Unit

Human Body Model (Tested per JS-001-2017) 2 kV

Machine Model (Tested per JESD22-A115C) 150 V

Charge Device Model (Tested per JS-002-2014) 1.5 kV

Latch-Up (Tested per JESD78E; Class II, Level A, +125°C (TJ)) 100 mA

Thermal Resistance (Typical) JA (°C/W) JC (°C/W)

32 Ld QFN Package (Notes 4, 5) 29 1.2


Junction Temperature -55 +150 °C

Operating Temperature -40 +125 °C

Storage Temperature Range -65 +150 °C

Pb-Free Reflow Profile see TB493



FN9310 Rev.0.00 Page 13 of 47Sep 11, 2018


2.3 Recommended Operating Conditions

2.4 Electrical Specifications


Temperature -40 +125 °C

VIN to GND 4.5 40 V

VCC5V, EN/UVLO, FB_IN to GND 0 5.25 V

VDD to GND 0 5.6 V

EXTBIAS to GND 0 36 V

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C.


(Note 6) TypMax

(Note 6) Unit

VIN Supply

Input Voltage Range VIN 4.5 40.0 V

VIN Supply Current

Shutdown Current (Note 7) IVINQ EN = 0V, PGOOD is floating 2.7 6.0 µA

Operating Current (Note 8) IVINOP PGOOD is floating 4.7 6.0 mA

VCC5V Supply

Internal LDO Output Voltage VCC5V VIN = 8V, IL = 0mA 4.70 5.10 5.25 V

VIN = 40V, IL = 0mA 4.70 5.10 5.25 V

VIN = 4.5V, IL = 5mA 4.00 4.25 V

VIN > 5.6V, IL = 10mA 4.65 5.00 V


IVCC_MAX VVCC5V = 0V, VIN = 8V 120 mA

VDD Supply

Internal LDO Output Voltage VDD VIN = 12V, EXTBIAS = 0V, IL = 0mA 5 5.3 5.6 V

VIN = 40V, EXTBIAS = 0V, IL = 0mA 5 5.3 5.6 V

VIN = 4.5V, EXTBIAS = 12V, IL = 0mA 5 5.3 5.6 V

VIN = 40V, EXTBIAS = 12V, IL = 0mA 5 5.3 5.6 V

VIN = 4.5V, EXTBIAS = 0V, IL = 30mA 3.9 4.3 V

VIN = 4.5V, EXTBIAS = 7.8V, IL = 30mA 4.8 5.2 V

VIN > 8.6V, EXTBIAS = 0V, IL = 75mA 4.8 5.2 V

VIN = 4.5V, EXTBIAS > 9.0V, IL = 75mA 4.8 5.2 V


IVDD_MAX VVDD = 0V, EXTBIAS = 0V, VIN = 12V 120 mA

VVDD = 4.5V, EXTBIAS = 12V, VIN = 4.5V 160 mA

EXTBIAS Supply

Switch Over Threshold Voltage, Rising

VEXT_THR EXTBIAS voltage 4.5 4.8 5 V

Switch Over Threshold Voltage, Falling

VEXT_THF EXTBIAS voltage 4.25 4.45 4.7 V

FN9310 Rev.0.00 Page 14 of 47Sep 11, 2018


VIN UVLO

VIN Rising UVLO Threshold (Note 10) VUVLOTHR VIN voltage, 0mA on VCC5V and VDD 3.20 3.50 3.85 V

VIN Falling UVLO Threshold VUVLOTHF VIN voltage, 0mA on VCC5V and VDD 3.0 3.2 3.4 V

VCC5V Power-On Reset

VCC5V Rising POR Threshold VPORTHR VCC5V voltage, 0mA on VCC5V and VDD 3.7 4.0 4.3 V

VCC5V Falling POR Threshold VPORTHF VCC5V voltage, 0mA on VCC5V and VDD 3.30 3.55 3.75 V

EN/UVLO Threshold

EN Rise Threshold VENSS_THR VIN > 5.6V 0.75 1.05 1.30 V

EN Fall Threshold VENSS_THF VIN > 5.6V 0.60 0.90 1.10 V

EN Hysteresis VENSS_HYST VIN > 5.6V 70 150 300 mV

UVLO Rise Threshold VUVLO_THR VIN > 5.6V 1.77 1.80 1.83 V

UVLO Hysteresis Current IUVLO_HYST VIN = 12V, EN/UVLO = 1.815V 2.5 4.2 5.5 µA

Soft-Start Current

SS/TRK Soft-Start Charge Current ISS SS/TRK = 0V 2.00 µA

Default Internal Minimum Soft-Starting

Default Internal Output Ramping Time tSS_MIN SS/TRK open 1.7 ms

Power-Good Monitors

PGOOD Upper Threshold VPGOV 107 109 112 %

PGOOD Lower Threshold VPGUV 87 90 92 %

PGOOD Low Level Voltage VPGLOW I_SINK = 2mA 0.35 V

PGOOD Leakage Current IPGLKG PGOOD = 5V 0 150 nA

PGOOD Timing

VOUT Rising Threshold to PGOOD Rising (Note 9)

tPGR 1.1 5 ms

VOUT Falling Threshold to PGOOD Falling

tPGF 80 µs

Reference Section

Internal Voltage Loop Reference Voltage

VREFV 0.800 V


TA = -40°C to +125°C -1.00 +1.00 %

Internal Current Loop Reference Voltage

VREFI 1.200 V


TA = -40°C to +125°C -1.00 +1.00 %

PWM Controller Error Amplifiers

FB_OUT Pin Bias Current IFBOUTLKG -50 0 +50 nA

FB_OUT Error Amp GM Gm1 1.75 mS

FB_OUT Error Amp Voltage Gain AV1 82 dB

FB_OUT Error Amp Gain-BW Product GBW1 8 MHz

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and “Typical Application Schematics” on page 5. VIN = 4.5V to 40V, or VDD = 5.3V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)


(Note 6) TypMax

(Note 6) Unit

FN9310 Rev.0.00 Page 15 of 47Sep 11, 2018


FB_OUT Error Amp Output Current Capability

±310 µA

COMP Max High Voltage VCOMP_HIGH FB_OUT = 0V 3.8 V

COMP Min Low Voltage VCOMP_LOW FB_OUT = 1V 0.01 V

FB_IN Pin Bias Current IFBINLKG -50 0 +50 nA

FB_IN Error Amp GM Gm2 12 µS

FB_IN Error Amp Voltage Gain AV2 72 dB

FB_IN Error Amp Gain-BW Product GBW2 5 MHz

FB_IN Active Range (Note 10) VFB_IN_ACT VCC5V = 5V 0 4.3 V

FB_IN Logic Low Threshold (Note 10) VFB_IN_L 0.2 V

FB_IN Logic High Threshold (Note 10) VFB_IN_H VCC5V = 5V 4.7 V

PWM Regulator

Buck Mode Minimum Off-Time tOFF_MIN1 220 ns

Buck Mode Minimum On-Time tON_MIN1 100 ns

Boost Mode Minimum Off-Time tOFF_MIN2 180 ns

Boost Mode Minimum On-Time tON_MIN2 140 ns

Buck Mode Peak-to-Peak Sawtooth Amplitude


Boost Mode Peak-to-Peak Sawtooth Amplitude


Buck Mode Ramp Offset VROFFSET1 0.88 0.95 1.11 V

Boost Mode Ramp Offset VROFFSET2 2.84 3.15 3.7 V

Current Sense, Current Monitors, and Average Current Loop

Input Current Sense Differential Voltage Range

VCS+ - VCS- -80 +150 mV

Input Current Sense Common-Mode Voltage Range

CMIRCS 0 40 V

IMON_IN Offset Current ICSOFFSET CS+ = CS- = 12V 17.5 20 22 µA

Input Current Sense Voltage to IMON_IN Current Source Gain

GmCS 12V common-mode voltage applied to CS+/- pins, 0 to 40mV differential voltage

170 200 220 µS

IMON_IN Error Amp GM Gm3 12 µS

IMON_IN Error Amp Voltage Gain AV3 72 dB

IMON_IN Active Range (Note 10) VIMON_IN_ACT VCC5V = 5V 0 4.3 V

IMON_IN Logic High Threshold (Note 10)

VIMON_IN_H VCC5V = 5V 4.7 V

IMON_IN Error Amp Gain-BW Product

GBW3 5 MHz

Output Current Sense Differential Voltage Range

VISEN+ - VISEN- -80 +150 mV

Output Current Sense Common-Mode Voltage Range

CMIRISEN 0 40 V

IMON_OUT Offset Current IISENOFFSET ISEN+ = ISEN- = 12V 17.5 20 22 µA



(Note 6) TypMax

(Note 6) Unit

FN9310 Rev.0.00 Page 16 of 47Sep 11, 2018


IMON_OUT Current ISEN+ = 12V. ISEN- = 11.96V 25.5 27.6 29 µA

Output Current Sense Voltage to IMON_OUT Current Source Gain

GmISEN 12V common-mode voltage applied to ISEN+/- pins, 0mV to 40mV differential voltage

170 200 220 µS

IMON_OUT Error Amp GM Gm4 12 µS

IMON_OUT Error Amp Voltage Gain AV4 72 dB

IMON_OUT Error Amp Gain-BW Product

GBW4 5 MHz

Switching Frequency and Synchronization

Switching Frequency fSW RT = 144kΩ 220 245 265 kHz

RT = 72kΩ 420 450 485 kHz

RT Open or to VCC5V 90 120 145 kHz

RT = 0V 470 575 650 kHz

RT Voltage VRT RT = 72kΩ 580 mV

SYNC Synchronization Range fSYNC 140 600 kHz

SYNC Input Logic High VSYNCH 3.2 V

SYNC Input Logic Low VSYNCL 0.5 V

Clock Output and Frequency Dither

CLKOUT Output High VCLKH ISOURCE = 1mA, VCC5V = 5V 4.55 V

CLKOUT Output Low VCLKL ISINK = 1mA 0.3 V

CLKOUT Frequency fCLK RT = 72kΩ 420 450 485 kHz

Dither Mode Setting Current Source IDITHER_MODE_SO 10 µA

Dither Mode Setting Threshold Low VDITHER_MODE_L 0.26 V

Dither Mode Setting Threshold High VDITHER_MODE_H 0.34 V

Dither Source Current IDITHERSO 8 µA

Dither Sink Current IDITHERSI 10 µA

Dither High Threshold Voltage VDITHERH 2.2 V

Dither Low Threshold Voltage VDITHERL 1.05 V

Diode Emulation Mode Detection

MODE Input Logic High 3.2 V

MODE Input Logic High 1 V

Buck Mode Diode Emulation Phase Threshold (Note 11)

VCROSS1 VIN = 12V 2 mV

Boost Mode Diode Emulation Shunt Threshold (Note 12)

VCROSS2 VIN = 12V -2 mV

Diode Emulation Burst Mode

Burst Mode Enter Threshold VIMONOUTBSTEN IMON_OUT pin voltage 0.815 0.84 0.855 V

Burst Mode Exit Threshold VMONOUTBSTEX IMON_OUT pin voltage 0.86 0.88 0.89 V

Burst Mode Peak Current Limit Input Shunt Set Point

VBST-CS VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins

16 27 39 mV



(Note 6) TypMax

(Note 6) Unit

FN9310 Rev.0.00 Page 17 of 47Sep 11, 2018


Burst Mode Peak FB Voltage Limit Set Point

VBST-VFB-UTH 0.82 V

Burst Mode Exit FB Voltage Set Point VBST-VFB-LTH 0.78 V

PWM Gate Drivers

Driver 1, 2 BOOT Refresh Trip Voltage

VBOOTRF1,2 BOOT voltage - PHASE voltage 3.45 3.9 4.35 V

Driver 1, 2 Source and Upper Sink Current

IGSRC1,2 2000 mA

Driver 1, 2 Lower Sink Current IGSNK1,2 3000 mA

Driver 1, 2 Upper Drive Pull-Up RUG_UP1,2 2.2 Ω

Driver 1, 2 Upper Drive Pull-Down RUG_DN1,2 1.7 Ω

Driver 1, 2 Lower Drive Pull-Up RLG_UP1,2 3 Ω

Driver 1, 2 Lower Drive Pull-Down RLG_DN 2 Ω

Driver 1, 2 Upper Drive Rise Time tGR_UP COUT = 1000pF 10 ns

Driver 1, 2 Upper Drive Fall Time tGF_UP COUT = 1000pF 10 ns

Driver 1, 2 Lower Drive Rise Time tGR_DN COUT = 1000pF 10 ns

Driver 1, 2 Lower Drive Fall Time tGF_DN COUT = 1000pF 10 ns

Overvoltage Protection

Output OVP Threshold VOVTH_OUT 112 114 116 %

Overcurrent Protection

LG2/OC_MODE Current Source IMODELG2 7.5 10 12.5 µA

LG2/OC_MODE Threshold Low VMODETHLOC 0.26 V

LG2/OC_MODE Threshold High VMODETHHOC 0.34 V

Pulse-by-Pulse Peak Current Limit Input Shunt Set Point

VOCSET-CS VCS+ - VCS-, 12V common-mode voltage applied to CS+/- pins

73 83 93 mV

Hiccup Peak Current Limit Input Shunt Set Point

VOCSET-CS-HIC VCS+ - VCS- 100 mV

Pulse-by-Pulse Negative Peak Current Limit Output Shunt Set Point

VOCSET-ISEN VISEN+ - VISEN-, 12V common-mode voltage applied to ISEN+/- pins

-70 -59 -48 mV

Hiccup and Current Input Constant Limit Set Point

VIMONINCC IMON_IN Pin Voltage 1.185 1.2 1.215 V

Input Constant and Hiccup Current Limit Set Point at CS+/- Input

VAVOCP_CS VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +125°C

44 51 64 mV

VCS+ - VCS-, 12V common-mode applied to CS+/- pins, RIMON_IN = 40.2k, TJ = -40°C to +85°C

44 51 60 mV

Output Constant and Hiccup Current Limit Set Point

VIMONOUTCC IMON_OUT Pin Voltage 1.185 1.2 1.215 V



(Note 6) TypMax

(Note 6) Unit

FN9310 Rev.0.00 Page 18 of 47Sep 11, 2018


Output Constant and Hiccup Current Limit Set Point at ISEN+/- Input

VAVOCP_ISEN VISEN+ - VISEN-, 12V common-modeapplied to ISEN+/- pins,RIMON_OUT = 40.2k, TJ = -40°C to +125°C

44 51 64 mV

VISEN+ - VISEN-, 12V common-mode applied to ISEN+/- pins, RIMON_OUT = 40.2k, TJ = -40°C to +85°C

44 51 60 mV

Hiccup OCP Off-Time tHICC_OFF 50 ms

Over-Temperature

Over-Temperature Shutdown TOT-TH 160 °C

Over-Temperature Hysteresis TOT-HYS 15 °C

Notes:6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.7. This is the total shutdown current with VIN = 5.6V and 40V.8. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive

current.9. When soft-start time is less than 4.5ms, tPGR increases. With internal soft-start (the fastest soft-start time), tPGR increases close

to its max limit 5ms.10. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.11. Threshold voltage at the PHASE1 pin for turning off the buck bottom MOSFET during DE mode.12. Threshold voltage between the ISEN+ and ISEN- pins for turning off the boost top MOSFET during DE mode.



(Note 6) TypMax

(Note 6) Unit

FN9310 Rev.0.00 Page 19 of 47Sep 11, 2018

ISL81401, ISL81401A 3. Typical Performance Curves

3. Typical Performance CurvesOscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted.

Figure 6. Shutdown Current vs Temperature Figure 7. Quiescent Current vs Temperature

Figure 8. VDD Load Regulation at 12V Input Figure 9. VDD Line Regulation at 20mA Load

Figure 10. VCC5V Load Regulation at 12VIN Figure 11. VCC5V Line Regulation at 20mA Load

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-60 -40 -20 0 20 40 60 80 100 120 140

Sh

utd

ow

n C

urr

en

t (μ

A)

Temperature (°C)

Vin = 12V Vin = 40V

Vin = 4.5V Vin = 5.6V

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

-60 -40 -20 0 20 40 60 80 100 120 140

Qu

iescen

t C

urr

en

t (m

A)

Temperature (°V)

Vin = 12V Vin = 40V

Vin = 4.5V Vin = 5.6V

0

1

2

3

4

5

6

0 20 40 60 80 100 120 140

VD

D(V

)

Load Current (mA)

VIN = 12V, Vextbias = 0

VIN = 4.5V, Vextbias = 12V

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

0 10 20 30 40 50

VD

D(V

)

VIN, Vextbias (V)

VDD vs VIN

VDD Vs Vextbias

0

1

2

3

4

5

6

0 20 40 60 80 100 120

VC

C5V

(V

)

Load Current (mA)

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

4.4 4.6 4.8 5.0 5.2 5.4 5.6

VC

C5V

(V

)

VDD (V)

FN9310 Rev.0.00 Page 20 of 47Sep 11, 2018


Figure 12. Switching Frequency vs Temperature Figure 13. Switching Frequency vs VIN, RT = 144k

Figure 14. 0.8V Reference Voltage vs Temperature Figure 15. 1.2V Reference Voltage vs Temperature

Figure 16. Normalized Output Voltage vs Voltage on Soft-Start Pin

Figure 17. Input Current IIN (DC) vs IMON_IN Pin Voltage,RS_IN = 3mΩ, RIM_IN = 37.4k

Oscilloscope plots are taken using the ISL81401EVAL1Z evaluation board, VIN = 9V to 40V, VOUT = 12V, IOUT = 10A, unless otherwise noted. (Continued)

200

250

300

350

400

450

500

-50 0 50 100 150

Sw

itch

ing

Fre

qu

en

cy (

kH

z)

Temperature (°C)

RT= 72kΩ

RT= 144kΩ

231

232

233

234

235

236

237

238

239

240

241

0 10 20 30 40 50

f SW

(kH

z)

VIN (V)

0.792

0.794

0.796

0.798

0.800

0.802

0.804

0.806

0.808

-50 0 50 100 150

0.8

V R

efe

ren

ce V

olt

ag

e (

V)

Temperature (°C)

1.195

1.196

1.197

1.198

1.199

1.200

1.201

1.202

1.203

1.204

1.205

-50 0 50 100 150

1.2

V R

efe

ren

ce V

olt

ag

e (

V)

Temperature (°C)

0

20

40

60

80

100

120

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

No

rmalized

Ou

tpu

t V

olt

ate

(%

)

Soft-Start Pin Voltage (V)

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

0 2 4 6 8 10

V_IM

ON

_IN

(V

)

IIN A)

TA = +25°C TA = +125°C

TA = -40°C

FN9310 Rev.0.00 Page 21 of 47Sep 11, 2018


Figure 18. Output Current IOUT (DC) vs IMON_OUT Pin Voltage, RS_OUT = 4mΩ, RIM_OUT = 43.2k

Figure 19. CCM Mode Efficiency

Figure 20. DEM Mode Efficiency Figure 21. CCM Load Regulation at +25°C

Figure 22. CCM Line Regulation at 10A Load +25°C Figure 23. Boost Mode Waveforms, VIN = 6V, IOUT = 8A, CCM Mode


0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

0 2 4 6 8 10

V_IM

ON

_O

UT

(V

)

IOUT(A)

TA = +25°C TA = +125°C

TA = -40°C

70

75

80

85

90

95

100

0.0 1.6 3.2 4.8 6.4 8.0

Eff

icie

nc

y (

%)

IOUT (A)

VIN = 6V VIN = 9V

VIN = 12V VIN = 24V

VIN = 36V

70

75

80

85

90

95

100

0 1 2 3 4 5 6 7 8

Eff

icie

nc

y (

%)

IOUT (A)

VIN = 6V VIN = 9V

VIN = 12V VIN = 24V

VIN = 36V

11.80

11.85

11.90

11.95

12.00

12.05

12.10

12.15

12.20

0 1 2 3 4 5 6 7 8

VO

UT

(V)

IOUT (A)

VIN = 6V VIN = 9V

VIN = 12V VIN = 24V

VIN = 36V

11.90

11.91

11.92

11.93

11.94

11.95

11.96

11.97

11.98

11.99

12.00

5 10 15 20 25 30 35

VO

UT

(V)

VIN (V) 4µs/Div

PHASE1 5V/Div

PHASE2 10V/Div

VOUT 200mV/Div

IL 10A/Div

FN9310 Rev.0.00 Page 22 of 47Sep 11, 2018


Figure 24. Buck-Boost Mode Waveforms,VIN = 12V, IOUT = 8A, CCM Mode

Figure 25. Buck Mode Waveforms, VIN = 40V, IOUT = 8A,CCM Mode

Figure 26. DEM Mode Waveforms, VIN = 6V, IOUT = 0.01A Figure 27. Burst Mode Waveforms, VIN = 6V, IOUT = 0.1A

Figure 28. Burst Mode Waveforms, VIN = 12V, IOUT = 0.1A Figure 29. Burst Mode Waveforms, VIN = 40V, IOUT = 0.1A


4µs/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 200mV/Div

IL 10A/Div

4µs/Div

PHASE1 50V/Div

PHASE2 10V/Div

VOUT 200mV/Div

IL 10A/Div

4µs/Div

PHASE1 5V/Div

VOUT 50mV/Div

IL 1A/Div

PHASE2 10V/Div

2ms/Div

PHASE1 5V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

2ms/Div

PHASE1 10V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

PHASE1 50V/Div

VOUT 200mV/Div

IL 10A/Div

PHASE2 10V/Div

2ms/Div

FN9310 Rev.0.00 Page 23 of 47Sep 11, 2018




Figure 32. Load Transient, VIN = 40V IOUT = 0A to 8A, 2.5A/µs, CCM

Figure 33. Line Transient, VIN = 6V to 40V, 1V/ms, IOUT = 0A

Figure 34. Line Transient, VIN = 40V to 6V, 0.5V/ms, IOUT = 0A

Figure 35. Start-Up Waveform, VIN = 6V IO = 8A, CCM


VOUT 200mV/Div

IOUT 5A/Div

2ms/Div

VOUT 200mV/Div

IOUT 5A/Div

2ms/Div

2ms/Div

VOUT 200mV/Div

IL 5A/Div

VOUT 200mV/Div

IL 10A/Div

VIN 20V/Div

10ms/Div

VOUT 200mV/Div

IL 10A/Div

VIN 20V/Div

20ms/Div 4ms/Div

PHASE1 5V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

FN9310 Rev.0.00 Page 24 of 47Sep 11, 2018


Figure 36. Start-Up Waveform, VIN = 12V IO = 8A, CCM Figure 37. Start-Up Waveform, VIN = 40V IO = 8A, CCM

Figure 38. OCP Response, Output Short-Circuited from No Load to Ground and Released, CCM Mode, VIN = 12V

Figure 39. Constant Voltage (CV) andConstant Current (CC) Operation

Figure 40. Bi-Directional OperationVIN = 18V, VIN Regulation at 6V, Remove VIN DC Source with 1A Load Applied on Input Terminals


4ms/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

4ms/Div

PHASE1 50V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 10A/Div

40ms/Div

PHASE1 10V/Div

PHASE2 10V/Div

VOUT 5V/Div

IL 20A/Div0

2

4

6

8

10

12

14

0 2 4 6 8 10 12

VO

UT

(V)

IOUT (A)

VIN = 6V VIN = 12V

VIN = 40V

VIN 5V/Div

VOUT 10V/Div

4ms/Div

IL 20A/Div

FN9310 Rev.0.00 Page 25 of 47Sep 11, 2018

ISL81401, ISL81401A 4. Functional Description

4. Functional Description

4.1 General DescriptionThe ISL81401 and ISL81401A implement a complete buck-boost switching control with a PWM controller, internal drivers, references, protection circuitry, current and voltage control inputs, and monitor outputs. Refer to Figure 5 on page 6.

The ISL81401 and ISL81401A are current-mode controllers. They use a proprietary control algorithm to automatically switch between Buck and Boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads. The controllers integrate four control loops to regulate not only VOUT, but also average IOUT and IIN for constant current control and VIN for reverse direction control.

The driver and protection circuits are also integrated to simplify the end design.

The part has an independent enable/disable control line, which provides a flexible power-up sequencing and a simple VIN UVP implementation. The soft-start time is programmable by adjusting the soft-start capacitor connected from SS/TRK.

4.2 Internal 5.3V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear Regulator (VCC5V)

The ISL81401 and ISL81401A provide two input pins, VIN and EXTBIAS, and two internal LDOs for VDD gate driver supply. A third LDO generates VCC5V from VDD. VCC5V provides power to all internal functional circuits other than the gate drivers. Bypass the linear regulator’s outputs (VDD) with a 10µF capacitor to the power ground. Also bypass the third linear regulator output (VCC5V) with a 10µF capacitor to the signal ground. VCC5V is monitored by a power-on-reset circuit, which disables all regulators when VCC5V falls below 3.5V.

Both LDOs from VIN and EXTBIAS can source over 75mA for VDD to power the buck and boost gate drivers. When driving large FETs at high switching frequency, little or no regulator current may be available for external loads. The LDO from VDD to VCC5V can also source over 75mA to supply the IC internal circuit. Although the current consumed by the internal circuit is low, the current supplied by VCC5V to the external loads is limited by VDD. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).

Also, at higher input voltages with larger FETs, the power dissipation across the internal 5.3V LDO increases. Excessive power dissipation across this regulator must be avoided to prevent junction temperature rise. Thermal protection may be triggered if die temperature increases above +150°C due to excessive power dissipation.

When large MOSFETs are used, an external 5V bias voltage can be applied to the EXTBIAS pin to alleviate excessive power dissipation. When the voltage at the EXTBIAS pin is higher than typical 4.8V, the LDO from EXTBIAS activates and the LDO from VIN is disconnected. The recommended maximum voltage at the EXTBIAS pin is 36V. For applications with VOUT significantly lower than VIN, EXTBIAS is usually back biased by VOUT to reduce the LDO power loss. EXTBIAS is allowed to activate only after soft-start is finished to avoid early activation during the VOUT rising stage. An external UVLO circuit might be necessary to ensure smooth soft-starting. Renesas recommends adding a 10µF capacitor on the EXTBIAS pin and using a diode to connect the EXTBIAS pin to VOUT to avoid the EXTBIAS pin voltage being pulled low at the VOUT short-circuit condition.

The two VDD LDOs have an overcurrent limit for short-circuit protection. The VIN to VDD LDO current limit is set to typical 120mA. The EXTBIAS to VDD LDO current limit is set to typical 160mA.

4.3 Enable (EN/UVLO) and Soft-Start OperationPulling the EN/UVLO pin high or low can enable or disable the controller. When the EN/UVLO pin voltage is higher than 1.3V, the three LDOs are enabled. After the VCC5V reaches the POR threshold, the controller is powered up to initialize its internal circuit. When EN/UVLO is higher than the 1.8V accurate UVLO threshold, the ISL81401 and ISL81401A soft-start circuitry becomes active. The internal 2µA charge current begins charging up the soft-start capacitor connected from the SS/TRK pin to GND. The voltage error amplifier reference voltage is

FN9310 Rev.0.00 Page 26 of 47Sep 11, 2018


clamped to the voltage on the SS/TRK pin. The output voltage thus rises from 0V to regulation as SS/TRK rises from 0V to 0.8V. Charging of the soft-start capacitor continues until the voltage on the SS/TRK pin reaches 3V.

Typical applications for the ISL81401 and ISL81401A use programmable analog soft-start or the SS/TRK pin for tracking. The soft-start time can be set by the value of the soft-start capacitor connected from SS/TRK to GND. Inrush current during start-up can be alleviated by adjusting the soft-starting time.

The typical soft-start time is set according to Equation 2:

When the soft-starting time set by external CSS or tracking is less than 1.5ms, an internal soft-start circuit of 1.5ms takes over the soft-start.

PGOOD toggles to high when the output voltage is in regulation.

Pulling the EN/UVLO lower than the EN threshold of 1.3V disables the PWM output and internal LDOs to achieve low standby current. The SS/TRK pin is also discharged to GND by an internal MOSFET with 70Ω rDS(ON). For applications with a larger than 1µF capacitor on the SS/TRK pin, Renesas recommends adding a 100Ω to 1kΩ resistor in series with the capacitor to share the power loss at the discharge.

With use of the accurate UVLO threshold, an accurate VIN Undervoltage Protection (UVP) feature can be implemented by feeding the VIN into the EN/UVLO pin using a voltage divider, RUV1 and RUV2, shown in Figure 41.

The VIN UVP rising threshold can be calculated by Equation 3.

where VUVLO_THR is the EN/UVLO pin UVLO rising threshold, typically 1.8V.

The VIN UVP falling threshold can be calculated by Equation 4.

where IUVLO_HYST is the UVLO hysteresis current, typically 4.2µA.

Figure 41. VIN Undervoltage Protection

tSS 0.8VCSS2A----------- =(EQ. 2)

EN/UVLO

VIN

RUV1

RUV2

ISL81401/ISL81041A

VUVRISE

VUVLO_THR RUV1 RUV2+ 1.1x10 6–– – RUV1RUV2RUV2

--------------------------------------------------------------------------------------------------------------------------------------------------=(EQ. 3)

VUVFALL

VUVLO_THR RUV1 RUV2+ IUVLO_HYST – RUV1RUV2RUV2

----------------------------------------------------------------------------------------------------------------------------------------------------------=(EQ. 4)

FN9310 Rev.0.00 Page 27 of 47Sep 11, 2018


4.4 Tracking OperationThe ISL81401 and ISL81401A can track an external supply. To implement tracking, connect a resistive divider between the external supply output and ground. Connect the center point of the divider to the SS/TRK pin of the ISL81401 and ISL81401A. The resistive divider ratio sets the ramping ratio between the two voltage rails. To implement coincident tracking, set the tracking resistive divider ratio exactly the same as the ISL81401 and ISL81401A output resistive divider given by Equation 5 on page 27. Make sure that the voltage at SS/TRK is greater than 0.8V when the master rail reaches regulation.

To minimize the impact of the 2µA soft-start current on the tracking function, Renesas recommends using resistors less than 10kΩ for the tracking resistive divider.

When the SS/TRK pin voltage is pulled down to less than 0.3V by the external tracking source, the prebias startup DEM function is enabled again. The output voltage may not be able to be pull down if the load current is not highenough.

When Overcurrent Protection (OCP) is triggered, the internal minimum soft-start circuit determines the 50ms OCP soft-start hiccup off-time.

4.5 Control LoopsThe ISL81401 and ISL81401A are current-mode controllers that can provide an output voltage above, equal to, or below the input voltage. Referring to Figure 2 on page 2 (Typical Application circuit) and Figure 5 on page 6 (Block Diagram), the Renesas proprietary control architecture uses a current sense resistor in series with the buck upper FET to sense the inductor current in Buck or Boost mode. The inductor current is controlled by the voltage on the COMP pin, which is the lowest output of the error amplifiers Gm1 - Gm4. As the simplest example, when the output is regulated to a constant voltage, the FB_OUT pin receives the output feedback signal, which is compared to the internal reference by Gm1. Lower output voltage creates higher COMP voltage, which leads to higher PWM duty cycle to push more current to the output. Conversely, higher output voltage creates lower COMP voltage, which leads to lower PWM duty cycle to reduce the current to the output.

The ISL81401 and ISL81401A have four error amplifiers (Gm1-4) which can control output voltage (Gm1), input voltage (Gm2), input current (Gm3), and output current (Gm4). In a typical application, the output voltage is regulated by Gm1, and the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. In other applications, such as a battery charger, the output current regulator (Gm4) implements constant current charging until a predetermined voltage is reached, at which point the output voltage regulator (Gm1) takes control.

4.5.1 Output Voltage Regulation LoopThe ISL81401 and ISL81401A provide a precision 0.8V internal reference voltage to set the output voltage. Based on this internal reference, the output voltage can be set from 0.8V up to a level determined by the feedback voltage divider, as shown in Figure 42 on page 28.

A resistive divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT pin. The output voltage value is determined by Equation 5.

where RFBO1 is the top resistor of the feedback divider network and RFBO2 is the bottom resistor connected from FB_OUT to ground, shown in Figure 42.

VOUT 0.8VRFBO1 RFBO2+

RFBO2---------------------------------------------

=(EQ. 5)

FN9310 Rev.0.00 Page 28 of 47Sep 11, 2018


As shown in Figure 42, the RCOMP, CCOMP1, and CCOMP2 network connected on the Gm1 regulator output COMP pin is needed to compensate the loop for stable operation. The loop stability can be affected by many different factors such as VIN, VOUT, load current, switching frequency, inductor value, output capacitance, and the compensation network on COMP pin. For most applications, 22nF is a good value for CCOMP1. A larger CCOMP1 makes the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. CCOMP2 is typically 1/10th to 1/30th of CCOMP1 to filter high frequency noise. A good starting value for RCOMP is 10k. Lower RCOMP improves stability but slows the loop response. Optimize the final compensation network with a bench test.

4.5.2 Input Voltage Regulation LoopAs shown in Figure 43, the input voltage VIN can be sensed by the FB_IN pin using a resistor divider RFBIN1/RFBIN2 and regulated by Gm2. When the FB_IN pin voltage falls below the 0.8V reference voltage, the COMP pin voltage is pulled low to reduce the PWM duty cycle and the input current. For applications with a high input source impedance, such as a solar panel, the input voltage regulation loop can prevent the input voltage from being pulled too low in high output load conditions. For applications with a low input source impedance, such as batteries, the VIN feedback loop can prevent the battery from being over-discharged. For applications with loads on the VIN supply, such as a DC back up system, the input voltage regulation loop can reduce the input current to negative area to reverse power conversion direction to discharge the backup battery or supper capacitor to supply a regulated VIN for the loads. The regulated input voltage value is determined by Equation 6.

FB_IN is a dual-function pin. It also sets the phase angle of the clock output signal on the CLKOUT/DITHER pin, shown in Table 2 on page 35. The VIN feedback loop is disabled when the FB_IN pin voltage is below 0.3V or above 4.7V. The VIN feedback loop is also disabled in DEM mode and during soft-start.

Figure 42. Output Voltage Regulator

Figure 43. VIN Feedback Loop

COMPFB_OUT

+

_

+

_0.8VREF

GM1

VOUT

RFBO1

RFBO2RCOMP

CCOMP1

CCOMP2

VIN 0.8VRFBIN1 RFBIN2+

RFBIN2------------------------------------------------

=(EQ. 6)

COMPFB_IN

+

_

+

_0.8VREF

GM2

VIN

RFBIN1

RFBIN2

FN9310 Rev.0.00 Page 29 of 47Sep 11, 2018


4.5.3 Input and Output Average Current Monitoring and Regulation LoopsAs shown in Figure 44, the ISL81401 and ISL81401A have two current sense operational amplifiers (op amps), A1 and A2, which monitor both input and output current. The voltage signals on the input and output current sense resistor RS_IN and RS_OUT are sent to the differential inputs of CS+/CS- and ISEN+/ISEN-, respectively, after the RC filters RS_IN1/CS_IN1, RS_IN2/CS_IN2, RS_OUT1/CS_OUT1, and RS_OUT2/CS_OUT2. Renesas recommends using a 1Ω value for RS_IN1, RS_IN2, RS_OUT1, and RS_OUT2, and a 10nF value for CS_IN1, CS_IN2, CS_OUT1, and CS_OUT2 to effectively damp the switching noise without delaying the current signal too much introducing too much error by the op amp bias current. The Gm op amps A1 and A2 then transfer the current sense voltage signals to current signals ICS and IISEN.

where

• IIN is the input current in Q1 drain

• VCSOFFSET is the A1 input offset voltage

• GmCS is the gain of A1

• VCSOFFSET GmCS = ICSOFFSET.

The typical value of ICSOFFSET is 20µA

where

• IOUT is the output current in Q4 drain

• VISENOFFSET is the A2 input offset voltage

• GmISEN is the gain of A2

• VISENOFFSET GmISEN = IISENOFFSET.

The typical value of IISENOFFSET is 20µA

Figure 44. Input and Output Average Current Monitoring and Regulation Loops

ICS IIN RS_IN VCSOFFSET+ GmCS=(EQ. 7)

IISEN IOUT RS_OUT VISENOFFSET+ GmISEN=(EQ. 8)

CS+

IMON_OUT

CS-

A1

+_

COMP

ISEN+ ISEN-

+_1.2V

Gm3 Gm4

IMON_IN

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

L

UG1

LG1

UG2

LG2

PH1 PH2

A2

1.2V

RIM_INRIM_OUT

RIM_IN1

CIM_IN1CIM_IN2 CIM_OUT2

CIM_OUT1

RIM_OUT1

RS_IN1 RS_IN2

CS_IN1 CS_IN2 CS_OUT1 CS_OUT2

RS_OUT1RS_OUT2

VCS_OFFSETVISEN_OFFSET

IcsIISEN

FN9310 Rev.0.00 Page 30 of 47Sep 11, 2018


By connecting resistor RIM_IN and RIM_OUT on the IMON_IN and IMON_OUT pins, the ICS and IISEN current signals are transferred to voltage signals. The RC networks on the IMON_IN and IMON_OUT pins RIM_IN1/CIM_IN1/CIM_IN2 and RIM_OUT1/CIM_OUT1/CIM_OUT2 are needed to remove the AC content in the ICS and IISEN signals and ensure stable loop operation. The average voltages at the IMON_IN and IMON_OUT pins are regulated to 1.2V by Gm3 and Gm4 for constant input and output current control.

The input constant current loop set point IINCC is calculated by Equation 9.

where RIMIN is the resistance of RIM_IN.

The output constant current loop set point IOUTCC is calculated by Equation 10.

where RIMOUT is the resistance of RIM_OUT.

Similar to the voltage control loops, the loop stability can be affected by many different factors such as VIN, VOUT, switching frequency, inductor value, output and input capacitance, and the RC network on the IMON_IN or IMON_OUT pin. Due to the high AC content in ICS and IISEN, large CIM_IN1 and CIM_OUT1 are needed. Larger CIM_IN1 and CIM_OUT1 can also make the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. For most applications, 47nF is a good value for CIM_IN1 and CIM_OUT1. CIM_IN2 and CIM_OUT2 are typically 1/10th to 1/30th of CIM_IN1 and CIM_OUT1 to filter high frequency noise. RIM_IN1 and RIM_OUT1 are needed to boost the phase margin. A good starting value for RIM_IN1 and RIM_OUT1 is 5k. Optimize the final compensation network with iSim simulation and bench testing.

4.6 Buck-Boost Conversion Topology and Control AlgorithmThe ISL81401 and ISL81401A use the Renesas proprietary buck-boost control algorithm to achieve optimized power conversion performance. The buck-boost topology is shown in Figure 45. The ISL81401 and ISL81401A control the four power switches Q1, Q2, Q3, and Q4 to work in either Buck or Boost mode. When VIN is far lower than VOUT, the converter works in Boost mode. When VIN is far higher than VOUT, the converter works in Buck mode. When VIN is equal or close to VOUT, the converter alternates between Buck and Boost mode as necessary to provide a regulated output voltage, which is called Buck-Boost mode. Figure 46 shows the relationship between the operation modes and VOUT - VIN.

RS_IN is a current sense resistor to sense the inductor current during Q1 on-time. As shown in the “Block Diagram” on page 6, the sensed signal is fed into the CS+ and CS- pins and used for peak or valley current-mode control, DEM control, input average current monitor, constant current control, and protections.

RS_OUT is a current sense resistor to sense the inductor current during Q4 on-time. As shown in the Block Diagram, the sensed signal is fed into the ISEN+ and ISEN- pins and used for negative peak inductor current limit, output average current monitor, constant current control, and protections.

Figure 45. Buck-Boost Topology Figure 46. Operation Modes vs VOUT - VIN

IINCC

1.2 ICSOFFSET– xRIMINRIMINxR

S_INxGm

CS

-------------------------------------------------------------------=(EQ. 9)

IOUTCC

1.2 IISENOFFSET– xRIMOUTRIMOUTxR

S_OUTxGm

ISEN

-------------------------------------------------------------------------------=(EQ. 10)

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

L

UG1

LG1

UG2

LG2

PH1 PH2

0

Boost Mode

Buck/Boost Mode

Buck Mode

VO

UT -

VIN

Q1 On, Q2 Off


Q4 On, Q3 Off


4-Switch PWM

Q3 Max Duty

Q3 Min Duty

Q2 Min Duty

Q2 Max Duty

FN9310 Rev.0.00 Page 31 of 47Sep 11, 2018


4.6.1 Buck Mode Operation (VIN >> VOUT)In Buck mode, Q4 is always on and Q3 is always off unless boot refresh or inductor negative peak current limit is tripped. Q1 and Q2 runs in a normal peak current controlled sync buck operation mode. Q1 turns on by the clock. During Q1 on-time, op amp A1 senses the inductor current by the voltage on RS_IN. Q1 turns off when the sensed signal combined with the slope compensation ramp is higher than the COMP pin voltage, which is the error signal from the upper voltage or current regulator. The equivalent circuit and operation waveforms are shown in Figure 47.

In Buck mode, the Q1 duty cycle is given by:

DQ1 = VOUT / VIN x 100%

As VIN decreases close to VOUT, DQ1 increases close to its maximum value decided by its minimum off-time. When DQ1 reaches its maximum value, the converter moves to Buck-Boost mode.

When VIN is much higher than VOUT, DQ1 decreases to close to its minimum duty cycle decided by its minimum on-time. To allow stable loop operation and avoid duty cycle jitter, Renesas recommends keeping the Q1 on-time always two to three times higher than the minimum on-time.

4.6.2 Boost Mode Operation (VIN << VOUT)In Boost mode, the converter Q1 is always on and Q2 is always off unless boot refresh or inductor negative peak current limit is tripped. Q3 and Q4 run in a normal valley current controlled sync boost operation mode. Q3 turns off by the clock. During Q3 off-time, op amp A1 senses the inductor current by the voltage on RS_IN. Q3 turns on when the sensed signal combined with the slope compensation ramp is lower than the COMP pin voltage which is the error signal from the upper voltage or current regulator. The equivalent circuit and operation waveforms are shown in Figure 48 on page 32.

Figure 47. Buck Mode Equivalent Circuit and Operation Waveforms

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

0V

5V

Q1

VIN VOUT

Q2

RS_IN RS_OUT

LUG1

LG1

PH1 PH2

FN9310 Rev.0.00 Page 32 of 47Sep 11, 2018


In Boost mode, the Q3 duty cycle is given by:

DQ3 = (1 - VIN / VOUT) x 100%

As VIN increases close to VOUT, DQ3 decreases close to its minimum value decided by its minimum on-time. When DQ3 reaches its minimum value, the converter moves to Buck-Boost mode.

When VIN is much lower than VOUT, DQ3 increases close to its maximum duty cycle decided by its minimum off-time. To allow stable loop operation and avoid duty cycle jitter, Renesas recommends keeping the Q3 off-time always two to three times higher than the minimum off-time.

4.6.3 Buck-Boost Mode Operation (VIN >=< VOUT)In Buck-Boost mode, the converter runs in one cycle of Buck mode followed by one cycle of Boost mode operation mode. It takes two clock cycles to finish a full buck-boost period.

When VIN is higher than VOUT, Q3 runs in minimum duty in the Boost mode cycle. Q1 duty cycle DQ1 is modulated in the buck cycle to keep VOUT in regulation. As VIN increases, DQ1 decreases. When DQ1 decreases to less than 66.7% of the clock period, the converter moves to Buck mode.

When VIN is lower than VOUT, Q1 runs in maximum duty in the Buck mode cycle. Q3 duty cycle DQ3 is modulated in the Boost mode cycle to keep VOUT in regulation. As VIN decreases, DQ3 increases. When DQ3 increases to more than 33.3% of the clock period, the converter moves to Boost mode.

Figure 48. Boost Mode Equivalent Circuit and Operation Waveforms

Q3

VIN VOUT

Q4

RS_IN RS_OUT

LUG2

LG2

PH1 PH2

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

0V

5V

FN9310 Rev.0.00 Page 33 of 47Sep 11, 2018


4.7 Light-Load Efficiency EnhancementThe ISL81401 and ISL81401A can be set to DEM and Burst mode to improve light-load efficiency by connecting the MODE pin to VCC5V.

When DEM mode is set, the buck sync FET driven by LG1 and the boost sync FET driven by UG2 are all running in DEM mode. The inductor current is not allowed to reverse (discontinuous operation) depending on the zero cross detection reference level VCROSS1 for buck sync FET and VCROSS2 for boost sync FET. At light load condition, the converter goes into diode emulation. When the load current is less than the level set by VIMONOUTBSTEN typical 0.84V on the IMON_OUT pin, the part enters Burst mode. Equation 11 sets the Burst mode operation enter condition.

where (refer to Figure 44 on page 29):

RIMOUT is the resistance of RIM_OUT

ISENOFFSET is the output current sense op amp internal offset current, typical 20µA

GmISEN is the output current sense op amp Gm, typical 195µS.

The part exits Burst mode when the output current increases to higher than the level set by VIMONOUTBSTEX typical 0.88V on the IMON_OUT pin. Equation 12 sets the Burst mode operation exit condition.

When the part enters Burst mode, the BSTEN pin goes low. To fully avoid any enter/exit chattering, a 4-10MΩ resistor can be added between BETEN and IMON_OUT pins to further expand the hysteresis.

In Burst mode, an internal window comparator takes control of the output voltage. The comparator monitors the FB_OUT pin voltage. When the FB_OUT pin voltage is higher than 0.82V, the controller enters Low Power Off mode. Some of the unnecessary internal circuitries are powered off. When the FB_OUT pin voltage drops to 0.8V, the controller wakes up and runs in a fixed level peak current controlled D/(1-D) Buck-Boost mode when VIN - VOUT < 2V and Buck mode when VIN -VOUT > 2V. In the D/(1-D) Buck-Boost mode, Q1 and Q3 conduct in D*T period, where D is the duty cycle and T is the switching period. Q2 and Q4 complimentarily conduct in (1-D)*T period. Q1 and Q3 are turned on by the clock signal and turned off when inductor current rises to the level that the input current sense op amp input voltage reaches VBST-CS, typical 27mV. After Q1 and Q3 are turned off, Q2 and Q4 are turned on to pass the energy stored in the inductor to the output until next cycle begins. The output

Figure 49. Buck-Boost Mode Equivalent Circuit and Operation Waveforms

CLOCK

Q1 UG1

Q2 LG1

Q3 LG2

Q4 UG2

IL

Q1

Q3

VIN VOUT

Q2

Q4

RS_IN RS_OUT

LUG1

LG1

UG2

LG2

PH1 PH2

RIMOUTx ISENOFFSET IOUTxRS_OUTxGmISEN+ 0.84V(EQ. 11)

RIMOUTx ISENOFFSET IOUTxRS_OUTxGmISEN+ 0.88V(EQ. 12)

FN9310 Rev.0.00 Page 34 of 47Sep 11, 2018


voltage increases in the wake up period. When the output reaches 0.82V again, the controller enters into Low Power Off mode again. When the load current increases, the Low Power Off mode period decreases. When the off mode period disappears and the load current further increases but still does not meet the Equation 12 exit condition, the output voltage drops. When the FB_OUT pin voltage drops to 0.78V, the controller exits Burst mode and runs in normal DEM PWM mode. The voltage error amplifier takes control of the output voltage regulation.

In Low Power Off mode, the CLKEN pin goes low. By connecting the BSTEN and CLKEN pins together in a multiple chip parallel system, the Burst mode enter/exit and burst on/off controls are all synchronized.

Because the VOUT is controlled by a window comparator in Burst mode, higher than normal low frequency voltage ripples appear on the VOUT, which can generate audible noise if the inductor and output capacitors are not chosen properly. Also, the efficiency in D/(1-D) Buck-Boost mode is low. To avoid these drawbacks, the Burst mode can be disabled by choosing a bigger RIMOUT to set the IMON_OUT pin voltage higher than 0.88V at no load condition, shown in Equation 13. The part runs in DEM mode only. Pulse Skipping mode can also be implemented to lower the light load power loss with much lower output voltage ripple as the VOUT is always controlled by the regulator Gm1.

4.8 Prebiased Power-UpThe ISL81401 and ISL81401A have the ability to soft-start with a prebiased output by running in forced DEM mode during soft-start. The output voltage is not pulled down during prebiased start-up. PWM mode is not active until the soft-start ramp reaches 90% of the output voltage times the resistive divider ratio. Forced DEM mode is set again when the SS/TRK pin voltage is pulled to less than 0.3V by either internal or external circuit.

The overvoltage protection function is still alive during soft-start of the DEM operation.

4.9 Frequency Selection Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency improves efficiency by reducing MOSFET switching loss. To meet the output ripple and load transient requirements, operation at a low switching frequency would require larger inductance and output capacitance. The switching frequency of the ISL81401 and ISL81401A is set by a resistor connected from the RT/SYNC pin to GND according to Equation 1 on page 10.

The frequency setting curve shown in Figure 50 assists in selecting the correct value for RT.

4.10 Phase Lock Loop (PLL)The ISL81401 and ISL81401A integrate a high performance PLL. The PLL ensures the wide range of accurate clock frequency and phase setting. It also easily synchronizes the internal clock to an external clock with the frequency either lower or higher than the internal setting.

Figure 50. RT vs Switching Frequency fSW

RIMOUTxISENOFFSET 0.88V(EQ. 13)

0

500

1,000

1,500

2,000

2,500

3,000

0 50 100 150 200 250

f SW

(kH

z)

RT (k�)

FN9310 Rev.0.00 Page 35 of 47Sep 11, 2018


As shown in Figure 51, an external compensation network of RPLL, CPLL1, and CPLL2 is needed to connect to the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩ for RPLL, 10nF for CPLL1, and 820pF for CPLL2. With the recommended compensation network, the PLL stability is ensured in the full clock frequency range of 100kHz to 600kHz.

4.11 Frequency Synchronization and DitheringThe RT/SYNC pin can synchronize the ISL81401 and ISL81401A to an external clock or the CLKOUT/DITHER pin of another ISL81401. When the RT/SYNC pin is connected to the CLKOUT/DITHER pin of another ISL81401, the two controllers operate in cascade synchronization with phase interleaving.

When the RT/SYNC pin is connected to an external clock, the ISL81401 and ISL81401A synchronizes to this external clock frequency. The frequency set by the RT resistor can be either lower or higher than, or equal to the external clock frequency.

The CLKOUT/DITHER pin outputs a clock signal with approximately 300ns pulse width. The signal frequency is the same as the frequency set by the resistor from the RT pin to ground or the external sync clock. The signal rising edge phase angle to the rising edge of the internal clock or the external clock to the RT/SYNC pin can be set by the voltage applied to the FB_IN and IMON_IN pins. The phase interleaving can be implemented by the cascade connecting of the upper chip CLKOUT/DITHER pin to the lower chip RT/SYNC pin in a parallel system. Table 2 shows the CLKOUT/DITHER phase settings with different FB_IN and IMON_IN pin voltages.

When FB_IN is connected to 4.5V, the VIN feedback control loop is disabled. When IMON_IN is connected to 4.5V, the average input current control loop and input current hiccup OCP are disabled.

In multi-chip cascade parallel operation, the CLKOUT pin of the upstream chip is connected to the RT/SYNC pin of the downstream chip. Renesas recommends leaving the RT/SYNC pin open for all the slave chips. The FB_IN, SS/TRK, COMP, FB_OUT, IMON_OUT, EN/UVLO, IMON_IN, and MODE pins of all the paralleled chips should be tied together. Refer to ISL81601 datasheet for the current sharing approach in parallel operation.

The CLKOUT/DITHER pin provides a dual function option. When a capacitor CDITHER is connected on the CLKOUT/DITHER pin, the internal circuit disables the CLKOUT function and enables the DITHER function. When the CLKOUT/DITHER pin voltage is lower than 1.05V, a typical 8µA current source IDITHERSO charges the capacitor on the pin. When the capacitor voltage is charged to more than 2.2V, a typical 10µA current source IDITHERSI discharges the capacitor on the pin. A sawtooth voltage waveform shown in Figure 52 is generated on the CLKOUT/DITHER pin. The internal clock frequency is modulated by the sawtooth voltage on the CLKOUT/DITHER pin. The clock frequency dither range is set to typically ±15% of the frequency set by the resistor on the RT/SYNC pin. The dither function is lost when the chip is synchronized to an external clock.

Figure 51. PLL Compensation Network

Table 2. CLKOUT Phase Shift vs FB_IN and IMON_IN Voltage

CLKOUT Phase Shift 120° 90° 60° 180°

FB_IN Voltage Active 1 1 Active

IMON_IN Voltage 1 Active 1 Active

Note: “1” means logic high 4.7V to 5V. “Active” means logic low 0V to 4.3V.

PLL_COMP

CPLL1

RPLL

CPLL2

ISL81401/ISL81401A

http://www.intersil.com/products/isl81601?utm_source=intersil&utm_medium=datasheet&utm_campaign=isl81401-401a-ds-body#documents

FN9310 Rev.0.00 Page 36 of 47Sep 11, 2018


The dither frequency FDITHER can be calculated by Equation 14. Renesas recommends setting CDITHER between 10nF and 1µF. With a too low CDITHER the part may not be able to set to Dither mode. With a higher CDITHER, the discharge power loss at disable or power off is higher, leading to a higher thermal stress to the internal discharge circuit.

4.12 Gate DriversThe ISL81401 and ISL81401A integrate two almost identical high voltage driver pairs to drive both buck and boost MOSFET pairs. Each driver pair consists of a gate control logic circuit, a low side driver, a level shifter, and a high side driver.

The ISL81401 and ISL81401A incorporate an adaptive dead time algorithm that optimizes operation with varying MOSFET conditions. This algorithm provides approximately 16ns dead time between the switching of the upper and lower MOSFETs. This dead time is adaptive and allows operation with different MOSFETs without having to externally adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead time circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. When the upper MOSFET gate-to-source voltage drops below a threshold of 1V, the LGATE is allowed to rise. Renesas recommends not using a resistor between the driver outputs and the respective MOSFET gates, because it can interfere with the dead time circuitry.

The low-side gate driver is supplied from VDD and provides a 3A peak sink and 2A peak source current. The high-side gate driver can also deliver the same currents as the low-side gate driver. Gate-drive voltage for the upper N-channel MOSFET is generated by a flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high-side MOSFET driver. As shown in Figure 53 on page 37, the boot capacitor is charged up to VDD by an external Schottky diode during low-side MOSFET on-time (phase node low). To limit the peak current in the Schottky diode, an external resistor can be placed between the BOOT pin and the boot capacitor. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance.

Figure 52. Frequency Dithering Operation

CLKOUT/DITHER

CDITHER

ISL81401

FDITHER

1

2.2V

1.05V

a. Frequency Dithering Operation

b. CLKOUT/DITHER Pin Voltage Waveform in Dither Operation

FDITHER3.865x10e 6–

CDITHER-----------------------------------------=(EQ. 14)

FN9310 Rev.0.00 Page 37 of 47Sep 11, 2018


At start-up, the low-side MOSFET turns on first and forces PHASE to ground to charge the BOOT capacitor to 5.3V if the diode voltage drop is ignored. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5.3V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5.3V regulator supplied from either VIN or EXTBIAS pin.

The BOOT to PHASE voltage is monitored internally. When the voltage drops to 3.9V at no switching condition, a minimum off-time pulse is issued to turn off the upper MOSFET and turn on the low-side MOSFET to refresh the bootstrap capacitor and maintain the upper driver bias voltage.

To optimize EMI performance or reduce phase node ringing, a small resistor can be placed between the BOOT pin to the positive terminal of the bootstrap capacitor.

4.13 Power-Good IndicatorThe power-good pin can monitor the status of the output voltage. PGOOD is true (open drain) 1.1ms after the FB_OUT pin is within ±10% of the reference voltage.

There is no extra delay when the PGOOD pin is pulled low.

Figure 53. Upper Gate Driver Circuit

BOOT

UGATE

PHASE

VDDVIN

ISL81401/ISL81401A

CB

RBOOT

ExternalSchottky

FN9310 Rev.0.00 Page 38 of 47Sep 11, 2018

ISL81401, ISL81401A 5. Protection Circuits

5. Protection CircuitsThe converter output and input are monitored and protected against overload, overvoltage, and undervoltage conditions.

5.1 Input Undervoltage Lockout The ISL81401 and ISL81401A include input UVLO protection, which keeps the devices in a reset condition until a proper operating voltage is applied. UVLO protection shuts down the ISL81401 and ISL81401A if the input voltage drops below 3.2V. The controller is disabled when UVLO is asserted. When UVLO is asserted, PGOOD is valid and is deasserted. If the input voltage rises above 4V, UVLO is deasserted to allow the start-up operation.

5.2 VCC5V Power-On Reset (POR)The ISL81401 and ISL81401A set their VCC5V POR rising threshold at 4V and falling threshold at 3.5V when supplied by VIN. EXTBIAS can activate only after VCC5V reaches its POR rising threshold.

5.3 Overcurrent Protection (OCP)

5.3.1 Input and Output Average Overcurrent ProtectionAs described in “Input and Output Average Current Monitoring and Regulation Loops” on page 29, the ISL81401 and ISL81401A can regulate both input and output currents with close loop control. This provides a constant current type of overcurrent protection for both input and output average current. It can be set to a hiccup type of protection by selecting a different value of the resistor connected between LG2/OC_MODE and GND.

The input and output constant or hiccup average OCP set points IINCC and IOUTCC can be calculated by Equations 9 and 10 in Input and Output Average Current Monitoring and Regulation Loops.

The average OCP mode is set by a resistor connected from the LG2/OC_MODE pin to ground during the initiation stage before soft-start. During the initiation stage, the LG2/OC_MODE pin sources out a typical 10µA current IMODELG2 to set the voltage on the pin. If the pin voltage is less than 0.3V, the OCP is set to Constant Current-mode. Otherwise, the OCP is set to hiccup mode.

In hiccup OCP mode, after the average current is higher than the set point for 32 consecutive switching cycles the converter turns off for 50ms before a restart-up is issued.

5.3.2 First Level Pulse-by-Pulse Peak Current LimitAs shown in Figure 44 on page 29 in Input and Output Average Current Monitoring and Regulation Loops, the inductor peak current is sensed by the shunt resistor RS_IN and op amp A1. When the voltage drop on RS_IN reaches the set point VOCSET-CS typical 83mV, Q1 is turned off in Buck mode or Q3 is turned off in Boost mode. The first level peak current limit set point IOCPP1 can be calculated by Equation 15.

IOCPP1

VOCSET CS–RS_IN

----------------------------------=(EQ. 15)

FN9310 Rev.0.00 Page 39 of 47Sep 11, 2018

ISL81401, ISL81401A 5. Protection Circuits

5.3.3 Second Level Hiccup Peak Current ProtectionTo avoid any false trip in peak current-mode operation, a minimum on or blanking time is set to the PWM signal. The first level pulse-by-pulse current limit circuit cannot further reduce the PWM duty cycle in the minimum on-time. In output dead short conditions, especially at high VIN, the inductor current runs away with the minimum on PWM duty. The ISL81401 and ISL81401A integrate a second level hiccup type of peak current protection. When the voltage drop on RS_IN reaches the set point VOCSET-CS-HIC (typical 100mV), the converter turns off by turning off all four switches Q1, Q2, Q3, and Q4 for 50ms before a restart is issued. The second level peak current protection set point IOCPP2 can be calculated by Equation 16.

5.3.4 Pulse-by-Pulse Negative Peak Current LimitIn cases of reverse direction operation and OVP protection, the inductor current goes to negative. The negative current is sensed by the shunt resistor RS_OUT and op amp A2 shown in Figure 44. When the voltage drop on RS_IN reaches the set point VOCSET-ISEN (typical -59mV), Q2 and Q4 are turned off and Q1 and Q3 are turned on. The negative peak current limit set point IOCPPN can be calculated by Equation 17.

The device can be damaged in negative peak current limit conditions. In these conditions, the energy flows from output to input. If the impedance of the input source or devices is not low enough, the VIN voltage increases. When VIN increases to higher than its maximum limit, the IC can be damaged.

5.4 Overvoltage ProtectionThe overvoltage set point is set at 114% of the nominal output voltage set by the feedback resistors. In the case of an overvoltage event, the IC attempts to bring the output voltage back into regulation by keeping Q1 and Q3 turned off and Q2 and Q4 turned on. If the OV condition continues, the inductor current goes negative to trip the negative peak current limit. The converter reverses direction to transfer energy from the output end to the input end. Input voltage is pushed high if the input source impedance is not low enough. The IC may be damaged if the input voltage goes to higher than its maximum limit. If the overvoltage condition is corrected and the output voltage drops to the nominal voltage, the controller resumes work in normal PWM switching.

5.5 Over-Temperature ProtectionThe ISL81401 and ISL81401A incorporate an over-temperature protection circuit that shuts the IC down when a die temperature of +160°C is reached. Normal operation resumes when the die temperature drops below +145°C through the initiation of a full soft-start cycle. During OTP shutdown, the IC consumes only 100µA current. When the controller is disabled, thermal protection is inactive. This helps achieve a very low shutdown current of 5µA.

IOCPP2

VOCSET-CS-HICRS_IN

--------------------------------------------=(EQ. 16)

IOCPPN

VOCSET-ISENRISEN

--------------------------------------=(EQ. 17)

FN9310 Rev.0.00 Page 40 of 47Sep 11, 2018

ISL81401, ISL81401A 6. Layout Guidelines

6. Layout GuidelinesCareful attention to layout requirements is necessary for successful implementation of ISL81401 and ISL81401A based DC/DC converters. The ISL81401 and ISL81401A switch at a very high frequency, so the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in an extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and ringing. Careful component selection and proper Printed Circuit Board (PCB) layout minimize the magnitude of these voltage spikes.

The three sets of critical components in a DC/DC converter using the ISL81401 and ISL81401A are the following:

• the controller

• the switching power components

• the small signal components

The switching power components are the most critical from a layout point of view because they switch a large amount of energy, which tends to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.

6.1 Layout Considerations(1) Place the input capacitors, buck FETs, inductor, boost FETs, and output capacitor first. Isolate these power

components on dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output high frequency decoupling ceramic capacitors very close to the MOSFETs.

(2) If signal components and the IC are placed in a separate area to the power train, use full ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise, use separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND together close to the IC. DO NOT connect them together anywhere else.

(3) Keep the loop formed by the input capacitor, the buck top FET, and the buck bottom FET as small as possible. Keep the loop formed by the output capacitor, the boost top FET, and the boost bottom FET as small as possible.

(4) Ensure the current paths from the input capacitor to the buck FETs, the power inductor, the boost FETs, and the output capacitor are as short as possible with maximum allowable trace widths.

(5) Place the PWM controller IC close to the lower FETs. The low side FETs gate drive connections should be short and wide. Place the IC over a quiet ground area. Avoid switching ground loop currents in this area.

(6) Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND pin. Connect the PGND pin to the ground plane by a via. Do not directly connect the PGND pin to the SGND EPAD.

(7) Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.

(8) Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output capacitors to load to avoid inductance and resistances.

(9) Use copper filled polygons or wide short traces to connect the junction of the buck or boost upper FET, buck or boost lower FET, and output inductor. Also keep the buck and boost PHASE nodes connection to the IC short. DO NOT oversize the copper islands for the PHASE nodes. Because the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.

(10) Route all high speed switching nodes away from the control circuitry.

(11) Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths including feedback resistors, current monitoring resistors and capacitors, soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors should be connected to this SGND plane.

FN9310 Rev.0.00 Page 41 of 47Sep 11, 2018

ISL81401, ISL81401A 6. Layout Guidelines

(12) Use a pair of traces with minimum loop for the input or output current sensing connection.

(13) Ensure the feedback connection to the output capacitor is short and direct.

6.2 General EPAD Design ConsiderationsFigure 54 illustrates how to use vias to remove heat from the IC.

Fill the thermal pad area with vias. A typical via array fills the thermal pad footprint so that their centers are three times the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow.

Connect all vias to the ground plane. The vias must have a low thermal resistance for efficient heat transfer. Ensure a complete connection of the plated through hole to each plane.

Figure 54. PCB Via Pattern

FN9310 Rev.0.00 Page 42 of 47Sep 11, 2018

ISL81401, ISL81401A 7. Component Selection Guideline

7. Component Selection Guideline

7.1 MOSFET ConsiderationsThe MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirement. Select these MOSFETs based upon rDS(ON), gate supply requirements, and thermal management considerations.

The buck MOSFETs’ maximum operation voltage is decided by the maximum VIN voltage, and the boost MOSFETs’ maximum operation voltage is decided by the maximum VOUT voltage. Choose the buck or boost MOSFETs based on their maximum operation voltage with sufficient margin for safe operation.

The MOSFETs’ power dissipation is based on conduction loss and switching loss. In Buck mode, the power loss of the buck upper and lower MOSFETs are calculated by Equations 18 and 19. The conduction losses are the main source of power dissipation for the lower MOSFET. Only the upper MOSFET has significant switching losses, because the lower device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the lower MOSFET’s body diode.

In Boost mode, there is only conduction loss on the buck upper MOSFET calculated by Equation 20.

In Boost mode, the boost upper and lower MOSFETs power loss are calculated by Equations 21 and 22. The conduction losses are the main component of power dissipation for the upper MOSFET. Only the lower MOSFET has significant switching losses, because the upper device turns on and off into near zero voltage. The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the upper MOSFET’s body diode.

In Buck mode, the conduction loss exists on the boost upper MOSFET calculated by Equation 23.

A large gate-charge increases the switching time, tSW, which increases the switching losses of the buck upper and boost lower MOSFETs. Ensure that all four MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications.

PUPPERBUCK

IOUT2 rDS ON VOUT

VIN-----------------------------------------------------------------------

IOUT VIN tSW fSW

2-----------------------------------------------------------------+=(EQ. 18)

PLOWERBUCK

IOUT2 rDS ON VIN VOUT–

VIN---------------------------------------------------------------------------------------=(EQ. 19)

PUPPERBUCK

IOUT2 VOUT

2

VIN2

---------------------------------------------- rDS ON =(EQ. 20)

PLOWERBOOST

IOUT2 VOUT

2

VIN2

----------------------------------------------VOUT VIN– rDS ON

VOUT-----------------------------------------------------------------

IOUT VOUT2 tSW fSW

2 VIN ---------------------------------------------------------------------------+=(EQ. 21)

PUPPERBOOST

IOUT2 rDS ON VOUT

VIN-----------------------------------------------------------------------=

(EQ. 22)

PUPPERBOOST IOUT2 rDS ON =(EQ. 23)

FN9310 Rev.0.00 Page 43 of 47Sep 11, 2018


7.2 Inductor SelectionThe inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current, and the ripple voltage is a function of the ripple current and the output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 24 for Buck mode and Equation 25 for Boost mode.

The ripple current ratio is usually 30% to 70% of the inductor average current at the full output load condition.

7.3 Output Capacitor SelectionIn general, select the output capacitors to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the inductor, so some inductor analysis is required to select the output capacitors.

One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to its new level. The ISL81401 and ISL81401A provide either 0% or maximum duty cycle in response to a load transient.

The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor.

The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is shown in Equation 26 for Buck mode and Equation 27 for Boost mode:

where COUT is the output capacitor(s) required, L is the inductor, ITRAN is the transient load current step, VIN is the input voltage, VOUT is output voltage, and DVOUT is the drop in output voltage allowed during the load transient.

High frequency capacitors initially supply the transient current and slow the load rate of change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the Equivalent Series Resistance (ESR) and voltage rating requirements as well as actual capacitance requirements.

In Buck mode, the output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by Equation 28:

where ILBuck is calculated in Equation 24.

ILBuck

VIN VOUT– VOUT

fSW L VIN ----------------------------------------------------------=(EQ. 24)

ILBoost

VOUT VIN– VIN

fSW L VOUT ----------------------------------------------------=(EQ. 25)

COUTBuck

L ITRAN 2

2 VIN VOUT– DVOUT ------------------------------------------------------------------=(EQ. 26)

COUTBoost

L VOUT ITRAN 2

2 VIN2 DVOUT

-------------------------------------------------------=(EQ. 27)

VRIPPLE ILBuck ESR =(EQ. 28)

FN9310 Rev.0.00 Page 44 of 47Sep 11, 2018


In Boost mode, the current to the output capacitor is not continuous. The output voltage ripple is much higher as defined by Equation 29:

where ILBoost is calculated in Equation 25 on page 43.

Place high frequency decoupling capacitors as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements.

Use only specialized low-ESR capacitors intended for switching regulator applications for the bulk capacitors. In most cases, multiple small case electrolytic capacitors perform better than a single large case capacitor.

The stability requirement on the selection of the output capacitor is that the ESR zero (fZ) is between 2kHz and 60kHz. The ESR zero can help increase phase margin of the control loop.

This requirement is shown in Equation 30:

In conclusion, the output capacitors must meet the following criteria:

• They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient.

• The ESR must be sufficiently low to meet the desired output voltage ripple due to the supplied ripple current.

• The ESR zero should be placed in a large range to provide additional phase margin.

7.4 Input Capacitor Selection The important parameters for the input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. In Buck mode the AC RMS input current varies with the load giving in Equation 31:

where DC is duty cycle.

The maximum RMS current supplied by the input capacitance occurs at VIN = 2 X VOUT, DC = 50% as shown in Equation 32:

In Boost mode, the input current is continuous. The RMS current supplied by the input capacitance is much smaller.

Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the MOSFETs to suppress the voltage induced in the parasitic circuit impedances.

Solid tantalum capacitors can be used, but use caution with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up.

VRIPPLE

IOUT VOUT

VIN----------------------------------------

ILBoost2

------------------------+

ESR =(EQ. 29)

COUT1

2 ESR fZ ------------------------------------=(EQ. 30)

IRMS DC DC2

– IOUT=(EQ. 31)

IRMS12--- IOUT=(EQ. 32)

FN9310 Rev.0.00 Page 45 of 47Sep 11, 2018

ISL81401, ISL81401A 8. Revision History

8. Revision History


0.00 Sep 11, 2018 Initial release

FN9310 Rev.0.00 Page 46 of 47Sep 11, 2018

ISL81401, ISL81401A 9. Package Outline Drawing

9. Package Outline DrawingL32.5x5B32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGERev 3, 5/10

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

6.

either a mold or mark feature.

3.

5.

4.

2.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW


TOP VIEW

5.00 A

5.0

0

B

INDEX AREAPIN 1

6

(4X) 0.15

32X 0.40 ± 0.10 4

A

32X 0.23

M0.10 C B16 9

4X

0.5028X

3.5

6PIN #1 INDEX AREA

3 .30 ± 0 . 15

0 . 90 ± 0.1BASE PLANE

SEE DETAIL "X"

SEATING PLANE

0.10 CC

0.08 C

0 . 2 REFC

0 . 05 MAX.0 . 00 MIN.

5

( 3. 30 )

( 4. 80 TYP )( 28X 0 . 5 )

(32X 0 . 23 )

( 32X 0 . 60)

+ 0.07

- 0.05

17

25

24

8

1

32

For the most recent package outline drawing, see L32.5x5B.

https://www.renesas.com/package-image/pdf/outdrawing/l32.5x5b.pdf

http://www.renesas.comRefer to "http://www.renesas.com/" for the latest and detailed information.

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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

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