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Intro to IEEE 1149.1 Boundary-Scan (JTAG) David Lavo [email protected] UC Santa Cruz January 27, 2005

Jtag Intro

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Page 1: Jtag Intro

Intro to IEEE 1149.1 Boundary-Scan (JTAG)

David Lavo

[email protected]

UC Santa Cruz

January 27, 2005

Page 2: Jtag Intro

© David Lavo Intro To Boundary-Scan 2

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

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© David Lavo Intro To Boundary-Scan 3

IEEE 1149.1 Boundary-Scan • Facilitates board testing• Provides an on-chip means of controlling

and testing pads• Boundary-scan components can also be

used for other test purposes:– Logic and RAM BIST control– Scan chain control– Scan wrapper config., test modes, etc.

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© David Lavo Intro To Boundary-Scan 4

Board Test

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Pad & Parametric Test

• 1149.1 can be used to control and exercise pads independent of the chip core

• Leakage on tri-state outputs• Measure voltage and current for output

pads driving 0 or 1• Test logic levels captured by input pads

at various voltages

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© David Lavo Intro To Boundary-Scan 6

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

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© David Lavo Intro To Boundary-Scan 7

1149.1 Hardware• Test Access Port: 5 pins

• TAP Controller– Finite State Machine– Internal registers (Bypass, Instruction, etc.)– Test control logic

• Boundary-Scan Register Chain

• Internal Data Registers (Optional)

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Boundary-Scan Components

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

I

O

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TAP Controller Components

TDI

TMS

TCK

TRST_N

TDO

Various TAP

Outputs:UpdateDR,CaptureDR,

TriState,Etc.

FiniteState

Machine

Instruction Register

Bypass Reg.

InstructionDecode

SOSI

Page 10: Jtag Intro

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0101

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BYPASS Instruction

• A mandatory instruction• The default instruction for TAPs with no

IDCODE register• Short scan path: 1 bit between TDI and

TDO• Usually loaded in chips that are idle

while other chips on the board are being tested

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BYPASS Data Path

TDI

TMS

TCK

TRST_N

TDO

FiniteState

Machine

Instruction Register

InstructionDecode

SOSI

Bypass Reg.

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EXTEST & SAMPLE/PRELOAD• EXTEST is the “workhorse” JTAG instruction

– Sample (“Capture”) & Drive (“Update”) output signals

– Sample & optionally drive input signals

• Data is first loaded into boundary register chain with SAMPLE/PRELOAD instruction– Samples inputs and outputs, pass-through– Loads boundary register with data

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SAMPLE/PRELOAD

SAMPLE/PRELOAD: Start

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

BYPASS

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TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0101

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Instruction Register Data Path

TDI

TMS

TCK

TRST_N

TDO

FiniteState

Machine

InstructionDecode

SOSI

Bypass Reg.

Instruction Register

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TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

0

0

1

0

1

1

1

0

1

0

0

0101

Exit2-IR

Update-IR

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© David Lavo Intro To Boundary-Scan 18

SAMPLE/PRELOAD

SAMPLE/PRELOAD: UpdateIR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

BYPASS SMP/PRLD

DATA

Page 19: Jtag Intro

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101Update-IR

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SAMPLE/PRELOAD: CaptureDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

SMP/PRLD

DATAMode=0

Capture (sample)

0 1 0 1

0 1 0 1

0

1

0

Page 21: Jtag Intro

Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101

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SAMPLE/PRELOAD: ShiftDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

SMP/PRLD

DATA0 1 0 11 0 1 0

0 1 0 1

1

0

0

01011010

0

1

1

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Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101

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© David Lavo Intro To Boundary-Scan 24

SAMPLE/PRELOAD: UpdateDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

SMP/PRLD

1 0 1 0

0101

0

1

1

Mode=0

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TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

0

0

1

0

1

1

1

0

1

0

0

0101Update-DR

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EXTEST: UpdateIR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

1 0 1 0

0101

0

1

1

EXTEST

EXTEST

Mode=1

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Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101Update-IR

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© David Lavo Intro To Boundary-Scan 28

DATA

EXTEST: CaptureDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

1 0 1 0

0101

0

1

1 EXTEST

1

1

1

1 1 1 1

Capture (sample)

1 1 1 1

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Update-DR

Exit2-DR

Pause-DR

Exit1-DR

Shift-DR

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101

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DATA

EXTEST: ShiftDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

EXTEST

1 1 1 10 0 0 0

1

1

1

0

0

0

1111 00001111

Page 31: Jtag Intro

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Capture-IR

TAP Controller State Diagram

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

0

0

1

0

1

1

Test-Logic-Reset

Run-Test/Idle

0

1

0

1

0

1

0

0

Select-IR-Scan

0

0

1

0

1

1

1

0

1

0

0

0101

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© David Lavo Intro To Boundary-Scan 32

EXTEST: UpdateDR

ChipCore

TAPController

TDI

TMS

TCK

TDO

TRST_N

DATA0 0 0 0

0000

0

0

0 EXTEST

Mode=1

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© David Lavo Intro To Boundary-Scan 33

Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

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Boundary-Scan Documentation• IEEE Standard:

– IEEE Std 1149.1-1990 & 1149.1a-1993: “IEEE Standard Test Access Port and Boundary-Scan Architecture”

– IEEE Std 1149.1b-1994: “Supplement to IEEE Std 1149.1-1990 ….” (BDSL)

– IEEE Std 1149.1-2001

• “The Boundary-Scan Handbook”, Second Edition (1998), by Ken Parker

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Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

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© David Lavo Intro To Boundary-Scan 36

Why JTAG is Cool

• Adds a lot of test functionality with a small amount of effort– Board test– Pad/parametric test– Enhanced debug and diagnosis– Control of TAP-based tests (BIST, clocks)

• Functionally simple• Ultra low performance: 5 to 10 MHz!

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Lots of Uses Besides Board Test

• On-chip access to BIST, programmable logic & EEPROMs, system and circuit test

• System configuration & maintenance:

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Why JTAG is a Pain

• Messes with chip timing!

• Complicates placement and routing

• Obtuse rules, motivations, language and documentation

• Requires some manual data entry or massaging

• No automated debugging tools

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1149.1 Timing Impact

• JTAG adds a mux, and sometimes a gate, into the data path– Insert JTAG early in design process!

• The impact can be reduced to just a load by using a “read-only” cell– Intended only for clocks and other sensitive

inputs– Some test capability is lost

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JTAG Input Cell/Macro

I

IEN

CoreLogic

SI

I

IEN

ShiftDR

CK1

CaptureDR

L L

SO

CK2

L

UpdateDR Jtag2Core

Data PathCapture

PathScan PathUpdate Path

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JTAG Read-Only Input Cell/Macro

I

IEN

CoreLogic

SI

I

ShiftDR

CK1

CaptureDR

L L

SO

CK2

Data PathCapture

PathScan PathUpdate Path

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© David Lavo Intro To Boundary-Scan 42

JTAG Output Cell/Macro

O

CoreLogic

SI

O

ShiftDR

CK1

CaptureDR

L L

SO

CK2

L

UpdateDR Jtag2Pad

Data PathCapture

PathScan PathUpdate Path

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JTAG Output-Enable Cell/Macro

OEN Core Logic

SI

OEN

ShiftDR

CK1

CaptureDR

L L

SO

CK2

L

UpdateDR

Jtag2Pad

TriState

PullDisable

PUEN PUEN

Data PathCapture

PathScan PathUpdate Path

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1149.1 Place & Route Impact

• Boundary-scan register cells should be placed near associated pads– Best location is routing track next to pads– Avoid long wires from registers to pads

• TAP signals can cause routing congestion– From 3 to 5 global signals from TAP to each

boundary-register cell (all around chip)– Need to budget for this early

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Placement of Boundary Registers

Core

Bad

Good

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© David Lavo Intro To Boundary-Scan 46

Global Routing Congestion

I

IEN

Input Pad

O

OEN

Output PadCoreLogic

SO

SI

I

IEN

O

OEN

SI

SO

Boundary Scan Chain

TAPController

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Outline

• What is 1149.1?

• 1149.1 Basics

• Documentation & Resources

• 1149.1 for the Designer

• Extended Uses for the TAP Controller

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© David Lavo Intro To Boundary-Scan 48

Beyond Board-Test: Extending the TAP Controller

• The TAP Controller runs the show for boundary-scan and other TAP-based tests

• Some TAP-based test functions have become increasingly complex & specialized– Test signal control – BIST control and capture– Scan shifting

• Most functions are based on TAP registers

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Static Register: IDCODE

• 32 Bits predefined in internal register:– Version (4 bits)– Part Number (16 bits)– Manufacturer (11 bits)– LSB is set to 1

• Scan out through TDO during IDCODE instruction

0

TDI

TDO

V P M 1

Instruction:

1010

BYPASSIDCODE

10100

VPM

1

XXXX

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Update-Only: User Register

• General-purpose bits• User defines and

connects signals• Scan in a value

(through TDI) to set• Used for test modes,

configurable logic, etc.• No capture capability

TDI

TDO

0 0 0 0

Instruction: SELUSER

0000

TAP State: UpdateDR

1 0 1 1

1011

0000

1011

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1 1 1 1

Capture/Update Register: RAMBIST

• Capture and update capability

• User-defined signals:– Drive RAMBIST enable– Read RAMBIST results

• Scan in a value (through TDI) to set

• Scan out results through TDO

TDI

TDO

Instruction:SELRAMBIST

TAP State:

1 1 1 01 0 1 X

R0

R1

R2

R3X4

ScanDRUpdateDRRUNRAMBIST

R1

R2

R3

RunTest

R1

R2

R3101X

1110

CaptureDRScanDR