Kia Adders

Fall 2008 EE 5323 - VLSI Design I - © Kia Bazargan 1

EE 5323 – VLSI Design IEE 5323 – VLSI Design I

Kia Bazargan

University of Minnesota

AddersAdders


References and Copyright

• Textbooks referenced [WE92] N. H. E. Weste, K. Eshraghian

“Principles of CMOS VLSI Design: A System Perspective”Addison-Wesley, 2nd Ed., 1992.

[Rab96] J. M. Rabaey“Digital Integrated Circuits: A Design Perspective”Prentice Hall, 1996.

[Par00] B. Parhami“Computer Arithmetic: Algorithms and Hardware Designs”Oxford University Press, 2000.


References and Copyright (cont.)

• Slides used [©Hauck] © Scott A. Hauck, 1996-2000;

G. Borriello, C. Ebeling, S. Burns, 1995, University of Washington

[©Prentice Hall] © Prentice Hall 1995, © UCB 1996

Slides for [Rab96] http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html

[©Oxford U Press] © Oxford University Press, New York, 2000 Slides for [Par00] With permission from the authorhttp://www.ece.ucsb.edu/Faculty/Parhami/files_n_docs.htm


Why Adders?

• Addition: a fundamental operation Basic block of most arithmetic operations Address calculation

• Faster, faster and faster• How?

Architectural level optimization Gate-level optimization Speed/area trade-off


Outline

• One-bit adder, basic ripple-carry

adder

• Carry-Lookahead adders (CLA)

• Brent-Kung adder


• One-bit Half Adder:

• One-bit Full Adder:

Adding Two One-bit Operands

Sum = A B Cin

Cout = A.B + B.Cin + A.Cin

FA

A B

CinCout

Sum

Sum = A B

Cout = A.BHA

A B

Cout

Sum

A B Sum Cout0 0 0 00 1 1 01 0 1 01 1 0 1

Cin A B Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1


N-Bit Ripple-Carry Adder: Series of FA Cells

• To add two n-bit numbers

C0FA

A0

S0

B0

FA

A1

S1

B1

FA

A2

S2

B2

FA

An-1

Sn-1

Bn-1

Cn. . .

• Note: adder delay = Tc * n

• Tc = (Cin:Cout delay)FA

A B

CinCout

Sum


4-bit Ripple Carry Addition: Example

C0FA

A0

S0

B0

FA

A1

S1

B1

FA

A2

S2

B2

FA

A3

S3

B3

C4 C1C2C3

T=1 00 10 10 01

00 10 01 11

0

00 00 00 00T=0

B=0101

A=0011

S=0000

S=0110

00 10 01 01T=2 S=0100

00 01 01 01T=3 S=0000

10 01 01 01T=4 S=1000


One-bit Full Adder Implementation

• Direct gate implementation

Cout = A.B + B.Cin + A.Cin = A.B + Cin. (A+B)

Sum = A B Cin

AB

CinSum

AB

AB

Cin Cout

32 Transistors Used32 Transistors Used

[WE92] p516


includes 111

excludes 000

One-Bit Full Adder: Share Logic

• An observation Almost always,

sum = NOT carry

Cin A B Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Sum = A.B.Cin + (A+B+Cin).Cout


One-Bit Full Adder: Transistor Implementation

Sum = A.B.C + (A+B+C).CoutCout = A.B + C.(A+B)

A B B

AC

ABA B

C

Cout

C B AABC

CBACBA

Sum

– Use inverters to get Cout and Sum– C transistors close to output– Cout delay: 2 inverting stages (1-stage

possible?)– Sum delay: 3 inverting stages (not an issue,

though)

28 Transistors28 Transistors28 Transistors28 Transistors

[WE92] p517[Rab96] p390


Outline


adder

•Carry-Lookahead adders

(CLA)

• Brent-Kung adder


Carry-Lookahead Adder: Idea

• New look: carry propagation• Idea:

Try to “predict” Ck earlier than Tc*k Instead of passing through k stages, compute

Ck separately using 1-stage CMOS logic

• Carry propagation: an example

Bit position

Carry

A B

Sum

7 6 5 4 3 2 1 0

1 0 0 1 1 1 1

0 1 0 0 1 1 0 1 +0 1 0 0 0 1 1 1

1 0 0 1 0 1 0 0


0-propagate

1-propagate generate

kill

(kill) (propagate) (propagate) (generate)

Carry-Lookahead Adder (CLA): One Bit

• What happens to thepropagating carry inbit position k? 0 0 - 0

0 1 C C 1 0 C C 1 1 - 1

C

A

A

B

BA

A

B

BCout

[Rab96] p391

p = A+B (or A B)

g = A.B

A B Cin Cout


CLA: Propagation Equations

• If C4=1, then either: g3 generated at bit pos 3

g2.p3 generated at bit pos 2, propagated 3

g1.p2.p3 generated at bit pos 1, propagated 2,3

g0.p1.p2.p3 generated at bit pos 0, propagated 1,2,3

Cin.p0.p1.p2.p3 input carry, propagated 0,1,2,3

• C4 = g3+ g2.p3 + g1.p2.p3 + g0.p1.p2.p3 + Cin.p0.p1.p2.p3

Implement Implement CC44 as a one-stage CMOS logic as a one-stage CMOS logic

large delay large delay

Implement Implement CC44 as a one-stage CMOS logic as a one-stage CMOS logic

large delay large delay


CLA: 12-Bit Example

p,g p,g p,g p,g

S0S1S2S3S4S5S6S7

p,g p,g p,g p,g

B0B1B2B3B5B6B7 B4

C0

C4

Carry Generator Carry Generator

C8

S8S9S10S11

p,g p,g p,g p,g

B9B10

A0A1A2A3A4A5A6A7A8A9A10A11B11 B8

Carry Generator

C12

00000 00000 00000T=0

01111101

01101001

11011010

0

B=A=

01001 11110 01111T=201001 00001 01111T=301011 00001 01111T=4


Summary: Carry Lookahead Adder

• CLA compared to ripple-carry adder: Faster (“4 times”?),

but delay still linear (w.r.t. # of bits) Larger area

o P, G signal generationo Carry generation circuitso Carry generation ckt for each bit position (no re-use)

• Limitation: cannot go beyond 4 bits of look-ahead Large p,g fan-out slows down carry generation


Outline


adder

• Carry-Lookahead adders (CLA)

•Brent-Kung adder


Binary Carry-Lookahead or Brent-Kung Adder

• Idea: use binary tree for carry propagation logarithmic delay

A7

F

A6A5A4A3A2A1

A0

A0A1A2A3A4A5A6A7

F

tp log2(N)

tp N

[© Prentice Hall]


Brent-Kung Adder

• Basic component

Concatenation

MSB LSB

gleft pleft gright pright

g p

(g, p)

g = gleft + pleft • gright

p = pleft • pright

(gleft, pleft) (gright pright)

[©Hauck]


No! Doesn’t know aboutC0-3 yet!

C5?

Brent-Kung Adder: Structure• Define (Gi, Pi)

generate and propagate for least significant i bits(G0,P0) = (g0,p0) gi = Ai.Bi pi = AiBi

for i>0: (Gi, Pi) = (gi, pi) • (Gi-1, Pi-1)

= (gi, pi) • (gi-1, pi-1) • . . . . • (g1, p1)

• Key to Brent-Kung adder – use tree structure to perform concatenations

7 6 5 4 3 2 1 0

7-6 5-4 3-2 1-0

7-4 3-0

7-0 [©Hauck]


Brent-Kung: the Complete Tree

tadd log2 (N) [© Prentice Hall]

(g0 ,p0)(g1 ,p1)

(g2 ,p2)

(g3 ,p3)

(g4 ,p4)

(g5 ,p5)

(g6 ,p6)

(g7 ,p7)

C0C1

C3

C7

C2

C6

C5

C4


Brent-Kung: Timing

[©Oxford U Press][Par00] p.102

x0x1x2x3x4x5x6x7x8x9x10x11

x12x13x14x15

s0s1s2s3s4s5s6s7s8s9s10s11s12s13s14s15

1

2

3

4

5

6

Level


Brent-Kung Adder: Summary

• Area On average, twice as large as ripple adder Layout of the cells is very compact

• Delay Logarithmic time Once carry signals are ready,

sum bits derived in const time Good for wide adders

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