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Kinetis KM35 Sub-Family Reference Manual Supports: MKM35Z256VLL7, MKM35Z256VLQ7, MKM35Z512VLL7, MKM35Z512VLQ7, MKM35Z256VLL7R, MKM35Z256VLQ7R, MKM35Z512VLL7R, MKM35Z512VLQ7R Document Number: KM35P144M75SF0RM Rev. 2, 03/2020

Kinetis KM35 Sub-Family Reference Manual...Kinetis KM35 Sub-Family Reference Manual Supports: MKM35Z256VLL7, MKM35Z256VLQ7, MKM35Z512VLL7, MKM35Z512VLQ7, MKM35Z256VLL7R, MKM35Z256VLQ7R,

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  • Kinetis KM35 Sub-Family ReferenceManual

    Supports: MKM35Z256VLL7, MKM35Z256VLQ7, MKM35Z512VLL7,MKM35Z512VLQ7, MKM35Z256VLL7R, MKM35Z256VLQ7R,

    MKM35Z512VLL7R, MKM35Z512VLQ7R

    Document Number: KM35P144M75SF0RMRev. 2, 03/2020

  • Kinetis KM35 Sub-Family Reference Manual, Rev. 2, 03/2020

    2 NXP Semiconductors

  • Contents

    Section number Title Page

    Chapter 1About This Document

    1.1 Overview.......................................................................................................................................................................47

    1.1.1 Purpose.........................................................................................................................................................47

    1.1.2 Audience...................................................................................................................................................... 47

    1.2 Conventions.................................................................................................................................................................. 47

    1.2.1 Numbering systems......................................................................................................................................47

    1.2.2 Typographic notation................................................................................................................................... 48

    1.2.3 Special terms................................................................................................................................................ 48

    Chapter 2Introduction

    2.1 KM35 introduction........................................................................................................................................................49

    2.2 Detailed block diagram................................................................................................................................................. 49

    2.3 KM35 feature set...........................................................................................................................................................50

    2.4 Device configuration.....................................................................................................................................................53

    2.4.1 Supported Packages..................................................................................................................................... 54

    2.5 Modules on the device.................................................................................................................................................. 55

    2.5.1 Core modules............................................................................................................................................... 55

    2.5.2 System modules........................................................................................................................................... 56

    2.5.3 Clock............................................................................................................................................................ 58

    2.5.4 Security modules..........................................................................................................................................59

    2.5.5 Analog modules........................................................................................................................................... 59

    2.5.6 Timer modules............................................................................................................................................. 61

    2.5.7 Communication interfaces........................................................................................................................... 62

    2.5.8 Human-machine interfaces.......................................................................................................................... 63

    Chapter 3Core Overview

    3.1 Introduction...................................................................................................................................................................65

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    3.1.1 Buses, interconnects, and interfaces............................................................................................................ 65

    3.1.2 System Tick Timer.......................................................................................................................................65

    3.1.3 Debug facilities............................................................................................................................................ 66

    3.1.4 Core privilege levels.................................................................................................................................... 66

    3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................66

    3.2.1 Interrupt priority levels................................................................................................................................ 66

    3.2.2 Non-maskable interrupt................................................................................................................................66

    3.2.3 Interrupt Channel Assignments....................................................................................................................67

    3.3 AWIC introduction....................................................................................................................................................... 69

    3.3.1 Wake-up sources.......................................................................................................................................... 69

    Chapter 4System Memory Map

    4.1 Introduction...................................................................................................................................................................71

    4.2 System Memory Map....................................................................................................................................................71

    4.3 Flash Memory Map.......................................................................................................................................................72

    4.4 SRAM memory map.....................................................................................................................................................72

    4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................73

    4.6 AIPS peripheral slot assignment...................................................................................................................................74

    4.7 Private peripherals........................................................................................................................................................ 77

    4.8 Private Peripheral Bus (PPB) memory map..................................................................................................................78

    4.8.1 GPIO accessibility in the memory map....................................................................................................... 78

    Chapter 5Clock Distribution

    5.1 Introduction...................................................................................................................................................................81

    5.2 High-level clocking diagram.........................................................................................................................................81

    5.3 Clock definitions...........................................................................................................................................................83

    5.3.1 Device clock summary.................................................................................................................................84

    5.4 Internal clocking requirements..................................................................................................................................... 85

    5.4.1 Clock divider values after reset....................................................................................................................85

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    5.4.2 VLPR mode clocking...................................................................................................................................86

    5.4.3 Enable PLL in VLPR or VLPR and PSTOP1 .............................................................................................86

    5.5 Clock Gating................................................................................................................................................................. 88

    5.6 Module clocks...............................................................................................................................................................88

    Chapter 6Reset and Boot

    6.1 Reset..............................................................................................................................................................................91

    6.1.1 System resets and sources............................................................................................................................ 91

    6.2 Boot...............................................................................................................................................................................95

    6.2.1 Boot sources.................................................................................................................................................95

    6.2.2 Boot options................................................................................................................................................. 95

    6.2.3 FOPT boot options....................................................................................................................................... 95

    6.2.4 Boot sequence.............................................................................................................................................. 96

    Chapter 7Power Management

    7.1 Introduction...................................................................................................................................................................99

    7.2 Power Modes................................................................................................................................................................ 99

    7.3 Entering and exiting power modes............................................................................................................................... 101

    7.4 Power mode transitions.................................................................................................................................................101

    7.5 Power modes shutdown sequencing............................................................................................................................. 102

    7.6 Module Operation in Low Power Modes......................................................................................................................103

    7.7 Clocking modes............................................................................................................................................................ 106

    7.7.1 Partial Stop...................................................................................................................................................106

    7.7.2 DMA Wakeup.............................................................................................................................................. 107

    7.7.3 Compute Operation...................................................................................................................................... 108

    7.7.4 Peripheral Doze............................................................................................................................................109

    7.8 Clock Gating................................................................................................................................................................. 110

    Chapter 8Security

    8.1 Introduction...................................................................................................................................................................111

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    8.2 External Watchdog Monitor......................................................................................................................................... 111

    8.2.1 EWM counter...............................................................................................................................................111

    8.2.2 EWM_out signal.......................................................................................................................................... 112

    8.2.3 EWM_in signal............................................................................................................................................ 112

    8.3 Robust Watchdog for Improved System Reliability.....................................................................................................113

    8.3.1 32-bit programmable timeout Period........................................................................................................... 113

    8.3.2 Independent Clock Source........................................................................................................................... 114

    8.3.3 Write Protection........................................................................................................................................... 114

    8.3.4 Robust Refresh Mechanism......................................................................................................................... 116

    8.3.5 Windowed Refresh.......................................................................................................................................116

    8.3.6 Fast Response to Code Runaway................................................................................................................. 116

    8.4 Watchdog configuration................................................................................................................................................118

    8.5 iRTC Write Protect State Machine............................................................................................................................... 118

    8.6 iRTC Tamper Detection Mechanism............................................................................................................................ 119

    8.6.1 Internal Tamper Condition 1: Battery removed when MCU is powered OFF............................................ 119

    8.6.2 Internal Tamper Condition 2: Battery removed when MCU is powered ON..............................................119

    8.6.3 External Tamper Condition: Off Chip Tamper Indication...........................................................................120

    8.6.4 Tamper Detection Flow............................................................................................................................... 120

    Chapter 9Debug

    9.1 Introduction...................................................................................................................................................................123

    9.2 Debug port pin descriptions..........................................................................................................................................123

    9.3 SWD status and control registers..................................................................................................................................124

    9.3.1 MDM-AP Control Register..........................................................................................................................125

    9.3.2 MDM-AP Status Register............................................................................................................................ 126

    9.4 Debug resets..................................................................................................................................................................128

    9.5 Micro Trace Buffer (MTB) ..........................................................................................................................................128

    9.6 Debug in low-power modes.......................................................................................................................................... 129

    9.7 Debug and security....................................................................................................................................................... 129

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    Chapter 10Signal Multiplexing and Pin Assignment

    10.1 Package Types.............................................................................................................................................................. 131

    10.2 Port control and interrupt module features................................................................................................................... 131

    10.3 KM35 Signal multiplexing and pin assignments..........................................................................................................133

    10.4 KM35 Pinouts............................................................................................................................................................... 140

    10.4.1 100-pin LQFP.............................................................................................................................................. 140

    10.4.2 144-pin LQFP.............................................................................................................................................. 141

    10.5 Module Signal Description Tables................................................................................................................................142

    10.5.1 Core Modules...............................................................................................................................................142

    10.5.2 System Modules...........................................................................................................................................143

    10.5.3 Clock Modules............................................................................................................................................. 144

    10.5.4 Analog..........................................................................................................................................................144

    10.5.5 Timer Modules.............................................................................................................................................145

    10.5.6 Communication Interfaces........................................................................................................................... 146

    10.5.7 Human-Machine Interfaces (HMI).............................................................................................................. 147

    Chapter 11Port Control and Interrupts

    11.1 Chip-specific PORT information..................................................................................................................................149

    11.1.1 Overview......................................................................................................................................................149

    11.1.2 Instantiation..................................................................................................................................................149

    11.1.3 PORT_PCRn register reset value.................................................................................................................149

    11.2 Introduction...................................................................................................................................................................150

    11.2.1 Overview......................................................................................................................................................150

    11.2.2 Features........................................................................................................................................................ 150

    11.2.3 Modes of operation...................................................................................................................................... 151

    11.3 External signal description............................................................................................................................................152

    11.4 Detailed signal description............................................................................................................................................152

    11.5 Memory map and register definition.............................................................................................................................152

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    11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................159

    11.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................. 161

    11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................162

    11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 162

    11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................163

    11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................164

    11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 164

    11.6 Functional description...................................................................................................................................................165

    11.6.1 Pin control.................................................................................................................................................... 165

    11.6.2 Global pin control........................................................................................................................................ 166

    11.6.3 External interrupts........................................................................................................................................166

    11.6.4 Digital filter..................................................................................................................................................167

    Chapter 12System Integration Module (SIM)

    12.1 Chip-specific SIM information.....................................................................................................................................169

    12.1.1 Instantiation..................................................................................................................................................169

    12.2 Introduction...................................................................................................................................................................169

    12.3 Features.........................................................................................................................................................................169

    12.4 Memory map and register definition.............................................................................................................................170

    12.4.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 171

    12.4.2 SOPT1 Configuration Register (SIM_SOPT1_CFG)..................................................................................172

    12.4.3 System Control Register (SIM_CTRL_REG)............................................................................................. 174

    12.4.4 System Device Identification Register (SIM_SDID)...................................................................................177

    12.4.5 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................179

    12.4.6 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................182

    12.4.7 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................185

    12.4.8 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................188

    12.4.9 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................189

    12.4.10 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 191

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    12.4.11 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 193

    12.4.12 Unique Identification Register High (SIM_UIDH)..................................................................................... 194

    12.4.13 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................194

    12.4.14 Unique Identification Register Mid-Low (SIM_UIDML)...........................................................................195

    12.4.15 Unique Identification Register Low (SIM_UIDL)...................................................................................... 195

    12.4.16 Miscellaneous Control Register (SIM_MISC_CTL)...................................................................................195

    12.4.17 ADC Compensation Register 0 (SIM_ADC_COMP0)............................................................................... 201

    12.4.18 ADC Compensation Register 1 (SIM_ADC_COMP1)............................................................................... 202

    12.5 Functional description...................................................................................................................................................202

    Chapter 13Inter-Peripheral Crossbar Switch (XBAR)

    13.1 Chip-specific XBAR information.................................................................................................................................203

    13.1.1 Overview......................................................................................................................................................203

    13.1.2 Instantiation Information..............................................................................................................................203

    13.1.3 Peripheral Interconnects...............................................................................................................................203

    13.2 Introduction...................................................................................................................................................................206

    13.2.1 Overview......................................................................................................................................................206

    13.2.2 Features........................................................................................................................................................ 206

    13.2.3 Modes of Operation..................................................................................................................................... 206

    13.2.4 Block Diagram............................................................................................................................................. 207

    13.3 Signal Descriptions....................................................................................................................................................... 207

    13.3.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs......................................................................................... 208

    13.3.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs.................................................................................................... 208

    13.3.3 DMA_REQ[n] - DMA Request Output(s)...................................................................................................208

    13.3.4 DMA_ACK[n] - DMA Acknowledge Input(s)............................................................................................208

    13.3.5 INT_REQ[n] - Interrupt Request Output(s).................................................................................................208

    13.4 Memory Map and Register Descriptions...................................................................................................................... 209

    13.4.1 Crossbar Select Register 0 (XBAR_SEL0)................................................................................................. 210

    13.4.2 Crossbar Select Register 1 (XBAR_SEL1)................................................................................................. 210

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    13.4.3 Crossbar Select Register 2 (XBAR_SEL2)................................................................................................. 211

    13.4.4 Crossbar Select Register 3 (XBAR_SEL3)................................................................................................. 211

    13.4.5 Crossbar Select Register 4 (XBAR_SEL4)................................................................................................. 212

    13.4.6 Crossbar Select Register 5 (XBAR_SEL5)................................................................................................. 212

    13.4.7 Crossbar Select Register 6 (XBAR_SEL6)................................................................................................. 213

    13.4.8 Crossbar Select Register 7 (XBAR_SEL7)................................................................................................. 213

    13.4.9 Crossbar Select Register 8 (XBAR_SEL8)................................................................................................. 214

    13.4.10 Crossbar Select Register 9 (XBAR_SEL9)................................................................................................. 214

    13.4.11 Crossbar Select Register 10 (XBAR_SEL10)............................................................................................. 215

    13.4.12 Crossbar Select Register 11 (XBAR_SEL11)............................................................................................. 215

    13.4.13 Crossbar Select Register 12 (XBAR_SEL12)............................................................................................. 216

    13.4.14 Crossbar Select Register 13 (XBAR_SEL13)............................................................................................. 216

    13.4.15 Crossbar Select Register 14 (XBAR_SEL14)............................................................................................. 217

    13.4.16 Crossbar Select Register 15 (XBAR_SEL15)............................................................................................. 217

    13.4.17 Crossbar Select Register 16 (XBAR_SEL16)............................................................................................. 218

    13.4.18 Crossbar Select Register 17 (XBAR_SEL17)............................................................................................. 218

    13.4.19 Crossbar Select Register 18 (XBAR_SEL18)............................................................................................. 219

    13.4.20 Crossbar Select Register 19 (XBAR_SEL19)............................................................................................. 219

    13.4.21 Crossbar Select Register 20 (XBAR_SEL20)............................................................................................. 220

    13.4.22 Crossbar Select Register 21 (XBAR_SEL21)............................................................................................. 220

    13.4.23 Crossbar Control Register 0 (XBAR_CTRL0)............................................................................................220

    13.4.24 Crossbar Control Register 1 (XBAR_CTRL1)............................................................................................223

    13.5 Functional Description..................................................................................................................................................225

    13.5.1 General......................................................................................................................................................... 225

    13.5.2 Functional Mode.......................................................................................................................................... 225

    13.6 Resets............................................................................................................................................................................ 225

    13.7 Clocks........................................................................................................................................................................... 226

    13.8 Interrupts and DMA Requests...................................................................................................................................... 226

    Chapter 14

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    Memory Mapped Arithmetic Unit (MMAU)

    14.1 Chip-specific MMAU information............................................................................................................................... 227

    14.1.1 Overview......................................................................................................................................................227

    14.1.2 Instantiation Information..............................................................................................................................227

    14.2 Introduction...................................................................................................................................................................227

    14.2.1 Features........................................................................................................................................................ 228

    14.2.2 Block diagram.............................................................................................................................................. 229

    14.2.3 Modes of operation...................................................................................................................................... 230

    14.3 External signal description............................................................................................................................................231

    14.4 Memory map and register definition.............................................................................................................................231

    14.4.1 Operand Register X0 (MMAU_X0)............................................................................................................ 232

    14.4.2 Operand Register X1 (MMAU_X1)............................................................................................................ 233

    14.4.3 Operand Register X2 (MMAU_X2)............................................................................................................ 233

    14.4.4 Operand Register X3 (MMAU_X3)............................................................................................................ 234

    14.4.5 Accumulator Register A0 (MMAU_A0)..................................................................................................... 235

    14.4.6 Accumulator Register A1 (MMAU_A1)..................................................................................................... 236

    14.4.7 Control/Status Register (MMAU_CSR)...................................................................................................... 237

    14.4.8 CSR Interrupt Flags Clearance Register (MMAU_CSR_IF_CLR).............................................................240

    14.4.9 MMAU register access in Busy State.......................................................................................................... 241

    14.5 Functional description...................................................................................................................................................242

    14.5.1 MMAU Programming Model...................................................................................................................... 242

    14.5.2 Numeric Types in MMAU...........................................................................................................................245

    14.5.3 MMAU Arithmetic Computation Description.............................................................................................248

    14.5.4 MMAU Software Interface.......................................................................................................................... 256

    Chapter 15System Mode Controller (SMC)

    15.1 Chip-specific SMC information....................................................................................................................................259

    15.1.1 Instantiation Information..............................................................................................................................259

    15.2 Introduction...................................................................................................................................................................259

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    15.3 Modes of operation....................................................................................................................................................... 260

    15.4 Memory map and register descriptions.........................................................................................................................261

    15.4.1 Power Mode Protection register (SMC_PMPROT).....................................................................................262

    15.4.2 Power Mode Control register (SMC_PMCTRL).........................................................................................263

    15.4.3 Stop Control Register (SMC_STOPCTRL).................................................................................................265

    15.4.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 266

    15.5 Functional description...................................................................................................................................................267

    15.5.1 Power mode transitions................................................................................................................................267

    15.5.2 Power mode entry/exit sequencing.............................................................................................................. 270

    15.5.3 Run modes....................................................................................................................................................272

    15.5.4 Wait modes.................................................................................................................................................. 274

    15.5.5 Stop modes...................................................................................................................................................275

    15.5.6 Debug in low power modes......................................................................................................................... 277

    Chapter 16Low-Leakage Wakeup Unit (LLWU)

    16.1 Chip-specific LLWU information.................................................................................................................................279

    16.1.1 Overview......................................................................................................................................................279

    16.1.2 Instantiation Information..............................................................................................................................279

    16.1.3 Wakeup Sources...........................................................................................................................................280

    16.1.4 Reset due to LLWU wakeup event.............................................................................................................. 281

    16.2 Introduction...................................................................................................................................................................281

    16.2.1 Features........................................................................................................................................................ 281

    16.2.2 Modes of operation...................................................................................................................................... 282

    16.2.3 Block diagram.............................................................................................................................................. 282

    16.3 LLWU signal descriptions............................................................................................................................................ 284

    16.4 Memory map/register definition................................................................................................................................... 284

    16.4.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................285

    16.4.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................286

    16.4.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................287

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    16.4.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................288

    16.4.5 LLWU Pin Enable 5 register (LLWU_PE5)................................................................................................290

    16.4.6 LLWU Pin Enable 6 register (LLWU_PE6)................................................................................................291

    16.4.7 LLWU Pin Enable 7 register (LLWU_PE7)................................................................................................292

    16.4.8 LLWU Pin Enable 8 register (LLWU_PE8)................................................................................................293

    16.4.9 LLWU Module Enable register (LLWU_ME)............................................................................................ 294

    16.4.10 LLWU Pin Flag 1 register (LLWU_PF1).................................................................................................... 296

    16.4.11 LLWU Pin Flag 2 register (LLWU_PF2).................................................................................................... 297

    16.4.12 LLWU Pin Flag 3 register (LLWU_PF3).................................................................................................... 299

    16.4.13 LLWU Pin Flag 4 register (LLWU_PF4).................................................................................................... 301

    16.4.14 LLWU Module Flag 5 register (LLWU_MF5)............................................................................................303

    16.4.15 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 304

    16.4.16 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 305

    16.4.17 LLWU Pin Filter 3 register (LLWU_FILT3).............................................................................................. 306

    16.4.18 LLWU Pin Filter 4 register (LLWU_FILT4).............................................................................................. 307

    16.5 Functional description...................................................................................................................................................308

    16.5.1 VLLS modes................................................................................................................................................ 309

    16.5.2 Initialization................................................................................................................................................. 309

    Chapter 17Power Management Controller (PMC)

    17.1 Chip-specific PMC information....................................................................................................................................311

    17.1.1 Instantiation Information..............................................................................................................................311

    17.2 Introduction...................................................................................................................................................................311

    17.3 Features.........................................................................................................................................................................311

    17.4 Low-voltage detect (LVD) system................................................................................................................................312

    17.4.1 LVD reset operation.....................................................................................................................................312

    17.4.2 LVD interrupt operation...............................................................................................................................312

    17.4.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 313

    17.5 I/O retention..................................................................................................................................................................313

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    17.6 Memory map and register descriptions.........................................................................................................................314

    17.6.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 314

    17.6.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 316

    17.6.3 Regulator Status And Control register (PMC_REGSC).............................................................................. 317

    Chapter 18Reset Control Module (RCM)

    18.1 Chip-specific RCM information................................................................................................................................... 319

    18.1.1 Instantiation Information..............................................................................................................................319

    18.2 Introduction...................................................................................................................................................................319

    18.3 Reset memory map and register descriptions............................................................................................................... 319

    18.3.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 320

    18.3.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 322

    18.3.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 323

    18.3.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 324

    18.3.5 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................325

    18.3.6 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................327

    Chapter 19Miscellaneous Control Module (MCM)

    19.1 Chip-specific MCM information.................................................................................................................................. 329

    19.1.1 Instantiation Information..............................................................................................................................329

    19.2 Introduction...................................................................................................................................................................329

    19.2.1 Features........................................................................................................................................................ 329

    19.3 Memory map/register descriptions............................................................................................................................... 330

    19.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................330

    19.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 331

    19.3.3 Platform Control Register (MCM_PLACR)................................................................................................331

    19.3.4 Process ID register (MCM_PID)................................................................................................................. 334

    19.3.5 Compute Operation Control Register (MCM_CPO)................................................................................... 335

    19.3.6 Master Attribute Configuration Register (MCM_MATCRn)......................................................................336

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    Chapter 20Bit Manipulation Engine (BME)

    20.1 Chip-specific BME information................................................................................................................................... 339

    20.1.1 Instantiation Information..............................................................................................................................339

    20.2 Introduction...................................................................................................................................................................339

    20.2.1 Overview......................................................................................................................................................340

    20.2.2 Features........................................................................................................................................................ 341

    20.2.3 Modes of operation...................................................................................................................................... 342

    20.3 Memory map and register definition.............................................................................................................................342

    20.4 Functional description...................................................................................................................................................342

    20.4.1 BME decorated stores.................................................................................................................................. 343

    20.4.2 BME decorated loads................................................................................................................................... 349

    20.4.3 Additional details on decorated addresses and GPIO accesses....................................................................355

    20.5 Application information................................................................................................................................................356

    Chapter 21Micro Trace Buffer (MTB)

    21.1 Chip-specific MTB information................................................................................................................................... 359

    21.1.1 Instantiation Information..............................................................................................................................359

    21.2 Introduction...................................................................................................................................................................359

    21.2.1 Overview......................................................................................................................................................360

    21.2.2 Features........................................................................................................................................................ 362

    21.2.3 Modes of operation...................................................................................................................................... 363

    21.3 External signal description............................................................................................................................................363

    21.4 Memory map and register definition.............................................................................................................................364

    21.4.1 MTB_RAM Memory Map...........................................................................................................................365

    21.4.2 MTB_DWT Memory Map...........................................................................................................................377

    21.4.3 System ROM Memory Map.........................................................................................................................387

    Chapter 22Crossbar Switch Lite (AXBS-Lite)

    22.1 Chip-specific AXBS-Lite information..........................................................................................................................393

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    22.1.1 Overview......................................................................................................................................................393

    22.1.2 Instantiation Information..............................................................................................................................394

    22.1.3 Crossbar Switch Master Assignments..........................................................................................................394

    22.1.4 Crossbar Switch Slave Assignments............................................................................................................394

    22.2 Introduction...................................................................................................................................................................395

    22.2.1 Features........................................................................................................................................................ 395

    22.3 Memory Map / Register Definition...............................................................................................................................395

    22.4 Functional Description..................................................................................................................................................396

    22.4.1 General operation.........................................................................................................................................396

    22.4.2 Arbitration....................................................................................................................................................396

    22.5 Initialization/application information........................................................................................................................... 398

    Chapter 23Peripheral Bridge (AIPS-Lite)

    23.1 Chip-specific AIPS-Lite information............................................................................................................................399

    23.1.1 Instantiation Information..............................................................................................................................399

    23.1.2 AIPS_Lite PACRA-P register reset values..................................................................................................399

    23.2 Introduction...................................................................................................................................................................399

    23.2.1 Features........................................................................................................................................................ 400

    23.2.2 General operation.........................................................................................................................................400

    23.3 Memory map/register definition................................................................................................................................... 400

    23.3.1 Peripheral Access Control Register (AIPS_PACRn)...................................................................................401

    23.3.2 Peripheral Access Control Register (AIPS_PACRn)...................................................................................404

    23.4 Functional description...................................................................................................................................................407

    23.4.1 Access support............................................................................................................................................. 407

    Chapter 24DMA Controller Module (DMA)

    24.1 Chip-specific DMA information...................................................................................................................................409

    24.1.1 Instantiation Information..............................................................................................................................409

    24.2 Introduction...................................................................................................................................................................409

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    24.2.1 Overview......................................................................................................................................................410

    24.2.2 Features........................................................................................................................................................ 411

    24.3 DMA Transfer Overview..............................................................................................................................................412

    24.4 Memory Map/Register Definition.................................................................................................................................413

    24.4.1 Source Address Register (DMA_SARn)..................................................................................................... 414

    24.4.2 Destination Address Register (DMA_DARn)............................................................................................. 415

    24.4.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................416

    24.4.4 DMA Control Register (DMA_DCRn)........................................................................................................418

    24.5 Functional Description..................................................................................................................................................423

    24.5.1 Transfer requests (Cycle-Steal and Continuous modes).............................................................................. 423

    24.5.2 Channel initialization and startup................................................................................................................ 424

    24.5.3 Dual-Address Data Transfer Mode.............................................................................................................. 426

    24.5.4 Advanced Data Transfer Controls: Auto-Alignment................................................................................... 427

    24.5.5 Termination..................................................................................................................................................428

    Chapter 25Direct Memory Access Multiplexer (DMAMUX)

    25.1 Chip-specific DMAMUX information......................................................................................................................... 429

    25.1.1 Instantiation Information..............................................................................................................................429

    25.1.2 DMA Request Sources.................................................................................................................................429

    25.2 Introduction...................................................................................................................................................................431

    25.2.1 Overview......................................................................................................................................................431

    25.2.2 Features........................................................................................................................................................ 432

    25.2.3 Modes of operation...................................................................................................................................... 433

    25.3 External signal description............................................................................................................................................433

    25.4 Memory map/register definition................................................................................................................................... 433

    25.4.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 434

    25.5 Functional description...................................................................................................................................................435

    25.5.1 DMA channels with periodic triggering capability......................................................................................435

    25.5.2 DMA channels with no triggering capability...............................................................................................437

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    25.5.3 Always-enabled DMA sources.................................................................................................................... 437

    25.6 Initialization/application information........................................................................................................................... 438

    25.6.1 Reset.............................................................................................................................................................438

    25.6.2 Enabling and configuring sources................................................................................................................438

    Chapter 26Memory Protection Unit (MPU)

    26.1 Chip-specific MPU information................................................................................................................................... 443

    26.2 Instantiation Information.............................................................................................................................................. 443

    26.3 Write Access Restrictions for RGD0 Registers............................................................................................................ 443

    26.4 Introduction...................................................................................................................................................................444

    26.5 Overview.......................................................................................................................................................................444

    26.5.1 Block diagram.............................................................................................................................................. 444

    26.5.2 Features........................................................................................................................................................ 445

    26.6 Memory map/register definition................................................................................................................................... 446

    26.6.1 Control/Error Status Register (MPU_CESR).............................................................................................. 448

    26.6.2 Error Address Register, slave port n (MPU_EARn)....................................................................................450

    26.6.3 Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 450

    26.6.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 451

    26.6.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 452

    26.6.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 452

    26.6.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 455

    26.6.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................456

    26.7 Functional description...................................................................................................................................................458

    26.7.1 Access evaluation macro..............................................................................................................................458

    26.7.2 Putting it all together and error terminations............................................................................................... 460

    26.7.3 Power management...................................................................................................................................... 461

    26.8 Initialization information.............................................................................................................................................. 461

    26.9 Application information................................................................................................................................................461

    Chapter 27

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    Flash Memory Module (FTFA)

    27.1 Chip-specific Flash Memory Module (FTFA)) information........................................................................................ 465

    27.2 Instantiation Information.............................................................................................................................................. 465

    27.3 Introduction...................................................................................................................................................................465

    27.3.1 Features........................................................................................................................................................ 466

    27.3.2 Block Diagram............................................................................................................................................. 467

    27.3.3 Glossary....................................................................................................................................................... 467

    27.4 External Signal Description.......................................................................................................................................... 469

    27.5 Memory Map and Registers..........................................................................................................................................469

    27.5.1 Flash Configuration Field Description.........................................................................................................469

    27.5.2 Program Flash IFR Map...............................................................................................................................469

    27.5.3 Register Descriptions................................................................................................................................... 470

    27.6 Functional Description..................................................................................................................................................479

    27.6.1 Flash Protection............................................................................................................................................479

    27.6.2 Interrupts...................................................................................................................................................... 480

    27.6.3 Flash Operation in Low-Power Modes........................................................................................................ 481

    27.6.4 Functional Modes of Operation................................................................................................................... 481

    27.6.5 Flash Reads and Ignored Writes.................................................................................................................. 481

    27.6.6 Read While Write (RWW)...........................................................................................................................482

    27.6.7 Flash Program and Erase..............................................................................................................................482

    27.6.8 Flash Command Operations.........................................................................................................................482

    27.6.9 Margin Read Commands............................................................................................................................. 487

    27.6.10 Flash Command Description........................................................................................................................488

    27.6.11 Security........................................................................................................................................................ 503

    27.6.12 Reset Sequence............................................................................................................................................ 506

    Chapter 28Flash Memory Controller (FMC)

    28.1 Chip-specific Flash Memory Controller (FMC) information....................................................................................... 507

    28.2 Instantiation Information.............................................................................................................................................. 507

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    28.3 Introduction...................................................................................................................................................................507

    28.3.1 Overview......................................................................................................................................................507

    28.3.2 Features........................................................................................................................................................ 508

    28.4 Modes of operation....................................................................................................................................................... 508

    28.5 External signal description............................................................................................................................................508

    28.6 Memory map and register descriptions.........................................................................................................................509

    28.7 Functional description...................................................................................................................................................509

    Chapter 29Watchdog Timer (WDOG)

    29.1 Chip-specific WDOG information................................................................................................................................511

    29.1.1 Overview......................................................................................................................................................511

    29.1.2 Instantiation Information..............................................................................................................................511

    29.1.3 Clock Connections....................................................................................................................................... 511

    29.2 Introduction...................................................................................................................................................................512

    29.3 Features.........................................................................................................................................................................512

    29.4 Functional overview......................................................................................................................................................513

    29.4.1 Unlocking and updating the watchdog.........................................................................................................515

    29.4.2 Watchdog configuration time (WCT).......................................................................................................... 516

    29.4.3 Refreshing the watchdog..............................................................................................................................517

    29.4.4 Windowed mode of operation......................................................................................................................517

    29.4.5 Watchdog disabled mode of operation.........................................................................................................517

    29.4.6 Low-power modes of operation................................................................................................................... 518

    29.4.7 Low-power and Debug modes of operation.................................................................................................518

    29.5 Testing the watchdog.................................................................................................................................................... 519

    29.5.1 Quick test..................................................................................................................................................... 519

    29.5.2 Byte test........................................................................................................................................................520

    29.6 Backup reset generator..................................................................................................................................................521

    29.7 Generated resets and interrupts.....................................................................................................................................521

    29.8 Memory map and register definition.............................................................................................................................522

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    29.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 523

    29.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 524

    29.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................525

    29.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 525

    29.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 526

    29.8.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 526

    29.8.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 527

    29.8.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................527

    29.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 527

    29.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 528

    29.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 528

    29.8.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 528

    29.9 Watchdog operation with 8-bit access.......................................................................................................................... 529

    29.9.1 General guideline......................................................................................................................................... 529

    29.9.2 Refresh and unlock operations with 8-bit access......................................................................................... 529

    29.10 Restrictions on watchdog operation..............................................................................................................................530

    Chapter 30External Watchdog Monitor (EWM)

    30.1 Chip-specific EWM information.................................................................................................................................. 533

    30.1.1 Overview......................................................................................................................................................533

    30.1.2 Instantiation Information..............................................................................................................................533

    30.1.3 Clock Connections....................................................................................................................................... 533

    30.1.4 Low Power Modes....................................................................................................................................... 534

    30.1.5 Implementation of EWM_CLKPRESCALER register ...............................................................................534

    30.2 Introduction...................................................................................................................................................................534

    30.2.1 Features........................................................................................................................................................ 535

    30.2.2 Modes of Operation..................................................................................................................................... 535

    30.2.3 Block Diagram............................................................................................................................................. 536

    30.3 EWM Signal Descriptions............................................................................................................................................ 537

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    30.4 Memory Map/Register Definition.................................................................................................................................538

    30.4.1 Control Register (EWM_CTRL)................................................................................................................. 538

    30.4.2 Service Register (EWM_SERV)..................................................................................................................539

    30.4.3 Compare Low Register (EWM_CMPL)...................................................................................................... 539

    30.4.4 Compare High Register (EWM_CMPH).....................................................................................................540

    30.4.5 Clock Control Register (EWM_CLKCTRL)...............................................................................................540

    30.4.6 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................ 541

    30.5 Functional Description..................................................................................................................................................542

    30.5.1 The EWM_out Signal.................................................................................................................................. 542

    30.5.2 The EWM_in Signal.................................................................................................................................... 543

    30.5.3 EWM Counter.............................................................................................................................................. 543

    30.5.4 EWM Compare Registers............................................................................................................................ 544

    30.5.5 EWM Refresh Mechanism...........................................................................................................................544

    30.5.6 EWM Interrupt.............................................................................................................................................544

    30.5.7 Selecting the EWM counter clock............................................................................................................... 544

    30.5.8 Counter clock prescaler................................................................................................................................545

    Chapter 31Analog Front End (AFE)

    31.1 Chip-specific AFE information.....................................................................................................................................547

    31.1.1 Overview......................................................................................................................................................547

    31.1.2 Instantiation Information..............................................................................................................................547

    31.1.3 Clock Sources.............................................................................................................................................. 547

    31.2 Introduction...................................................................................................................................................................549

    31.3 Features...................................................................................................................