Kinetis Mexeedev

TM

Freescale, the Freescale logo, CodeWarrior, ColdFire and Powerquicc are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Flexis, Processor Expert and QorIQ are

trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and

Power.org logos and related marks are trademarks and service marks licensed by Power.org. ARM is the registered trademark of ARM Limited. ARM Cortex-M4 and ARM Cortex-M3 are

trademarks of ARM Limited. © 2010 Freescale Semiconductor, Inc.

Freescale Kinetis SeminarARM Cortex-M4 Microcontrollers

Design Potential. Realized

Gonzalo Delgado & Paolo Alcantara

TMFreescale, the Freescale logo, CodeWarrior, ColdFire and Powerquicc are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Flexis, Processor Expert and QorIQ are




Freescale Confidential and Proprietary

Top Level Agenda

► Freescale Kinetis Overview

► System Architecture

► Peripherals Overview

► “Hands-On” Exercise

► Third Party Ecosystem

► Q&A, Close

2

Top Level Agenda

Freescale Kinetis 1-Day Seminar

TM





Freescale Kinetis Overview






Kinetis: Overview

The most scalable portfolio of low-power

ARM Cortex-M4 MCUs available today

Innovative 90nm Thin-Film Storage

Flash with FlexMemory embedded

EEPROM capability

Exceptional mixed-signal integration

One of the most comprehensive ARM®

enablement portfolios, including solutions

from Freescale as well as the ARM

connected community






MCU Portfolio: Solutions-Focused and Core Agnostic

32-bit

8-bit

16-bit

RS08 and S08

Built on…

Power

Architecture®

Technology

S12 and S12X

Digital Signal Controllers

ColdFire

ColdFire+

90nm

90nmNEW!

100-400+ MIPS

50-200 MIPS Application-oriented ultra-low power solutions with

optimized enablement, integration and cost for appliance,

metering and consumer applications.

Market-leading performance, reliability and software

enablement for automotive and industrial applications.

Scalable cost & power-optimized product families for

industrial, automotive and consumer applications.

Application-oriented solutions for automotive, motor

control and power conversion applications.

Giving customers an ideal solution regardless of architecture preference.

Kinetis

based on ARM®

Cortex™-M4 core

90nmNEW!

50-200 MIPS

Scalable, ultra-low-power product families with

bundled software enablement for industrial and

consumer applications.






Kinetis MCUsScalable Mixed-Signal Consumer and Industrial Microcontroller Families

First available broad-market MCU samples based on ARM Cortex-M4!

More than 40 New 90nm

ColdFire+ MCUs

More than 200 New 90nm

Kinetis MCUs

Market-leading software enablement – IDE, RTOS and initialization tools from Freescale and leading ARM

ecosystem providers to speed time to market

Hundreds of new 32-bit mixed-signal MCUs with huge performance,

memory and feature scalability

Ultra-low power consumption with flexible

power management to balance performance

and battery life

Innovative low-power 90nm thin film storage

flash process withFlexMemory EEPROM

capability

More than 240 new 90nm 32-bit

MCUs in scalable product families






Freescale’s Industrial and Multi-Market 32-bit MCU Portfolio

Kinetis MCUsColdFire+ MCUs

Offers customers great solutions for a variety of applications.

5V Capability

High-

performance

Timers

Human

Machine

Interface

Appliance

Low Power

USB

Connectivity

Encryption

Touch

Sensing

Consumer

Large,

Compatible

Portfolio

Full Connectivity

Offering

Low Power

Precision Analog

General

Purpose

Measurement

Engine

Power Line

Communication

Wireless

Capability

Energy &

Metering

Signal

Processing

High-Speed

Peripherals

Integrated

Analog and

Mixed-Signal

Precision

Analog

Ultra-Low

Power

Connectivity –

Continua

Factory

AutomationMedical

TM





Key DifferentiatorsMemory Technology, Low power, and Integration

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink

and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

90nm TFS Flash: Differentiators

Freescale’s 90nm Thin Film Storage (TFS) flash memory

technology with FlexMemory will deliver outstanding

performance, value, reliability and low power for next

generation industrial and consumer microcontrollers.

Industry leading bit-level reliability through

revolutionary silicon nano crystal technology

Fast, low-voltage transistors that provide low-

power read capability and help satisfy the

increasing demands of power-sensitive

applications with full flash operation specified

down to 1.71 volts

Flash access times of >30nsec; and excellent

area efficiency, enabling a rich level of memory

and peripheral integration across flash

densities, while maintaining optimal MCU cost




90nm TFS Flash: Differentiators

TFS Value = reliability, lower power, EEPROM, scalability

AttributeTraditional embedded

EEPROMFlexMemory

Read-while-write with

program memoryYes Yes

Granularity Byte write/erase Byte write/erase

Write Time~1-5msec

(byte write only)

~100usec

(word or byte program,

brown-outs w/o loss/corruption of

data)

Erase + Write Time ~5-10 msec ~750usec + ~750usec = ~1.5msec

Guaranteed

Endurance50-300K cycles (fixed)

Can exceed 10Mcycles

[configurable]

Write Voltage ≥ 2.0V ≥ 1.71V

Flexibility Fixed by part numberConfigurable

[Quantity vs. Endurance]




Kinetis Power Modes

Values subject to change

Typical

Recovery

Time:

35us

4us

4us

4us

35us

100us+ EE restore

4us

Starting @

<200uA/MHz

1.2uA - 7uA

1uA - 5uA

750nA - 2uA

500nA – 1.5uA

IDD:




Mode Definition

Run MCU can be run at full speed.

Wait Allows peripherals to function, while CPU goes to sleep reducing power consumption.

VLP RunCPU and peripheral clock maximum frequency is restricted. CPU/Platform clock

is restricted to 2MHz. Flash access is restricted to 1MHz. LVD is off.

VLP Wait Similar to VLP Run, with CPU in sleep to further reduce power.

Stop MCU is in static state. Lowest power mode that retains all registers while maintaining LVD protection.

VLP StopMCU is in static state with LVD operation off. Lowest power mode with

ADC, LPT, RTC, LCD, HSCMP, DAC, and pin interrupts functional.

LL StopMCU is in low leakage state retention power mode. LLWU controls wakeup sources

including LPT, RTC, LCD, HSCMP, DAC and select pin interrupts.

VLL Stop 3Powering down most internal logic. All system RAM contents are retained and I/O states held.

LLWU controls wakeup sources (up to 16 GPIOs, LPT, RTC, LCD, HSCMP, and DAC)

VLL Stop 2 Similar to VLL Stop 3, partial system RAM retention. FlexRAM contents can optionally be retained.

VLL Stop 1 Similar to VLL Stop 3, with only 32 byte register file retention.

Kinetis Power Modes




ARM Cortex-M4(F) Processor

Dotted boxes denote optional blocks

Cortex-M4(F) new features

Single cycle MAC (Up to 32 x 32 + 64 -> 64)

DSP extensions by default

Single Precision Floating Point Unit (optional)

Freescale IP and Innovation

On-chip instructions / data cache (optional)

Cross-Bar Switch (concurrent multi-master/slave access)

On-chip DMA for CPU off-load

Low-leakage Wake-up (in addition to AWIC) Unit

Freescale IP for Digital Signal Processing

Motor Control:

Advanced algorithms, longer lifespan, power efficiency

Automation

High calculation and algorithm bandwidth at a low cost

Power management

Designed for low/battery powered systems

Audio and Video

5x performance improvement over software, making batteries last longer

TM




trademarks of ARM Limited. © 2010 Freescale Semiconductor, Inc.14

Kinetis Family200 scalable and compatible Devices




Kinetis Family Overview

Development

Bundled IDE

w/ Processor

Expert

Bundled OS

USB, TCP/IP,

Security

Modular Tower

H/ware

Development

System

Application

Software

Stacks,

Peripheral

Drivers & App.

Libraries

(Motor Control,

HMI, USB)

Broad 3rd party

ecosystem

Common

Digital IP

CRC

I2C

SAI (I2S)

UARTs/SPIs

Programmable

Delay Block

External Bus

Interface

Motor Control

Timers, PIT, LPT

eSDHC

RTC

Common

Analog IP

16-bit ADCs

Programmable

Gain Amplifiers

12-bit DACs

High-speed

Comparators

Low-power

Touch Sensing

Common

System IP

32-bit ARM

Cortex-M4 Core

w/ DSP Instructions

Next Generation

Flash Memory

High Reliability,

Fast Access

FlexMemory w/

EEPROM capability

SRAM

Memory

Protection Unit

eDMA

Low Voltage,

Low Power Multiple

Operating Modes,

Clock Gating

(1.71V-3.6V , optional

with 5V tolerant I/O)

-40°C to 105°C

K70512KB-1MB,

196-256pin

K60 256KB-1MB,

100-256pin

K50128-512KB,

64-144pin

K40 64-512KB,

64-144pin

K30 64-512KB,

64-144pin

K2032KB-1MB,

32-144pin

K1032KB-1MB,

32-144pin

*128k Flash and higher

**120MHz & 150MHz only

***256 pin only




CPU Frequency Options

Maximum CPU

Frequency Across Kinetis

Families




Embedded Memory Options

Kinetis

Families

WITHOUT

FlexMemory

Kinetis

Families

WITH

FlexMemory




USBDIGITAL I/O

DIG

ITA

L I

/O

DIG / ANA I/O + sLCD

K40

64-pin or 80-pin

DIG

/ A

NA

I/O

+ L

CD

96 segments

(8 x 12)

192 segments

(8 x 24)

USB + sLCDUSB

DIG

ITA

L I

/O

DIG

/ A

NA

I/O

DIGITAL I/O

K20

48-pin

USB

Pin Compatibility Across Families

DIGITAL I/O

DIG

ITA

L I

/O

DIG

/ A

NA

I/O

K10

48-pin

General Purpose

LCD

power

pins

K10 K30 & K20 K40 = Add Segment LCDDigital & Analog I/O signals maintain placement order

Segment LCD signals are muxed with existing Digital & Analog I/O signals

Most Digital I/O signals muxed with Segment LCD signals become available on added pins by larger package

DIGITAL I/O = UART, SPI, I2C, CAN, TIMER, etc. ANALOG I/O = OSC, ADC, CMP, etc.

K10 K20 & K30 K40 = Add USBThe only difference will be 4 extra USB pins and 4 less digital I/O pins

DIGITAL I/O

DIG

ITA

L I

/O

DIG / ANA I/O + LCD

K30

64-pin or 80-pin

DIG

/ A

NA

I/O

+ L

CD

96 segments

(8 x 12)

192 segments

(8 x 24)

K20 K60 = Add EthernetAll Ethernet signals are muxed with existing Digital & Analog I/O signals

TM





Kinetis PeripheralsHMI, Connectivity, Communications, Interfaces, Integrity & Security




Feature Summary: HMI (Human Machine Interface)

Low Power Touch Sensing

(All Kinetis families)

Low Power Segment LCD

(K30, K40 families)

Graphics LCD

(K70 family)

Audio Interface (DSP + IIS)


Low power wake-up via touch, H/ware module

avoids polling method of s/ware implementations

Blink mode operation reduces power, Failure

detection in s/ware of segment, connector or LCD-

to-connector faults

8-bit QVGA (MCU), 24-bit SVGA with ext. memory

Bus Master – memory to LCD data transfer with no

CPU intervention

M4 core - fast/efficient processing, IIS - easy

integration of audio processing h/ware

MCU1 2 34 5 67 8 9

*0 #




Feature Summary: Connectivity & Communications

IEEE 1588 Compliant

10/100 Ethernet MAC

(K50, K60, K70 families)

USB host/device/OTG

(FS/LS) Controller

(K20, K40, K60, K70 families)

USB host/device/OTG

(HS) Controller

(K20, K60, K70 families)

CAN, UART (ISO7816),

DSPI, IIC, IIS


Hardware time stamping provides precision clock

synchronization for real-time industrial control, AMD Magic

Wake-Up Pack [wake-up source for AWIC]

DCD (Device Charge Detect) optimizes charging current/time

extending battery life, Low voltage regulator supplies 120mA at

3.3V for powering ext. components from 5V input

USB LS/FS Device/Host/OTG 2.0 complaint with internal PHY

and USB HS Device/Host/OTG 2.0 compliant with up to

480Mbps with external ULPI PHY

Multiple comms. interfaces for simple and efficient data

exchange supported by eDAM, industrial network bridging and

audio interfacing

Carrier Modulator Transmitter

(All Kinetis Families)Infra Red waveform generation for remote control applications

www.freescale.com/MQX [= FREE RTOS, RTCS, .... ]




Feature Summary: Mixed Signal (Analogue)

16-bit ADC


12-bit DAC


Comparator


Programmable Gain Amplifier


Analog Voltage Reference


Fast, accurate signal conditioning, configurable resolution,

sample time, avaraging, self calibration, level/compare mode,

speed and power (8/10/12/16-bit)

Analog signal generation (DMA and buffer support) for audio

applications

Fast, accurate motor over-current protection with internal 6-bit

DAC, band gap and external or internal voltage reference

x64 gain for small amplitude signal boost

Accurate on-chip Vref eliminates need for external Vref -

reduced system cost

FlexTimer [PIT & LPT]

(All Kinetis Families)

Input / output, combine, pulse measurement, PWM functions;

double buffered, fault detect & dead time, Quadrature encoder,

self test, DMA trigger, gloabel time base [8ch, 2ch, 2ch]




Feature Summary: Security

Flash Security


Memory Protection Unit


DryIce & Tamper Detection

(K60, K70 families)

Cryptographic Acceleration

Unit (K50, K60, K70 families)

H/w Cyclic Redundancy Check


4-level protection limits access to flash resources

safeguarding user’s IP

Data protection and increased software reliability

Voltage, frequency, temperature & external sensing for

physical attack detection, independent VBAT & EXTAL32

Faster than s/ware implementations with only minimal CPU

intervention Wide variety of algorithms supported

Validation of memory contents and communication data for

enhanced system integrity [initial seed and polynomial,

transpose and final XOR]




Feature Summary: External Interfaces

FlexBus


DRAM Controller

(K60, K70 families)

NAND Flash Controller

(K10, K20, K60, K70 families)

Secure Digital Host Controller


Connection of ext. memories & peripherals e.g. graphics

displays. Supports up to 6 chip selects [no additional BOM]

Connection of DDR, DDR2 and low-power DDR memories

Connection of up to 32-bit ECC current & future NAND types

ECC management handled in h/ware – minimizes s/ware

overhead

Connection of SD, SDIO, MMC or CE-ATA cards for in-

application software upgrades, media files or Wi-Fi support

TM





Enablement & EcosystemDevelopment Tools & Hardware, 3rd Parties




Choose Your Partner: The Freescale MCU Ecosystem

IDE: Tools Compliers, Debuggers

GNU Tools

HW BDM Debugger/Emulators

Run-Time Software: RTOS, Stacks, File System

ARM® Cortex™ Microcontroller Software Interface Standard - hardware abstraction layer

MQX Support /

Design Services

Audio/Video

Codecs

GUI

Graphical

Security /

Medical

EVBs & System

Design

Ind. Protocol

Stacks

eGUI

http://www.keil.com/

http://images.google.co.uk/imgres?imgurl=http://www.phaedsys.org/principals/segger/seggerimages/jlink.gif&imgrefurl=http://www.phaedsys.org/principals/segger/seggerjlink.html&usg=__NpwFEqv8ey1WRm9SgyTLGeRl9gk=&h=402&w=301&sz=21&hl=en&start=3&itbs=1&tbnid=fBC_ecAdCWQLEM:&tbnh=124&tbnw=93&prev=/images?q=segger+j-link&gbv=2&hl=en&sa=G

http://images.google.co.uk/imgres?imgurl=http://www.arm.com/community/product_images/3385.jpg&imgrefurl=http://www.arm.com/community/display_product/rw/ProductId/3390/&usg=__k2ZCnEfLsu38pk2P8iykFhWhU6I=&h=1030&w=1322&sz=71&hl=en&start=2&itbs=1&tbnid=_gCv2_KX1Xl3NM:&tbnh=117&tbnw=150&prev=/images?q=Raisonance+RLink+(Pro)&gbv=2&hl=en&sa=G






Cortex-M4 Math and DSP Libraries

Vector Math Absolute value Add (element by element) Vector dot product Multiply elements Invert sign (negate) Add constant offset Scale by constant Shift left/right Subtract (element by element)Fast Math Sine, Cosine, Square rootInterpolation (linear and bilinear)Complex Math Complex conjugate Complex magnitude Complex magnitude squared Complex by complex multiplication Complex by real multiplication Complex dot productStatistics Maximum / minimum value Mean Power Root mean square (RMS) Standard Deviation Variance

Filtering Biquad cascade direct form 1 (IIR) Convolution Partial convolution FIR (transversal) filter Polyphase FIR decimator Polyphase FIR interpolator LMS adaptive filter Normalized LMS adaptive filter Sparse FIR filter Correlation 64-bit high precision biquad filters FIR lattice filters Direct form 2 transposed IIR filter IIR lattice filtersTransforms Complex forward FFT Real FFT Inverse real FFT Discrete cosine transform Inverse discrete cosine transformMatrix addition, subtraction, transpose, scaling, inversionController PID controller Field oriented control (clarke and park transforms)

Free ARM Cortex-M4 Math & DSP libraries

CodeWarrior, IAR, Keil, and CMSIS C callable and operating system independent functions

Functions optimized for ARM Cortex-M4 using compiler intrinsics for DSP/SIMD instructions

Separate functions for 8-bit, 16-bit, 32-bit integers and 32-bit floating-point values

Supports many math and DSP functions:




Kinetis Enablement

+ Tower System

Modular, expandable and cost-effective

development platform for 8/16/32-bit

MCUs and MPUs

Rapid eval and prototyping with

maximum HW reuse.

Supported by a diverse range of MCU

and peripheral plug-in boards and a

growing web community

Open source hardware platform for

prototyping application development

Freescale MQX + MCU

Free MQX RTOS

MQX Core

PSP & BSP

+

Full-featured, scalable, proven RTOS

Simplifies HW management, streamlines

SW development

Reduces development costs while

speeding time to market

Comprehensive solution for

embedded control and connectivity

+ CodeWarrior IDE

Eclipse environment

Processor Expert code

generation wizard

Build, debug and flash tools

Software analysis

Kernel-aware debug

Host platform support

Visual and automated framework to

accelerate development time

One-stop-shop for silicon, IDE & RTOS






The Freescale Tower SystemA modular development platform

for 8/16/32-bit MCUs & MPUs

• Quickly combine Tower Modules to build a

prototype of your application

• Modules sold individually or in kits

• Open Source: Build your own Tower Module

to integrate your IP

• Cost-optimized hardware

• Software support from Freescale and Third

Parties

• Growing community of Third Party hardware

support

• On-line community: www.towergeeks.org

Primary Elevator

Board Connectors

MCU/MPU Module:

• Tower controller board

• Standalone or in Tower System

Secondary ElevatorPeripheral Module:

• Up to 3 per system: Serial, Memory, LCD,..

• Mix & match with different MCU modules

Part Number Contents SRP

TWR-K40X256 TWR-K40X256 module $69

TWR-K40X256-KIT

TWR-K40X256 module

TWR-ELEV module

TWR-SER module

$139

TWR-K60N512 TWR-K60N512 module $69

TWR-K60N512-KIT

TWR-K60N512 module

TWR-ELEV module

TWR-SER module

$139

TWR-SENSOR-PAKTWR-LCDTWR-MEM




Top Level Agenda

► Welcome and Introductions






► Q&A, Close

30

Top Level Agenda


TM





Kinetis System Architecture




System Agenda

► Cortex M4 Overview

► Kinetis System Architecture

► Flash Performance

► FlexMemory

► Low Power Modes

32



and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 33




Cortex M4 is fully compatible with Cortex M3

and adds :

•DSP & SIMD instructions

•Optional s.p. Floating Point




2,2

44

8,8

19

FIR q15fixed point

41

IIR q31fixed point

8,5

96

PID q15fixed point

8,3

10

Matrix Mulfixed point

13

,61

9

15

8,8

78

Correlationfloating point

2,4

62

27

2,4

62

DSP Library Benchmark: Cortex-M3 vs. Cortex-M4

Cortex-M3 Cortex-M4 Memory Access

Cycles

Cycles: smaller numbers are

better

-7

5%

-3

5%

-6

9%

-7

0%

-9

1%

•Cortex-M4 SIMD + FPU

•Fix point: ~2x faster

•Floating point: ~10x faster

DSP Library Performance ( CMSIS 2.0 )

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,







Bus Structure

Core

CacheSRAM AHB Masters

Flash

IPS Slaves

Bus Fabric

AHB Slaves





MP

U

All access to

SRAM is via

the MPU




Architecture of devices available today

Up to

512k

bytes

100

MHz

No SP FPU

100MHz

No Cache

Up to 512kB

No NFC

No LCDC

No SDRAM

No DryICE

4K EERAM

4 Kbyte

EERAM




System Agenda




► FlexMemory

► Low Power Modes

40

TM




Kinetis: Flash Performance




Clock Domains (100 MHz)

Platform

100 MHz

IPS Peripherals

50 MHz

Flash

25 MHz

50 MHz




Flash Memory Controller

►Flash System Architecture

• “Dual Bank, x64 Flash Memory”

• “Consecutive x32, word aligned reads with no wait states”

• FMC effectively reads 128bit records from flash each access

43




System Agenda




► FlexMemory

► Low Power Modes

44

TM




Flex Memory




• FlexMemory is a memory block that

can be configured as EEPROM and/or

flash memory

• Combination of TFS flash array

(FlexNVM) + SRAM block (FlexRAM) +

hardware state machine.

What is FlexMemory?

• Fully embedded in the MCU –

avoids software complexity and

eliminates system resource

impact on CPU/flash/RAM of

EEPROM emulation schemes

• Can be accessed

simultaneously with the main

program memory

• Can be used for storing

additional application program

code, data tables or byte

write/erase system data

Main Program

Memory

Firmware

FlexNVM

Fle

xR

AM

Firmware

Memory

Interface &

Control Logic

Fle

xM

em

ory

XBS




Feature list [1]

P-Flash (Program Flash)

256 Kbytes of P-Flash memory composed of one logical 256 Kbyte

Flash block divided into 128 sectors of 2 Kbytes

P-Flash protection scheme prevents accidental program or erase of

stored data

Automated, built-in, program and erase algorithms with verify

Section programming for faster bulk programming times

Read access to P-Flash memory possible while programming or erasing

data in the D-Flash memory or EERAM

47




Feature list [2]

D-Flash (Data Flash)

Up to 256 Kbytes of D-Flash memory with 2 Kbyte sectors

D-Flash protection scheme prevents accidental program or erase of

stored data

Automated, built-in program and erase algorithms with verify

Section programming for faster bulk programming times

Read access to D-Flash memory possible while programming or erasing

data in the P-Flash memory

48




Feature list [3]

EERAM

Up to 4 Kbytes of EERAM configured for EEE or traditional RAM operations

When configured for EEE (EEPROM Emulation):

EERAM protection scheme prevents accidental program or erase of data

Built-in hardware emulation scheme to automate EEE record maintenance

Programmable EEE Data Set Size and D/E-Flash Partition Code allows EEE

memory endurance trade-offs

Supports EERAM aligned writes of 1, 2, or 4 bytes at a time

Read access to EERAM possible while programming or erasing data in the

P-Flash or D-Flash memory

When configured as Traditional RAM

Read and write access possible to the EERAM while programming or

erasing data in the P-Flash or D-Flash memory

49




FTFL Commands

50

Supported Embedded Commands:

Read 1s Block

Read 1s Section

Program Check

Read Resource

Program Longword

Erase Flash Block

Erase Flash Sector

Program Section

Read 1s All Blocks

Read Once

Program Once

Erase All Blocks

Verify Backdoor Access Key

Program Partition

Set EERAM Function

The address of FCCOBn registers are not in normal sequence

(3,2,1,0,7,6,5,4,B,A,9,8)




Useful Information

►Program flash is guaranteed to minimum 10K cycles over full operating

specification

Parameter Min Typ Max

Tacc at Full Power 28 ns

Tacc at Low Power 800 ns[1]

Twakeup from VLLS mode 4 us

Twakeup from POR 20 us

Tpgm 50 us 75 us 500 us

Terase 2 ms 5 ms 200 ms




System Agenda




► FlexMemory

► Low Power Modes

52

TM




Kinetis – Low Power Modes & Wakeup

Modes, NVIC, AWIC, LLWU




Power Modes, Current & Wake-Up Times

Typical

Recovery

Time:

35us

4us

4us

4us

35us

100us+ EE restore

4us

Starting @

<200uA/MHz

12uA

6uA

4uA

2uA

IDD:




Power Modes: Definition

Mode Definition

Run MCU can be run at full speed.

Wait Allows peripherals to function, while CPU goes to sleep reducing power consumption.

VLP RunCPU and peripheral clock maximum frequency is restricted. CPU/Platform clock

is restricted to 2MHz. Flash access is restricted to 1MHz. LVD is off.

VLP Wait Similar to VLP Run, with CPU in sleep to further reduce power.

Stop MCU is in static state. Lowest power mode that retains all registers while maintaining LVD protection.

VLP StopMCU is in static state with LVD operation off. Lowest power mode with

ADC, LPT, RTC, LCD, CMP, DAC, and PIN interrupts functional.

LL StopMCU is in low leakage state retention power mode. LLWU controls wakeup sources

including LPT, RTC, LCD, CMP, DAC and select PIN interrupts.

VLL Stop 3Powering down most internal logic. All system RAM contents are retained and I/O states held.

LLWU controls wakeup sources (up to 16 GPIOs, LPT, RTC, LCD, CMP, and DAC)

VLL Stop 2 Similar to VLL Stop 3, partial system RAM retention. FlexRAM contents can optionally be retained.

VLL Stop 1 Similar to VLL Stop 3, with only 32 byte register file retention.

NOTE: The WFI instruction invoke both wait and stop modes. The MCU exits the low-power mode via an interrupt




Top Level Agenda







► Q&A, Close

56

Top Level Agenda


TM





Kinetis Peripherals Overview




Peripherals Overview - Agenda

Section 1: Communications Peripherals

UART , DSPI , I2C, FlexCAN , USB , Ethernet , SSI

Section 2: Analog Peripherals

ADC & PGA , DAC , Vref , HSCMP

Section 3: Timers

PDB , FlexTimer, CMT, LPT, PIT, Watchdog & EWM,

RTC

Section 4: HMI

TSI , sLCD

Section 5: Security & Integrity

CRC, CAU, RNG, RTC

Section 6: Memory Interfaces

FlexBus, eSDHC, NAND- CTRL, DRAM-CTRL

Section 6: Programming & Debugging




Pin Muxing: Alternate functions

59

•Some pins have fixed ( power or analog ) function :

Vdd,Vss,Vdda,Vssa, Vrefh,Vrefl, VREF_OUT, USB_DP/DM, DACx_OUT,

Extal32 , Xtal32, Vbat, Reset, Vout33, Vregin, some differential and single

ended ADC inputs

.

•BUT most pins have several “Alternate” functions – up to 8 !

e.g.

DAC output

RTC crystal and

battery




PORT Module: Port Control Register

Every pin has a dedicated (32-bit) PCR register.

e.g. On K60 144bga ball“A3” corresponding to PORTD bit 5 (PTD5 ) has

PORTD_PCR5 register associated, where we can get/set for that pin only :

1. Interrupt flag (w1c )

2. Interrupt configuration : int/dma, edge/level, low/high, rising/falling/both

3. Mux control : can select Disabled (analog) or Alternate function Alt1 -> Alt7

4. Drive Strength low/high

5. Open drain yes/no

6. Slew Rate : fast/slow

7. Pull Resistor Enable : yes/no, pull-up or pull-down

8. Passive filter enable : optional passive lowpass filter (10-30MHz BW )

PCR settings are always in effect – regardless of what module is

connected to the pin

Note : a lock bit in each PCR register can make it read-only until next reset




Section 1 – Communications Peripherals




Part 1 of 7 - UART

Modified IP : MCF51AG128

It is not “Just a UART”:

• It is 6 UARTs on 144pin packages• All 6 UARTs support LIN

• All 6 UARTs support IrDA• Check routing in SIM; only UART0 &, UART1 <-> CMP

• UART0 supports ISO7816 (SIM, smartcards)

• At 100MHz:• UART0 /1– 6.25 Mbits/s

• UART2-5 – 3.13 Mbits/s

• Reduced CPU Loading• Rx, Tx from UART can assert DMA request

• UART0, UART1 have 8-entry Rx, Tx FIFOs

• All UARTs have optional RTS, CTS

• UART2-5 have double-buffered registers

• Address-Match feature• Low Power enablement

• Muxed to several alternate ports • e.g. UART0 available on 4 ports for 144pin package




Part 2 of 7 – DSPI [1]

63

Re-use IP :

MCF532x/7x, MCF5445x,

others

DSPI = “DMA” Serial Peripheral Bus:

A 3-wire, full duplex synchronous bus

• 3 SPIs on 144pin packages• Master and Slave Modes• Very Fast

• Max Master speed is fBUS/2 , 25MHz• Max Slave speed is fBUS/4 , 12.5 MHz

• FIFO Architecture• 4-entry Transmit FIFO• 4-entry Receive FIFO

• DMA Capable “Queued Mode”• Command Buffer in system RAM• “Tx FIFO not full” DMA trigger • “Rx FIFO not empty” DMA trigger

• Up to 6 Peripheral Chip Selects• Can be expanded with external mux

• Muxed to several alternate ports • e.g. DSPI0 available on 3 ports for 144pin package




Part 3 of 7 - I2C

Modified IP : MCF51AG128

Standard I2C Features, of course:• Multi-master operation

• 7-bit address or 10-bit address extension

• Software-selectable acknowledge bit

• Interrupt-driven byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• START and STOP signal generation and detection

• Repeated START signal generation and detection

• Acknowledge bit generation and detection

• Muxed to several alternate ports • e.g. I2C0 available on 3 ports for 144pin package




Part 4 of 7 – FlexCAN

Modified IP: MCF52xx

“FlexCAN3”

Compliant to CAN protocol Ver 2.0B

• Standard data and remote frames

• Extended data and remote frames

• Zero to eight bytes data length

• Programmable bit rate up to 1 Mb/sec

• Content-related addressing

Flexible Mailboxes Architecture

• 16 mailboxes

• Zero to eight bytes data length

• Each configurable as Rx or Tx

• Individual Rx Mask Registers per Mailbox

• Full featured Rx FIFO with storage capacity

for up to 6 frames and automatic internal

pointer handling

Start-of-Frame Identifier Control Data CRC ACK End-of-Frame Interframe SpaceIdle Idle




Part 4 of 7 – FlexCAN [2]

New Features

• Extended ID Filtering

• Safe mechanism for ID filter re-configuration

• Match incoming IDs against:

• 128 extended IDs, or 256 standard IDs or

• 512 partial IDs, with up to 32 individual masking capability

• Flexible Mailboxes

• Rx Mailboxes can be configured with the same acceptance criteria

• Reception Queue

• Allows the CPU more time to service received messages

• Selectable priority of message reception between Mailbox and Rx FIFO

Start-of-Frame Identifier Control Data CRC ACK End-of-Frame Interframe SpaceIdle Idle




Part 5 of 7 - USB

67

USB-oriented Modules:

USB ecosystem is an integration of three modules:

• On chip voltage regulator• Device charger detection module (DCD)• Full-speed USB 2.0 dual-role module (Host / device)

Re-use IP:

MCF5225x, MCF51JM

VBUS

D+

D-

GND

Voltage

regulator

DCD

3.3v

USB

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Part 5 of 7 – USB [2]

68

USB voltage regulator is independent of the MCU

Enabled even if the MCU is not powered. 5v USB voltage input

• 3.3v output @ 120mA

• Output pin: Vreg33

• Can supply MCU

On chip voltage regulator

• Drop-out is 300mV

• Modes:

• Run (120uA)

• Standby (1uA)

• Shutdown

NEW IP






69

Main Features

• Full-speed USB 2.0 Compliant

• Dual Role Operation – Host/Device

• 16-off, double-buffered, bidirectional endpoints

• Onchip USB full-speed PHY

• Low Power Operation

• Integrated with DCD Module

Only 2 pins to Remember!• D+ USB0_DP

• D- USB0_DM

• Both shared with DCD Block

• Dedicated, so no pin muxing required.

USB Engine

VBUS

D+

D-

GND

DCD

USB

Re-use IP:

MCF5225x, MCF51JM






70

Device Charger Detection DCD

Background:

• USB Battery Charger Spec Rev 1.1 Compliant

• I am a USB Device, Full Speed USB2.0

• I have a rechargeable battery

• I want to know if the host into which I am plugged can provide sufficient charging current

• Negotiated during device attachment

• D+ and D- sink/source currents, detected by DCD module

• Charger Port Detection

• Charger Type Detection

• About 40ms after D-pin connect debounce.

NEW IP

NEW

IP





Part 6 of 7 - Ethernet

71

Modified IP: MCF5441x

Ethernet Module “MAC-NET” ( 10/100 MAC )

► Supports legacy FEC buffer descriptors

► compatible with FEC used on ColdFire

► Supports MII and RMII interfaces

► IEEE1588

► Implements a hardware acceleration block

► For IP, TCP, UDP and ICMP protocol services

► Supports AMD magic packet detection with interrupt

to wake up MCU from low power mode




Part 7 of 7 - SSI

72

Re-use IP:

MCF532x/7x, MCF5445x,

others

Synchronous Serial Interface:

A full duplex synchronous bus, typically for audio

• 1 SSI on 144pin packages• Supports a variety of formats:

• AC97• I2S• „Normal‟ Modes

• Synchronous, also Gate Clock mode• Asynchronous

• Network (TDM) Mode

• FIFO Architecture• Dual 15-entry, 32-bit Transmit FIFOs• Dual 15-entry 32-bit Receive FIFOs

• DMA Capable • “Tx FIFOn empty” DMA trigger • “Rx FIFOn full” DMA trigger

• Muxed to several alternate ports • SSI available on 3 ports for 144pin package




Section 2 – Analog Peripherals




Part 1 of 4 – ADC16

SAR architecture with up to 16-bit resolution

• Up to 4 pairs of differential and 24 single-ended external

analog inputs + various internal channels

• Single or continuous conversion (automatic return to idle after

single conversion)

• Configurable sample time and conversion speed/power

• Input clock selectable from up to four sources

• Operation in low power modes

• Asynchronous clock source for lower noise operation

• Selectable hardware conversion trigger with hardware

channel select

• Automatic compare with interrupt for less-than, greater-than

or equal-to, within range , or out-of-range, programmable

value

• Temperature sensor

• Hardware average function

• Selectable voltage reference: external or alternate

• Self-calibration mode

• Programmable Gain Amplifier (PGA) with up to x64 gain

Two independent ADC blocks

available in current silicon




12 bit DAC – Overview & Features

75

• Low power, general purpose 12 bit dac

• Two blocks available on current devices

• 16 word FIFO with hw or sw triggering,

and configurable watermark.

• Selectable reference voltage

• Output available on-chip and off-chip

• Interrupt or DMA request generation

• Mantains static voltage output

in Stop modes.

• Operational range : Vdd = 1.71 to 3.6V

Vref.= 1.15V to 3.6V

• 16 word FIFO can be triggered form

programmable PDB update pulses and

can update the output word pointer in 3

modes :• Circular Buffer mode

• Swing (Up-Down) mode

• One Time Scan mode

DAC & buffer

16 word FIFO

Part 2 of 4 – DAC12




Part 3 of 4 – VREF

►Features

• 1.20 V nominal output ( Factory Trimmed )

• Tight regulation mode for external use

• < 33ppm/ºC temp variation

In critical 0-50 C° temp range

Adds to PMC bandgap reference , but with higher performance

and more features

•VREF module connects to : 1. dedicated VREF_OUT pin ( only in tight regulation mode ) 2. DAC ( as voltage reference input )3. ADC ( as reference and channel input ) 4. HSCMP 0,1 .

Static in LLS, off in VLLSx, functional in all other modes




► Comparator Features:

• operation over entire supply

range and rail-to-rail inputs

• optional output to MCU pin for all

comparators

• configurable rising and falling

edge interrupts

• option to generate DMA request

• wake-up source for all MCU low-

power modes

• operation in continuous,

sampled, or windowed modes

• programmable filter to change

output state only when

consecutive samples agree

• four software-controlled levels of

hysteresis

77

Part 4 of 4 – HSCMP




Section 3 - Timers

CAU

LPT




PDB functionality

The purpose of PDB (Programmable Delay Block ) is to

synchronize by means of hw the activity of certain

peripherals, by generating :

programmable delays between input triggers and

output triggers

periodical output triggers

► output triggers from PDB are available to : ADC16, DAC12,

HSCMPx

► input triggers can be sourced to PDB from : external pin,

CMP, PIT, FTM, RTC, LPT, software

79

Part 1 of 7 - PDB




Part 2 of 7 - FlexTimer

Timing & Control / PWM - Overview

Up to 3 FlexTimer with 2ch, 2ch and 8ch [ main user registers are buffered ]

Support for motor control , power management, and digital lighting solutions

FTM is based/backwards compatible with HC9S08 TPM but with several key enhancements

[ signed up counter, deadtime insertion, fault inputs, enhanced triggering function, initialization and polarity ]

16bit (un)signed counter [ divide-by 1,2,3,8,16,32,64, or 128 ]

• Free-running or with initial and final value

• Up or up-down counting

Clock Options:

• Bus Clock [default]

• FFCLK [Fixed Frequency Clock]

[ 1/2 of system clock frequency ]

• EXTCLK [External Clock Path]

[ 2 Pins, 1/4 of system clock ]

• Global Time Base

[ Synchronization of FTM modules (two ore more) ]

Multiple sources of interrupts [ OR'd together ]

NOTE

The FTM1 and FTM2 configuration differs from the FTM0 configuration by reduced

number of channels and by adding support for quadrature decoder mode.




Part 3 of 7 - CMT

Carrier Modulation TransmitterFeature Overview

Provides means to generate the protocol timing

and carrier signals for encoding schemes

Incorporates hardware to off-load the critical

and/or lengthy timing requirements

Support Interrupt and DMA request

[ i.e. interrupt on end of cycle ]

Modulator disabled allow infrared output use

Modes of operation:

• Time with independent control of high/low times

[ Modulator can gate the carrier onto the modulator output ]

• Baseband

[ Modulator can control the logic level of the modulator output ]

• Frequency shift key (FSK)

[ Modulator can count carrier periods and instruct the carrier generator to alternate

between two carrier frequencies whenever a modulation period (mark + space counts) ]

• Direct software control of CMT_IRO pin [ infrared output ]

• Extended space operation in time, baseband, and FSK modes

[ Extended Space Operation can be used to emulate a zero mark event ]




Part 4 of 7 - LPT

Low-Power TimerFeature Overview

16bit free-running counter

• Reset on compare

• Pulse counter with compare

• Input pins and rising or falling edge

• CMP output used in pulse counter mode

Interrupt and HW trigger on Timer Compare

Modes [ across all power modes ]:

Pulse Counter, with glitch filter is bypassed / enabled

[ glitch filter clock sources are 1kHz LPO, EXTAL, EXTAL32, IRC ]

Time Counter, with presacle bypassed / enabled

[ increment 22.....216 ]

Continue operating through most system reset events

• The LPT is reset only on global POR or LVD

• AWIC and LLWU Wake-up Source




Part 5 of 7 - PIT

Periodic Interrupt TimerFeature Overview

4 x 32bit timers [ system clock source ]

• Stopping and Starting

• Modifying Running Timer Period

• Dynamically Setting a New Load Value [without restarting]

Independent timeout periodes for each timer

• Generate triggers at periodic intervals

[ timer reaches '0' ]

• Generate DMA trigger pulses

• Generate maskable Interrupts

• Counter values (current state) could be read

Functional in RUN and VLPR mode

Seperate Vectors PIT Ch0...Ch3

DMA transfer Ch0 ... Ch3

Provide an automatic mechanism totransmit bytes, frames or packets atfixed intervals without the need forprocessor intervention.




Part 6 of 7 - COP & EWM

Computer Operating Properly & External Watchdog Monitor

Feature Overview - Watchdog (COP)

Independent-clocked Watchdog

[ monitors the operation of the system by expecting periodic refreshing ]

Programmable Timeout Period and Window Refresh Option

Unlock sequence for allowing updating of configuration registers

[ within 256 clock cycles being unlocked, need update after unlocking, otherwise it resets the system ]

Ability to TESET Watchdog [ Timer and RESET ]

• Quick Test: Small timeout value programmed

• Byte Test: Individual bytes of timer tested

• Read-Test: Read-only access to read/check WDOG counter value

Fully Functional in RUN, STOP, VLPR, VLPW, VLPS

Feature Overview - EWM

8bit ripple counter

Redundant Watchdog, monitors external circuits

EWM does not reset the MCU

EWM_IN Pin: Allows an external circuit to control the EWM_OUT

EWM_OUT Pin: When asserted is used to reset or place the external circuit into safe mode




Part 7 of 7 - RTCReal Time Clock

EXTAL32 can be used as main

oscillator source (cost reduction)

Feature Overview

32bit monotonic counter

32bit Alarm [ invalidated on DryIce tamper detect &

alarm/interrupt at a predefined time ]

16bit prescaler with compensation

[ can correct errors between 0.12 … 3906 ppm ]

Independent Battery Power Supply

[ VBAT, supply RTC & VBAT-Register ]

Independent 32.768kHz OSC [EXTAL32]

Automatic Gain Control

[ optimize power consumption ]

Alarm Pin [ optional, not on all devices ]

Register write protection

Fully functional in all modes

[ AWIC and LLWU Wake-up Source ]




Section 4 – HMI Peripherals

sLCD




Part 1 of 2 - TSI

87

►16 input capacitive touch sensing pins

• Wide measuring capacitance range ( 1- 500pF )

• Each with individual result registers – 16 bit resolution

• Automatic detection of Electrode Capacitance Change with programmable upper and

lower threshold (for each electrode)

►Capacitive touch sensing detection across all power modes

• Automatic periodic scan or software triggered single scan of selected pins

• Configurable resolution / scan speed

►TSI low power mode

• Module can scan a single electrode in any VLLSx low power mode and wake-up MCU on

touch detection

• Low power mode current adder can be <1uA




Part 1 of 2 – TSI [2]

88

Generates the electrode

scan sequenceTakes the decision on

each measurement

Measures a single capacitanceTSI block diagram




Part 2 of 2 - sLCD

Available on all K30 and K40 devices and some future K50 devices

Connects LCD glasses with static drive or up to 1/8 duty cycle –>

Fewer pins required to drive LCD segments (up to 320 )

48 pins required for 320 segments in 8x40 mode



Low power blinking mode

Programmable blink modes and frequency in all low power modes

Can alternate two patterns on LCD ( in 4x mode or less ) or blank entire LCD

periodically

Internal charge pump provides all voltages required to power up LCD

glass at 3 or 5 volts

Internal software selectable regulated power supply that keeps constant voltage

across LCD glass to avoid degradation

kinetis sLCD offers 4 bits resolution trim to digitally adjust contrast control




Segment fault detection capability

Hardware support for segment LCD display errors

Front and back plane assignment FP and BP can be software selectable to be either FP or BP, making board layout an

easier task and very flexible for changes

BackPlane re-assignment

Assist in vertical scrolling on dot-matrix displays

LCD waveforms functional in all low-power modes

Allow the LCD to work in any low power mode

LCD registers are only initialized after Power on Reset.

For low power modes reduce the time to initialize the code.

Part 2 of 2 – sLCD [2]




Section 5: Security & Integrity

CAU

LPT




RNGB, MMCAU & CRC

Pseudo-Random Number Generator (RNGB)

Memory-Mapped Cryptographic Acceleration Unit (CAU)

Hardware Cycle Redundancy Check Generator support 16bit & 32bit (CRC)

DEFAULT

Security & Integrity




Part 1 of 3 - CRC

Cyclical Redundancy Check

AN3795Document show CRC Module can be used to check in-application

SOFTWARE for corruption and verify DATA integrity.

Feature Overview

The 16/32-bit code is calculated for 32-bit of data at a time

Programmable initial seed value and polynomial

Optional 'Final XOR' with 0xFFFFFFFF or 0xFFFF

Support transpose register

[ required for certain CRC standards ]

• Input data

• CRC result

• Transpose types are

No Transposition

Bits in bytes are transposed, bytes are not transposed

Both bits in bytes and bytes are transposed

Only bytes are transposed, no bits in a byte are transposed




Part 2 of 3 - RNG and CAURandom Number Generator

Crypto Acceleration UnitFeature Overview - RNGB

Performs seed generation and

random number generation

Use TRNG and PRNG to achieve true

randomness & cryptographic strength

Self Test Mode

[ verify HW is functioning (~29,000 cycles) ]

Feature Overview - MMCAU

Coprocessor, connected to Private Peripheral Bus (PPB).

Supports hardware implementation of a set of specialized

operations to improve throughput of SW based security

encryption or decryption operations and message digest functions.

Acceleration of the DES, 3DES, AES, MD5, SHA-1 and SHA-256 algorithms.

Freescale provides an optimized, callable C-function library that provides the

appropriate software building blocks to implement higher-level security functions.

Simple, flexible programming model and the ability to sent up to three commands in one data write operation

True Random Number Generator (TRNG) Pseudo-Random Number generator (PRNG)




Section 6 - Memory Interfaces

CAU

LPT

DRAM*

*256 pin only




Part 1 of 3 - FlexBus

Interface to (a)synchronous devices

[Flash, Smart LCDs, FPGAs, SRAM,

PROM, EPROM, EEPROM]Feature Overview

Designed to connect up to 6 external devices

[ 6 independent, user-programmable chip-selects ]

8-, 16-, and 32-bit port sizes with configuration

for multiplexed or non-multiplexed address

and data buses [ with optional burst support ]

Auto-acknowledge feature

• Primary and optional secondary wait state counter

• Useful for interfacing to burst

• Data access time [if subsequent data's are faster]

Programmable

• Address-setup time with respect to the

assertion of chip select

• Address-hold time with respect to the

negation of chip select and transfer direction

Package 144 104 100 81 80 64 48 32

Signals

Muxed

mode

Non-muxed

mode

LCD

mode

FlexBus Modes of Operation [ non LCD devices ]

Package 144 104 100 81 80 64

Signals

Muxed

mode

Non-muxed

mode

LCD

mode

FlexBus Modes of Operation [ LCD devices ]

AN3854NO inverter required [FB_A[0] to BHE/BLE]

NO additional external address lacth required




Feature Overview

Card bus clock frequency up to 50 MHz

1bit / 4bit SD and SDIO modes

Up to 200Mbps of data transfer (using 4 parallel data lines)

1bit / 4bit / 8bit MMC modes

Up to 416Mbps of data transfer (using 8 parallel data lines, single data rate mode)

1bit / 4bit / 8bit CE-ATA devices

Single Block, Multi Block read and write

Block sizes of 1 ~ 4096 bytes

SD MMC CE-ATA SD/SDIO

SD 1bit MMC 1bitIdentification Mode

(up to 400 kHz)

CE-ATA 1-bitSD/SDIO

full speed mode

(up to 25 MHz)

SD 4bit MMC 4bitMMC full speed mode

(up to 20 MHz)CE-ATA 4-bit

SD/SDIO

high speed mode

(up to 50 MHz)

MMC 8bitMMC high speed mode

(up to 52 MHz)CE-ATA 8-bit

Part 2 of 3 - eSDHC

Enhanced Secure Digital Host Controller




Part 3 of 3 - NAND-CTRL, DRAM-CTRLExternal Memory Interfaces - Summary

Feature Overview - DRAM Controller

External Data Bus Interface: 8-bits / 16-bits

Up to 125 MHz Clock and 250 MHz Data

Supports: DDR, DDR2, LPDDR

Fully asynchronous operation with an independent PLL.

Supports burst of 16 bytes and 32 bytes

Feature Overview - NAND Flash Controller

NAND Flash Interface: 8-bits / 16-bits (shares FlexBus pins)

Supports all NAND Flash products (SLC & MLC) regardless of density / organization

[ with page size of 512+16B/2K+64B/4K+128B/4K+218B/8K ]

By-passable ECC mode, NFC supports 4/6/8/12/16/24/32 bits error correction

MLC NAND Flash:

Multi-Level per Cell able to store

multi bits [cheaper due to higher

density]

Opposed to SLC NAND Flash:

Single-Level per Cell

Robust timing recovery makes board routing easier !!!




Section 6 - Programming and Debugging

Cortex-M4

Debug Topology





Debug Interface

4pin or 5pin JTAG [ IEEE 1149.1 ]

JTAG_CLK

JTAG_DO

JTAG_DI

JTAG_MS

JTAG_TRST

(optional JTAG Reset)

2pin cJTAG [ IEEE 1149.7 ]

JTAG_CLK

JTAG_MS

2pin Serial Wire Debug (ARM SWD)

SWD_CLK (available on JTAG_CLK pin)

SWD_DIO (available on JTAG_MS pin)

ARM Real-Time Trace Interface

Debug in Low Power Modes

In low power modes in which the debug modules are kept

static or powered off, the debugger cannot gather any debug

data for the duration of the low power mode.

In the case that the debugger is held static, the debug port

returns to full functionality as soon as the low power mode

exits and the system returns to a state with active debug.

In the case that the debugger logic is powered off, the

debugger is reset on recovery and must be reconfigured

once the low power mode is exited.





Flash Programming Methodes

Resident flash programming routines for firmware updates in the field via communication interfaces




Top Level Agenda







► Q&A, Close

106

Top Level Agenda





Exercises




Top Level Agenda







► Q&A, Close

108

Top Level Agenda





Top Level Agenda







► Q&A, Close

109

Top Level Agenda





Q&A




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