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Lecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books websites authors pages and other from various books, websites, authors pages, and other sources for academic purpose only. The instructor does not claim any originality . CSCE 5730: Digital CMOS VLSI Design 1

Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

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Page 1: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Lecture 2: VLSI OverviewCSCE 5730

Digital CMOS VLSI DesignInstructor: Saraju P. Mohanty, Ph. D.

NOTE: The figures, text etc included in slides are borrowedfrom various books websites authors pages and otherfrom various books, websites, authors pages, and othersources for academic purpose only. The instructor doesnot claim any originality.

CSCE 5730: Digital CMOS VLSI Design 1

y g y

Page 2: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Lecture Outline

• Historical development of computersI t d ti t b i di it l t• Introduction to a basic digital computer

• Five classic components of a computer• Microprocessor• IC design abstraction levelIC design abstraction level• Intel processor family

D l t l t d f IC• Developmental trends of ICs• Moore’s Law

CSCE 5730: Digital CMOS VLSI Design 2

Page 3: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Introduction to Digital Circuits

CSCE 5730: Digital CMOS VLSI Design 3

Page 4: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

What is a digital Computer ?

A fast electronic machine that acceptsdigitized input information, processes itg p paccording to a list of internally storedinstruction, and produces the resultingp goutput information.

List of instructions Computer program

Internal storage Memory

CSCE 5730: Digital CMOS VLSI Design 4

Page 5: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Different Types and Forms of Computer

• Personal Computers (Desktop PCs)• Notebook computers (Laptop computers)• Handheld PCsHandheld PCs• Pocket PCs

W k t ti (SGI HP IBM SUN)• Workstations (SGI, HP, IBM, SUN)• ATM (Embedded systems)• Supercomputers

CSCE 5730: Digital CMOS VLSI Design 5

Page 6: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Five classic components of a Computer

Computer

Processor

Computer

Memory Devices

Control Input

Datapath Output

(1) Input (2) Output (3) Datapath (4) Controller and(1) Input, (2) Output, (3) Datapath, (4) Controller, and (5) Memory

CSCE 5730: Digital CMOS VLSI Design 6

Page 7: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

What is a microprocessor ?

• A microprocessor is an integrated circuit (IC) built on a tinypiece of silicon. It contains thousands, or even millions, ofpiece of silicon. It contains thousands, or even millions, oftransistors, which are interconnected via superfine traces ofaluminum. The transistors work together to store and manipulatedata so that the microprocessor can perform a wide variety ofdata so that the microprocessor can perform a wide variety ofuseful functions. The particular functions a microprocessorperforms are dictated by software. (source : Intel)

• Simply speaking, microprocessor is the CPU on a single chip.CPU stands for “central processing unit” also known asp gprocessor.

P b “ l ” “ i l ” A• Processor can be “general purpose” or “special purpose”. Aspecial purpose processor is also known as “application specificintegrated circuit” (ASIC).

CSCE 5730: Digital CMOS VLSI Design 7

Page 8: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

What is an Integrated Circuit ?

• An integrated circuits is a silicon semiconductorcrystal containing the electronic components forcrystal containing the electronic components fordigital gates.Integrated Circuit is abbreviated as IC• Integrated Circuit is abbreviated as IC.

• The digital gates are interconnected toimplement a Boolean function in a IC .

• The crystal is mounted in a ceramic/plasticmaterial and external connections called “pins”are made available.

• ICs are informally called chips.

CSCE 5730: Digital CMOS VLSI Design 8

Page 9: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

How does a microprocessor look?

(1) ASIC (2) Sun UltraSparc (3) PentiumPro

CSCE 5730: Digital CMOS VLSI Design 9

Page 10: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Historical Development

CSCE 5730: Digital CMOS VLSI Design 10

Page 11: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Technology: Highest Growth in History• 1958: First integrated circuit

– Flip-flop using two transistorsFlip flop using two transistors– Built by Jack Kilby at Texas Instruments

• 20032003– Intel Pentium 4 processor (55 million transistors)– 512 Mbit DRAM (> 0.5 billion transistors)512 Mbit DRAM ( 0.5 billion transistors)

• 53% compound annual growth rate over 45yearsy– No other technology has grown so fast so long

• Driven by miniaturization of transistorsDriven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on societyy y

CSCE 5730: Digital CMOS VLSI Design 11

Page 12: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Industry : Annual Sales• 1018 transistors manufactured in 2003

– 100 million for every human on the planet100 million for every human on the planet• 340 Billion transistors manufactured in 2006.

(World population 6 5 Billion!)(World population 6.5 Billion!)200

Globa

100

150

l Sem

icon(B

illions o

50

nductor Bil

of US

$)

01982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

lings

CSCE 5730: Digital CMOS VLSI Design 12

Page 13: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Invention of the Transistor• Invention of transistor is the driving factor of

growth of the VLSI technologygrowth of the VLSI technology• Vacuum tubes ruled in first half of 20th century

Large expensive power hungry unreliableLarge, expensive, power-hungry, unreliable• 1947: first point contact transistor

– John Bardeen and Walter Brattain at Bell Labs– Earned Nobel prize in 1956

CSCE 5730: Digital CMOS VLSI Design 13

Page 14: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Transistor Types

• Bipolar transistorsn p n or p n p silicon structure– n-p-n or p-n-p silicon structure

– Small current into very thin base layer controls largecurrents between emitter and collectorcurrents between emitter and collector

– Base currents limit integration density• Metal Oxide Semiconductor Field Effect• Metal Oxide Semiconductor Field Effect

Transistors (MOSFET)MOS d MOS MOSFETS– nMOS and pMOS MOSFETS

– Voltage applied to insulated gate controls currentbetween source and drainbetween source and drain

– Low power allows very high integration

CSCE 5730: Digital CMOS VLSI Design 14

Page 15: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

The Babbage Difference Machine in 1832g

CSCE 5730: Digital CMOS VLSI Design 15

Page 16: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

The First Electronic Computer in 1946 (ENIAC)p ( )

CSCE 5730: Digital CMOS VLSI Design 16

Page 17: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

How a Home PC Looks Today??

CSCE 5730: Digital CMOS VLSI Design 17

Page 18: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

First Integrated Circuit - 1958The First Integrated Circuit – Jack Kilby, Texas Instruments

1 Transistor and 4 Other Devices on 1 Chip1 Transistor and 4 Other Devices on 1 ChipWinner of the 2000 Nobel Prize

CSCE 5730: Digital CMOS VLSI Design 18

Page 19: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

First Commercial Planar IC - 1960

Fairchild -- One Binary Digital (Bit) Memory Device on a Chip4 Transistors and 5 Resistors4 Transistors and 5 Resistors

Start of Small Scale Integration (SSI)!! We are in VLSI!!

CSCE 5730: Digital CMOS VLSI Design 19

Page 20: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

First IC Created with Computer-Aided D i T l 1967Design Tools -- 1967

MOSAIC – FairchildMOSAIC Fairchild

CSCE 5730: Digital CMOS VLSI Design 20

Page 21: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

First 1,024 Bit Memory Chip -- 1970

1970’• 1970’s processesusually had onlynMOS transistors

– Inexpensive, butconsume power whileidlidle.

• 1980s-present: CMOSprocesses for low idleprocesses for low idlepower

Intel Corporation DRAM

CSCE 5730: Digital CMOS VLSI Design 21

Page 22: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Intel 4004 : 2.3K Transistors (1971)

CSCE 5730: Digital CMOS VLSI Design 22

Page 23: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Pentium : 3.1M Transistors (1993)

CSCE 5730: Digital CMOS VLSI Design 23

Page 24: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Pentium II : 7.5M Transistors (1997)

CSCE 5730: Digital CMOS VLSI Design 24

Page 25: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Pentium III : 28.1M Transistors (1999)

CSCE 5730: Digital CMOS VLSI Design 25

Page 26: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Pentium IV : 52M Transistors (2001)

CSCE 5730: Digital CMOS VLSI Design 26

Page 27: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Core 2 Duo: 291M Transistors (2006)

Core 2 Duo T5000/T7000 series mobile processors, calledPenryn uses 800M of 45 nanometer devices (2007)

CSCE 5730: Digital CMOS VLSI Design 27

Penryn uses 800M of 45 nanometer devices (2007).

Page 28: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Circuit Design Flow

CSCE 5730: Digital CMOS VLSI Design 28

Page 29: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Integrated Circuits Categories There are many different types of ICs as listed below.

IC Categories FunctionsIC Categories FunctionsAnalog ICs Amplifiers

FiltersDigital ICs Boolean Gates

Encoders/DecodersMultiplexers / DemultiplexersFlip-flopsCountersCountersShift Registers

Hybrid ICs Mixed Signal Processorsy gInterface ICs Analog-Digital Converters

Digital-Analog Converters

CSCE 5730: Digital CMOS VLSI Design 29

Page 30: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Levels of Integration (Chip Complexity)Categorized by the number of gates contained in the chip.

IC Number of Functional ExamplesComplexity Gates Complexity

p

SSI <10 Basic gates Inverters, AND gates, OR gates, NANDgates, NOR gatesg g

MSI 10-100 Basic gates Exclusive OR/NORSub modules Adders subtractors encodersSub-modules Adders, subtractors, encoders,

decoders, multiplexers, demultiplexers, counters, flip-flops

LSI 100-1000s Functional modules Shift registers stacksLSI 100 1000s Functional modules Shift registers, stacksVLSI 1000s-

100,000Major building

blocksMicroprocessors, memories

ULSI >100 000 Complete systems Single chip computers digital signalULSI >100,000 Complete systems Single chip computers, digital signalprocessors

WSI >10,000,000 Distributed systems Microprocessor systems

CSCE 5730: Digital CMOS VLSI Design 30

Page 31: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Digital Logic Families• Various circuit technology used to implement an IC at

lower level of abstraction.• The circuit technology is referred to as a digital logic family• The circuit technology is referred to as a digital logic family.

RTL - Resistor-transistor Logic obsoleteDTL Diode transistor logic obsoleteDTL - Diode-transistor logic obsoleteTTL - Transistor-transistor logic not much used

ECL - Emitter-coupled logic high-speed ICsECL - Emitter-coupled logic high-speed ICsMOS - Metal-oxide semiconductor high-component densityCMOS - Complementary Metal-oxide widely used, low-power high-C OS Co p e e a y e a o desemiconductor

de y used, o po e gperformance and high-packingdensity IC

BiCMOS Bi l C l t hi h t d hi h dBiCMOS - Bipolar ComplementaryMetal-oxide semiconductor

high current and high-speed

GaAs - Gallium-Arsenide very high speed circuitsy g p

CSCE 5730: Digital CMOS VLSI Design 31

Page 32: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Design Abstraction Levels

SYSTEM

MODULE

+

GATE

MODULE

CIRCUIT

GATE

GDEVICE

n+n+S

GD

CSCE 5730: Digital CMOS VLSI Design 32

Page 33: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Digital Circuits : Logic to Device

(NAND Gate) (IEC Symbol)( Gate) ( C Sy bo )

(Transistor Diagram) (Layout Diagram)

CSCE 5730: Digital CMOS VLSI Design 33

( g ) (Layout Diagram)

Page 34: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Implementation Approaches for Digital ICs

Digital Circuit Implementation Approaches

Custom Semi-custom

Cell-Based Array-Based

St d d C llStandard Cells Macro Cells Pre-diffused Pre-wired(FPGA)Compiled Cells (Gate Arrays)

CSCE 5730: Digital CMOS VLSI Design 34

Page 35: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Implementation Approaches for Digital ICs• Full-custom: all logic cells are customized. A general purpose

microprocessor is designed this way.• Semi-custom: all of the logic cells are from predesigned cell libraries

(reduces the manufacture lead time of the IC)• Standard-cell based IC uses predesigned logic cells such as ANDStandard cell based IC uses predesigned logic cells such as AND

gates, OR gates, MUXs, FFs,.., etc.• Macrocells (also called megacells) are larger predesigned cells,

h i t ll i tsuch as microcontrollers, even microprocessors, etc.• Gate-Array, Sea-of-Gates or prediffused arrays contains array of

transistors or gates which can be connected by wires to implementg y pthe chip.

• Programmable-Logic-Array (PLA) is an example of fuse-basedFPGA design (NOTE: Fuse based nonvolatile and volatile areFPGA design. (NOTE: Fuse-based, nonvolatile and volatile arethree types of FPGAs)

CSCE 5730: Digital CMOS VLSI Design 35

Page 36: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Digital IC Fabrication Flow

CSCE 5730: Digital CMOS VLSI Design 36

Page 37: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Technology Growth and Moore's Law

CSCE 5730: Digital CMOS VLSI Design 37

Page 38: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Different Attributes of an IC or chipWe will briefly discuss the VLSI technological

growth based on these attributes.g

• Transistor count of a chip

• Operating frequency of a chip

• Power consumption of a chip

• Power density in a chip

• Size of a device used in chip

NOTE: Chip is informal name for IC

CSCE 5730: Digital CMOS VLSI Design 38

NOTE: Chip is informal name for IC.

Page 39: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Moore’s Law

G• 1965: Gordon Moore plotted transistor oneach chip– Transistor counts have doubled every 26 months

• Many other factors grow exponentially– clock frequencyclock frequency– processor performance

CSCE 5730: Digital CMOS VLSI Design 39

Page 40: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Trend

PowerPower,Operatingfrequency andfrequency, andThroughputhavehaveincreased.

1967 2007

VLSI technology is the fastest growing technology in human history.

40

1967 2007

CSCE 5730: Digital CMOS VLSI Design

Page 41: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Technology Scaling Trend

Source: Bendhia 2003

CSCE 5730: Digital CMOS VLSI Design 41

Page 42: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Evolution in Complexity

CSCE 5730: Digital CMOS VLSI Design 42

Page 43: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Why Scaling?

• Technology shrinks by 0.7/generationWi h i i 2 f i• With every generation can integrate 2x more functionsper chip; chip cost does not increase significantly

• Cost of a function decreases by 2x• Cost of a function decreases by 2x• But …

– How to design chips with more and more functions?g p– Design engineering population does not double every two

years…• Hence a need for more efficient design methods• Hence, a need for more efficient design methods

– Exploit different levels of abstraction

CSCE 5730: Digital CMOS VLSI Design 43

Page 44: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Increase in Transistor Count

Pentium IV (55 Million transistors)

Transistors on Lead Microprocessors double every 2 years

CSCE 5730: Digital CMOS VLSI Design 44

Page 45: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Die Size Growth

100m

m)

8080 8086286

386486 Pentium ® procP6

10

e si

ze (m

40048008

80808085

8086Die ~7% growth per year

~2X growth in 10 years

11970 1980 1990 2000 2010

Year

Die size grows by 14% to satisfy Moore’s Law

CSCE 5730: Digital CMOS VLSI Design 45

Page 46: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Increase in Operating Frequency

10000D bl

P6

1000

Mhz

)

Doubles every2 years

P6Pentium ® proc

486386286808510

100

quen

cy (

28680868085

80808008

1

10

Freq

800840040.1

1970 1980 1990 2000 2010C t I t lYear

Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel

CSCE 5730: Digital CMOS VLSI Design 46

Page 47: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Power will be a major problem

5KW18KW

100000

5KW 1.5KW

500W 1000

10000

Wat

ts)

8086286

386486

Pentium® proc

10

100

ower

(W

4004800880808085 386

1

10P

0.11971 1974 1978 1985 1992 2000 2004 2008

YearYear

Power delivery and dissipation will be prohibitive

CSCE 5730: Digital CMOS VLSI Design 47

Page 48: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Power density

10000) Rocket

1000

(W/c

m2

Nuclear

RocketNozzle

100

Den

sity

Reactor

40048008 8085

8086

286 386486

Pentium® procP610

Pow

er

Hot Plate

8080 286 48611970 1980 1990 2000 2010

YYear

Power density too high to keep junctions at low temp

CSCE 5730: Digital CMOS VLSI Design 48

Page 49: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Challenges in Digital Design

“Microscopic Problems” “Macroscopic Issues”Microscopic Problems• Ultra-high speed design• Interconnect• Noise, Crosstalk

p• Time-to-Market• Millions of Gates• High-Level Abstractions,

• Reliability, Manufacturability• Power Dissipation• Clock distribution.

• Reuse & IP: Portability• Predictability• etc.

Everything Looks a Little Different…and There’s a Lot of Them!

CSCE 5730: Digital CMOS VLSI Design 49

Page 50: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Productivity TrendsProductivity Trends

10,000,000 100,000,00010,000(M)

100,000

100,000

1,000,000

1,000,000

10,000,000Logic Tr./ChipTr./Staff Month.

1,000

100

r per

Chi

p

1,000

10,000

ty f -M

o.

xity

1,000

10,000

10,000

100,00058%/Yr. compoundedComplexity growth rate10

1

Tra

nsis

tor

10

100

Prod

uctiv

itTr

ans.

/Sta

ff

Com

plex

10

100

100

1,000xxx

xxx

x21%/Yr. compound

Productivity growth rate

x0.1

0.01

0 001

Logi

c

0 01

0.1

1

P(K

) T

1

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

100.001 0.01

S S t hSource: Sematech

Complexity outpaces design productivityC t ITRS R d

CSCE 5730: Digital CMOS VLSI Design 50

Courtesy, ITRS Roadmap

Page 51: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Trend : CPUVLSI Trend : CPU• Core 2 Duo has 291M transistors (2006).• Core 2 Duo T5000/T7000 series mobile

processors, called Penryn uses 800M of( )45 nanometer devices (2007).

Core 2 Quad: (2006)Source: http://www gearfuse com/

CSCE 5730: Digital CMOS VLSI Design 51

Source: http://www.gearfuse.com/

Page 52: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Trend : GPU

GeForce 6800

Source: GPU Gems 2

CSCE 5730: Digital CMOS VLSI Design52

Source: GPU Gems 2

Page 53: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

VLSI Trend : Salient Points

• Increased Complexity: 340 Billion transistorsIncreased Complexity: 340 Billion transistorsmanufactured in 2006.

(World population 6.5 Billion!)• High Power Dissipation: Power dissipation per transistor

has reduced, but power dissipation of overall chipincreasingincreasing.

• Increased Parallelism with Multicore Architecture: Toarchive highest performance multiples have been putarchive highest performance multiples have been puttogether in the same die.

• Smaller Process Technology: Use of smaller nanoscaleCMOS technology, 32nm node and high- CMOS.

• Reduced Time-to-market: For competitiveness and profit.

CSCE 5730: Digital CMOS VLSI Design53

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Circuit Design Metrics

CSCE 5730: Digital CMOS VLSI Design 54

Page 55: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Design Metrics

H t l t f f di it l• How to evaluate performance of a digitalcircuit (gate, block, …)?

C t– Cost– Reliability

Scalability– Scalability– Speed (delay, operating frequency)– Power dissipation– Power dissipation– Energy to perform a function

CSCE 5730: Digital CMOS VLSI Design 55

Page 56: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Cost of Integrated Circuits

• NRE (non-recurrent engineering) costsdesign time and effort mask generation– design time and effort, mask generation

– one-time cost factorR t t• Recurrent costs– silicon processing, packaging, test– proportional to volume– proportional to chip area

CSCE 5730: Digital CMOS VLSI Design 56

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NRE Cost is Increasing

CSCE 5730: Digital CMOS VLSI Design 57

Page 58: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Die Cost

Single die

Wafer

G i t 12” (30 )Going up to 12” (30cm)

CSCE 5730: Digital CMOS VLSI Design 58

Page 59: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Cost per Transistor

0 10 111

cost: cost: ¢¢--perper--transistortransistor

Fabrication capital cost per transistor (Moore’s law)

0 0010 001

0.010.01

0.10.1 Fabrication capital cost per transistor (Moore s law)

0.000010.00001

0.00010.0001

0.0010.001

0.00000010.0000001

0.0000010.000001

19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012

CSCE 5730: Digital CMOS VLSI Design 59

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Yield%100

per wafer chipsofnumber Totalper wafer chips good of No.

Ypp

yieldDieper waferDiescostWafer cost Die

yieldDieper waferDies

areadie2

diameterwafer areadie

diameter/2wafer per wafer Dies2

areadie2areadie

CSCE 5730: Digital CMOS VLSI Design 60

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Defects

area dieareaunit per defects1yield die

is approximately 3

44area)(diecost die f

NOTE: Solve Example 1.3 , page-18 of Rabaey text book.

CSCE 5730: Digital CMOS VLSI Design 61

p , p g y

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Some Examples (1994)So e a p es ( 99 )Chip Metal

lLine idth

Wafer t

Def./ 2

Area 2

Dies/f

Yield Die tlayers width cost cm2 mm2 wafer cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601 4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0 70 $1700 1 6 256 48 13% $272Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

CSCE 5730: Digital CMOS VLSI Design 62

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Reliability―Noise in Digital Integrated CircuitsNoise in Digital Integrated Circuits

v(t) VDD

i(t)v(t) VDD

Inductive coupling Capacitive coupling Power and groundnoise

CSCE 5730: Digital CMOS VLSI Design 63

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Mapping between analog and digital signalspp g g g g

V

Slope = -1V OH

Vout

V

VOH“ 1”

OHVIH

Undefined

DC Operation:Voltage Transfer

Ch t i tiUndefinedRegion

Characteristic

Slope = -1

V OL“ 0” V

VIL

V IL V IH V in

OL0 VOL

CSCE 5730: Digital CMOS VLSI Design 64

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Definition of Noise Marginsg

"1"

VNoise margin high

VIHUndefined

VOH NMH

Noise margin lowVIL

UndefinedRegion

VONML g

"0"

VOL

Gate Output Gate Input

CSCE 5730: Digital CMOS VLSI Design 65

Page 66: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Noise Budget

• Allocates gross noise margin to expectedsources of noisesources of noise

• Sources: supply noise, cross talk, interference,offsetoffset

• Differentiate between fixed and proportionalnoise sources

CSCE 5730: Digital CMOS VLSI Design 66

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Key Reliability Properties• Absolute noise margin values are deceptive

– a floating node is more easily disturbed than a node driven by alow impedance (in terms of voltage)

• Noise immunity is the more important metric – thebilit t icapability to suppress noise sources

• Key metrics: Noise transfer functions, Output impedance of thedriver and input impedance of the receiver;driver and input impedance of the receiver;

CSCE 5730: Digital CMOS VLSI Design 67

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Fan-in and Fan-out

MN

M

Fan-out N Fan-in M

CSCE 5730: Digital CMOS VLSI Design 68

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The Ideal Gate

V out

Ri = Ro = 0o Fanout = NMH = NML = VDD/2g = NMH NML VDD/2

V in

CSCE 5730: Digital CMOS VLSI Design 69

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Delay Definitions

Vin

50%

t t

t

Vout

tpHL tpLH

90%90%

50%

tf trt10%

CSCE 5730: Digital CMOS VLSI Design 70

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A First-Order RC Network

voutR

vin C

tp = ln (2) t = 0.69 RC

Important model – matches delay of inverter

CSCE 5730: Digital CMOS VLSI Design 71

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Power Dissipation

Instantaneous power:Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power: P = V iPpeak = Vsupplyipeak

Average power:Average power:

Tt Ttsupply d

VdP )(1

t t supplysupply

ave dttiT

dttpT

P )(1

CSCE 5730: Digital CMOS VLSI Design 72

Page 73: Lecture 2: VLSI Overview - Saraju MohantyLecture 2: VLSI Overview CSCE 5730 Digital CMOS VLSI Design Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides

Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =Energy Delay Product (EDP)

quality metric of gate = E tp

CSCE 5730: Digital CMOS VLSI Design 73

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Summary

• Digital integrated circuits have come a long way andg g g ystill have quite some potential left for the comingdecadesS i t ti h ll h d• Some interesting challenges ahead– Getting a clear perspective on the challenges and potential

solutions is the purpose of this bookp p• Understanding the design metrics that govern digital

design is crucialC t li bilit d d di i ti– Cost, reliability, speed, power and energy dissipation

CSCE 5730: Digital CMOS VLSI Design 74