Lecture19 Timing

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EE141 EECS141 1 Lecture #19


  Project Phase 2 now on the web-site.   Hw 6 due today.   New homework to be posted in a week.   Cory Hall closed on Monday (Power Outage)

  Instructional computers in 353 Cory should come back on line on Tu.

 Enjoy Spring Break!

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 Last lecture  Registers

 Today’s lecture   Timing

 Reading (Ch 10)


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D Clk

Q D Clk

Q

  Register: edge-triggered stores data when clock rises

Clk Clk D D Q Q

  Latch: level-sensitive clock is low - hold mode clock is high - transparent


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D Clk

Q

D

Q

Clk tclk-q thold

PWm tsetup

td-q

Delays can be different for rising and falling data transitions

T


D Clk

Q

D

Q

Clk

tclk-q

thold

T

tsetup

Delays can be different for rising and falling data transitions

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tclk-q tclk-q,min

tlogic tlogic,min

tsetup, thold


Cycle time (max): TClk > tclk-q + tlogic + tsetup

Race margin (min): thold < tclk-q,min + tlogic,min

tclk-q tclk-q,min

tlogic tlogic,min

tsetup, thold

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  Clock skew   Spatial variation in temporally equivalent clock

edges; deterministic + random, tSK

  Clock jitter   Temporal variations in consecutive edges of the

clock signal; modulation + random noise   Cycle-to-cycle (short-term) tJS   Long term tJL

  Variation of the pulse width   Important for level sensitive clocking


Sources of clock uncertainty

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  Both skew and jitter affect the effective cycle time and the race margin

Clk

Clk

tSK

tJS


# of registers

Clk delay Insertion delay Max Clk skew

Earliest occurrence of Clk edge Nominal – δ/2

Latest occurrence of Clk edge

Nominal + δ /2

δ

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Launching edge arrives before the receiving edge

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Receiving edge arrives before the launching edge

CLK1

CLK2

T CLK

δ

T CLK - δ

2

1

4

3


Minimum cycle time: Tclk + δ = tclk-q + tsetup + tlogic

Worst case is when receiving edge arrives early (negative δ)

tclk-q tclk-q,min

tlogic tlogic,min

tsetup, thold

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Hold time constraint: t(clk-q,min) + t(logic,min) > thold + δ

Worst case is when receiving edge arrives late Race between data and clock

tclk-q tclk-q,min

tlogic tlogic,min

tsetup, thold


Clk TCLK

tsetup tclk-Q tlogic

Latest point of launching

Earliest arrival of next cycle

tJS - δ

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If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

tclk-q + tlogic + tsetup < TCLK – tJS,1 – tJS,2 + δ

tclk-q + tlogic + tsetup - δ + 2tJS < TCLK

Skew can be either positive or negative


Clk tclk-q,min

tlogic,min

Earliest point of launching

Data must not arrive before this time

Clk thold

Nominal clock edge

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Minimum logic delay

If launching edge is early and receiving edge is late:

tclk-q,min + tlogic,min – tJS,1 > thold + tJS,2 + δ

tclk-q,min + tlogic,min > thold + 2tJS+ δ (This assumes jitter at launching and receiving clocks are independent – which usually is not true)


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Reference Pipelined


(Domino logic almost always uses latch-based clocking)

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  In a flip-flop based system:   Data launches on one rising edge

–  And must arrive before next rising edge   If data arrives late, system fails

–  If it arrives early, wasting time   Flip-flops have hard edges

  In a latch-based system:   Data can pass through latch while it is transparent   Long cycle of logic can borrow time into next cycle

–  As long as each loop finished in one cycle


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  Flip-flops generally easier to use   Most digital ASICs designed with register-based

timing   But, latches (both pulsed and level-sensitive)

allow more flexibility   And hence can potentially achieve higher

performance   Latches can also be made more tolerant of clock

un-certainty   More in EE241


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 Make things cheaper:  Want to sell more functions (transistors)

per chip for the same money  Or build same products cheaper   Price of a transistor has to be reduced

 But also want to be faster, smaller, lower power…


  Benefits of 30% “Dennard” scaling (1974):   Double transistor density   Reduce gate delay by 30% (increase operating

frequency by 43%)   Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequency)   Die size used to increase by 14% per

generation (not any more)   Technology generation spans 2-3 years

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2X reduction every ~5 years

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tp decreases by 30%/year f increases by 43%

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EE141 EECS141 37 Lecture #16 From Kuroda


• Full Scaling (Constant Electrical Field)

• Fixed Voltage Scaling

• General Scaling

ideal model — dimensions and voltages scale together by the same factor S

most common model until 1990’s only dimensions scale, voltages remain constant

most realistic for today’s situation — voltages and dimensions scale with different factors

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  W, L, tox: 1/S   VDD, VT: 1/S

  Area: WL   Cox: 1/tox   CL: CoxWL   ID: Cox(W/L)(VDD-VT)2

  Req: VDD/IDSAT

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  W, L, tox: 1/S   VDD, VT: 1/S

  tp: ReqCL

  Pavg: CLVDD2/tp

  Pavg/A: CoxVDD2/tp


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  W, L, tox: 1/S   VDD, VT: 1/S

  Area: WL   Cox: 1/tox   CL: CoxWL   ID: WCoxvsat(VDD-VT-VVSAT/2)

  Req: VDD/IDSAT


  W, L, tox: 1/S   VDD, VT: 1/S

  tp: ReqCL

  Pavg: CLVDD2/tp

  Pavg/A: CoxVDD2/tp

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  What will did cause this model to break?   Leakage set by kT/q

–  Temp. does not scale –  VT set to minimize power

  Power actually increased –  Leakage increased drastically –  f increased faster than device speed – Hit cooling limit

  Process Variation – Hard to build very small things accurately (less

averaging)

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Lecture19 Timing