11
3642 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Linear Voltage-Control Scheme With Duty-Ratio Feedforward for Digitally Controlled Parallel Inverters Xiaotian Zhang, Student Member, IEEE, and Joseph W. Spencer Abstract—When a classical digital controller is applied to paral- lel inverters, there is a tradeoff with respect to the stability, dynamic response, and control accuracy. In a practical design, the stability of the system should be considered first. To ensure sufficient mar- gin in stability in a digitally controlled system, the proportional gains in the feedback path are limited. To solve these problems, a linear voltage-control scheme with duty-ratio feedforward is pro- posed. The control parameters are chosen according to the stable operating condition derived in the z-domain. In this paper, the closed-loop transfer function and output impedance for both the classical controller and the proposed controller are derived the- oretically. A comparison reveals the advantages of the proposed control scheme, i.e., a unity closed-loop gain, no phase shift, good current sharing, and low total harmonic distortion of the output voltage. The theoretical results are verified by the experimental setup of a system with two digitally controlled inverters connected in parallel. Index Terms—Digital control, duty-ratio feedforward, linear voltage control, parallel inverters, z-domain model. I. INTRODUCTION I N DIGITALLY controlled parallel inverters, the concept of “wireless” is becoming particularly interesting. Since the load sharing performance is influenced by the output filter and the line impedance between each inverter, designing the con- troller usually determines how accurately the inverters share the load. For inverters with the same circuit and control param- eters, it seems that the load can be shared equally. However, due to inconsistencies in the filter and measurement parame- ters between each inverter, guaranteeing equal sharing under all circumstances is not straightforward. For this reason, droop con- trol methods have been developed [1]–[17], which are suitable for parallel inverters with considerable unknown differences of the filter parameters and line impedance between each module. This strategy is based on the conventional frequency and voltage droop according to the output power, which achieves accurate active power sharing but cannot achieve accurate reactive power sharing due to the mismatched line impedances [1], [2]. Manuscript received January 14, 2011; revised March 18, 2011, April 30, 2011; accepted May 15, 2011. Date of current version December 6, 2011. Rec- ommended for publication by Associate Editor Y.-M. Chen. The authors are with the Department of Electrical Engineering and Elec- tronics, University of Liverpool, Liverpool, L69 3GJ, U.K. (e-mail: xiaotian@ liv.ac.uk; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2011.2157834 In order to improve the sharing accuracy of the reactive or harmonic current, the frequency droop method has been ex- tended [3]. However, it is not practical to inject a series of har- monic signals and calculate the power for each component. More realistic methods are proposed in [4], [5], and [6], which enforce the output impedance of the inverters. Output current feedback is used as a virtual impedance loop in these methods. To suppress the harmonic distortion when nonlinear loads are connected, the voltage reference is generated with a droop according to each harmonic component of the output current [7], [8]. This har- monic sharing method is similar to the scheme proposed in [9], which can be considered as decreasing the magnitude of output impedance at harmonic frequencies. These control strategies are all combined with the droop methods to obtain a good sharing accuracy. In the previous literature, sharing is mainly implemented by using droop control methods. For a high-performance parallel inverters’ system, droop controller may result in poor transient response performance [18] or reduced voltage regulation due to the frequency changes. For digitally controlled parallel inverters connected with short cables (small line impedance), the droop controller can be removed if the voltage controller is capable of overcoming the asymmetric hardware parameters. Without droop controller, synchronizing inverters to the grid is straight- forward. However, if the controller is insufficient to achieve accurate load sharing, the droop controller must be used to compensate the error. In order to achieve a good controller, the feedback gains of the inverters at the fundamental and harmonic frequencies should be relatively high. The proportional gains of each inverter are usually limited, since it will reduce the sta- bility margin significantly in digitally controlled systems [19]. Therefore, an additional resonant compensator is proposed to enhance the gain at the fundamental frequency [13], [14]. The proportional plus resonant compensator can achieve high gain at selected frequencies, reducing the sensitivity versus the circuit parameters (including parasite parameters). Nevertheless, when this controller is applied, the tradeoff between stability, dynamic performance, and control accuracy has to be made. With higher proportional gains applied, the steady-state error is reduced, but the system may become unstable. On the other hand, a compen- sator with a high gain resonated at the fundamental frequency has little influence on stability, but it brings significant phase shift, especially, when the line frequency varies (which is even worse when the droop controller is used). In this paper, the stability of the digitally controlled in- verter is investigated. The limitation of the proportional gains is 0885-8993/$26.00 © 2011 IEEE

Linear Voltage-Control Scheme With Duty-Ratio Feedforward for Digitally Controlled Parallel Inverters

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3642 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Linear Voltage-Control Scheme With Duty-RatioFeedforward for Digitally Controlled

Parallel InvertersXiaotian Zhang, Student Member, IEEE, and Joseph W. Spencer

Abstract—When a classical digital controller is applied to paral-lel inverters, there is a tradeoff with respect to the stability, dynamicresponse, and control accuracy. In a practical design, the stabilityof the system should be considered first. To ensure sufficient mar-gin in stability in a digitally controlled system, the proportionalgains in the feedback path are limited. To solve these problems, alinear voltage-control scheme with duty-ratio feedforward is pro-posed. The control parameters are chosen according to the stableoperating condition derived in the z-domain. In this paper, theclosed-loop transfer function and output impedance for both theclassical controller and the proposed controller are derived the-oretically. A comparison reveals the advantages of the proposedcontrol scheme, i.e., a unity closed-loop gain, no phase shift, goodcurrent sharing, and low total harmonic distortion of the outputvoltage. The theoretical results are verified by the experimentalsetup of a system with two digitally controlled inverters connectedin parallel.

Index Terms—Digital control, duty-ratio feedforward, linearvoltage control, parallel inverters, z-domain model.

I. INTRODUCTION

IN DIGITALLY controlled parallel inverters, the concept of“wireless” is becoming particularly interesting. Since the

load sharing performance is influenced by the output filter andthe line impedance between each inverter, designing the con-troller usually determines how accurately the inverters share theload. For inverters with the same circuit and control param-eters, it seems that the load can be shared equally. However,due to inconsistencies in the filter and measurement parame-ters between each inverter, guaranteeing equal sharing under allcircumstances is not straightforward. For this reason, droop con-trol methods have been developed [1]–[17], which are suitablefor parallel inverters with considerable unknown differences ofthe filter parameters and line impedance between each module.This strategy is based on the conventional frequency and voltagedroop according to the output power, which achieves accurateactive power sharing but cannot achieve accurate reactive powersharing due to the mismatched line impedances [1], [2].

Manuscript received January 14, 2011; revised March 18, 2011, April 30,2011; accepted May 15, 2011. Date of current version December 6, 2011. Rec-ommended for publication by Associate Editor Y.-M. Chen.

The authors are with the Department of Electrical Engineering and Elec-tronics, University of Liverpool, Liverpool, L69 3GJ, U.K. (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2157834

In order to improve the sharing accuracy of the reactive orharmonic current, the frequency droop method has been ex-tended [3]. However, it is not practical to inject a series of har-monic signals and calculate the power for each component. Morerealistic methods are proposed in [4], [5], and [6], which enforcethe output impedance of the inverters. Output current feedback isused as a virtual impedance loop in these methods. To suppressthe harmonic distortion when nonlinear loads are connected, thevoltage reference is generated with a droop according to eachharmonic component of the output current [7], [8]. This har-monic sharing method is similar to the scheme proposed in [9],which can be considered as decreasing the magnitude of outputimpedance at harmonic frequencies. These control strategies areall combined with the droop methods to obtain a good sharingaccuracy.

In the previous literature, sharing is mainly implemented byusing droop control methods. For a high-performance parallelinverters’ system, droop controller may result in poor transientresponse performance [18] or reduced voltage regulation due tothe frequency changes. For digitally controlled parallel invertersconnected with short cables (small line impedance), the droopcontroller can be removed if the voltage controller is capableof overcoming the asymmetric hardware parameters. Withoutdroop controller, synchronizing inverters to the grid is straight-forward. However, if the controller is insufficient to achieveaccurate load sharing, the droop controller must be used tocompensate the error. In order to achieve a good controller, thefeedback gains of the inverters at the fundamental and harmonicfrequencies should be relatively high. The proportional gains ofeach inverter are usually limited, since it will reduce the sta-bility margin significantly in digitally controlled systems [19].Therefore, an additional resonant compensator is proposed toenhance the gain at the fundamental frequency [13], [14]. Theproportional plus resonant compensator can achieve high gain atselected frequencies, reducing the sensitivity versus the circuitparameters (including parasite parameters). Nevertheless, whenthis controller is applied, the tradeoff between stability, dynamicperformance, and control accuracy has to be made. With higherproportional gains applied, the steady-state error is reduced, butthe system may become unstable. On the other hand, a compen-sator with a high gain resonated at the fundamental frequencyhas little influence on stability, but it brings significant phaseshift, especially, when the line frequency varies (which is evenworse when the droop controller is used).

In this paper, the stability of the digitally controlled in-verter is investigated. The limitation of the proportional gains is

0885-8993/$26.00 © 2011 IEEE

ZHANG AND SPENCER: LINEAR VOLTAGE-CONTROL SCHEME WITH DUTY-RATIO FEEDFORWARD 3643

Fig. 1. Single-phase digitally controlled inverter. (a) Power circuit. (b) Con-troller.

obtained, which must be followed during the design. A goodtradeoff between stability and control accuracy is achieved byusing a linear voltage-control scheme [20], [21] with duty-ratiofeedforward [22]. Compared to the classic proportional plus theresonant controller, the proposed linear voltage-control schemewith duty-ratio feedforward highlights many advantages such assimple structure, low sensitivities, good sharing performance,and higher output voltage quality. The theoretical results havebeen verified by the experimental setup consisting of two digi-tally controlled inverters connected in parallel.

II. LIMITATION OF PROPORTIONAL GAINS IN DIGITALLY

CONTROLLED INVERTERS

The typical power-circuit prototype and controller for avoltage-controlled inverter are shown in Fig. 1. The powercircuit consists of an H bridge and an output LC filter. Thecontroller, as shown in Fig. 1(b), is a cascaded digital con-troller consisting of a capacitor voltage and an inductor cur-rent feedback with duty-ratio feedforward. The inductor currentis sensed for the internal-current feedback loop, where i∗L isthe ideally sampled quantity. Although the capacitor currentfeedback is an alternative solution, since the load usually hasa negligible dynamic behavior, the two feedback schemes areequivalent [23]. The capacitor voltage is sensed for the external-voltage feedback loop, where v∗

o is the ideally sampled quan-tity. Both the sampling period and the switching period areTs = 1/fs . The duty-ratio calculated from the samples is up-dated at each sampling instant; therefore, the duty-ratio updatedelay1 is z−1 . In digitally controlled systems, using the s-domainmodel for stability analysis will lead to inaccurate results. There-fore, in order to choose the control parameters in the feedbackpath, the stability of the system is studied in the small-signalz-domain.

The small-signal z-domain model [24] is applied to the digitalcontroller with cascaded control loops. The current control loopwith a digital pulse width modulator (PWM) modeled by a

1Once the circuit variables are sampled, the digital processor calculates theduty-ratio value, which needs some time. In the same time, the PWM compareregister is waiting for the next sampling instant to update the duty-ratio value.Hence, this duty-ratio update delay has already included the computation delay.

Fig. 2. Model for the current control loop of the digitally controlled inverter.

pulse-to-continuous transfer function G∗PWM(s) is represented

as in Fig. 2. If the average duty ratio D is scaled into the rangeof 0 ≤ D ≤ 1, where D = 0 and D = 1 represent the inverterachieving minimum output −Vdc and maximum output Vdc ,respectively, the transfer function of the zero-order-hold (ZOH)and PWM in the small-signal model can be represented as

G∗PWM(s) = Ts(αe−sτ1 + (1 − α)e−sτ2 ) (1)

where the ratio α (0 ≤ α ≤ 1) is the duration of the fallingedge of the carrier relative to the sampling period Ts , which canresult in end-of-on-time sawtooth, begin-of-on-time sawtooth,and symmetric-on-time triangle carriers. τ1 = (α − αD)Ts andτ2 = (α + D − αD)Ts . In (1), the gain Ts and the delay e−sτ1 , 2

are introduced by the ZOH and the PWM generator, respectively.Assuming that the total delay of the switches drive and signals’transport is τi , when the cable resistance is negligible and a pureresistor R is loaded in Fig. 1(a), the transfer function from u∗ toi∗L in the z-domain can be derived as

Giu (z) = Z{G∗PWM(s)VdcGiL vs

(s)e−sτi } (2)

with

GiL vs(s) =

s/L + 1/LCR

s2 + s(1/CR + rL/L) + (R + rL )/LCR. (3)

This z-transform can be derived by splitting Giu (z) into

Giu (z)=αVdcTs

(Aie

a(τ1 +τi −Ts )

z − e−aTs+

Bieb(τ1 +τi −Ts )

z − e−bTs

)

+(1−α)VdcTs

(Aie

a(τ2 +τi −Ts )

z − e−aTs+

Bieb(τ2 +τi −Ts )

z − e−bTs

)

(4)

with

a =12

(1

CR+

rL

L+√

Δ)

, b =12

(1

CR+

rL

L−√

Δ)

,

Δ =(

1CR

+rL

L

)2

− 4(R + rL )LCR

, Ai =aCR − 1

LCR(a − b),

and

Bi =1 − bCR

LCR(a − b).

Hence, the transfer function Giu (z) becomes

Giu (z) =Ni1z + Ni0

z2 + D1z + D0(5)

with Ni1 =VdcTs(αAie−a(Ts−τ1−τi ) +(1−α)Aie

−a(Ts −τ2 −τi ) +αBie

−b(Ts −τ1 −τi ) + (1 − α)Bie−b(Ts −τ2 −τi )), Ni0 = −Vdc

3644 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Ts D0 (αAi ea(τ1 + τi ) + (1 − α)Aie

a(τ2 +τi ) + αBieb(τ1 +τi ) +

(1 − α)Bieb(τ2 +τi )), D1 = −e−aTs − e−bTs , and D0 =

e−(a+b)Ts . The discrete-time closed-loop transfer function fromi∗ref to u∗ without feedforward is written as

G1(z) =kc

Vd cz−1

1 + kc

Vd cz−1Giu (z)

. (6)

The characteristic equation of (6) is

z3 + D1z2 +

(D0 +

Ni1kc

Vdc

)z +

Ni0kc

Vdc= 0. (7)

It can be derived that D0 = e−(1/RC +rL /L)Ts and Ai + Bi =1L . If fs � 1√

LC, fs � rL

L , and the delay τi is very small com-pared to one switching period, under the extreme condition of

no load, i.e., R = ∞, it can be approximated that a = j√

1LC ,

b = −j√

1LC (the real parts of a and b are much smaller than

their imaginary parts), D0 = 1, and D1 = −2 (the absolutevalue of D1 reduces if fs

√LC is close to 1). When the sawtooth

carriers are used, e.g., the end-of-on-time carrier with α = 0 andτ2 = DTs , Ni1 and Ni0 , respectively, becomes

Ni1 = VdcTs

((Ai + Bi) cos

(√1

LC(1 − D)Ts

)

−j(Ai − Bi) sin

(√1

LC(1 − D)Ts

))(8)

and

Ni0 = −VdcTsD0

((Ai + Bi) cos

(√1

LCDTs

)

+j(Ai − Bi) sin

(√1

LCDTs

)). (9)

If the assumption of the cos(√

(1/LC)DTs

)≈ 1 is used,

(Ai + Bi) cos(√

(1/LC)DTs) is much bigger than (Ai −Bi) sin(

√(1/LC)DTs). Then, the approximation of Ni1 =

VdcTs/L and Ni0 = −VdcTs/L can be obtained. Similarly,when the triangle carriers are used, e.g., the symmetric-on-time carrier with α = 1/2, τ1 = (1 − D)Ts/2, and τ2 =(1 + D)Ts/2, the approximation of Ni1 = VdcTs/L and Ni0 =−VdcTs/L can be derived using the same approach. Substi-tuting the approximated values of D0 = 1, D1 = −2, Ni1 =VdcTs/L, and Ni0 = −VdcTs/L into (7), the equation becomes(

z2 − z +Tskc

L

)(z − 1) = 0. (10)

If Tskc/L < 0, the pole

z =12

+12

√1 − 4Tskc

L

will be out of the unit circle. If Tskc/L > 1, there will be twoconjugated poles out of the unit circle. Therefore, the internal

TABLE 1PARAMETERS OF THE INVERTER

Fig. 3. Root loci of the internal current loop. (a) End-of-on-time modulatorwith D = 0.75. (b) Symmetric-on-time modulator with D = 0.5.

loop stable condition is

0 < kc <L

Ts. (11)

Numerical results are also provided to verify the approximatedanalytical stability condition (11). By using the parameters inTable I, the root loci of the internal loop with different carriersare shown in Fig. 3. The accurate results for maximum kc canbe obtained. In Fig. 3(a) and (b), the maximum gain values arekc = 27.7 and kc = 28.5, respectively, which are smaller thanthe analytical result of L/Ts = 32.8 in (11). This is becausethat the numerical result of D0 = −1.83 (fs

√LC = 2.55) and

the approximation of D0 = −2 (fs

√LC � 1) are different.

However, regardless of the carriers and average duty ratio, theapproximated result in (11) is acceptable, and kc is usuallymuch smaller than the critical value L/Ts in practice. This kc

is also related to the external-voltage loop stability. In order tofind proper control parameters, the entire model of the cascadedcontroller is required [18].

The digitally controlled inverter with cascaded control loopsis schematically represented in Fig. 4, where

Gvo vs(s) =

1/LC

s2 + s(1/CR + rL/L) + (R + rL )/LCR.

(12)The discrete transfer function from u∗ to v∗

o is written as

Gvu (z) = Z{G∗PWM(s)VdcGvo vs

(s)e−sτv } (13)

ZHANG AND SPENCER: LINEAR VOLTAGE-CONTROL SCHEME WITH DUTY-RATIO FEEDFORWARD 3645

Fig. 4. Model for the cascaded control loops of the digitally controlled inverter.

with τv a negligible delay introduced by the drive and transport.The transfer function Gvu (z) can be derived as

Gvu (z)=αVdcTs

(Avea(τ1 +τv −Ts )

z − e−aTs+

Bveb(τ1 +τv −Ts )

z − e−bTs

)

+(1−α)VdcTs

(Avea(τ2+τv −Ts )

z − e−aTs+

Bveb(τ2 +τv −Ts )

z − e−bTs

)

(14)

with Av = −1/LC(a − b) and Bv = 1/LC(a − b). Therefore,Gvu (z) can be written in a shorter form as

Gvu (z) =Nv1z + Nv0

z2 + D1z + D0(15)

with Nv1 =VdcTs(αAve−a(Ts−τ1−τv ) +(1−α)Ave−a(Ts −τ2 −τv )

+ αBve−b(Ts −τ1 −τv ) + (1 − α)Bve−b(Ts −τ2 −τv )) and Nv0 =−VdcTs D0 (αAv ea(τ1 +τv ) + (1 − α)Avea(τ2 +τv ) + αBv ×eb(τ1 +τv ) + (1 − α)Bveb(τ2 +τv )). Hence, according to Fig. 4,the closed-loop transfer function from v∗

ref to v∗o without

feedforward can be written as

G2(z) =Gv (z)G1(z)Gvu (z)

1 + Gv (z)G1(z)Gvu (z). (16)

The stability usually limits the proportional gains in the digitallycontrolled converters [19]. Root loci are used to find the propervalue of kv . To ensure enough stability, kc = 8 is chosen. Then,the external-voltage loop stability can be studied based on thez-domain closed-loop transfer function of (16). With the param-eters in Table I, when the inverter is not loaded, the root lociof the external voltage loop with different carriers and averageduty ratios are shown in Fig. 5.

It can be seen in Fig. 5(a) and (b) that the external-voltage-loop stability condition for the end-of-on-time modulator is de-pendent on D. When D = 0.5 and D = 0.75, the critical valuesare given by kv = 0.108 and kv = 0.091, respectively. How-ever, for the symmetric-on-time modulator, the stable conditionis always kv < 0.108. This is because when the end-of-on-timecarrier is used, the transfer function of G∗

PWM(s) = Tse−sDTs

is dependent on D, and consequently, the closed-loop transferfunction of (16) is also dependent on D. When D is bigger,the delay is bigger and the stable range of kv is reduced, whichis a big disadvantage for its application in an ac system. Onthe other hand, when the triangle carriers are used, the ap-proximation of G∗

PWM(s) = Tse− s T s

2 [18] results in an averageduty-ratio-independent transfer function. The delay is half of

Fig. 5. Root loci of the external current loop. (a) End-of-on-time modulatorwith D = 0.5. (b) End-of-on-time modulator with D = 0.75. (c) Symmetric-on-time modulator with D = 0.5. (d) Symmetric-on-time modulator with D =0.75.

the switching period. In this case, the closed-loop transfer func-tions are almost the same with different D values. Therefore,the stability condition slightly differs while D is changing. Thestability condition for triangle carriers is also equivalent to thecondition when sawtooth carriers are used with D = 0.5 (half ofthe switching period delay). As uniform sampling with a saw-tooth carrier cannot obtain the average values of the inductorcurrent and avoid switching noises [25], [26], in this paper thesymmetric-on-time modulator is used. The proportional gainsare chosen as kc = 8 and kv = 0.05 to ensure stability. Theproportional gains are also associated with the inverter outputimpedance, which will be illustrated in the next section.

III. CONTROLLER DESIGN FOR POWER SHARING

The closed-loop transfer function and output impedance areinvestigated in this section. The analysis is performed in largesignal to obtain duty-ratio-independent transfer functions. How-ever, the analysis should be restricted to the frequency rangeunder the half of the sampling frequency fs/2. The exact modelof the digitally controlled inverter is shown in Fig. 6, where thePWM equivalent delay GPWM(s) is comprised of the duty-ratioupdate delay and the switching delay. Since the duty ratio is up-dated at each sampling instant, the duty-ratio update delay isone switching period. If the symmetric-on-time carrier is used,the switching delay is approximately equivalent to a half of theswitching period [26]. As a result, GPWM(s) can be written as

GPWM(s) = e−32 sTs . (17)

3646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Fig. 6. Model of the digitally controlled inverter.

In Fig. 6, the ideal samplers are used to take the samples into thedigital controller. On the other hand, the samples are convertedto continuous-time signals by ZOHs. The transfer function ofthe ideal sampler is 1/Ts , if the input signal contains frequen-cies lower than fs/2 [27]. The transfer function of the ZOHis known as G∗

ZOH(s) = 1 − e−sTs /s. Moreover, the transferfunctions of GiL d(s), Gvo d(s), GiL io

(s), and Gvo io(s) in Fig. 6

are expressed as

GiL d(s) =sCVdc

s2LC + srLC + 1(18)

Gvo d(s) =Vdc

s2LC + srLC + 1(19)

GiL io(s) =

1s2LC + srLC + 1

(20)

and

Gvo io(s) =

sL + rL

s2LC + srLC + 1(21)

respectively.The digital compensator in the voltage-control loop is a func-

tion of z. There are two design strategies for digital controllers.One is the direct digital design [24] based on the z-domainmodel. The other one is the indirect design, which converts theknown s-domain controller into the z-domain [26]. For ac sys-tems, where resonant controllers are used, the indirect design isvery good at implementing the continuous-time transfer func-tions. Hence, in this paper, the indirect design is used and thecompensator is designed into the z-domain by using bilineartransform. The voltage compensator is obtained from a knownGv (s) by

Gv (z) = Gv (s)|s= 2T s

z −1z + 1

. (22)

In reverse, mathematically, Gv (s) = Gv (z)|z= 1 + s T s / 2

1−s T s / 2. As

is known that z = esTs ≈ 1+sTs /21−sTs /2 , therefore, Gv (z) =

Gv (z)|z=es T s ≈ Gv (z)|z= 1 + s T s / 2

1−s T s / 2= Gv (s). Similarly, kc and

kff in the digital controller are also equivalent to theircontinuous-time transfer function for the frequency lower thanfs/2. Therefore, the transfer function of the voltage path inFig. 6 is equivalent to

Gvp(s) = Gv (s)GZOH(s) (23)

with GZOH(s) being the transfer function of the ideal sam-pler and the ZOH. It is approximated that GZOH(s) =1 − e−sTs /sTs . The transfer functions of the current path andthe feedforward path are

Gcp(s) =kc

VdcGZOH(s) (24)

and

Gffp(s) =kff

VdcGZOH(s) (25)

respectively. Hence, the continuous equivalent transfer functionsfor the entire digital controller are derived and the analysis ofload sharing performance can be studied. According to Fig. 6,the closed-loop transfer function from vref to vo is, as shown(26), at the bottom of the page and the output impedance transferfunction from io to vo is, as shown (27), at the bottom of thepage.

A. Proportional Plus Resonant Feedback Control

As described in the previous section, for digitally controlledconverters, the proportional gains are limited by the stabilityconditions. In practice, the integral compensator, resonant com-pensator or repetitive compensator, etc. is used together withthe proportional compensator to improve the steady-state per-formance. For an ac system operating at the fundamental fre-quency, the integral compensator is not usually used since it hashigh gain in the low-frequency range. However, the resonantcompensator has high gain at resonant frequency and low gainat other frequencies. Therefore, the proportional plus resonantcompensator is widely used to enhance the control accuracy inac systems. This compensator implemented in the digital con-troller is derived by using bilinear transform, which is writtenas

GvP R (z) = kv + k1az1z

2 + bz1z + cz1

Az1z2 + Bz1z + Cz1(28)

with Az1 = 4T 2

s+ 4ξω1

Ts+ ω2

1 , Bz1 = − 8T 2

s+ 2ω2

1 , Cz1 =4

T 2s− 4ξω1

Ts+ ω2

1 , az1 = 4ξω1Ts

, bz1 = 0, and cz1 = − 4ξω1Ts

. Thecontinuous equivalent s-domain transfer function of GvP R (z)is

GvP R (s) = kv + k12ξω1s

s2 + 2ξω1s + ω21. (29)

G(s) =(Gvp(s)Gcp(s) + Gffp(s))VdcGPWM(s)

s2LC + sC(Gcp(s)VdcGPWM(s) + rL ) + Gvp(s)Gcp(s)VdcGPWM(s) + 1(26)

Z(s) =sL + (Gcp(s)VdcGPWM(s) + rL )

s2LC + sC(Gcp(s)VdcGPWM(s) + rL ) + Gvp(s)Gcp(s)VdcGPWM(s) + 1. (27)

ZHANG AND SPENCER: LINEAR VOLTAGE-CONTROL SCHEME WITH DUTY-RATIO FEEDFORWARD 3647

To evaluate the proportional plus resonant compensator, the per-formance at the fundamental frequency is studied. It can be de-rived that ω2

1LC = 0.0016 and ω1C = 0.0031 Ω−1 . Therefore,at the fundamental frequency, the denominators of (26) and (27)are mainly determined by Gvp(s)Gcp(s)VdcGPWM(s) + 1.When the proportional plus resonant compensator without feed-forward (kff = 0) is used [14], the gain of the closed-loop trans-fer function approaches unity when the gain in the feedback path,i.e., Gvp(s)Gcp(s) is high enough. Since ω1L = 0.515 Ω, at thefundamental frequency, Gcp(s)VdcGPWM(s) is much highercompared to sL in (27). Therefore, with a relative big k1 , theoutput impedance magnitude at the fundamental frequency isclose to 1/k1 . At harmonic frequencies, the output impedancemagnitude of the proportional plus resonant compensator con-trolled inverter is nearly kc/(kvkc + 1). As described in theprevious section, kv should be small enough to ensure the in-verter stability, which will lead to big output impedances atharmonic frequencies. When nonlinear loads are connected, thecurrent containing harmonic frequencies on the respective con-siderable output impedance will result in voltage distortion. Inorder to be able to trade off between voltage distortion andsharing performance, additional feedback has to be used [7].

B. Linear Voltage Feedback Scheme Using Duty-RatioFeedforward

Since the voltage on the inverter side inductor is usuallyvery small, the average switch voltage Vdcd and the outputvoltage vo are almost identical. Therefore, by adding the voltagereference value directly to the PWM, the compensator only hasto compensate for the small difference between Vdcd and vo

instead of compensating for vo entirely [22]. With duty-ratiofeedforward, the tracking error will be much smaller. Accordingto Fig. 1, the feedforward duty ratio is

dff = kffvref

Vdc. (30)

As illustrated in the previous section, when a classic propor-tional plus resonant compensator without feedforward (kff = 0)is used, the gain of G(s) close to unity is achieved by a largenumerator of (26), i.e., by choosing a large gain of Gv (s)kc . Aresonant compensator with high gain can achieve large Gv (s)at the fundamental frequency. However, high resonant gain willbring big phase error around the resonant frequency, which isnot acceptable in practice. When feedforward (kff = 1) is ap-plied, the gain of G(s) is always close to unity. Hence, in thecase of feedforward, the steady-state accuracy does not dependon a high gain in the feedback path. On the other hand, theclassic proportional plus resonant compensator arrangement isdesigned for linear load sharing [14]. In this case, additionalcompensation has to be used for nonlinear load sharing. In [7]and [8], an additional output current feedback scheme is pro-posed to achieve the required virtual impedance at hth harmonicfrequency, where the measurement of output current is neces-sary. Therefore, to avoid using additional measurements, the

Fig. 7. Root loci of the external voltage loop when resonant compensators areused. (a) Proportional compensator plus fundamental frequency resonant com-pensator. (b) Proportional compensator plus 13th harmonic frequency resonantcompensator.

linear voltage compensator written as

Gv (z) = kv +13∑

h=1,odd

khazhz2 + bzhz + czh

Azhz2 + Bzhz + Czh(31)

is used, with Azh = 4T 2

s+ 4ξωh

Ts+ ω2

h , Bzh = − 8T 2

s+

2ω2h , Czh = 4

T 2s− 4ξωh

Ts+ ω2

h , azh = 4ξωh

Ts, bzh = 0, and

czh = − 4ξωh

Ts. The respective continuous equivalent voltage

compensator is

Gv (s) = kv +13∑

h=1,odd

kh2ξωhs

s2 + 2ξωhs + ω2h

. (32)

It can be approximated from (27) that the output impedance athth harmonic frequency is comprised of two parts in parallel,i.e., kc/(kvkc + 1) and 1/kh . Compared to the classic propor-tional plus resonant compensator (h3,odd = 0), the proposedlinear voltage compensator has fixed the impedance at each har-monic frequency (less than 13th). The advantage of choosing asmall kv is that the output impedance in the low-frequency rangeis large. With a large output impedance in the low-frequencyrange, it has good suppression of low frequency and dc currentcirculating in the parallel inverters. On the other hand, at hthharmonic frequencies, the output impedance magnitude is ap-proximately equal to 1/kh , which can be adjusted according tothe requirement. The most important parameters of the linearvoltage compensator are ξ and kh . Again, the stability conditionshould be satisfied first. As is shown in (19), the absolute valuesof azh and czh are almost as ξωhTs times as the absolute valuesof Azh and Czh . If the value of khξωhTs is much smaller thankv , the proportional gain is more dominant for the stability con-dition. Normally, it is true that khξωhTs � kv . Fig. 7 shows theroot loci of voltage loop when resonant compensators are usedwith the proportional compensator. When the additional com-pensator resonates at the fundamental frequency, the root lociare derived by increasing kv while maintaining k1 = 260kv .When the additional compensator resonates at 13th harmonicfrequency, the root loci are derived by maintaining k13 = 20kv .With ξ = 0.01 [20], in both cases khξωhTs = 0.041kv is sat-isfied. It can be seen from Fig. 7(a) and (b) that the stability

3648 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

TABLE 2PARAMETERS OF THE CONTROLLER

boundaries are reduced to kv < 0.098 and kv < 0.097, respec-tively. However, it can be seen that in practice with relative smallresonant gains, the proportional gain is the most important factorfor stability. Note that the harmonic resonant frequency cannotapproach the sampling frequency. If a very high ωh is required,the relevant gain kh should be reduced to maintain the stability.The frequency domain response with different kh , ξ, and ωh hasbeen studied in [21] for compensators’ design. These resultscan also be used for the design of the resonant compensators.A bigger ξ results in a wider passband, but there is a tradeoffbetween passband and stability. A bigger kh results in highertracking capability and lower output impedance, but the sharingaccuracy will decline if the cable impedance is large. Usually,kh is chosen according to the output power level. When thesystem is designed for high output current, kh should be bigand although the circular current increases, it is small comparedto the high output current. On the contrary, if the system isoperating in low power level, kh should be relatively small tosuppress the circular current. Although the output impedance isthen increased, such small output current results in acceptablevoltage droop and distortion. With properly adjusted kh and kv

according to the output power level, a good tradeoff of currentsharing and output voltage quality can be achieved.

The control parameters are chosen as listed in Table II. Figs. 8and 9 show the Bode diagrams of the closed-loop transfer func-tion and the output impedance, respectively. It can be seen fromFig. 8 that as a relative small resonant gain (k1 = 20kv ) is used,the gain of the closed-loop transfer function at the fundamen-tal frequency for the classic proportional plus resonant controlscheme is close to unity (|G(jω1)| = 0.89). However, there is alarge phase error when the frequency varies around the funda-mental frequency, which will be increased by higher resonantgains. In contrast, by using the proposed linear voltage-controlscheme with duty-ratio feedforward, the gain of the closed-looptransfer function is unity (|G(jω1)| = 1.0) and the phase erroraround the fundamental frequency is close to zero, achieving

Fig. 8. Bode diagram of the closed-loop transfer function (full line: linearvoltage-control scheme with duty-ratio feedforward; dashed line: classic pro-portional plus resonant control scheme).

Fig. 9. Bode diagram of output impedance (full line: linear voltage-controlscheme with duty-ratio feedforward; dashed line: classic proportional plus res-onant control scheme).

good tracking performance. On the other hand, the feedforwarddoes not affect the system stability, since the structure of thefeedback loop is not changed by the feedforward.

The output impedance Bode diagram (see Fig. 9) shows thatthe classic proportional plus resonant compensator has a re-sistive output impedance with magnitude close to 1

k1= 1.0

at the fundamental frequency. However, the magnitude of theoutput impedance at other harmonic frequencies is close tokc/(kvkc + 1) = 5.7. In contrast, the output impedance mag-nitude of the proposed linear voltage compensator at each har-monic frequency is almost equal to 1/kh = 1.0. With a relativelarge value of kh , the output-voltage distortion can be suppressedby the linear voltage compensator.

C. Sensitivities of the Closed-Loop Transfer Function andOutput Impedance

In practical parallel inverter systems, there are small dif-ferences between the parameters for each module. Assuming

ZHANG AND SPENCER: LINEAR VOLTAGE-CONTROL SCHEME WITH DUTY-RATIO FEEDFORWARD 3649

Fig. 10. Sensitivities of the closed-loop transfer function versus filter param-eters (full line: L = 1642 μH and rL = 0.4 Ω; dashed line: L = 2100 μH andrL = 1 Ω).

that the drivers, switches, and DSPs have negligible difference,the main difference usually comes from measurements and fil-ters. By using calibrated analog-to-digital converter (ADC), themeasurements deviations can be eliminated. However, the pa-rameters of the filters are fixed and the differences cannot beeliminated. Then, a good controller means, by using this con-troller in each inverter, the parameters differences between dif-ferent modules are negligible in the power sharing point of view.Since there is no additional droop control, the sensitivities ofthe closed-loop transfer function and output impedance versusfilter parameters should be reduced. The sensitivities versus thecapacitance of the LC filter are not of interest since the ca-pacitors poles are connected in parallel through short cables tothe point of common couple (PCC). These capacitors can beconsidered as a lumped capacitor. Therefore, the sensitivitiesversus the inductance and the parasite resistance of the filterdetermine the sharing accuracy. By using the proposed linearvoltage compensator with duty-ratio feedforward, the sensitiv-ity of the closed-loop transfer function versus the inductanceand the parasite resistance is, as shown (33), at the bottom ofthe page.

On the other hand, the sensitivity of the output impedanceversus the inductance and the parasite resistance is, as shown(34), at the bottom of the page.

It can be seen from (33) and (34) that at any harmonic fre-quency, when higher gain of Gv (jωh)kc is achieved, the sen-sitivities of the closed-loop transfer function and the outputimpedance will be significantly reduced. Figs. 10 and 11 showthe Bode diagrams of the closed-loop transfer function andthe output impedance with different filter parameters, respec-

Fig. 11. Sensitivities of the output impedance versus filter parameters (fullline: L = 1642 μH and rL = 0.4Ω; dashed line: L = 2100 μH and rL = 1Ω).

Fig. 12. Schematic of the experimental setup of the parallel inverters system.

tively. When a large difference exists in filter parameters, thegains of the closed-loop transfer function at the fundamentalfrequency are almost identical (see Fig. 10). Although the out-put impedances have magnitude difference (see Fig. 11), thisdifference does not affect the sharing performance too much(error is less than 10%). Since the linear voltage compensatorachieves high gains at resonant frequencies, the filter parame-ters discordance can be neglected from sharing accuracy pointof view.

IV. EXPERIMENTAL RESULTS

The sharing performance was experimentally evaluated bytwo 115 V, 1 kW inverters connected in parallel. The circuitparameters in Table I are used. The experimental setup of theparallel inverters system is shown in Fig. 12. Two invertersare synchronized to the grid and connected to the common

∂G(s)∂(sL + rL )

= − sC(Gvp(s)Gcp(s) + Gffp(s))VdcGPWM(s)(s2LC + sC(Gcp(s)VdcGPWM(s) + rL ) + Gvp(s)Gcp(s)VdcGPWM(s) + 1)2 . (33)

∂Z(s)∂(sL + rL )

= − Gvp(s)Gcp(s)VdcGPWM(s) + 1(s2LC + sC(Gcp(s)VdcGPWM(s) + rL ) + Gvp(s)Gcp(s)VdcGPWM(s) + 1)2 . (34)

3650 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

Fig. 13. Output voltage and currents of the two parallel inverters with the proportional plus resonant and droop controller (X-axis: time, 5 ms/div; Y-axis:magnitude of output currents and voltage; Channel 1: output current of Inverter 1, 5 A/div; Channel 2: output current of Inverter 2, 5 A/div; Channel 3: outputvoltage, 50 V/div). (a) Linear loads. (b) Linear load and nonlinear load. (c) Nonlinear load.

Fig. 14. Output voltage FFT results of the two parallel inverters with the proportional plus resonant and droop controller (X-axis: Frequency, 125 Hz/div; Y-axis:magnitude, 10 dB/div; Window: flattop). (a) Linear loads. (b) Linear load and nonlinear load. (c) Nonlinear load.

loads through HO5VV-F cables. The resistances of the cablesof Inverters 1 and 2 are 0.071 and 0.047 Ω, respectively. Theinductances of the cables are negligible (less than 0.1 μH).The inductor’s parameters of Inverters 1 and 2 are L1 = 1632μH (and rL1 = 0.38 Ω) and L2 = 1623 μH (and rL2 = 0.39Ω), respectively. The filter capacitances are C1 = 10.3 μF andC2 = 10.2 μF, respectively. Due to the experimental condition,the output currents are measured by two shunt resistors (withrsh1,2 = 0.1 Ω, ±1% resistance tolerance). The oscilloscope isTektronix TDS 2014B with four nonisolated channels, whosegrounds are all connected at the PCC in Fig. 12.

The control method was implemented using twoTMS320F28335 from Texas Instruments. The H bridges of thebuck inverters are Mitsubishi Intelligent Power Modules (IPM).The switches are driven indirectly via optical couplers and thedeadband time is 2.67 μs. The symmetric-on-time modulator isused and the duty-ratio is updated at each sampling instant. Themeasurements are calibrated from power circuit side to ADCside. By producing a group of reference dc current or voltagesignals on measurements’ input (x1 , x2 , . . . , xn ), there are agroup of digital output values from the ADC (y1 , y2 , . . . , yn ).When the linear combination of polynomial basis functions isused, these overdetermined equations related to the ADC out-put values and real circuit values are solved with least-squaresmethod. For an analog current or the voltage value of x, themeasured digital value of ADC is y. The required linear func-tion is assumed to be p(y) = β1y + β0 , where the result of p(y)should approach the value of x. Define x = (x1 , x2 , . . . , xn )T ,

β = (β1 , β0)T , y = (y1 , y2 , . . . , yn )T , and

M =[

y1 y2 · · · yn

1 1 · · · 1

]. (35)

The coefficients β1 and β0 are related to the overdeterminedequation MTβ = x. However, β1 and β0 can be solved by theleast-squares method

β = (MMT)−1Mx. (36)

The experimental waveforms and the relevant fast Fourier trans-form (FFT) results of the classic proportional plus resonantcontroller with the droop method are shown in Figs. 13 and 14,respectively. The parameters in Table II are used, without har-monic compensators and feedforward. Since changing operatingfrequency may result in a poor resonant control performance,the droop method of P − V droop and Q − φ boost is used [8],with the droop coefficient and boost coefficient of 1 × 10−5 and1 × 10−4 , respectively. Although the current sharing (3.6 A) isgood when linear loads are connected [see Fig. 13(a)], the out-put voltage amplitude is only 99 V. When a nonlinear load isconnected, the output voltage is severely distorted [Fig. 13(b)and (c)]. The FFT results of the output voltage when a nonlinearload is connected [Fig. 14(b) and (c)] show that the output volt-age has much higher distortion compared to the results whenonly linear loads are connected [Fig. 14(a)]. The distortion onthe output voltage also affects the output current waveforms.When a linear load and a nonlinear load are connected, the cal-culated output-voltage total harmonic distortion (THD) result is

ZHANG AND SPENCER: LINEAR VOLTAGE-CONTROL SCHEME WITH DUTY-RATIO FEEDFORWARD 3651

Fig. 15. Output voltage and currents of the two parallel inverters with the proposed controller (X-axis: time, 5 ms/div; Y-axis: magnitude of output currents andvoltage; Channel 1: output current of Inverter 1, 5 A/div; Channel 2: output current of Inverter 2, 5 A/div; Channel 3: output voltage, 50 V/div). (a) Linear loads.(b) Linear load and nonlinear load. (c) Nonlinear load.

Fig. 16. Output voltage FFT results of the two parallel inverters with the proposed controller (X-axis: frequency, 125 Hz/div; Y-axis: magnitude, 10 dB/div;Window: flattop). (a) Linear loads. (b) Linear load and nonlinear load. (c) Nonlinear load.

2.9%. When one nonlinear load is connected, the THD is 5.3%.Note that the maximum THD 5% limit was established by theinternational regulations [28]. The output-voltage distortion isnot well suppressed by the classic controller without additionalcompensation.

To obtain a relatively fair comparison between the two con-trol schemes, the same parameters listed in Table II are used forthe proposed controller. The experimental output currents andvoltage waveforms of the proposed control scheme are shownin Fig. 15. The relevant output voltage FFT results are shownin Fig. 16. The output currents of the two inverters are clearlyequal (3.9 A) with linear loads connected. Moreover, the outputvoltage is pure sinusoidal and the RMS value is 112 V [see Fig.15(a)]. When a nonlinear load is connected, the output voltage isdistorted [see Fig. 15(b) and (c)] due to the existence of the lineimpedances and output impedances. However, with properly de-signed output impedance, the distortion can be suppressed underacceptable tolerance. When a linear load and a nonlinear load areconnected, the output-voltage THD is 1.2%. When a nonlinearload is connected, the THD is 1.5%. A comparison of the exper-imentally measured performance of the two control schemes issummarized in Table III. It can be seen that in an environmentwith a highly distorted output current, output-voltage distortionis inevitable. However, compared to the classic proportionalplus the resonant controller, the proposed linear voltage-controlscheme with duty-ratio feedforward is more capable to providea better voltage-tracking capability and lower output-voltagedistortion to improve the output-voltage quality.

TABLE 3OUTPUT PERFORMANCE COMPARISON OF THE CLASSIC CONTROLLER AND THE

PROPOSED CONTROLLER

V. CONCLUSION

For wireless-connected parallel inverters connected throughshort cables, high sharing accuracy can be achieved by usingproperly designed controller without droop control. The designof the controller is very important. In digitally controlled invert-ers, the internal-current-loop proportional gain is limited by thefilter inductance and the sampling frequency, while the external-voltage-loop proportional gain is also limited by stability con-ditions. To improve the sharing accuracy and voltage quality,the control scheme of the linear voltage compensator with duty-ratio feedforward is used. The theoretical analysis shows thatthe closed-loop transfer function using the proposed controlscheme remains unity gain over a wide frequency range. Com-pared to a classic proportional plus resonant control scheme, theclosed-loop transfer function of the proposed control scheme has

3652 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011

better voltage-tracking performance and less phase er-rors around the fundamental frequency. The virtual outputimpedance resonated at harmonic frequencies suppresses theharmonic distortion when nonlinear loads are connected. Theexperimental comparison between the proposed control schemeand the classic proportional plus resonant control scheme re-veals the main features of the parallel inverters using the linearvoltage compensator with duty-ratio feedforward: good sharingaccuracy, better voltage-tracking capability, and lower THD ofthe output voltage.

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Xiaotian Zhang (S’11) was born in Xi’an, China, in1983. He received the B.S. (Hons.) and M.S. degreesin electrical engineering from Jiaotong University,Xi’an, China, in 2006 and 2009, respectively.

Since 2009, he has been with the Department ofElectrical Engineering and Electronics, University ofLiverpool, Liverpool, U.K. His research interests in-clude modeling, control, and nonlinear phenomenaof switching converters, power factor correction, andgrid-connected inverters for distributed generation.

Joseph W. Spencer received the B.Eng (Hons.) andPh.D. degrees in electrical engineering from the Uni-versity of Liverpool, Liverpool, U.K.

He became an Academic Staff Member in 1989and is currently the Director for the Centre of Intelli-gent Monitoring Systems and Head of the Departmentof Electrical Engineering and Electronics, Universityof Liverpool. He worked in the industrial sector re-lated to high voltage engineering for many years.

Dr. Spencer is a member of an international studygroup on arc discharges and Honorary Treasure for

the series of international conferences on gas discharges and their applications.He is also a Fellow of the Institution of Engineering and Technology.