We started with an nMOS pass element but realized right away that this wasn't going to work properly.

DCOP when running nMOS pass element, notice that the output seen is 3 V

DC Sweep with nMOS pass element; notice how the output starts from 2.4 V even when the input is 3.4V. Looking at this we knew that the reason because of this was that our pass element needed to be in the linear region at all times. In order to do so, we needed to use a pMOS pass element.

Schematic of Linear Voltage regulator with a one stage op amp and cMOS pass element with 3 mA load

Schematic showing the DCOP of the Device. The output is more closer to 3 V

DC Sweep from 3.15 V to 7.5 V. The voltages shown are really close to 3 V.

A zoomed out view of the DC sweep where one can not really see a difference in the voltage output graph (yellow).

AC analysis of one stage op amp showing that it is stable.

After observing that our one stage op amp was working correctly and was stable we decided that it was time to implement our error amplifier as a a two stage opamp. We knew that an nMOS pass element would not work well so we used a pMOS pass element of the same width and length as in our one stage op amp. The width and length of the two stage op amp used was the same as the width and lengths used in our labs 6 and 7. The pass element width and length was chosen so that the device would stay in the triode/linear region of operation.

Schematic of overall ldo showing the 2 stageopamp as a symbol and using a PMOS device as a pass element

schematic for checking stability of linear voltage regulator (LDO); notice how the negative feedback is broken so that the transfer function/bode plot can be analyzed from there

Graph showing the stability of our two stage opamp

schematic showing specs of the PMOS pass element

schematic showing the PWL setup, as you can see in the voltage source labeled as VDD

PWL analysis of Linear voltage regulator

schematic showing various loads, the one with that is the most stable is the one with longer range of ~3V input

stability of the the 2 stage op amp

DC Sweep of LDO, notice how output (yellow) is around 3V for a large amount of range of inputs

PWL of LDO, taking a step back, as you can see there is a little dip when voltage input changes; however the voltage output remains relatively around 4 pm.

This is the same exact image as the first one except you are looking at each graph generated individually

PWL with no load, not a large dip

PWL with 3mA load; notice the large dip when changing the input voltage drastically

References Rincon-Mora, Gabriel A. Analog IC Design with Low-dropout Regulators. New York: McGraw-

Hill, 2009. 

G. A. Rincon-Mora and P. E. Allen,  Study and design of low drop-out regulators,  submitted to IEEE Trans. Circuits Syst. 

B. Razavi, Design of CMOS Integrated Circuits, McGraw Hill, 2001  Jim Williams (March 1, 1989). "High Efficiency Linear Regulators" A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, Wiley, New York, 1984.