S E C T I O N S

Summer 2003 Yield Management Solutions36

Get ready for slowdown in deviceshrinks, shift litho R&D to otherissues, says NIST directorBy J. Robert LinebackThe Semiconductor Reporterwww.semireporter.com

Feb. 24, 2003 Karen H. Brown

SANTA CLARA, Calif. — The semiconductor i n d u s t rym u s t so o n sh i f t its emphasis from steadily shrinking devicefeature sizes on two-year technology cycles to muchb roader eff o rts in cost reduction and wafer-fab pro d u c t i v i t yif chip makers want to continue leveraging Moore's Lawthis decade, warned the deputy director of the U.S.National Institute of Standards and Technology ( N I S T )h e re in a speech before lithography expert s .

Dubbing the upcoming period a "lithographer's vacation,"K a ren H. Brown cautioned that optical e x p o s u re tools —s u c h as new 193-nm scanners — and photomask pro c e s s e swere simply unable to keep up with the accelerateddevice-shrink targ e t s now contained in the industry'stechnology roadmap. Instead of forcing optical tools top r i n t feature sizes much smaller than 60-to-50 nano-meters, the chip industry must take a different tack and much-needed break from the aggre s s i v e shrinks oftransistor gates and half-pitch design rules no widelyassociated with Moore's Law, Bro w n told a couple hundredexperts at KLA-Tencor Corporation's Lithography UsersForum prior to the start of the SPIE Microlithographyconference in Santa Clara.

"If the tool isn't going to make smaller feature sizesbecause you have reached the physical limits, then maybethose people [lithographers] can work on something elsefor a while," she told the group, which responded withnervous laughter. Later, while Brown fielded questionsat the Sunday evening event, one lithography expertasked if it was going to be a "paid vacation."

Brown then admitted that the term "vacation" may notbe the best way to describe the upcoming period forl i t h o g r a p h y development, but she urged attendees ofthe SPIE Microlithography conference this week to lookbeyond the technologies and processes that were mostfamiliar to them.

"There are a lot of technologies out there that can becost effective and save a lot of money for specific levels

What happened to cheaperand not just smaller inMoore's Law?Somewhere along the way in the past three decades,Moore's Law — the industry's gauge for predictingtransistor integration on ICs — turned into mostly a rule for device shrinks with heavy emphasis onaggressive lithography technologies, observed KarenH. Brown, deputy director of the U.S. NationalInstitute of Standards and Technology (NIST).

It was not always that way, she noted during herspeech before a group of lithography and metrologyexperts Sunday night in Santa Clara before the startof this week's SPIE Microlithography conference.

Ever since Intel Corp. co-founder Gordon Moore firstproposed the his curve for doubling transistors on achip every 18 to 24 months in the mid-60s, Moore'sLaw has become a golden rule to keep the chipindustry on track with next-generation process tech-nologies and integration on a die. But the emphasistoday may be too much on costly lithography shrinkswith not enough attention to Moore's law for lowercosts, Brown told the group.

"In some ways it [Moore's law] is the same but insome ways it has changed. Originally, it was [focusedon] transistors per chip or unit area, but that trans-lated into cost per function because if you can stuffmore transistors into the same area, you get morefunctions for the same amount of cost or less cost perfunction," she noted. However, the emphasis sincethe mid-1990s "became the lithography feature size."

Summer 2003 Yield Management Solutions 37

used in photomasks and device structures," said Brown,who is also acting director of NIST and a former direc-tor of lithography at industry consortium InternationalSematech.

"You don't have to take cost out at the gate level. Costcan be taken out at other levels and you can take costout by how you do the design," she told the group, sug-gesting that a variety of lithography technologies couldhelp to solve the high cost of photomasks and otherprocesses while 157-nm and extreme ultraviolet (EUV)lithography is given more time for development.

The dilemma facing the semiconductor industry iswhether or not to press harder to ready 157-nm wave-length lithography tools for production in just a coupleyears or to continue using complicated and expensive re s-olution enhancement techniques in reticles to printsmaller feature sizes with 193-nm scanners. Not all ofthe experts attending the lithography meeting on

Sunday agreed with Brown, but the NIST deputy direc-tor p redicted that existing optical lithography systems andp ro c e s s e s would no longer support device shrinks after2004 or 2005.

" S o m e w h e re in here," she said, pointing to slide showing ap l o t for device shrinks in the industry's lithographyroadmap, "things are going to slow down because 157-nmisn't going to be in manufacturing in 2005, and EUVLwill probably not be in manufacturing in 2006. So theindustry is going to have to figure out how to look atwhat we have [here] and deal with the reality of the situation — things are not going to shrink as fast as weshow here." Brown added that the industry must alsowork harder to "fig u re out how to deal with the pro b l e min an economical and cost-effective way."

B rown suggested that the upcoming "lithographer'sv a c a t i o n " period could be used to help improve existingoptical lithography systems and photomask technologiesto put them back on track in terms of cost for many ICapplications — such as lower volume ASICs. The timecould also be used to help struggling lithographyequipment makers, photomask shops and other infra-structure suppliers recoup investments while re g a i n i n gfinancial health after the industry's worst downturn ever,she added.

A c c o rding to Brown, it takes $200 to $300 million tod e v e l o p a lithography tool, which today might haveonly a lifecycle of two years — "the 157-nm tools areprojected to be in use [for critical dimensions] from2005 to 2007," she said, referring to current roadmaptargets of EUV lithography being i n t roduced around the2007 timeframe for the 45-nm pro c e s s technology node.

"You cannot recover your investment. You can hardlymake them work right," Brown warned. "So it is achance for equipment companies — especially in thistimeframe when money is not just pouring in the doors— to look at how they are spending the money, and doit more cost eff e c t i v e l y ... It is a balancing scenario — howdo we use this time to catch up and have more coste ffective tools and more robust pro c e s s e s ? "

" A ff o rdability and cost are issues we need to think about.We need to make smaller feature sizes — yes — and weneed to do other things — yes — but we need to dothem cost effectively," said Brown, a former IBM Corp.lithography researcher and developer for 22 years. "Weneed cost-effective resolution enhanced masks [such asoptical proximity correction, or OPC, and phase-shift-ing]. That means masks will not cost $400,000 apiece,"she added, referring to current projections of $1 millionor more per photomask set in 90-nm processes.

"We need development of mask infrastructure because itis lagging behind, and it does not allow us to do manythings cost effectively or at all. Perhaps we could [cutcosts and implement shrinks] if we spent time, energy,and money on that," Brown said.

Copyright 2003, Intervalis LLC

In her talk before the KLA-Tencor-hosted g a t h e r i n g ,B rown proposed going back to the original emphasisof cost-per-function "or something else as defined by Moore's Law" without "necessarily having thelithography line [for shrinks] going straight down."

Without some new approach — such as immersionl i t h o g r a p h y, which is now being studied as a potentialoptical lithography extender — Brown suggested thatthe photolithography curve for shrinks will flattenout or only go down slightly from 2004 until nearlythe end of decade. "We need new technology now tocontinue the shrinks," she said, adding that 157-nmand EUV lithography are not even close to pro v i d i n gfeasible solutions in the next couple of years.

"My prediction is the industry will find a new solution — a new paradigm for how to makeM o o re's Law stay on track in cost-per-function," she said, suggesting that designers work more closely with lithographers and process engineersto keep technology from stalling out. "Maybeslower cycles in feature size shrinks will allowm o re cost-effective tool development because youhave more time and re s o u rces to focus on specifictypes of answers."

She urged better communications between lithog-raphy and design groups. Perhaps that means lith-ography engineers will have to impose strict limitsand rules on IC designers, who cannot break theimposed design rules for the next four or five years— even with resolution enhancement techniques,B rown suggested. "Maybe lithographers shouldbecome designers," she added.

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