A Scan Architecture For High Test Coverage & Low Power Consumption

7th July 2015Binod KumarM.Tech(EE)

Outline

Two conflicting goals in the Scan technique Logic Insertion between Scan chains Introduction to California Scan Architecture(CSA) Working of CSA Results of CSA An alternative architecture to CSA Algorithm followed by the alternative architecture Proposal of a new architecture based on CSA Proof of Suitablity of the new architecture

Two Conflicting Goals in the Scan technique

Most of the bits in test patterns generated by automatic test pattern generation (ATPG) tools are dont-care bits.

To reduce power consumption during scan shift-in operation, dont-care bits can be assigned using the repeat-fill technique.

To enhance defect coverage, dont-care bits can be assigned using the random-fill technique. But this approach increases overall power consumption during the scan shift-in operation.

Logic Insertion between Scan chains

Scan Chain modification has been sugested to overcome the abnormal switching activity during the scan shift operation

In this example, to scan-in 1010 requires 3 toggles whereas the modified pattern 1101 requires 2 toggles.

CALIFORNIA SCAN ARCHITECTURE(CSA)

Proposed by Kyoung Youn Cho, Subhasish Mitra and Edward J. McCluskey in ITC 2007.

CSA provides a trade-off between test quality and power consumption by modifying test patterns during the scan shift-in operation.

Scan chain modification method changes scan chain paths for a specific test set that contains only care bits while CSA utilizes dont-care bit assignments to reduce switching activity during the scan shift operation.

CSA provides a modified version, rather than an exact copy, of the scan shift-in pattern to the combinational logic.

CALIFORNIA SCAN ARCHITECTURE(CSA)

Above are 2 possible implementations of CSA.

Types of Pattern Filling

Repeat Filling-assigns the last care bit 0 filling-fills with all zeroes 1 filling-fills with all ones Random Filling-fills randomly Toggle Filling-assigns dont-care bits using logic-0

and logic-1 alternately. These assignments can improve defect coverage while they increase switching activity during the scan shift-in operation

Illustration of Types of Pattern Filling

Technique ATPG provided pattern Filled Pattern

0 filling 10xxxxxx1xx1 100000001001

1 filling 10xxxxxx1xx1 101111111111

Repeat filling 10xxxxxx1xx1 100000001111

Random filling 10xxxxxx1xx1 100100101001

Toggle filling 10xxxxxx1xx1 101010101101

Working of the CSA

In CSA, the test patterns that are shifted into scan chains have their dont-care bits assigned using the repeat-fill technique.The patterns applied to the combinational logic are altered in the test application process so that they correspond to toggle-fill patterns.

This modification of patterns enhances the defect coverage of test patterns.

CSA operation

This table shows correspondence between scan shift-in patterns and patterns applied to the combinational logic.It is clear that CSA does not depend on a specific test set or scan flip-flop reordering.

States of scan cells during scan shift-in

Pattern to be applied to the combinational logic is 01101010 wich is fairly random & hence not affecting test coverage while scan-in pattern is 11000000 which has very less switching activity.

Experimental Results Of CSA

Authors have compared the results of their own architecture with the following architectures:

1.Traditional Scan architecture with repeat filling

(TSA_rpt)

2.Traditional Scan architecture with random filling

(TSA_rnd)

In results,their architecture is represented as CSA_rpt since CSA also employs repeat filling.

A possible implementation of Traditional Scan architecture(TSA) is shown beow:

Experimental Results Of CSA (b19)

Experimental Results of switching activity for SSF test sets

CSA results for SSF test sets

In the case of the SSF test sets, The number of observed gate input combinations shows a bettercorrelation with defect detection than the SSF coverage. An observed gate input combination of an internal gate is a logic combination applied to the gate inputs with the gate output being sensitized to at least one observation point, such as a primary output or a scan flip-flop .

CSA_rpt provides more Gate Input Combinations (GIC) compared to TSA_rpt.

CSA results for SSF test sets

Experimental Results-->N-detect coverage: SSF test sets

Alternative to CSA

This architecture employs selective connection of the Q' of one flipflop to D of the next flipflop.

This method finds out the scan-in pattern from the pattern provided by the ATPG tool without employing any pattern filling technique whereas CSA finds out the scan-in pattern after the pattern filling has been done.

Alternative to CSA

Algorithm followed by the alternative architecture

The Disadvantage with CSA

Let's consider that we need to apply the pattern 0000000 to the combinational logic.

By CSA,101010 has to be scanned in resulting in a larger switching activity,instead scanning in 0000000 itself is a wise option.

Cell6 cell5 cell4 cell3 cell2 cell1

0 1 ? ? ? ? ?

1 0 0 ? ? ? ?

0 1 1 1 ? ? ?

1 0 0 0 0 ? ?

0 1 1 1 1 1 ?

1 0 0 0 0 0 0

The Disadvantage with CSA

CSA pays the penalty of higher scan-in shift power for those patterns which have no (or very less) bit transitions in them because even for them it needs a toggled pattern to be scanned in.

A mechanism which decides in an intelligent way for what is to be scanned in after seeing the pattern to be applied.

Proposed architecture

Idea is to achieve the low switching activity of CSA_rnd and high test coverage of TSA_rnd.

We propose to employ XOR instead of the inverter employed in CSA.

Operation of the Proposed architecture

XOR operation is like: c=(not a)b + a(not b) Here, a=scanbit_applied,

b=select_xor,

c=scan_in When b=0,c=a (BUFFER operation)

scan_in is same as scanbit_applied When b=1,c=(not a)

INVERTER operation as CSA. select_xor decides what is to be scanned in depending on the pattern

which is to be applied to the combinational logic (which has been provided by the ATPG tool)

Proof of the suitablity of the proposed architecture.

To check whether buffer-insertion or inverter insertion is beneficial for lower scan-in switching activity , counting of patterns for ISCAS'89 circuits was done to find out the number of patterns that give less toggling with buffer insertion and those that give less toggling with inverter insertion.

3 kinds of pattern filling(0 fill,repeat fill,random fill) were tried out.

Procedure applied for random fill

Step 1:

Find the pattern which needs to be scanned-in as per CSA(inverter insertion) from the pattern given by ATPG tool (after random fill)

Step 2:

Count the number of toggles in the pattern found out in Step 1. Step 3:

Count the number of toggles present in the pattern itself. Step 4:

if Step 2 count is less then this pattern needs inverter insertion otherwise this pattern needs buffer insertion(that is to say it is to be scanned-in as it is).Mark this pattern accordingly in the appropriate category.

Repeat the above steps for all the patterns and then do counting of patterns in the two Categories.

ISCAS'89 circuits: Random fill

circuit Total patterns Less-toggles-buffer Less-toggles-inv.

s1196 148 74 74

s9234 130 56 74

s38417 335 212 123

s38584 125 57 68

s15850 115 55 60

s13207 128 63 65

ISCAS'89 circuits:Repeat fill,0 fill

circuit patterns buffer inverter

s13207 128 128 0

s15850 115 113 2

circuit patterns buffer inverter

s13207 128 125 3

circuit 115 112 3

0 fill Repeat fill

DISCUSSION

For random fill,The number of patterns which give less less toggles with buffer and those which give less less toggles with inverter is almost equal suggesting that almost for half of the patterns we can save the unnecessary switching activity arising out of the inverter insertion as propsed in CSA architecture.

Experiment employing TetraMax can give exact fault coverage for different kinds of test sets.

References

Sinanoglu, O. and A. Orailoglu, Modeling Scan Chain Modifications for Scan-in Test Power Minimization, Proc. Intl. Test Conf ., pp. 602-611, 2003.

Kyoung Youn Cho, Subhasish Mitra, and Edward J. McCluskeyCalifornia Scan Architecture for High Quality and Low Power Testing,INTERNATIONAL TEST CONFERENCE(ITC),2007.

S. Gupta, T. Vaish and S. Chattopadhyay, Flip-flop chaining architecture for power-efficient scan during test application, in Proc. Asia Test Symp., pp. 410- 413, 18-21, Dec. 2005.

Cho, K. Y., S. Mitra, and E. J. McCluskey, Gate Exhaustive Testing, Proc. Intl. Test Conf ., Paper 31.3,2005.

Guo, R., et al., Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive, Proc. VLSI Test Symp ., pp. 66-71, 2006.

THANKS FOR YOUR ATTENTION

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