LPC2148 Tieng viet

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    LPC 2148

    1.2 Tnh nng:

    - Vi iu khin 16/32-bit ARM7TDMI-S.

    - 40K RAM tnh (32K + 8K), 512K Flash.

    - Tch hp USB 2.0.

    - 2 b 10-bit ADC.

    - 1 b 10-bit DAC.

    - 2 b 32-bit timer, 6 ng iu xung.

    -ng h thi gian thc vi tn s ng vo 32kHz.

    - Khnng thit lp u tin, nh a chcho ngt.

    - 45 chn GPIO (ng vo/ra a dng).

    - 9 chn ngt ngoi (tch cc cnh hoc tch cc mc).

    - CPU clock t ti a 60MHz thng qua b PLL lp trnh c.

    - Xung PLCK hot ng c lp.

    1.7 On-chip Flash Memory:

    LPC 2148 c 512K b nh Flash c thc dng lu tr code v d liu. Trong khi thcthi ng dng, vn c th xa hoc lp trnh Flash thng qua IAP (In Application Programming). Khi trnh loader trn chip c s dng, b nh trng cn li l 500K.

    B nh Flash c thghi xa c t nht 100000 ln, lu tr d liu n 20 nm.

    1.8 On-chip Static RAM:

    LPC 2148 c 32K RAM tnh, c thc truy xut theo n v byte, half word & word.

    Biu khin SRAM s dng phng thc write-back buffer ngn chn tnh trng treoCPU khi c thao tc ghi. Bm lun gi d liu cui cng tchng trnh gi ti b nh. D liuchc ghi vo SRAM khi c 1 thao tc ghi khc tchng trnh.

    3.8 Phase Locked Loop (PLL):

    LPC 2148 c 2 b PLL: PLL0 v PLL1. Ng ra PLL0 dng to xung h thng CCLK, ng ra PLL1dng cung cp xung cho USB vi tn sxc nh l 48MHz. Xung thch anh bn ngoi c gil Fosc, khi PLL khng c kt ni th CCLK = Fosc.

    PLL0 v PLL1 nhn tn s xung vo t 10-25MHz, xung ny c nhn ln thnh t 10-60MHz (choCCLK) v 48MHz (cho USB clock) bng b CCO (Current Controled Oscillators). S nhn (M) c thl 1 s nguyn t 1-32, trn thc t chti a l 6 (Fsco = 10MHz & CCLK = 60MHz). B CCO hotng trong khong tn s t 156-320MHz, do cn c 1 b chia tn s bo m tn s lm vicca CCO trong khi PLL cung cp tn s mong mun. S chia (P) c th l 2, 4, 8, 16. Ng ra ca PLLl 1 xung c duty cycle l 50%.

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    Ta c cng thc:

    CCLK = Fosc x M

    Fcco = CCLK x 2 x P = Fosc x M x2 x P

    PLL c iu khin qua thanh ghi PLLCON. S nhn (M) v s chia (P) ca PLL c iu khinbi thanh ghi PLLCFG. Hai thanh ghi ny c bo v trnh sthay i t ngt hoc tt PLL bv mi hot ng ca chip u ph thuc vo PLL0 (v b ny cung cp xung h thng). Tng t

    cho b PLL1 ca USB.

    C 2 bPLL u tt khi Reset chip hoc khi vo ch Power-down, chng chc khi ngbng phn mm. Chng trnh phi cu hnh v kch hot b PLL, i PLL lock, sau kt ni voPLL vi vai tr nh ngun xung h thng.

    BPLL c iu khin bi cc thanh ghi: PLLCON, PLLCFG, PLLSTAT, PLLFEED.

    PLL Control Register (PLL0CON & PLL1CON):

    PLLCON cha cc bit kch hot v kt ni PLL. Kch hot PLL cho php kha cu hnhhin ti (vi 2 s M & P). Kt ni PLL lm chip v ton b cc chc nng chy theo xung

    nhp t ng ra PLL.

    Bit K hiu ngha Gi tr sau Reset

    0 PLLE bit = 1: cho php kch hot PLL 0

    v kha ti tn s yu cu.

    1 PLLC khi PLLE v PLLC = 1 th PLL c 0

    kt ni nh ngun xung cho vi iu khin

    7:2 - Reserved n/a

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    PLL Configuration Register (PLL0CFG & PLL1CFG):

    PLLCFG cha gi tr s nhn M v s chia P ca b PLL.

    Bit K hiu ngha Gi tr sau Reset

    4:0 MSEL s nhn M 0

    6:5 PSEL s chia P 0

    7 - Reserved n/a PLL Status Register (PLL0STAT & PLL1STAT):

    PLLSTAT l thanh ghi chc, n cha cc gi tr thc s ca b PLL ti thi im cthanh ghi ny.

    Bit K hiu ngha Gi tr sau Reset

    4:0 MSEL s nhn hin ti ang c s dng bi b PLL 0

    6:5 PSEL s chia hin ti ang c s dng bi b PLL 0

    7 - Reserved n/a8 PLLE bit = 1: bPLL ang c kch hot 0

    9 PLLC bit = 1: bPLL ang c kch hot 0

    v kt ni.

    10 PLOCK bit = 0: PLL cha c kha 0

    bit = 1: PLL c kha vi tn s yu cu

    15:11 - Reserved n/a

    PLL Feed Register (PLL0FEED & PLL1FEED)Sau khi bPLL c kt ni, mi thay i trong 2 thanh ghi PLLCON & PLLCFG skhng c tc dng. thay i cu hnh PLL chn, phi ghi vo thanh ghi PLLFEEDtheo 1 th txc nh:

    Ghi 0xAA vo PLLFEED

    Ghi 0x55 vo PLLFEED

    Thao tc ghi phi theo ng th t, v lin k nhau.

    *******************************************************

    V d: tnh ton tn s PLL: gi s tn s thch anh l 12MHz v tn s chip CCLK l60MHz, khng s dng USB.

    Fosc: tn sdao ng thch anh

    Fcco: tn sdao ng ca PLL CCO

    CCLK: ng ra PLL, ng thi l xung h thng

    Ta c:

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    CCLK = Fosc x M M = 5

    Fcco = CCLK x 2 x P

    156 MHz < Fcco < 320 MHz 1.3 < P < 2.7 P = 2

    Bng gi tr ca MSEL & PSEL:

    PSEL bits 6:5 ca PLLCFG P

    00 101 2

    10 4

    11 8

    MSEL bits 4:0 PLLCFG M

    00000 1

    00001 2

    11110 31

    11111 32

    Vy PSEL = 01 v MSEL = 00100

    Gi tr ghi vo thanh ghi PLLCFG s l 0x00000024

    3.11 VPB Divider:

    B chia VPB (VLSI Peripheral Bus) quyt nh quan h gia clock h thng (CCLK) v clock dngcho cc thit b ngoi vi (PCLK). Gi tr mc nh ca b chia VPB l PCLK = 1/4 CCLK.

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    VPBDIV Register:

    Bit K hiu ngha Gi tr sau Reset

    1:0 VPBDIV 00: PCLK = 1/4 CCLK 00

    01: PCLK = CCLK

    10: PCLK = 1/2 CCLK

    11: no effect7:2 - Reserved n/a

    5.1 Vectored Interrupt Controler (VIC):

    Khi iu khin ngt c th nhn 32 yu cu ngt, phn thnh 3 loai: FIQ, vectored IRQ & non-vectored IRQ.

    Fast Interrupt reQuest (FIQ) c mc u tin cao nht.

    Vectored IRQs c mc u tin trung bnh. Chc 16/32 yu cu ngt c th gn voloi ny ti 1 thi im. Bt k yu cu ngt no cng c thc gn vo 16 khevectored IRQ (vectored IRQ slot). Trong khe 0 c mc u tin cao nh t v khe15 c mc u tin thp nht.

    Non-vectored IRQs c mc u tin thp nht.

    Khi 1 ngt xy ra, VIC xc nh xem ngt thuc loi no, sau nhy n hm phc v ngt tngng.

    FIQ: nhy n trnh phc v ngt dnh cho FIQ.

    Vectored IRQ: nhy n trnh phc v ngt dnh cho IRQ. Non-vectored IRQ: nhy n trnh phc v ngt mc nh.

    Nu c nhiu hn 1 ngt xy ra VIC sxc nh xem ngt no c mc u tin cao nht v nhy ntrnh phc v ngt . Trong trng hp vectored IRQ, nu khng tm thy a chtrnh phc v ngttng ng, trnh phc v ngt mc nh sc gi.

    VIC Register:

    Bit 31 30 29 28 27 26 25 24

    K

    hiu - - - - - - - -

    Bit 23 22 21 20 19 18 17 16

    K

    hiu- USB AD1 BOD I2C1 AD0 EINT3 EINT2

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    Bit 15 14 13 12 11 10 9 8

    K

    hiuEINT1 EINT0 RTC PLL SPI1/SSP SPI0 I2C0 PWM0

    Bit 7 6 5 4 3 2 1 0

    Khiu UART1 UART0 TMR1 TMR0 ARMCore1 ARMCore0 - WDT

    ** Cc thanh ghi co k hiu (1)u c cu trc bit nh trn. Gi tr sau khi Reset ca ccthanh ghi ny l 0x00000000.

    VICIRQStatus(1):

    Truy cp: c.

    Bit 31:0 Mc logic 1 chngt t ngun ngt ti bit tng ng c cho php v l

    IRQ. VICFIQStatus(1):

    Truy cp: c.

    Bit 31:0 Mc logic 1 chngt t ngun ngt ti bit tng ng c cho php v lFIQ.

    VICRawIntr(1):

    Truy cp: c.

    VICIntSelect(1)

    :

    Truy cp: c, ghi.

    Bit 31:0 - Mc logic 0: ngt t ngun ngt ti bit tng ng c xp vo IRQ.

    - Mc logic 1: ngt t ngun ngt ti bit tng ng c xp vo FIQ.

    VICIntEnable(1):

    Truy cp: c, ghi.

    Bit 31:0 - Khi c c: mc 1 chngun ngt ti bit tng ng c cho php.

    - Khi c ghi: mc 0: no effect.mc 1: cho php ngt t ngun ngt ti bit tng ng.

    VICIntEnClr(1):

    Truy cp: ghi.

    Bit 31:0 - Ghi mc 0: no effect.

    - Ghi mc 1: xa bit tng ng trong VICIntEnable, khng cho php ngtt ngun ngt ti bit tng ng.

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    VICSoftInt(1):

    Truy cp: c, ghi.

    Bit 31:0 - Ghi mc logic 0: no effect.

    - Ghi mc logic 1: yu cu 1 ngt t ngun ngt ti bit tng ng bngphn mm.

    VICSoftIntClear(1)

    :Truy cp: ghi.

    Bit 31:0 - Ghi mc logic 0: no effect.

    - Ghi mc logic 1: xa bit tng ng trong VICSoftInt.

    VICProtection:

    Kim sot quyn truy cp vo VIC registers bng phn mm trong User mode.

    VICVectAdrr:

    Khi ngt xy ra, trnh phc v ngt c thanh ghi ny v nhy ti a chtrong . VICDefVectAdrr:

    Thanh ghi ny gia chtrnh phc v ngt cho cc ngt thuc non-vectored IRQ. Khitrnh phc v ngt c thanh ghi VICVectAdrr v khng c IRQ slot no m nhn ngt nyth a chtr v l gi tr trong thanh ghi ny.

    VICVectAdrr0 VICVectAddr15:

    Cc thanh ghi ny gia chca trnh phc v ngt (ISR) cho 16 IRQ slots. Khi xy rangt, gi tr ca 1 trong cc thanh ghi ny sc a n trnh phc v ngt khi trnh ny

    c thanh ghi VICVectAdrr. VICVectCntl0 VICVectCntl15:

    Mi thanh ghi trong 16 thanh ghi ny iu khin 1 vectored IRQ slot. Slot 0 c mc u tincao nht v slot 15 c mc u tin thp nht. Ch rng vic disable 1 IRQ slot trong ccthanh ghi VICVectCntl khng lm disable ngt, ngt chb chuyn sang dng non-vectoredIRQ.

    Bit K hiu ngha Gi tr sau Reset

    4:0 int_request/ s hiu ca cc ngt 0

    sw_int_assig5 IRQslot_en ghi mc 1: cho php ngt c trong slot ny 0

    31:6 - Reserved n/a

    Cc ngun ngt s hiu

    WDT 0

    ARMCore0 2

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    ARMCore1 3

    TIMER0 4

    TIMER1 5

    UART0 6

    UART1 7

    PWM0 8

    I2C0 9

    SPI0 10

    SPI1/SSP 11

    PLL 12

    RTC 13

    EINT0 14

    EINT1 15

    EINT2 16

    EINT3 17

    ADC0 18

    I2C1 19

    BOD 20

    ADC1 21 USB 22

    7.1 Pin Connect Block

    Vic cu hnh kt ni gia cc chn ca vi iu khin vi cc khi chc nng trn chip cho php 1chn c khnng thc hin nhiu chc nng thng qua cu hnh cc thanh ghi iu khin PIN. Khila chn 1 chc nng cho 1 chn th cc chc nng khc khng th hot ng c trn cng chn (nhng vn c th trn cc chn khc).

    Cc thanh ghi iu khin bao gm: PINSEL0, PINSEL1, PINSELL2 (Pin funtion Select register).

    PINSEL0:

    Bit K hiu ngha Gi tr sau Reset

    1:0 P0.0 00 GPIO Port 0.0 0001 TXD (UART0)10 PWM111 Reserved

    3:2 P0.1 00 GPIO Port 0.1 00

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    01 RxD (UART0)10 PWM311 EINT0

    5:4 P0.2 00 GPIO Port 0.2 0001 SCL0 (I2C0)10 Capture 0.0 (Timer 0)11 Reserved

    7:6 P0.3 00 GPIO Port 0.3 00

    01 SDA0 (I2C0)10 Match 0.0 (Timer 0)11 EINT1

    9:8 P0.4 00 GPIO Port 0.4 0001 SCK0 (SPI0)10 Capture 0.1 (Timer 0)11 AD0.6

    11:10 P0.5 00 GPIO Port 0.5 0001 MISO0 (SPI0)10 Match 0.1 (Timer 0)11 AD0.7

    13:12 P0.6 00 GPIO Port 0.6 0001 MOSI0 (SPI0)10 Capture 0.2 (Timer 0)11 AD1.0

    15:14 P0.7 00 GPIO Port 0.7 0001 SSEL0 (SPI0)10 PWM211 EINT2

    17:16 P0.8 00 GPIO Port 0.8 0001 TXD UART110 PWM4

    11 AD1.119:18 P0.9 00 GPIO Port 0.9 0001 RxD (UART1)10 PWM611 EINT3

    21:20 P0.10 00 GPIO Port 0.10 0001 RTS (UART1)10 Capture 1.0 (Timer 1)11 AD1.2

    23:22 P0.11 00 GPIO Port 0.11 0001 CTS (UART1)

    10 Capture 1.1 (Timer 1)11 SCL1 (I2C1)25:24 P0.12 00 GPIO Port 0.12 00

    01 DSR (UART1)10 Match 1.0 (Timer 1)11 AD1.3

    27:26 P0.13 00 GPIO Port 0.13 0001 DTR (UART1)10 Match 1.1 (Timer 1)11 AD1.4

    29:28 P0.14 00 GPIO Port 0.14 00

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    01 DCD (UART1)10 EINT111 SDA1 (I2C1)

    31:30 P0.15 00 GPIO Port 0.15 0001 RI (UART1)10 EINT211 AD1.5

    PINSEL1:

    Bit K hiu ngha Gi tr sau Reset

    1:0 P0.16 00 GPIO Port 0.16 0001 EINT010 Match 0.2 (Timer 0)11 Capture 0.2 (Timer 0)

    3:2 P0.17 00 GPIO Port 0.17 0001 Capture 1.2 (Timer 1)

    10 SCK1 (SSP)11 Match 1.2 (Timer 1)

    5:4 P0.18 00 GPIO Port 0.18 0001 Capture 1.3 (Timer 1)10 MISO1 (SSP)11 Match 1.3 (Timer 1)

    7:6 P0.19 00 GPIO Port 0.19 0001 Match 1.2 (Timer 1)10 MOSI1 (SSP)11 Capture 1.2 (Timer 1)

    9:8 P0.20 00 GPIO Port 0.20 00

    01 Match 1.3 (Timer 1)10 SSEL1 (SSP)11 EINT3

    11:10 P0.21 00 GPIO Port 0.21 0001 PWM510 AD1.611 Capture 1.3 (Timer 1)

    13:12 P0.22 00 GPIO Port 0.22 0001 AD1.710 Capture 0.0 (Timer 0)11 Match 0.0 (Timer 0)

    15:14 P0.23 00 GPIO Port 0.23 0001 VBUS10 Reserved11 Reserved

    17:16 P0.24 00 Reserved 0001 Reserved10 Reserved11 Reserved

    19:18 P0.25 00 GPIO Port 0.25 0001 AD0.410 Aout(DAC)

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    11 Reserved21:20 P0.26 00 Reserved 00

    01 Reserved10 Reserved11 Reserved

    23:22 P0.27 00 Reserved 0001 Reserved10 Reserved

    11 Reserved25:24 P0.28 00 GPIO Port 0.28 0001 AD0.110 Capture 0.2 (Timer 0)11 Match 0.2 (Timer 0)

    27:26 P0.29 00 GPIO Port 0.29 0001 AD0.210 Capture 0.3 (Timer 0)11 Match 0.3 (Timer 0)

    29:28 P0.30 00 GPIO Port 0.30 0001 AD0.3

    10 EINT311 Capture 0.0 (Timer 0)31:30 P0.31 00 GPO Port only 00

    01 UP_LED10 CONNECT11 Reserved

    PINSEL2:

    Bit K hiu ngha Gi tr sau Reset

    1:0 - Reserved n/a

    2 GPIO/ 0: P1.31-P1.26 used as GPIO

    DEBUG 1: P1.31-P1.26 used as a Debug port

    3 GPIO/ 0: P1.25-P1.16 used as GPIO

    TRACE 1: P1.25-P1.16 used as a Trace port

    31:4 - Reserved n/a

    8.1 General Purpose Input/Output ports (GPIO):

    LPC 2148 c 2 port:

    Port 0: P0.0-P0.23, P0.25, P0.28-P0.30: input/output

    P0.31: output only

    Port 1: P1.16-P1.31: intput/output.

    Vic truy cp cc port c th chia lm 2 cch: slow GPIO v fast GPIO. Cu hnh vic truy cp ccport theo 2 phng thc ni trn bng thanh ghi SCS (System Control and Status flags register).

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    SCS (System Control and Status flag register):

    Bit K hiu ngha Gi tr sau Reset

    0 GPIO0M bit chn mode port 0 0

    0: slow 1: fast

    1 GPIO1M bit chn mode port 1 00: slow 1: fast

    31:2 - Reserved n/a

    Cc thanh ghi qun l xut nhp port 0:

    + Slow GPIO:

    IO0DIR:

    Bit K hiu ngha Gi tr sau Reset

    31:0 P0xDIR bit 0 tng ng vi P0.0 0x000000000: chn tng ng l input1: chn tng ng l output

    IO0SET:

    Bit K hiu ngha Gi tr sau Reset

    31:0 P0xSET 0: no effect 0x000000001: chn tng ng c set bng 1

    IO0CLR:

    Bit K hiu ngha Gi tr sau Reset

    31:0 P0xCLR 0: no effect 0x000000001: chn tng ng c set bng 0

    IO0PIN:

    Trng thi ca port 0 lun lun c c trong thanh ghi ny, d l input/output hay bt kchc nng no. Vic ghi vo thanh ghi IO0SET v IO0CLR chnh hng ti cc chn cbit tng ng bng 1 cn vic ghi vo thanh ghi IO0PIN snh hng ti ton b port 0.

    + Fast GPIO:

    FIO0DIR*:

    Tng t IO0DIR.

    FIO0MASK*:

    Qun l cc chn theo tp hp cc bit c gi tr 0 trong FIO0MASK. Vic ghi vo cc thanhghi FIO0SET, FIO0CLR, FIO0PIN chc tc dng vi tp hp chn nh ngha trongFIO0MASK, vic c t FIO0PIN cng vy.

    FIO0SET*:

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    Tng tIO0SET nhng chc tc dng vi tp hp chn nh ngha trong FIO0MASK. FIO0CLR*:

    Tng tIO0CLR nhng chc tc dng vi tp hp chn nh ngha trong FIO0MASK. FIO0PIN*:

    Tng tIO0PIN nhng chc tc dng vi tp hp chn nh ngha trong FIO0MASK.* Ngoi ra, i vi Fast GPIO cn c cc thanh ghi truy cp theo n v byte, half-word:

    v di vi FIO0DIR cn c:- FIO0DIR0: qun l t P0.0-P0.7- FIO0DIR1: qun l t P0.8-P0.15- FIO0DIR2: qun l t P0.16-P0.23- FIO0DIR3: qun l t P0.24-P0.31- FIO0DIRL: qun l t P0.0-P0.15- FIO0DIRU: qun l t P0.16-P0.31

    Cc thanh ghi qun l xut nhp port 1: tng t port 0 (IO1DIR, FIO1DIR).

    V d: Code C

    1. Cu hnh chn P0.7 l output v a ra 1 xung trn chn ny:IO0DIR = 0x0000 0080 ;pin P0.7 configured as outputIO0CLR = 0x0000 0080 ;P0.7 goes LOW

    IO0SET = 0x0000 0080 ;P0.7 goes HIGH

    IO0CLR = 0x0000 0080 ;P0.7 goes LOW

    2. Xut d liu ng thi trn cc chn P0.8-P0.15 m khng lm nh hng ti cc chncn li:Cch 1:

    IO0PIN = (IO0PIN & 0xFFFF00FF) | 0x0000A500

    Cch 2:FIO0MASK = 0xFFFF00FF;

    FIO0PIN = 0x0000A500;

    Cch 3:FIO0MASKL = 0x00FF;

    FIO0PINL = 0xA500;

    Cch 4:FIO0PIN1 = 0xA5;

    15.1 Timer/ Counter TIMER0 and TIMER1:

    Tnh nng chnh:

    - 32-bit Timer/Counter vi b chia 32-bit lp trnh c (Programmable Prescaler).- 4 knh chn bt gi tr ca Timer khi xy ra chuyn trng thi ng vo nh trc,c th gy ra ngt.

    - 4 thanh ghi cha cc gi trcho trc (Match Register), khi gi tr ca Timer bnggi tr cha trong cc thanh ghi ny s to ra 1 ngt v:

    - Tip tc chy Timer.- Dng Timer.- Reset Timer.- Thay i 1 ng ra nh trc:

    - set bng 1- set bng 0

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    - o gi tr- khng lm gi c

    Timer/Counter c thit km xung PCLK hoc 1 xung cp ngoi. Hot ng caTimer/Counter v bPrescaler: thanh ghi PC tng ln 1 sau mi chu k PCLK, khi gi tr ca PC +1bng gi tr ca thanh ghi PR (c t trc) th PC = 0 v thanh ghi TC (Timer Counter) tng ln 1

    Cc chn c chc nng lin quan n Timer/Counter:

    - Capture Signal: s chuyn trng thi trn cc chn ny th gi tr trong TC scload vo 1 trong cc thanh ghi CR0-CR3 (Capture Register), c th gy ra ngt. Baogm cc chn:

    - CAP0.0: P0.2, P0.22 & P0.30

    - CAP0.1: P0.4 & P0.27

    - CAP0.2: P0.6, P0.16 & P0.28

    - CAP0.3: P0.29

    - CAP1.0: P0.10

    - CAP1.1: P0.11

    - CAP1.2 P0.17 & P0.19

    - CAP1.3: P0.18 & P0. 21

    i vi cc chn c cng chc nng, khi c nhiu hn 1 chn c chn, chn cs thp hn sc s dng. V d: i vi CAP0.1 th chn P0.4 sc uu tins dng.

    - External Match Output: khi gi tr trong TC bng gi tr ca 1 trong cc thanh ghiMR0-MR3 th ng ra cc chn ny sc set bng 0, 1, o gi tr hoc khnglm g c, c th gy ra ngt.

    - MAT0.0: P0.3 & P0.22

    - MAT0.1: P0.5 & P0.27

    - MAT0.2: P0.16 & P0.28

    - MAT0.3: P0.29

    - MAT1.0: P0.12

    - MAT1.1: P0.13

    - MAT1.2: P0.17 & P0.19

    - MAT1.3: P0.18 & P0.20

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    i vi MAT, khi c nhiu chn c cng chc nng c chn, chng sc iukhin song song vi nhau.

    Cc thanh ghi iu khin Timer/Counter: Interrupt Register (T0IR & T1IR):

    Khi xy ra ngt do Match hoc Capture th cc bit tng ng trong TCIR c set ln 1.Ghi mc logic 1 vo 1 bit s xa c ngt tng ng vi bit (vic ny thng c lm

    ngay trong hm phc v ngt update trng thi ngt, nu khng ngt s lin tc xy ra).

    Bit K hiu ngha Gi tr sau Reset

    0 MR0_Int c ngt cho Match 0 01 MR1_Int c ngt cho Match 1 02 MR2_Int c ngt cho Match 2 03 MR3_Int c ngt cho Match 3 04 CR0_Int c ngt cho Capture 0 05 CR1_Int c ngt cho Capture 1 06 CR2_Int c ngt cho Capture 2 0

    7 CR3_Int c ngt cho Capture 3 0

    Timer Control Register (T0TCR & T1TCR):

    Bit K hiu ngha Gi tr sau Reset

    0 Counter 0: disable Timer/Counter 0Enable 1: enable Timer/Counter

    1 Counter khi bit ny bng 1, TC v PC c Reset. 0Reset tnh trng Reset c gi nguyn ti khi

    bit Counter Enable = 0.

    7:2 - Reserved n/a Count Control Register (T0CTCR & T1CTCR):

    Bit K hiu ngha Gi tr sau Reset

    1:0 Timer/ 00: Timer mode 00Counter 01: Counter mode tch cc cnh lnMode 10: Counter mode tch cc cnh xung

    11: Counter mode tch cc cnh ln & xung3:2 Count 00: CAP0.0 & CAP1.0 c dng cho Counter mode 00

    Input 01: CAP0.1 & CAP1.1 c dng cho Counter modeSelect 10: CAP0.2 & CAP1.2 c dng cho Counter mode

    11: CAP0.3 & CAP1.3 c dng cho Counter mode7:4 - Reserved n/a

    Timer Counter (T0TC & T1TC):

    Prescale Register (T0PR & T1PR):

    Prescale Counter (T0PC & T1PC):

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    PC tng ln 1 sau mi chu k ca PCLK, khi PC + 1 = PR th TC tng ln 1 v PC = 0.

    Match Register (T0MR0-3 & T1MR0-3):

    Khi TC = MRx, Timer c th b dng li hoc Reset, c th gy ra 1 ngt.

    Match Control Register (T0MCR & T1MCR):

    Bit K hiu ngha Gi tr sau Reset

    0 MR0I 1: ngt khi TC = MR0 00: khng cho php ngt

    1 MR0R 1: TC b Reset khi TC = MR0 02 MR0S 1: dng TC, set bit TR[0] v 0 011:3 tng t cho MR1, MR2 & MR3 015:12 - Reserved n/a

    Capture Register (T0CR0-3 & T1CR0-3):

    Gi tr ca TC sc load vo 1 trong cc thanh ghi CR khi xy ra 1 chuyn trng thitrn cc chn CAP.

    Capture Control Register (T0CCR & T1CCR):

    Bit K hiu ngha Gi tr sau Reset

    0 CAP0RE 1: Capture tch cc cnh ln 01 CAP0FE 1: Capture tch cc cnh xung 02 CAP0I 1: gy ra ngt khi TC0 c load vo CR0 011:3 tng t cho CAP1, CAP2 & CAP3 015:12 - Reserved n/a

    Khi set c 2 bit CAPxRE v CAPxFE th CAP xy ra khi c c cnh ln v cnh xung.

    External Match Register (T0EMR & T1EMR):

    Bit K hiu ngha Gi tr sau Reset

    0 EM0 trng thi ca MAT0.0/MAT1.0 01 EM1 trng thi ca MAT0.1/MAT1.1 02 EM2 trng thi ca MAT0.2/MAT1.2 03 EM3 trng thi ca MAT0.3/MAT1.3 0

    5:4 EMC0 quyt nh trng thi ng ra trn cc chn MAT0.0 00v MAT1.0 khi TC = MR0

    00: khng lm g c01: xa chn MAT0.0/MAT1.010: set chn MAT0.0/MAT1.0 ln 111: o gi tr chn MAT0.0/MAT1.0

    11:6 tng t cho EMC1, EMC2 & EMC3 0015:12 - Reserved n/a

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    Minh ha:

    16.1 PulseWidth Modulator (PWM):

    B to xung PWM c thit k da trn b Timer/Counter, hot ng theo xung PCLK. Nguyn tchot ng da trn cc Match events ca 7 match register. C 2 loi xung:

    - Single Edge: tt ccc xung u c set ln 1 ngay khi bt u 1 xung PWM,xung c set v 0 khi gi tr ca timer counter bng vi gi tr ca 1 trong ccMatch register 1-6. C th c ti a 6 xung Single Edge ng thi, tt c cc xung

    u c cng tn sc iu khin bi Match register 0 (khi gi tr ca timercounter bng gi tr trong Match register 0 th kt thc 1 xung PWM v bt u 1xung mi).

    - Double Edge: cc xung c set bng 0 khi bt u 1 xung PWM, c set ln 1bng 1 Match register v set v 0 bng 1 Match register khc. Cc xung doubleedge cng c tn sc iu khin bi Match register 0.

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    PWM2 & PWM4: double edgePWM5: single edge

    Bng cc knh PWM:

    KnhSingle Edge Double Edge

    Set by Reset by Set by Reset by

    1 Match 0 Match 1 - -

    2 Match 0 Match 2 Match 1 Match 2

    3 Match 0 Match 3 Match 2 Match 3

    4 Match 0 Match 4 Match 3 Match 4

    5 Match 0 Match 5 Match 4 Match 5

    6 Match 0 Match 6 Match 5 Match 6

    Ta c th thy c ti a 3 xung double edge ng thi (knh 2, 4 & 6) c thc iukhin c lp bng 7 Match register.

    Cc thanh ghi iu khin PWM:

    PWM Interrupt Register (PWMIR):

    Khi xy ra ngt do 1 knh PWM (xy ra match trn cc Match registers) th bit tng ng

    trong PWMIR sc set ln 1. Sau khi xy ra ngt phi ghi 1 vo bit xa c ngt(tng t T0IR & T1IR).

    Bit K hiu ngha Gi tr sau Reset

    0 PWM0_Int c ngt PWM knh 0 01 PWM1_Int c ngt PWM knh 1 02 PWM2_Int c ngt PWM knh 2 03 PWM3_Int c ngt PWM knh 3 07:4 - Reserved n/a8 PWM4_Int c ngt PWM knh 4 0

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    9 PWM5_Int c ngt PWM knh 5 010 PWM6_Int c ngt PWM knh 6 015:11 - Reserved n/a

    PWM Timer Control Register (PWMTCR):

    Bit K hiu ngha Gi tr sau Reset

    0 Counter 0: disable Counter 0Enable 1: enable Counter1 Counter khi bit ny bng 1, TC v PC c Reset. 0

    Reset tnh trng Reset c gi nguyn ti khibit Counter Enable = 0.

    2 - Reserved n/a3 PWM 0: disable PWM 0

    Enable 1: enable PWM7:4 - Reserved n/a

    PWM Timer Counter (PWMTC):

    Tng t T0TC & T1TC.

    PWM Prescale Register (PWMPR):

    Tng t T0PR & T1PR.

    PWM Prescale Counter (PWMPC):

    Tng t T0PC & T1PC.

    PWM Match Register (PWMMR0-6):Tng t cc Match register ca Timer, khi xy ra match trn cc thanh ghi PWMMR0-6 tac th cho dng timer, reset hoc yu cu ngt.

    PWM Match Control Register (PWMMCR):

    Bit K hiu ngha Gi tr sau Reset

    0 PWMMR0I 1: ngt khi PWMTC = PWMMR0 (match 0) 01 PWMMR0R 1: reset timer khi match 0 02 PWMMR0S 1: dng timer khi match 0 0

    20:3 tng t cho PWMMR1-6 031:21 - Reserved n/a

    PWM Control Register (PWMPCR):

    Kch hot v chn loi xung trn cc knh PWM.

    Bit K hiu ngha Gi tr sau Reset

    1:0 - Reserved n/a2 PWMSEL2 0: xung PWM2 l xung single edge 0

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    1: xung PWM2 l xung double edge6:3 tng t cho cc xung PWM3-6 08:7 - Reserved n/a9 PWMENA1 0: disable PWM1 0

    1: enable PWM114:10 tng t cho PWM6-2 015 - Reserved n/a

    PWM Latch Enable Register (PWMLER):

    Khi ghi ln cc thanh ghi PWMMR0-6, d liu c lu gi trong cc shadow register. Khixy ra match 0 (bt u 1 xung PWM), d liu chc ghi ln cc thanh ghiPWMMR0-6 khi cc bit tng ng trong PWMLER c set bng 1, xung PWM mi shot ng da trn cc gi tr mi. Nu xy ra vic chuyn gi tr t cc shadow registersang cc match register th cc bit tng ng trong PWMLER sc xa tng.

    Bit K hiu ngha Gi tr sau Reset

    6:0 cc bit tng ng cho PWMMR0-6 0

    7 - Reserved n/a

    17.1 Analog to Digital Converter (ADC):

    LPC 2148 c 2 b ADC (ADC0 & ADC1) c th la chn ng vo t 1 trong 14 chn (ADC0: 6,ADC1: 8). o in p t 0 Vref (Vref khng c vt qu VDDA). Thi gian chuyn i 10 tithiu l 2.44 us. Busrt conversion mode cho php tng lp li vic chuyn i. B ADC hot ngtheo xung VPB, tn s ti a l 4.5 MHz, 1 php chuyn i y cn 11 chu k. C th khi ngchuyn i bng phn cng da trn vic chuyn i trng thi ng vo ca cc chn cho trc.

    Cc thanh ghi iu khin b ADC:

    A/D Control Register (AD0CR & AD1CR):

    Bit K hiu ngha Gi tr sau Reset

    7:0 SEL la chn cc chn AD chuyn i. 0x01bit 0 la chn chn AD0.0/AD1.0bit 7 la chn chn AD0.7/AD1.7bit no c set ln 1 th cc chn tngng sc chn. Gi tr mc nh l chnAD0.0/AD1.0 c chn.

    15:8 CLKDIV xung hot ng ca b ADC bng xung PCLK 0chia cho gi tr CLKDIV + 1. Xung hot ngti a ca b ADC l 4.5 MHz

    16 BURST 1: cho php lp li vic chuyn i tng theo 0cc chtrong trng CLKS.0: vic chuyn i do phn mm kim sotv cn 11 chu k cho 1 chuyn i.

    19:17 CLKS chn cc ch cho BURST: 000000: 11 clocks/ 10 bits

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    001: 10 clocks/ 9 bits010: 9 clocks/ 8 bits011: 8 clocks/ 7 bits100: 7 clocks/ 6 bits101: 6 clocks/ 5 bits110: 5 clocks/ 4 bits111: 4 clocks/ 3 bits

    20 - Reserved n/a

    21 PDN 0: ch power-down 01: ch bnh thng23:22 - Reserved n/a26:24 START khi BURST = 0, iu khin khi no b ADC 0

    bt u chuyn i.khi BURST = 1, START phi bng 000.

    000: no start001: start now010: bt u chuyn i khi c chuyn

    trng thi trn chn P0.16011: P0.22

    100: MAT0.1101: MAT0.3110: MAT1.0111: MAT1.1

    27 EDGE bit ny chc tc dng khi START = 010-111 00: bt u khi c cnh ln1: bt u khi c cnh xung

    31:28 - Reserved n/a

    A/D Global Data Register (AD0GDR & AD1GDR):

    Bit K hiu ngha Gi tr sau Reset

    5:0 - Reserved n/a15:6 RESULT khi DONE = 1, in p chn Ain bng n/a

    Vref nhn vi gi tr ny.23:16 - Reserved n/a26:24 CHN xc nh ngun ca RESULT n/a

    000: t knh 0111: t knh 7

    29:27 - Reserved n/a

    30 OVERRUN c set ln 1 khi c 1 hoc nhiu kt qu 0chuyn i b mt hoc ghi ln trc khit kt quvo RESULT. Bit ny c xakhi c thanh ghi ny.

    31 DONE bit ny bng 1 khi hon thnh 1 chuyn i, 0c xa khi thanh ghi ny c c v thanhghi ADCR c ghi.

    A/D Global Start Register (ADGSR):

    Cho php khi to ng thi 2 b ADC0 & ADC1

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    Bit K hiu ngha Gi tr sau Reset

    15:0 - Reserved n/a31:16 tng t bit 31:16 trong ADCR, c tc dng

    ln c 2 b ADC.

    A/D Status Register (AD0STAT & AD1STAT):

    Bit K hiu ngha Gi tr sau Reset

    0 DONE0 c DONE knh 0 01 DONE1 c DONE knh 1 02 DONE2 c DONE knh 2 03 DONE3 c DONE knh 3 04 DONE4 c DONE knh 4 05 DONE5 c DONE knh 5 06 DONE6 c DONE knh 6 07 DONE7 c DONE knh 7 08 OVERRUN0 c OVERUN knh 0 0

    9 OVERRUN1 c OVERUN knh 1 010 OVERRUN2 c OVERUN knh 2 011 OVERRUN3 c OVERUN knh 3 012 OVERRUN4 c OVERUN knh 4 013 OVERRUN5 c OVERUN knh 5 014 OVERRUN6 c OVERUN knh 6 015 OVERRUN7 c OVERUN knh 7 016 ADINT c ngt ca bADC, c set khi hon thnh 0

    chuyn i 1 knh bt k31:17 - Reserved n/a

    A/D Interrupt Enable Register (AD0INTEN & AD1INTEN):Bit K hiu ngha Gi tr sau Reset

    0 ADINTEN0 0: khng gy ngt khi hon thnh chuyn 0i trn knh 0.1: gy ngt khi hon thnh chuyn i trnknh 0

    7:1 tng t cho knh 1-7 08 ADGINTEN 0: chcho php yu cu ngt trn cc knh 0

    1: chcho php yu cu ngt khi bit DONEtrn thanh ghi ADGDR c set.

    31:9 - Reserved n/a

    A/D Data Register (AD0DR0-7 & AD1DR0-7):

    Bit K hiu ngha Gi tr sau Reset

    5:0 - Reserved n/a15:6 RESULT kt qu chuyn i trn knh 0 n/a29:16 - Reserved n/a30 OVERRUN n/a

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    31 DONE n/a

    3.5 External Interrupt:

    LPC2148 c 4 ngun ngt ngoi c thdng kch hot vi iu khin t ch Power-down.

    Cc chn ngt ngoi:

    EINT0: P0.1 & P0.16EINT1: P0.3 & P0.14EINT2: P0.7 & P0.15EINT3: P0.9, P0.20 & P0.30

    Cc thanh ghi iu khin ngt:

    External Interrupt Flag register (EXTINT):

    Bit K hiu ngha Gi tr sau Reset

    0 EINT0 c set ln 1 khi xy ra chuyn trng 0thi gy ra ngt (c quy nh trongEXTMODE & EXTPOLAR) trn chnEINT0

    3:1 tng t cho EINT1, EINT2 & EINT3 07:4 - Reserved n/a

    Ghi 1 vo cc bit EINT0-3 sxa cc bit tng ng. Trong ch tch cc mc, cc btny chc xa khi cc chn ang trong trng thi khng tch cc.

    Interrupt Wakeup register (INTWAKE):

    Cho php cc ngt ngoi v cc ngun khc c khnng kch hot vi iu khin t chPower-down.

    Bit K hiu ngha Gi tr sau Reset

    0 EXTWAKE0 cho php kch hot vi iu khin bng EINT0 03:1 tng t cho EXTWAKE1-3 04 - Reserved n/a5 USBWAKE cho php kch hot vk bng USB 0

    13:6 - Reserved n/a14 BODWAKE cho php kch hot vk bng BOD 015 RTCWAKE cho php kch hot vk bng RTC 0

    External Interrupt Mode register (EXTMODE):

    Bit K hiu ngha Gi tr sau Reset

    0 EXTMODE0 0: EINT0 l tch cc mc 01: EINT0 l tch cc cnh

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    3:1 tng t cho EXTMODE1-3 07:4 Reserved n/a

    External Interrupt Polarity register (EXTPOLAR):

    Bit K hiu ngha Gi tr sau Reset

    0 EXTPOLAR0 0: EINT0 l tch cc mc thp hoc tch 0cc cnh xung (ty vo EXTMODE0)1: EINT0 l tch cc mc cao hoc tchcc cnh ln

    3:1 tng t cho EXTPOLAR1-3 07:4 Reserved n/a

    Khi la chn cc chn input cho ngt ngoi, ta c th la chn nhiu hn 1 chn cho 1ngun ngt, khi cc tn hiu sc x l ty vo cc ch:

    - ch tch cc mc thp, cc tn hiu trn cng 1 ngun EINTx sc AND li

    thnh 1 tn hiu duy nht.- ch tch cc mc cao, cc tn hiu trn cng 1 ngun EINTx sc OR lithnh 1 tn hiu duy nht.

    - ch tch cc cnh (ln hoc xung), chn c s nh nht sc s dng.V d: t PINSEL0 v PINSEL1 ta chn ngun cho EINT3 l P0.9, P0.20 v P0.30, ngtc t ch tch cc mc thp, khi tn hiu t 3 chn ny sc AND li thnhngun cho EINT3.