LTC1854/LTC1855/LTC1856 - 8-Channel, ±10V Input 12-/14-/16 … · 2014-11-27 · 1 ltc1854/ltc1855/ltc1856 185456fa com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 muxout+ muxout– adc+ adc–

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LTC1854/LTC1855/LTC1856

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COMCH0CH1CH2CH3CH4CH5CH6CH7MUXOUT+

MUXOUT–

ADC+

ADC–

AGND1

CONVSTRD

SCKSDI

DGNDSDO

BUSYOVDDDVDDAVDD

AGND3AGND2

REFCOMPVREF

LTC1854/LTC1855/LTC1856

SOFTWARE-PROGRAMMABLESINGLE-ENDED OR

DIFFERENTIAL INPUTS±10V BIPOLAR INPUT RANGE

10μF0.1μF 10μF

10μF 0.1μF1μF

10μF

3V TO 5V5V5V

2.5V

0.1μF

μPCONTROLLINES

0.1μF

8-Channel, ±10V Input12-/14-/16-Bit, 100ksps ADC

Converters with Shutdown

The LTC®1854/LTC1855/LTC1856 are 8-channel, lowpower, 12-/14-/16-bit, 100ksps, analog-to-digital con-verters (ADCs). These ADCs operate from a single 5Vsupply and the 8-channel multiplexer can be programmedfor single-ended inputs, pairs of differential inputs, orcombinations of both. In addition, all channels are faultprotected to ±30V. A fault condition on any channel willnot affect the conversion result of the selected channel.

An onboard precision reference minimizes external com-ponents. Power dissipation is 40mW at 100ksps and lowerin two power shutdown modes (27.5mW in Nap mode and40mW in Sleep mode.) DC specifications include ±3LSBINL for the LTC1856, ±1.5LSB INL for the LTC1855 and±1LSB for the LTC1854.

The internal clock is trimmed for 5ms maximum conver-sion time and the sampling rate is guaranteed at 100ksps.A separate convert start input and data ready signal (BUSY)ease connections to FIFOs, DSPs and microprocessors.

■ Single 5V Supply■ Sample Rate: 100ksps■ 8-Channel Multiplexer with ±30V Protection■ ±10V Bipolar Input Range

Single Ended or Differential■ ±3LSB INL for the LTC1856, ±1.5LSB INL for the

LTC1855, ±1LSB INL for the LTC1854■ Power Dissipation: 40mW (Typ)■ SPI/MICROWIRETM Compatible Serial I/O■ Power Shutdown: Nap and Sleep■ SINAD: 87dB (LTC1856)■ Operates with Internal or External Reference■ Internal Synchronized Clock■ 28-Pin SSOP Package

100kHz, 12-Bit/14-/16-Bit Sampling ADC

■ Industrial Process Control■ Multiplexed Data Acquisition Systems■ High Speed Data Acquisition for PCs■ Digital Signal Processing

LTC1856 Typical INL Curve

DESCRIPTIO

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FEATURES

APPLICATIO SU

TYPICAL APPLICATIO

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, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

CODE–32768

INL

(LSB

)

0

0.5

1.0

32767

185456 G01

–0.5

–1.0

–2.0–16384 0 16384

–1.5

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1.5

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LTC1854/LTC1855/LTC1856

185456fa

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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TOP VIEW

G PACKAGE28-LEAD PLASTIC SSOP

28

27

26

25

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16

15

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

MUXOUT+

MUXOUT–

ADC+

ADC–

AGND1

CONVST

RD

SCK

SDI

DGND

SDO

BUSY

OVDD

DVDD

AVDD

AGND3

AGND2

REFCOMP

VREF

A

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W

A

W

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ARBSOLUTE XI TI S

Supply Voltage (OVDD = DVDD = AVDD = VDD) ........... 6VGround Voltage Difference

DGND, AGND1, AGND2, AGND3 ...................... ±0.3VAnalog Input Voltage

ADC+, ADC–

(Note 3) ................... (AGND1 – 0.3V) to (AVDD + 0.3V)CH0-CH7, COM .................................................. ±30V

Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10VDigital Output Voltage .... (DGND – 0.3V) to (DVDD + 0.3V)Power Dissipation .............................................. 500mWOperating Temperature Range

LTC1854C/LTC1855C/LTC1856C ............ 0∞C to 70∞CLTC1854I/LTC1855I/LTC1856I .......... –40∞C to 85∞C

Storage Temperature Range ................. –65∞C to 150∞CLead Temperature (Soldering, 10 sec) ................. 300∞C

TJMAX = 110∞C, qJA = 95∞C/W

(Notes 1, 2)

ORDER PART NUMBER

LTC1855CGLTC1855IG

PACKAGE/ORDER I FOR ATIOU UW

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25∞C.MUXOUT connected to ADC inputs. (Notes 5, 6)

CO VERTER A D ULTIPLEXER CHARACTERISTICS

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Order Options Tape and Reel: Add #TRLead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBFLead Free Part Marking: http://www.linear.com/leadfree/

LTC1854CGLTC1854IG

LTC1856CGLTC1856IG

LTC1854 LTC1855 LTC1856PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITSResolution ● 12 14 16 BitsNo Missing Codes ● 12 14 15 BitsTransition Noise 0.06 0.25 1 LSBRMS

Integral Linearity Error (Note 7) ● ±1 ±1.5 ±3 LSBDifferential Linearity Error ● –1 1 –1 1.5 –2 4 LSBBipolar Zero Error (Note 8) ● ±5 ±8 ±23 LSBBipolar Zero Error Drift ±0.1 ±0.1 ±0.1 ppm/∞CBipolar Zero Error Match 3 4 10 LSBBipolar Full-Scale Error External Reference (Note 11) ● ±0.34 ±0.14 ±0.1 %

Internal Reference (Note 11) ±0.45 ±0.40 ±0.4 %Bipolar Full-Scale Error Drift External Reference ±2.5 ±2.5 ±2.5 ppm/∞C

Internal Reference ±7 ±7 ±7 ppm/∞CBipolar Full-Scale Error Match 5 10 15 LSBInput Common Mode Range ● ±10 ±10 ±10 VInput Common Mode Rejection Ratio 96 96 96 dB

http://www.linear.com/leadfree/

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LTC1854/LTC1855/LTC1856

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PARAMETER CONDITIONS MIN TYP MAX UNITS

Analog Input Range CH0 to CH7, COM ±10 V

ADC+, ADC– (Note 3) ADC– ±2.048 V

Impedance CH0 to CH7, COM 31 kWMUXOUT+, MUXOUT– 5 kW

Capacitance CH0 to CH7, COM 5 pF

Sample Mode ADC+, ADC– 12 pF

Hold Mode ADC+, ADC– 4 pF

Input Leakage Current ADC+, ADC–, CONVST = Low ● ±1 mA

The ● denotes the specifications which apply over the full operating temperature range, otherwisespecifications are at TA = 25∞C. (Note 5)A ALOG I PUT

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The ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25∞C. MUXOUT connected to ADC inputs. (Note 5)DY A IC ACCURACY

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LTC1854 LTC1855 LTC1856SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 74 83 87 dB

THD Total Harmonic Distortion 1kHz Input Signal, –102 –95 –101 dBFirst Five Harmonics

Peak Harmonic or Spurious Noise 1kHz Input Signal –99 –99 –103 dB

Channel-to-Channel Isolation 1kHz Input Signal –120 –120 –120 dB

–3dB Input Bandwidth 1 1 1 MHz

Aperture Delay –70 –70 –70 ns

Aperture Jitter 60 60 60 ps

Transient Response Full-Scale Step 4 4 4 ms(Note 9)

Overvoltage Recovery (Note 12) 150 150 150 ns

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LTC1854/LTC1855/LTC1856

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The ● denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at TA = 25∞C. (Note 5)


VREF Output Voltage IOUT = 0 ● 2.475 2.50 2.525 V

VREF Output Temperature Coefficient IOUT = 0 ±10 ppm/∞CVREF Output Impedance –0.1mA £ IOUT £ 0.1mA 8 kWVREFCOMP Output Voltage IOUT = 0 4.096 V

The ● denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at TA = 25∞C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VDD = 5.25V ● 2.4 V

VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V

IIN Digital Input Current VIN = 0V to VDD ● ±10 mA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage VDD = 4.75V, IO = –10mA, OVDD = VDD 4.74 VVDD = 4.75V, IO = –200mA, OVDD = VDD ● 4 V

VOL Low Level Output Voltage VDD = 4.75V, IO = 160mA, OVDD = VDD 0.05 VVDD = 4.75V, IO = 1.6mA, OVDD = VDD ● 0.10 0.4 V

IOZ Hi-Z Output Leakage VOUT = 0V to VDD, RD = High ● ±10 mA

COZ Hi-Z Output Capacitance RD = High 15 pF

ISOURCE Output Source Current VOUT = 0V –10 mA

ISINK Output Sink Current VOUT = VDD 10 mA

I TER AL REFERE CE CHARACTERISTICSU U U

DIGITAL I PUTS A D DIGITAL OUTPUTS

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Positive Supply Voltage (Notes 9 and 10) 4.75 5.00 5.25 V

Positive Supply Current ● 8.0 12 mANap Mode 5.5 7 mASleep Mode CONVST = 0V or 5V 8.0 13 mA

Power Dissipation 40.0 mWNap Mode 27.5 mWSleep Mode CONVST = 0V or 5V 40.0 mW

The ● denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25∞C. (Note 5)POWER REQUIRE E TS

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LTC1854/LTC1855/LTC1856

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The ● denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25∞C. (Note 5)TI I G CHARACTERISTICS

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSAMPLE(MAX) Maximum Sampling Frequency Through CH0 to CH7 Inputs ● 100 kHzThrough ADC+, ADC– Only 166 kHz

tCONV Conversion Time ● 4 5 ms

tACQ Acquisition Time Through CH0 to CH7 Inputs ● 4 msThrough ADC+, ADC– Only 1 ms

fSCK SCK Frequency (Note 13) ● 0 20 MHz

tr SDO Rise Time See Test Circuits 6 ns

tf SDO Fall Time See Test Circuits 6 ns

t1 CONVST High Time ● 40 ns

t2 CONVST to BUSY Delay CL = 25pF, See Test Circuits ● 15 30 ns

t3 SCK Period ● 50 ns

t4 SCK High ● 10 ns

t5 SCK Low ● 10 ns

t6 Delay Time, SCKØ to SDO Valid CL = 25pF, See Test Circuits ● 25 45 ns

t7 Time from Previous SDO Data Remains CL = 25pF, See Test Circuits ● 5 20 nsValid After SCKØ

t8 SDO Valid After RDØ CL = 25pF, See Test Circuits ● 11 30 ns

t9 RDØ to SCK Setup Time ● 20 ns

t10 SDI Setup Time Before SCK≠ ● 0 ns

t11 SDI Hold Time After SCK≠ ● 7 ns

t12 SDO Valid Before BUSY≠ RD = Low, CL = 25pF, See Test Circuits ● 5 20 ns

t13 Bus Relinquish Time See Test Circuits ● 10 30 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.Note 2: All voltage values are with respect to ground with DGND, AGND1,AGND2 and AGND3 wired together unless otherwise noted.Note 3: When these pin voltages are taken below ground or above AVDD =DVDD = OVDD = VDD, they will be clamped by internal diodes. This productcan handle currents of greater than 100mA below ground or above VDDwithout latchup.Note 4: When these pin voltages are taken below ground they will beclamped by internal diodes. This product can handle currents of greaterthan 100mA below ground without latchup. These pins are not clampedto VDD.Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwisespecified.Note 6: Linearity, offset and full-scale specifications apply for a single-ended analog MUX input with respect to ground or ADC+ with respect toADC– tied to ground.

Note 7: Integral nonlinearity is defined as the deviation of a code from astraight line passing through the actual end points of the transfer curve.The deviation is measured from the center of the quantization band.Note 8: Bipolar zero error is the offset voltage measured from –0.5LSBwhen the output code flickers between 0000 0000 0000 0000 and 11111111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 111111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 11111111 1111 for the LTC1854.Note 9: Guaranteed by design, not subject to test.Note 10: Recommended operating conditions.Note 11: Full-scale bipolar error is the worst case of –FS or +FSuntrimmed deviation from ideal first and last code transitions, divided bythe full-scale range, and includes the effect of offset error.Note 12: Recovers to specified performance after (2 • FS) inputovervoltage.Note 13: t6 of 45ns maximum allows fSCK up to 10MHz for rising capturewith 50% duty cycle and fSCK up to 20MHz for falling capture (with 5nssetup time for the receiving logic).

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LTC1854/LTC1855/LTC1856

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LTC1855 Nonaveraged4096-Point FFT PlotLTC1855 Typical INL Curve LTC1855 Typical DNL Curve

TYPICAL PERFOR A CE CHARACTERISTICS

UW

CODE–32768

INL

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)

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185456 G01

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LTC1856 Nonaveraged4096-Point FFT PlotLTC1856 Typical INL Curve LTC1856 Typical DNL Curve

LTC1854 Nonaveraged4096-Point FFT PlotLTC1854 Typical DNL CurveLTC1854 Typical INL Curve

CODE–8192

INL

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0.4

0.2

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8191

185455 G04

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FREQUENCY (kHz)0 15 25 50

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5 10 20 30 40 4535

MAG

NITU

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B)

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fSAMPLE = 100kHzfIN = 1kHzSINAD = 83dBTHD = –95dB

CODE–2048

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INL

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185456 G07

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1024 2047CODE

–2048–1.0

DNL

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–1024 0

185456 G08

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1024 2047FREQUENCY (kHz)

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MAG

NITU

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B)

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40

185456 G09

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10 20 30 50

fSAMPLE = 100kHzfIN = 1kHzSINAD = 73.6dBTHD = –102dB


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LTC1854/LTC1855/LTC1856

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TEMPERATURE (°C)–50

–0.25

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LTC1855 SINADvs Input Frequency

LTC1855 Total HarmonicDistortion vs Input Frequency

LTC1855 Channel-to-ChannelOffset Error Matching vsTemperature




INPUT FREQUENCY (kHz)1

74

SINA

D (d

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TOTA

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TOTA

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1001 10

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LTC1854/LTC1855/LTC1856

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LTC1856 Power SupplyFeedthrough vs Ripple Frequency

Supply Current vs Supply Voltage Supply Current vs Temperature


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LTC1854 Channel-to-Channel GainError Matching vs Temperature



Change in REFCOMP Voltagevs Load Current

Internal Reference Voltagevs Temperature


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CHAN

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2.520

2.515

2.510

2.505

2.500

2.495

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2.485

2.480100

LOAD CURRENT (mA)–50

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REF

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PI FU CTIO SCOM (Pin 1): Common Input. This is the negative refer-ence point for all single-ended inputs. It must be free ofnoise and is usually connected to the analog ground plane.

CH0 (Pin 2): Analog MUX Input.








MUXOUT+ (Pin 10): Positive MUX Output. Output of theanalog multiplexer. Connect to ADC+ for normal operation.

MUXOUT– (Pin 11): Negative MUX Output. Output of theanalog multiplexer. Connect to ADC– for normal operation.

ADC+ (Pin 12): Positive Analog Input to the Analog-to-Digital Converter.

ADC– (Pin 13): Negative Analog Input to the Analog-to-Digital Converter.

AGND1 (Pin 14): Analog Ground.

VREF (Pin 15): 2.5V Reference Output. Bypass to analogground with a 1mF tantalum capacitor.

REFCOMP (Pin 16): Reference Buffer Output. Bypass toanalog ground with a 10mF tantalum and a 0.1mF ceramiccapacitor. Nominal output voltage is 4.096V.

AGND2 (Pin 17): Analog Ground.

AGND3 (Pin 18): Analog Ground. This is the substrateconnection.

AVDD (Pin 19): 5V Analog Supply. Bypass to analog groundwith a 0.1mF ceramic and a 10mF tantalum capacitor.

DVDD (Pin 20): 5V Digital Supply. Bypass to digital groundwith a 0.1mF ceramic and a 10mF tantalum capacitor.

OVDD (Pin 21): Positive Supply for the Digital OutputBuffers (3V to 5V). Bypass to digital ground with a 0.1mFceramic and a 10mF tantalum capacitor.

BUSY (Pin 22): Output shows converter status. It is lowwhen a conversion is in progress.

SDO (Pin 23): Serial Data Output.

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LTC1854/LTC1855/LTC1856

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UU WFU CTIO AL BLOCK DIAGRA

2.5VREFERENCE

INTERNALCLOCK

1.6384X

4.096V

8k

AGND1

CONTROLLOGIC

SERIAL I/O

INPUT MUX

AGND3AGND2REFCOMPVREF

ADC–MUXOUT+MUXOUT– ADC+

DGND

AVDD DVDD

MUX ADDRESS

DATA OUT

CONVST

19 20

28

25

2

3

9

1

22

26

27

21

23

24181716151312101114

SDI

BUSY

SCK

RD

OVDD

SDO

18545 BD

12-/14-/16-BITSAMPLING ADC

+

–COM

CH7

CH1

•••

CH0

DGND (Pin 24): Digital Ground.

SDI (Pin 25): Serial Data Input.

SCK (Pin 26): Serial Data Clock.

UUU

PI FU CTIO SRD (Pin 27): Read Input. This active low signal enables thedigital output pin SDO and enables the serial interface, SDIand SCK are ignored when RD is high.

CONVST (Pin 28): Conversion Start. The ADC starts aconversion on CONVST’s rising edge.

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t2 (CONVST to BUSY Delay)t2

CONVST

BUSY

2.4V

0.4V18545 TD02

t6 (Delay Time, SCK� to SDO Valid)t7 (Time from Previous Data Remains Valid After SCK�)

t6t7

SCK

SDO2.4V

0.4V

0.4V18545 TD04

t8 (SDO Valid After RD�)t8

RD

SDO2.4V

0.4V

0.4V18545 TD05

Hi-Z

t9 (RD� to SCK Setup Time)

t9

0.4V

2.4V

18545 TD06

RD

SCK

TI I G DIAGRA S

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t1 (For Short Pulse Mode)

t1

CONVST 50%

18545 TD01

50%

t3, t4, t5 (SCK Timing)

SCK

18545 TD03

t4 t5

t3

Load Circuits for Access Timing

1k

(A) Hi-Z TO VOH AND VOL TO VOH

25pF

1k

5V

DNDN

(B) Hi-Z TO VOL AND VOH TO VOL

25pF

18545 TC01

Load Circuits for Output Float Delay

1k

(A) VOH TO Hi-Z

25pF

1k

5V

DNDN

(B) VOL TO Hi-Z

25pF

18545 TC02

TEST CIRCUITS

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LTC1854/LTC1855/LTC1856

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t10 (SDI Setup Time Before SCK�)t10

SCK

SDI2.4V

2.4V

0.4V18545 TD07

t11 (SDI Hold Time After SCK�)t11

SCK

SDI2.4V

2.4V

0.4V18545 TD08

t12 (SDO Valid Before BUSY�, RD = 0)t12

BUSY

SDO2.4V

B15

2.4V

18545 TD09

t13 (BUS Relinquish Time)t13

RD

SDO

2.4V

18545 TD1010%

90% Hi-Z

TI I G DIAGRA SW WU

13

LTC1854/LTC1855/LTC1856

185456fa

OVERVIEW

The LTC1854/LTC1855/LTC1856 are innovative, multi-channel ADCs. The on-chip resistors provide attenuationand offset for each channel. The precisely trimmed attenu-ators ensure an accurate input range. Because they pre-cede the multiplexer, errors due to multiplexeron-resistance are eliminated.

The input word selects the single ended or differentialinputs for each channel or pair of channels. Overrangeprotection is provided for unselected channels. Anoverrange condition on an unused channel will not affectthe conversion result on the selected channel.

CONVERSION DETAILS

The LTC1854/LTC1855/LTC1856 use a successive approxi-mation algorithm and an internal sample-and-hold circuitto convert an analog signal to a 12-/14-/16-bit serial out-put respectively. The ADCs are complete with a precisionreference and an internal clock. The control logic provideseasy interface to microprocessors and DSPs. (Please referto the Digital Interface section for the data format.)

The analog signals applied at the MUX input channels arerescaled by the resistor divider network formed by R1, R2and R3 as shown below. The rescaled signals appear onthe MUXOUT (Pins 10, 11) which are also connected to theADC inputs (Pins 12, 13) under normal operation.

APPLICATIO S I FOR ATIO

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Before starting a conversion, an 8-bit data word is clockedinto the SDI input on the first eight rising SCK edges toselect the MUX address and power down mode. The ADCenters acquisition mode on the falling edge of the sixthclock in the 8-bit data word and ends on the rising edge ofthe CONVST signal which also starts a conversion (seeFigure 7). A minimum time of 4ms will provide enough timefor the sample-and-hold capacitors to acquire the analogsignal. Once a conversion cycle has begun, it cannot berestarted.

During the conversion, the internal differential 12-/14-/16-bit capacitive DAC output is sequenced by the SAR from themost significant bit (MSB) to the least significant bit (LSB).The input is successively compared with the binaryweighted charges supplied by the differential capacitiveDAC. Bit decisions are made by a high speed comparator.At the end of a conversion, the DAC output balances theanalog input (ADC+ – ADC–). The SAR contents (a 12-/14-/16-bit data word) which represents the difference of ADC+

and ADC– are loaded into the 12-/14-/16-bit shift register.

DRIVING THE ANALOG INPUTS

The input range for the LTC1854/LTC1855/LTC1856 is±10V and the MUX inputs are overvoltage protected to±30V. The input impedance is typically 31kW; therefore, itshould be driven with a low impedance source. Widebandnoise coupling into the input can be minimized by placinga 3000pF capacitor at the input as shown in Figure 2. AnNPO-type capacitor gives the lowest distortion. Place thecapacitor as close to the device input pin as possible. If anamplifier is to be used to drive the input, care should betaken to select an amplifier with adequate accuracy, linear-ity and noise for the application. The following list is asummary of the op amps that are suitable for driving theLTC1854/LTC1855/LTC1856. More detailed informationis available in the Linear Technology data books and onlineat www.linear.com.

LT®1007: Low noise precision amplifier. 2.7mA supplycurrent ±5V to ±15V supplies. Gain bandwidth product8MHz. DC applications.

MUXINPUT

R125k

REFCOMP

CH SELR3

10k

18545 AI01R217k

MUXOUT

14

LTC1854/LTC1855/LTC1856

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LT1227: 140MHz video current feedback amplifier. 10mAsupply current. ±5V to ±15V supplies. Low noise and lowdistortion.

LT1468/LT1469: Single and dual 90MHz, 16-bit accurateop amp. Good AC/DC specs. ±5V to ±15V supplies.

LT1677: Single, low noise op amp. Rail-to-rail input andoutput. Up to ±15V supplies.


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3000pF

18545 F02

AIN+

AIN–

CH0

CH1

MUXOUT+

MUXOUT–

ADC+

ADC–

••••

Figure 2. Analog Input Filtering

Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit

LT1792: Single, low noise JFET input op amp, ±5Vsupplies.

LT1793: Single, low noise JFET input op amp, 10pA biascurrent, ±5V supplies.

LT1881/LT1882: Dual and quad, 200pA bias current, rail-to-rail output op amps. Up to ±15V supplies.

LT1844/LT1885: Dual and quad, 400pA bias current, rail-to-rail output op amps. Up to ±15V supplies. Fasterresponse and settling time.

INTERNAL VOLTAGE REFERENCE

The LTC1854/LTC1855/LTC1856 have an on-chip, tem-perature compensated, curvature corrected, bandgap ref-erence, which is factory trimmed to 2.50V. The full-scalerange of the LTC1854/LTC1855/LTC1856 is equal to ±10V.The output of the reference is connected to the input of again of 1.6384x buffer through an 8k resistor (see Figure3). The input to the buffer or the output of the reference is

2.5VREFERENCE

INTERNALCLOCK

1.6384X

4.096V

8k

AGND1

CONTROLLOGIC

SERIAL I/O

INPUT MUX

AGND3AGND2REFCOMPVREF

ADC–MUXOUT+MUXOUT– ADC+

DGND

AVDD DVDD

MUX ADDRESS

DATA OUT

CONVST

SDI

BUSY

SCK

RD

OVDD

SDO

18545 F01


+

–COM

CH7

CH1

•••

CH0

15

LTC1854/LTC1855/LTC1856

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Figure 4. Bipolar Transfer Characteristics

18545 F04

011...111

011...110

000...001

000...000

111...111

111...110

100...001

100...000

FS – 1LSB–(FS – 1LSB) INPUT VOLTAGE (V)

OUTP

UT C

ODE

available at VREF (Pin 15). The internal reference can beoverdriven with an external reference if more accuracy isneeded. The buffer output drives the internal DAC and isavailable at REFCOMP (Pin 16). The REFCOMP pin can beused to drive a steady DC load of less than 2mA. Drivingan AC load is not recommended because it can cause theperformance of the converter to degrade.

successive integer LSB values (i.e., –FS+0.5LSB,–FS+1.5LSB, –FS+2.5LSB, … FS–1.5LSB, FS–0.5LSB).The output is two’s complement binary with:

1FS FS)

6556620V

65536305.2 VLSB = = =–(– m

In applications where absolute accuracy is important,offset and full-scale errors can be adjusted to zero duringa calibration sequence. Offset error must be adjustedbefore full-scale error. Zero offset is achieved by adjustingthe offset applied to the “–” input. For single-ended inputs,this offset should be applied to the COM pin. For differen-tial inputs, the “–” input is dictated by the MUX address.

For zero offset error, apply –0.5LSB to the “+” input andadjust the offset at the “–” input until the output codeflickers between 0000 0000 0000 0000 and 1111 11111111 1111 for the LTC1856, between 00 0000 0000 0000and 11 1111 1111 1111 for the LTC1855 and between0000 0000 0000 and 1111 1111 1111 for the LTC1854.

For full-scale adjustment, an input voltage of FS – 1.5LSBsshould be applied to the “+” input and the appropriatereference adjusted until the output code flickers between0111 1111 1111 1110 and 0111 1111 1111 1111 for theLTC1856, between 01 1111 1111 1110 and 01 1111 11111111 for the LTC1855 and between 0111 1111 1110 and0111 1111 1111 for the LTC1854.

These adjustments as well as the factory trims affect allchannels. The channel-to-channel offset and gain errormatching are guaranteed by design to meet the specifica-tions in the Converter Characteristics table.


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Figure 3. Internal or External Reference Source

2.5VREFERENCE

18545 F03

12-/14-/16-BITCAPACITIVE DAC

1.6384X BUFFER

8kVREF

1μF

152.5V

16 REFCOMP

0.1μF

4.096V

10μF

For minimum code transition noise the VREF pin and theREFCOMP pin should each be decoupled with a capacitorto filter wideband noise from the reference and the buffer.

FULL SCALE AND OFFSET

Figure 4 shows the ideal input/output characteristics forthe LTC1856. The code transitions occur midway between

16

LTC1854/LTC1855/LTC1856

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cated output supply pin (OVDD) that controls the outputswings of the digital output pins (SDO, BUSY) and allowsthe part to interface to either 3V or 5V digital systems. TheSDO output is two’s complement.

Timing and Control

Conversion start and data read are controlled by twodigital inputs: CONVST and RD. To start a conversion andput the sample-and-hold into the hold mode bring CONVSThigh for at least 40ns. Once initiated it cannot be restarteduntil the conversion is complete. Converter status isindicated by the BUSY output, which goes low while theconversion is in progress.

Figures 6a and 6b show two different modes of operationfor the LTC1856. For the 12-bit LTC1854 and 14-bitLTC1855, the last four and two bits of the SDO will outputzeros, respectively. In mode 1 (Figure 6a), RD is tied low.The rising edge of CONVST starts the conversion. The dataoutputs are always enabled. The MSB of the data output isavailable after the conversion. In mode 2 (Figure 6b),CONVST and RD are tied together. The rising edge of theCONVST signal starts the conversion. Data outputs are inthree-state at this time. When the conversion is complete(BUSY goes high), CONVST and RD go low to enable thedata output for the previous conversion.


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Figure 5. LTC1856 Histogram for 4096 Conversions

DC PERFORMANCE

One way of measuring the transition noise associatedwith a high resolution ADC is to use a technique where aDC signal is applied to the input of the MUX and theresulting output codes are collected over a large numberof conversions. For example in Figure 5 the distribution ofoutput code is shown for a DC input that has been digitized4096 times. The distribution is Gaussian and the RMScode transition is about 1LSB for the LTC1856.

DIGITAL INTERFACE

Internal Clock

The ADC has an internal clock that is trimmed to achievea typical conversion time of 4ms. No external adjustmentsare required and, with the maximum acquisition time of 4ms,throughput performance of 100ksps is assured.

3V Input/Output Compatible

The LTC1854/LTC1855/LTC1856 operate on a 5V supply,which makes the devices easy to interface to 5V digitalsystems. These devices can also interface to 3V digitalsystems: the digital input pins (SCK, SDI, CONVST andRD) of the LTC1854/LTC1855/LTC1856 recognize 3V or5V inputs. The LTC1854/LTC1855/LTC1856 have a dedi-

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LTC1854/LTC1855/LTC1856

185456fa

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18

LTC1854/LTC1855/LTC1856

185456fa

SGL/DIFF

SELECT1

SELECT0

DON'TCARE

DON'TCARE

MUX ADDRESS

18545 AI03

ODDSIGN

NAP

POWER DOWNSELECTION

SLEEP

Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856

01234567

CHANNEL

COM (–)

8 Single-Ended

+++++++0,1

CHANNEL

4 Differential

2,3

4,5

6,7

+ (–) +

+ (–)

+ (–)

+ (–)– (+)

– (+)

– (+)

– (+)

4567

CHANNEL

COM (–)

Combinations ofDifferential and Single-Ended

+++++

+0,1

2,3

––

COM (UNUSED)

Changing theMUX Assignment “On the Fly”

COM (–)

4,5

6,7

4,5

1ST CONVERSION 2ND CONVERSION

+–+–

+–

++7

6

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SERIAL DATA INPUT (SDI) INTERFACE

The LTC1854/LTC1855/LTC1856 communicate with mi-croprocessors and other external circuitry via a synchro-nous, full duplex, 3-wire serial interface (see Figure 7).The shift clock (SCK) synchronizes the data transfer witheach bit being transmitted on the falling SCK edge andcaptured on the rising SCK edge in both transmitting andreceiving systems. The data is transmitted and receivedsimultaneously (full duplex).

An 8-bit input word is shifted into the SDI input whichconfigures the LTC1854/LTC1855/LTC1856 for the nextconversion. Simultaneously, the result of the previousconversion is output on the SDO line. At the end of the dataexchange the requested conversion begins by applying arising edge on CONVST. After tCONV, the conversion iscomplete and the results will be available on the next datatransfer cycle. As shown below, the result of a conversion

is delayed by one conversion from the input word re-questing it.

SDI

SDO SDO WORD 0

SDI WORD 1

DATATRANSFER

SDO WORD 2

SDI WORD 3

SDO WORD 1

SDI WORD 2

DATATRANSFER

tCONVA/D

CONVERSION

tCONVA/D

CONVERSION

18545 AI02

MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION

Table 1. Multiplexer Channel Selection

MUX ADDRESSSGL/DIFF

SELECT1 0

ODDSIGN

1 0 0 0 + –1 0 0 1 + –1 0 1 0 + –1 0 1 1 + –1 1 0 0 + –1 1 0 1 + –1 1 1 0 + –1 1 1 1 + –

SGL/DIFF

ODDSIGN

SELECT1 0

0 0 0 0 + –0 0 0 1 + –0 0 1 0 + –0 0 1 1 + –0 1 0 0 – +0 1 0 1 – +0 1 1 0 – +0 1 1 1 – +

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 COM

SINGLE-ENDED CHANNEL SELECTION

INPUT DATA WORD

The LTC1854/LTC1855/LTC1856 8-bit data word is clockedinto the SDI input on the first eight rising SCK edges.Further inputs on the SDI pin are then ignored until the nextconversion. The eight bits of the input word are defined asfollows:

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LTC1854/LTC1855/LTC1856

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MUX ADDRESS

The first four bits of the input word assign the MUXconfiguration for the requested conversion. For a givenchannel selection, the converter will measure the voltagebetween the two channels indicated by the + and – signsin the selected row of Table 1. Note that in differentialmode (SGL/DIFF = 0) measurements are limited to fouradjacent input pairs with either polarity. In single-endedmode, all input channels are measured with respect toCOM. Both the “+” and “–” inputs are sampled simulta-neously so common mode noise is rejected. Bits 5 and 6of the input words are Don’t Care bits.

POWER DOWN SELECTION (NAP, SLEEP)

The last two bits of the input word (Nap and Sleep) deter-mine the power shutdown mode of the LTC1854/LTC1855/LTC1856. See Table 2. Nap mode is selected when Nap =1 and Sleep = 0. The previous conversion result will beclocked out and a conversion will occur before enteringthe Nap mode. The Nap mode starts at the end of the con-version which is indicated by the rising edge of the BUSYsignal. Nap mode lasts until the falling edge of the 2nd SCK(see Figure 9). Automatic nap will be achieved if Nap = 1is selected each time an input word is written to the ADC.

Table 2. Power Down Selection

NAP SLEEP POWER DOWN MODE

0 0 Power On

1 0 Nap

X 1 Sleep

Sleep mode will occur when Sleep = 1 is selected,regardless of the selection of the Nap input. The previousconversion result can be clocked out and the Sleep modewill start on the falling edge of the last (16th) SCK. Noticethat the CONVST should stay either high or low in sleepmode (see Figure 10). To wake up from the sleep mode,apply a rising edge on the CONVST signal and then applySleep = 0 on the next SDI word and the part will wake upon the falling edge of the last (16th) SCK (see Figure 11).

In Sleep mode, all bias currents are shut down and only thepower on reset circuit and leakage currents (about 10mA)remain. Sleep mode wake-up time is dependent on thevalue of the capacitor connected to the REFCOMP (Pin 16).The wake-up time is typically 40ms with the recom-mended 10mF capacitor connected on the REFCOMP pin.

DYNAMIC PERFORMANCE

FFT (Fast Fourier Transform) test techniques are used totest the ADC’s frequency response, distortion and noiseat the rated throughput. By applying a low distortion sinewave and analyzing the digital output using an FFTalgorithm, the ADC’s spectral content can be examinedfor frequencies outside the fundamental. Figure 12 showsa typical LTC1856 FFT plot which yields a SINAD of 87dBand THD of –101dB.

20

LTC1854/LTC1855/LTC1856

185456fa


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21

LTC1854/LTC1855/LTC1856

185456fa

SIGNAL-TO-NOISE AND DISTORTION RATIO

The Signal-to-Noise and Distortion Ratio (SINAD) is theratio between the RMS amplitude of the fundamental inputfrequency to the RMS amplitude of all other frequencycomponents at the A/D output. The output is band limitedto frequencies from above DC and below half the samplingfrequency. Figure 12 shows a typical SINAD of 87dB witha 100kHz sampling rate and a 1kHz input.

TOTAL HARMONIC DISTORTION

Total Harmonic Distortion (THD) is the ratio of the RMSsum of all harmonics of the input signal to the fundamentalitself. The out-of-band harmonics alias into the frequencyband between DC and half the sampling frequency. THD isexpressed as:

THD = 20logV2

232

42 2

1

+ + +V V VV

N...

where V1 is the RMS amplitude of the fundamental fre-quency and V2 through VN are the amplitudes of thesecond through Nth harmonics.

BOARD LAYOUT, POWER SUPPLIESAND DECOUPLING

Wire wrap boards are not recommended for high resolu-tion or high speed A/D converters. To obtain the bestperformance from the LTC1854/LTC1855/LTC1856, aprinted circuit board is required. Layout for the printedcircuit board should ensure the digital and analog signallines are separated as much as possible. In particular, careshould be taken not to run any digital track alongside ananalog signal track or underneath the ADC. The analoginput should be screened by AGND.

In applications where the MUX is connected to the ADC, itis possible to get noise coupling into the ADC from thetrace connecting the MUXOUT to the ADC. Therefore,reducing the length of the traces connecting the MUXOUTpins (Pins 10, 11) to the ADC pins (Pins 12, 13) canminimize the problem. The unused MUX inputs should begrounded to prevent noise coupling into the inputs.

Figure 13 shows the power supply grounding that will helpobtain the best performance from the 12-bit/14-bit/16-bitADCs. Pay particular attention to the design of the analogand digital ground planes. The DGND pin of the LTC1854/


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Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot


185456 F12

5 10 20 30 40 4535

MAG

NITU

DE (d

B)

–60

–40

–20

0

–80

–100

–70

–50

–30

–10

–90

–110

–130–120


22

LTC1854/LTC1855/LTC1856

185456fa


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18545 F13

ADC+

LTC1854/LTC1855/LTC1856 DIGITALSYSTEM

OVDDDGND

24 21

ADC–

10μF

DVDD

20

10μF

AVDD

19

AGND

14, 17, 18

10μF

REFCOMP

16

10μF

VREF

15

12MUXOUT+

LTC1854/LTC1855/LTC1856

MUXOUT–

10CH0CH1CH2CH3CH4CH5CH6CH7COM

11 13

1μF

ANALOG GROUND PLANEDIGITAL

GROUND PLANE

+–

Figure 13. Power Supply Grounding Practice

LTC1855/LTC1856 can be tied to the analog ground plane.Placing the bypass capacitor as close as possible to thepower supply pins, the reference and reference bufferoutput is very important. Low impedance common returnsfor these bypass capacitors are essential to low noise op-eration of the ADC, and the foil width for these tracks shouldbe as wide as possible. Also, since any potential difference

in grounds between the signal source and ADC appears asan error voltage in series with the input signal, attentionshould be paid to reducing the ground circuit impedanceas much as possible. The digital output latches and theonboard sampling clock have been placed on the digitalground plane. The two ground planes are tied together atthe ADC through a wide, low inductance path.

23

LTC1854/LTC1855/LTC1856

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PACKAGE DESCRIPTIOG Package

28-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

G28 SSOP 0204

0.09 – 0.25(.0035 – .010)

0° – 8°

0.55 – 0.95(.022 – .037)

5.00 – 5.60**(.197 – .221)

7.40 – 8.20(.291 – .323)

1 2 3 4 5 6 7 8 9 10 11 12 1413

9.90 – 10.50*(.390 – .413)

2526 22 21 20 19 18 17 16 1523242728

2.0(.079)MAX

0.05(.002)MIN

0.65(.0256)

BSC0.22 – 0.38

(.009 – .015)TYPMILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.77.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

24

LTC1854/LTC1855/LTC1856

185456fa

„ LINEAR TECHNOLOGY CORPORATION 2006

LT 0407 REV A • PRINTED IN THE USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

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TYPICAL APPLICATIO

RELATED PARTS

2.5VREFERENCE

INTERNALCLOCK

1.6384X

4.096V

8k

AGND1

CONTROLLOGIC

SERIAL I/O

INPUT MUX

AGND3AGND2REFCOMPVREFADC–MUXOUT+MUXOUT– ADC+ DGND

AVDD DVDD

MUX ADDRESS

DATA OUT

CONVST 28

25

22

26

27

21

23

3V TO 5V

SDI

BUSY

SCK

RD

OVDD

SDO

18545 TA03


+

–

COM

19 20

5V5V

1

2

3

9 CH7

14 11 10 12 13 15 16 17 18 241μF

0.1μF

CH1SINGLE-ENDEDOR DIFFERENTIAL

CHANNELSELECTION

(SEE TABLE 1)

INPUT RANGE: ±10V

•••

CH0

10μF

0.1μF10μF

8-BIT SERIAL DATA INPUT

16 SHIFT CLOCK CYCLES

16-BIT SERIAL DATA OUT

10μF 0.1μF10μF 0.1μF

PART NUMBER DESCRIPTION COMMENTSSampling ADCsLTC1418 14-Bit, 200ksps, Single 5V or ±5V ADC 15mW, Serial/Parallel I/OLTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605LTC1608 16-Bit, 500ksps, ±5V ADC 90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604LTC1609 16-Bit, 200ksps Serial ADC Configurable Unipolar/Bipolar Input, Up to 10V Single 5V SupplyLTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC Programmable MUX and Sequencer, Parallel I/OLTC1859/LTC1858/ 16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs Software-Selectable Spans, Pin Compatible withLTC1857LTC1864/LTC1865 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP Single 5V Supply, 850mA with AutoshutdownLTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP Single 3V Supply, 450mA with Autoshutdown

LTC1856/LTC1855/LTC1854DACsLTC1588/LTC1589 12-/14-/16-Bit, Serial, SoftSpan IOUT DACs Software-Selectable Spans, ±1LSB INL/DNLLTC1592LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit UpgradeLTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit UpgradeLTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant ResistorsLTC1650 16-Bit Serial VOUT ±5V DAC Low Power, Low Glitch, 4-Quadrant MultiplicationLTC2704-16/ 16-Bit, 14-Bit, 12-Bit, Serial, Quad SoftSpan Software-Selectable Spans, ±2LSB INL, ±1LSB INL,LTC2704-14/ VOUT DACs Force/Sense OutputLTC2704-12

Documents

LTC1854/LTC1855/LTC1856 - 8-Channel, ±10V Input 12-/14-/16 … · 2014-11-27 · 1 ltc1854/ltc1855/ltc1856 185456fa com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 muxout+ muxout– adc+ adc–