L’upgrade del Silicon Vertex Trigger (SVT) di CDF

April 2006 Alberto Annovi- IFAE 2006 1

SVT

SVTL’upgrade del Silicon Vertex

Trigger (SVT) di CDF

IFAE 2006

Alberto AnnoviIstituto Nazionale di Fisica Nucleare

Laboratori Nazionali di Frascati


SVT

Outline

• the Silicon Vertex Trigger (SVT)

• Motivations

• Working principles

• Performance

• Upgrade


SVT

Why and how?

• Trigger on B hadronic decays– B physics studies, eg. CP violation in B decays, Bs mixing– new particle searches, eg. Higgs, Supersymmetry

• A b-trigger is particularly important at hadron colliders– large B production cross section for B physics– high energy available to produce new particles decaying to b quarks– overwhelming QCD background O(103)

• need to improve S/B at trigger level

• Detect large impact parameter tracks from B decays using the fact that (B)1.5 ps

secondary vertex

primary vertex

Technical challenge!

~ 1 mm


SVT

SVT: Input & Output

Inputs:– L1 tracks from XFT (, pT)– digitized pulse heights

from SVX II

Functionalities:– hit cluster finding– pattern recognition– track fitting

Outputs:– reconstructed tracks

(d, , pT)


SVT

SVT Design ConstraintsDetector

Raw Data

Level 1 pipeline: 42 clock cycles

Level 1Trigger

L1Accept

Level 2Trigger

Level 2 buffer: 4 events

L2Accept

DAQ buffers

L3 Farm

Level 1•7.6 MHz Synchromous Pipeline•5.5 s Latency•30 kHz accept rate

Level 2• Asynchromous 2 Stage Pipeline•20 s Latency•800 Hz accept rate

Mass Storage (100 Hz)

7.6 MHz Crossing rate

•30 kHz input rate•O(103) SVX strips/event•2-D low-res COT tracks

•Latency O(20) sec•No Dead Time•Resolution offline

•SVT upgrade keep it fast @ high luminosity

SVX read out after L1

At L3 it is too late

SVT here


SVT

Roads1. Find low

resolution track candidates called “roads”. Solve most of the pattern recognition

2. Then fit tracks inside roads.Thanks to 1st step it is much easier

offline quality

Super Bin (SB)

Tracking in 2 steps


SVT

The Event

...

The Pattern Bank

Pattern matching


SVT

•Dedicated device: maximum parallelism•Each pattern with private comparator•Track search during detector readout

AM: Associative Memory

Bingo scorecard

AM = BINGO PLAYERS

HIT # 1447

PATTERN NPATTERN 1 PATTERN 2 PATTERN 3

PATTERN 5PATTERN 4


SVT

New AM chip

• Parallel pattern recognition is performed by the Associative Memory an array of AMchips

• Pattern recognition happens during detector readout!

• Standard Cell UMC 0.18 m 10x10 mm die - 5000 patterns (was 128)6 input hit buses (4Gbit/s)tested up to 40 MHz, simulated up to 50 MHz

• 3000 production chips on April 2005good yield 70%

Original AM chip


SVT

2nd step: Track Fitting

• Track confined to a thin pattern: fitting becomes easy

• Linear expansion in the hit positions xi: – Chi2 = Sumk ( (cik xi)^2 )– d = d0+ai xi ; phi = phi0+ bi xi ; Pt = ...

• Fit reduces to a few scalar products: fast evaluation– (DSP, FPGA …)

• Constants from detector geometry– Calculate in advance– Correction of mechanical alignments via linear algorithm

• fast and stable• A tough problem made easy !


SVT

Constraint surface


SVT

SVT crates in CDF counting room


SVT

0 10 20 30 40 50Latency (s)

Performance @ 10x1031

20 s

-500 -250 0 250 500

(m)

35m 33mresol beam = 48m

0.00 0.05 0.10 0.15Impact parameter (cm)

Effi

cien

cy

Given a fiducial offline track with SVX hits in 4/4 layers used by SVT

0.8

SVTImpact parameter


SVT

d

phi

d

Online beamline fit & correction

Subtracted

Raw

x

y

d

<d> = Ybeamcos – Xbeamsin


SVT

Hadronic B decays with SVT

• L1:•Two XFT tracks•Pt > 2 GeV; Pt1 + Pt2 > 5.5 GeV < 135°

• L2:•d0>100 m for both tracks•Validation of L1 cuts with >20°•Lxy > 200 m•d0(B)<140 m

Two body decays

@ 3 x 1031 cm-2 s-1

SVT

The SVT advantage:3 orders of magnitude


SVT

Signal yield: ~2300 events S/B 6.5 (peak value)

Mhh (GeV)

Ks

D0

Hadron-hadron mass distribution

See tomorrow talks for up to date B--> h h’ (M. Morello) and Bs mixing (Salamanna)

SVT for hadronic Bs decays --> sesitivity at high ms


SVT

SVT upgrade

• Speed up SVT execution– cope with high lumi– reduce dead-time --> increase LVL1 bandwidth --> physics output– extra features

• forward muon/electron trigger (Silicon only tracking)• release SVT upper impact parameter cut beyond 1mm

– (CDF note PUB/CDF7359 to be published as NIM)

• How to do that?– more powerful Associative Memory (32k --> 512k patterns)

• Improve pattern recognition resolution– Reduce number of roads to fit

– Replace AMS, RW, HB, TF with Pulsar boards• Support 512k pattern/wedge• Higher clock frequency --> faster track fitting & I/O

Deadtime L2 processing time * L1 Accept rate


SVT

TsukubaChicagoFermilab

Chicago

Pisa1st Pulsar:

Sequencer & Road Warrior

Associative Memory 512k

patterns

2nd Pulsar:Hit Buffer

3nd Pulsar:Track Fitter


SVT

24 AM++ installation

• 2 AM++ per 30 degrees• 512k patterns• pattern width 240m

•was 600m with 32kpatt.

Currently using 512k patterns for maximum speed.Extend tracking applications:•release upper I.p. cut•Pt down to 1.5GeV

<# of fits> RMS # fits

32k patt 32 42

128k patt 20 32

512k patt 12 18Lumi = 100E30 cm-2s-1


SVT

Pulsar in SVT++Implement new boards with Pulsars:•Fast enough to handle the new amount of data•SVT interface built in•Developers can concentrate on firmware (= board functionalities)

The Pulsar board is a programmable board: 3 powerful FPGAsembedded RAM

all CDF connectors modular mezzanines

S-link I/ORAM extension

Pulsar @ CDF --> FPGAs @ board devel.

RAM mezzanine 4Mx48bits


SVT

The CDF’s Road Warrior

RW:Remove ghosts

• majority logic: 4/5 SVX hits + XFT track•better efficiency

• problem: duplicate roads (ghost)• because of missing layers

• a common problem

A clean solution for ghost removal:• the road warrior board receives roads as they are found• store them in a dedicated Associative Memory

• FPGA based• each road is compared on-the-fly with previous roads

• AM algorithm: identify and drop duplicate roads• O(10) clock cycles latency

proceedings of 2004 IEEE (NSS / MIC), Rome, Italy, 16-22 Oct 2004


SVT

impact of L2 upgrades on L1 bandwidth

0

2

4

6

8000 10000 12000 14000 16000 18000 20000 22000 24000 26000

Series1

Series2

Dead

t im

e %

L1 accept rate (Hz)

Before SVTUpgrade

Lumi 20-50E30

Summer 2005Lumi 90E30

18KHz 25KHz +7kHz (+40%) L1A bandwidth @ double inst. lumi.

Lumi 45E30

• full SVT upgradelumi 150E30


SVT

SVT SLIM5 (LVL1)Fast Track

(LVL2)

Next challenge is silicon tracking at both Level 1 & Level 2

LHC, Super B factory

What next ?

IEEE Trans.Nucl.Sci.51:391-400,2004


SVT

AMchip receives up to 6 parallel busesfor 6 layers at frequency:AMchip now: 50 MHz (Level 2)Next generation: 100 MHz or more Goal: use SAME CHIP for Level 2 & 1

SLIM5: Tracking (detector + TDAQ) R&D for SuperB but TDAQ could be OK for Level 1 at SLHC

1 AM for each enough-small space-time Patterns

Hits: position+time stampAll patterns inside a single chip

N chips for N overlapping eventsidentified by the time stamp

Event1AMchip1

Event2AMchip2

Event3AMchip3

EventNAMchipN

Main problem: AM input Bandwidth,even if powerful: >10 Gbits/sec divide the detector in thin sectors. Each AM searches in a small


SVT

SUMMARY

• The design and construction of SVT was a significant step forward in the technology of fast track finding

• We use a massively parallel/pipelined architecture combined with some innovative techniques such as the associative memory, linearized track fitting and road warrior

• CDF is triggering on impact parameter and collecting data leading to significant physics results

• B-physics, and not only, at hadron colliders substantially benefits of on-line tracking with off-line quality

• The system is modular and easy to upgrade

• The SVT technology is ready for other applications!


SVT

BACKUP SLIDES


SVT

SVX II

2.5 cm

10.6 cm

90 cm

-sector


SVT

AM chip internal structure

DB<11:0>

HIT COUNTER

AB<6:0> (OUTPUT MODE)

ADDRESS ENCODER

pattern 0

12 bits word12 bits compar.

COUNTSHIFT

pattern 1 pattern 127

HITBIT

DA

TA

BU

S M

UL

TIP

LE

XE

R

ADDRESS DECODERAB<6:0> ( R/W MODE)

SELECT PLANEDECODER

SELP<2:0>

OPC<3:0>ENP*SEL*

CLKACLKB

OR*

CO

NT

RO

L

MATCH BIT

layer0

layer1

layer3

layer2

layer4

layer5

HITBIT

HITBIT




SVT

Upgrading SVT

Hit Finders

Merger

Associative Memory

Hit Buffer

Track Fitter

to Level 2

COT tracks fromXTRP

12 fibers

hits

roads

hits

x 12 phi sectors

Sequencerraw data fromSVX front end

Road Warrior

RW:Remove ghosts

Reduce SVT processing time: c1+c2*N(Hit) +c3*N(Comb.)

1. More patterns thinner roads less fakes2. Move Road Warrior before the HB3. New TF++, HB++, AMS++, AM++ @ > 40MHz


SVT

xi

Non-linear geometrical constraint for a circle:

F(x1 , x2 , x3 , …) = 0

But for sufficiently small displacements:

F(x1 , x2 , x3 , …) ~ a0 + a1x1 + a2x2 + a3x3 + … = 0

with constant ai(first order expansion of F)

From non-linear to linear constraints


SVT

Dead Time vs. L1 Accept Rate

SVT @ 0.5 x 1032

SVT @ 3 x 1032

UPGRADE @ 3 x 1032


SVT

SVX only

Good tracks from just 4 closely spaced silicon layers

I.p. as expected due to the lack of curvature information

impact parameter distribution

~ 87 m

Silicon onlyno XFT


SVT

The Device

Hit Finder

AM Sequencer AM Board

Hit Buffer

Track Fitter

Detector Data

Hits

SuperStrip

MatchingPatterns

Roads

Roads + Corresponding

Hits

L2 CPU Tracks +

Corresponding Hits


SVT

Where could we insert FTK?

Fast Track + few(Road Finder) CPUs

Track dataROB

high-qualitytracks:Pt>1 GeV

Ev/sec = 50~100 kHz

Very low impact on DAQ

PIPELINE

LVL1

Fast network connectionCPU FARM (LVL2 Algorithms)

CALO MUON TRACKER

BufferMemory

ROD

BufferMemory

FEFE

Raw dataROBs

2nd output 1st output

No changeto LVL2


SVT

AMS/RW status (Pisa)

• AMS and RW firmware implemented and tested

• next step implement SVT firmware tools

• ON SCHEDULE

Pisa had the most risky responsibilities, but we are now in very good shape


SVT

Non italian responsabilities

• Pulsars – Pulsar production arrived– Large RAM mezzanine production done – Small RAM mezzanine prototype under test– ON SCHEDULE

• TF– First firmware written

– Standalone tests starting– ON SCHEDULE

• HB– Firmware writing just started

– BEHIND SCHEDULE

– More man power (firmware engineer joined)


SVT

• AM++ & AMSRW: A. Annovi, A. Bardi, M. Bitossi, M.Dell’Orso, P. Giannetti, P. Giovacchini, M. Piendibene, F. Spinella, L. Sartori, R. Tripiccione, S. Torre, I. Pedron, P. Catastini, S. Belforte, L. Ristori

• HB++: I. Furic, T. Maruyama, S. Chappa, M. Aoki, E. Berry

• TF++ & SRAM mezzanines: J. Adelman, U. Yang, F. Tang, M. Shochet, H. Sanders

• Software: R. Carosi, S. Torre, B. Simoni, A. Annovi, P. Giovacchini, M. Rescigno, B. Di Ruzza, A. Cerri, J. Bellinger, G. Volpi, F. Sforza

• Great support from Pulsar, DAQ, review committee, Silicon and operations people & Dervin’s group

• INFN & Fermilab support

SVT upgrade people


SVT

TRIGGER: Tracking @ Level 2 & Level 1

1. Atlas/CDF USA-Pisa group working for physics case forFTK (Gruppo V –Pisa project 2000-02) @ Level 2http://hep.uchicago.edu/cdf/shochet/ftk_12_05/meeting.htmlProposal discussed during 2006 – If approved USA funds autumn 2006a) small prototype (using CDF AMchip) as soon as possible; b) upgrade for high luminosity; c) upgrade for SLHCItaly will be required to partecipate

2. Try to use same AMchip for simplified tracking @ Level 1

http://hep.uchicago.edu/cdf/shochet/ftk_12_05/meeting.html










SVT

Save ~10s @ 100E30

TF: RMS=18

TF++: RMS=10.7

Summer 2005 installation


SVT

New AM chip

• Standard Cell UMC 0.18 m 10x10 mm die - 5000 patterns6 input hit busestested up to 40 MHz, simulated up to 50 MHz

• 116 prototype chips on September 2004MPW run – low yield 37%

• 3000 production chips on April 2005good yield 70%private masks better process parameter tuning for dense memory


SVT

AM chip & system

• Undoable with standard electronics (90’s)

Full custom VLSI chip - 0.7m (INFN-Pisa)

• 128 patterns, 6x12bit words each• Working up to 40 MHz

• Limit to 2-D• 6 layers: 5 SVX + 1 COT • ~250 micron bins 32k roads / 300 sector• >95% coverage for Pt > 2 GeV


SVT

Upgrade is on schedule

•AM++ and RW with 32k patterns have been already used in test runs for data taking •Plan to install AM++ with 32k pattern in July•Studies of 128k patterns coverage and efficiency are underway•Plan to install TF++ as soon as it will be ready (August) then move to 128k•HB++ expected to be installed during fall with 512k pattern memory

Real data AM++

AMS/RW

Documents

L’upgrade del Silicon Vertex Trigger (SVT) di CDF