Main DCM

Design and implementation of lossless high speed data compression and Decompression using VHDL

CHAPTER 1

INTRODUCTION

BVC Institute of Technology & Science Page 1


The objective of the project is to design a lossless data compression system which

operates in high-speed to achieve high compression rate. By using architecture of

compressor, the data compression rates are significantly improved. Also inherent

scalability of architecture is possible.

To achieve higher compression rates using compression/decompression

architecture with least increase in latency .At present there is an insatiable demand

for ever-greater bandwidth in communication networks and forever-greater storage

capacity in computer system. This led to the need for an efficient compression

technique.

The main parts of the system are the data compressor and the control blocks

providing control signals for the Data compressor, allowing appropriate control of

the routing of data into and from the system. The Data compressor can process four bytes

of data into and from a block of data every clock cycle. This is to ensure that adequate

data is present for compressor to process rather than being in an idle state.

The compression is the process that is required either to reduce the volume

of information to be transmitted – text, fax and images or reduce the bandwidth that is

required for its transmission – speech, audio and video. The compression technique is first

applied to the source information prior to its transmission.

The decompression system has the following components– Array and Processing

Unit. Array has the same function as that of the array unit which is used in the

Compressor. It is also of the same length. Processing unit checks the incoming match hit

data and if it is 0, it indicates that the data is not present in the Array, so it stores the data

in the Array and if the match hit data is 1, it indicates the data is present in the Array, then

it instructs to find the data from the Array with the help of the address input and sends as

output to the data out.



1.1 BLOCK DIAGRAM OF 32 Bit COMPRESSION SYSTEM:

ARRAY :

Array is of length of 64X32 bit locations. This is used to store the unmatched

incoming data and when a new data comes, the incoming data is compared with

all the Data stored in this array. If a match occurs, the corresponding match location

is sent as output else the incoming data is stored in next free location of the array

& is sent as Output.

CAM COMPARATOR:

The cam comparator is used to send the match location Of the CAM dictionary

as output if a match has occurred. This is done by getting match Information as input from

the comparator.



The number of bits in a CAM word is usually large, with existing

implementations ranging from 36 to 144 bits. A typical CAM employs a table size

ranging between a few hundred entries to 32K entries, corresponding to an address space

ranging from 7 bits to 15 bits. The length of the CAM varies with three possible values of

16, 32 or 64 tuples trading complexity for compression.

FIG. CONCEPTUAL VIEW OF CAM

The no. of tuples present in the dictionary has an important effect on

compression. In principle, the larger the dictionary the higher the probability of

having a match and improving compression. On the other hand, a bigger dictionary uses

more bits to code its locations degrading compression when processing small data

blocks that only use a fraction of the dictionary length available. The width of the

CAM is fixed with 4bytes/word.



Content Addressable Memory (CAM) compares input search data against a table of

stored data, and returns the address of the matching data. CAMs have a single

clock cycle throughput making them faster than other hardware and software-based

search systems.

The input to the system is the search word that is broadcast onto the searchlines to

the table of stored data. Each stored word has a matchline that indicates whether

the search word and stored word are identical (the match case) or are different (a mismatch

case, or miss). The matchlines are fed to an encoder that generates a binary match

location corresponding to the matchline that is in the match state. An encoder is used in

systems where only a single match is expected. The overall function of a CAM is to take a

search word and return the matching memory location.

COMPARATOR:

Suppose the output of the comparator goes high for any input, the match is found

and the corresponding address is retrieved and sent as output along with one bit to

indicate that match is found. At the same time, suppose no match occurs, or no matched

data is found, the incoming data is stored in the array and it is sent as the output. These are

the functions of the three components of the Compressor.



1.2 BLOCK DIAGRAM OF 32 BIT DECOMPRESSION SYSTEM:

Array is of length of 64X32bit locations. This is used to store the

unmatched in coming data and when the next new data comes, that data is compared with

all the data stored in this array. If the incoming data matches with any of the data stored in

array, the Comparator generates a match signal and sends it to Cam Comparator.



The last component is the Cam comparator and is used to send the

incoming data and all the stored data in array one by one to the comparator.

Suppose output of comparator goes high for any input, then the match is found

and the corresponding address (match location) is retrieved and sent as output along

with one bit to indicate the match is found. At the same time, suppose no match is found,

then the incoming data stored in the array is sent as output. These are the functions of

the three components of the XMatchPro based compressor.

The decompressor has the following components – Array and Processing






output to the data out.

The Control has the input bit called C/ D i.e., Compression / Decompression

indicates whether compression or decompression has to be done. If it has the value 0 then

compressor is stared when the value is 1 decompression is done.



CHAPTER 2

LOSSLESS COMPRESSION SYSTEM

2.1 INTRODUCTION:



With the increase in silicon densities, it is becoming feasible for

compression systems to be implemented in chip. A system with distributed memory

architecture is based on having data compression and decompression engines

working independently on different data at the same time. This data is stored in

memory distributed to each processor. The objective of the project is to design a lossless

data compression system which operates in high-speed to achieve high compression rate.

By using the architecture of compressors, the data compression rates are significantly

improved. Also inherent scalability of architecture is possible.

The main parts of the system are the Xmatchpro based data compressors

and the control blocks providing control signals for the Data compressors, allowing

appropriate control of the routing of data into and from the system. Each Data compressor

can process four bytes of data into and from a block of data in every clock cycle. The

data entering the system needs to be clocked in at a rate of 4 bytes in every clock

cycle. This is to ensure that adequate data is present for all compressors to process rather

than being in an idle state.

2.2 COMPRESSION TECHNIQUES:

At present there is an insatiable demand for ever-greater bandwidth in

communication networks and forever-greater storage capacity in computer system.

This led to the need for an efficient compression technique. The compression is the

process that is required either to reduce the volume of information to be

transmitted – text, fax and images or reduce the bandwidth that is required for its

transmission – speech, audio and video. The compression technique is first applied to the

source information prior to its transmission.



Compression algorithms can be classified in to two types, namely

Lossless Compression

Lossy Compression

LOSSLESS COMPRESSION:

In this type of lossless compression algorithm, the aim is to reduce the

amount of source information to be transmitted in such a way that, when the

compressed information is decompressed, there is no loss of information. Lossless

compression is said, therefore, to be reversible. i.e., Data is not altered or lost in the

process of compression or decompression. Decompression generates an exact replica of

the original object.

The Various lossless Compression Techniques are,

Pack bits encoding

CCITT Group 3 1D

CCITT Group 3 2D

Lempel-Ziv and Welch algorithm LZW

Huffman

Arithmetic

Applications of lossless compression are transferring data over a network as

a text file since, in such applications, it is normally imperative that no part of the

source information is lost during either the compression or decompression operations

and file storage systems (tapes, hard disk drives, solid state storage, file servers)

LOSSY COMPRESSION:



The aim of the Lossy compression algorithms is normally not to reproduce

an exact copy of the source information after decompression but rather a version of it that

is perceived by the recipient as a true copy.

The Lossy compression algorithms are:

JPEG (Joint Photographic Expert Group)

MPEG (Moving Picture Experts Group)

CCITT H.261 (Px64)

Example applications of lossy compression are the transfer of digitized

images and audio and video streams. In such cases, the sensitivity of the human eye or ear

is such that any fine details that may be missing from the original source signal

after decompression are not detectable.

TEXT COMPRESSION:

There are three different types of text – unformatted, formatted and

hypertext and all are represented as strings of characters selected from a defined set. The

compression algorithm associated with text must be lossless since the loss of just a single

character could modify the meaning of a complete string. The text compression is

restricted to the use of entropy encoding and in practice, statistical encoding methods.

There are two types of statistical encoding methods which are used with

text: one which uses single character as the basis of deriving an optimum set of code

words and the other which uses variable length strings of characters. Two examples of the

former are the Huffman and Arithmetic coding algorithms and an example of the latter is

Lempel-Ziv (LZ) algorithm.

The majority of work on hardware approaches to lossless data compression has

used an adapted form of the dictionary-based Lempel-Ziv algorithm, in which a large



number of simple processing elements are arranged in a systolic array [1], [2], [3], [4].

PREVIOUS WORK ON LOSSLESS COMPRESSION METHODS:

A second Lempel-Ziv method used a content addressable memory (CAM)

capable of performing a complete dictionary search in one clock cycle [5], [6], [7]. The

search for the most common string in the dictionary (normally, the most computationally

expensive operation in the Lempel-Ziv algorithm) can be performed by the CAM in a

single clock cycle, while the systolic array method uses a much slower deep

pipelining technique to implement its dictionary search. However, compared to the

CAM solution, the systolic array method has advantages in terms of reduced

hardware costs and lower power consumption, which may be more important criteria in

some situations than having faster dictionary searching.

Thet hardware main memory data compression is both feasible and

worthwhile.The authors also describe the design and implementation of a novel

compression method, the XMatchPro algorithm. The authors exhibit the substantial impact

such memory compression has on overall system performance. The adaptation of

compression code for parallel implementation is investigated by Jiang and Jones [9].

They recommended the use of a processing array arranged in a tree-like structure.

Although compression can be implemented in this manner, the

implementation of the decompressor’s search and decode stages in hardware would

greatly increase the complexity of the design and it is likely that these aspects

would need to be implemented sequentially. An FPGA implementation of a binary

arithmetic coding architecture that is able to process 8 bits per clock cycle

compared to the standard 1 bit per cycle is described by Stefo et al [10].

Although little research has been performed on architectures involving several

independent compression units working in a concurrent cooperative manner, IBM has



introduced the MXT chip [11], which has four independent compression engines

operating on a shared memory area. The four Lempel-Ziv compression engines are

used to provide data throughput sufficient for memory compression in computer

servers.

STATISTICAL METHODS:

Statistical Modeling of lossless data compression system is based on

assigning values to events depending on their probability. The higher the value, the

higher the probability. The accuracy with which this frequency distribution reflects

reality determines the efficiency of the model.

In Markov modeling, predictions are done based on the symbols that precede the

current symbol. Statistical Methods in hardware are restricted to simple higher order

modeling using binary alphabets that limits speed, or simple multi symbol alphabets

using zeroth-order models that limits compression. Binary alphabets limit speed

because only a few bits (typically a single bit) are processed in each cycle while

zeroth order models limit compression because they can only provide an inexact

representation of the statistical properties of the data source.

DICTIONARY METHODS:

Dictionary Methods try to replace a symbol or group of symbols by a dictionary

location code. Some dictionary-based techniques use simple uniform binary codes

to process the information supplied. Both software and hardware based dictionary

models achieve good throughput and competitive compression.

The UNIX utility ‘compress’ uses Lempel-Ziv-2 (LZ2) algorithm and the



data compression Lempel-Ziv (DCLZ) family of compressors initially invented by

Hewlett-Packard[16] and currently being developed by AHA[17],[18] also use LZ2

derivatives. Bunton and Borriello present another LZ2 implementation in [19] that

improves on the Data Compression Lempel-Ziv method. It uses a tag attached to each

dictionary location to identify which node should be eliminated once the dictionary

becomes full.

2.3 FUNCTIONS OF LOSSLESS COMPRESSION:

BASICS OF COMMUNICATION:

A sender can compress data before transmitting it and a receiver can decompress

the data after receiving it, thus effectively increasing the data rate of the communication

channel. Lossless data compression is the process of encoding a body of data into

a smaller body of data that can at a later time be uniquely decoded back to the original

data.

Sender

Encoder Decoder Receiver

FIG. SIMPLIFIED BLOCK DIAGRAM OF DATA COMMUNICATION

Lossless compression removes redundant information from the data

while they are being transmitted or before they are stored in memory, and lossless

decompression reintroduces the redundant information to recover fully the original

data. In the same way, the data is compressed before it is stored and decompressed

when it is retrieved, thus increasing the effective capacity of the storage device.

PROPOSED METHOD:

The Algorithm that can be implemented for High Speed Data Compression. It



gives the basic idea about how the Data Compression is carried out using the Lempel-

Ziv Algorithm and how it could be altered for Parallelism of the algorithm. The author

describes the Lempel-Ziv algorithm as a very efficient universal data compression

technique, based upon an incremental parsing technique, which maintains codebooks

of parsed phrases at the transmitter and at the receiver.

An important feature of the algorithm is that it is not necessary to determine a

model of the source, which generates the data. According to the author, in an attempt to

increase the speed of the algorithm of general purpose processors, the algorithm has been

parallelised to run on two processors.

BACKGROUND:

The architecture for a high-performance lossless data compressor that is

organized around a selectively shiftable Content Addressable Memory, which permits

full matching, the processor offers very high performance with good compression of

computer-based data. The author also gives details about the operation, architecture

and performance of the Data Compression Techniques. He also introduces the

XMatchPro lossless data compressor.

The parallelism in Data Compression Techniques and the authors explain

the Parallel Architecture for High Speed Data Compression. In this paper, the author

expresses Data Communication as an essential component of high-speed data

communication and storage.

The various methods of Data Compression and their Techniques and drawbacks

and propose a new methodology for a high speed Parallel Lossless Data

Compression. The authors describes the research and hardware implementation of a



high performance parallel multi compressor chip which could able to meet the intensive

data processing demands of highly concurrent system.

The authors also investigate the performance of alternative input and output

routing strategies for realistic data sets demonstrate that the design of parallel

compression devices involves important trade offs that affect compression performance,

latency and throughput. Compression ratio achieved by the proposed universal code

uniformly approaches the lower bounds on the compression ratios attainable by

block-to-variable codes and variable-to-block codes designed to match a completely

specified source.

ADVANTAGES

The use of lossless data compression can bring about a number of increasingly

important benefits to an electronic system. The term ‘lossless’ means that the

original data can be exactly recreated after a decompression operation, and should

not be confused with audio and video compression systems (such as JPEG and

MPEG) which are lossy and hence only recreate an approximation of the original

data.

The most obvious benefit of data compression is a reduction in the volume of data

which must be stored. This is important where the storage media itself is costly

(such as memory) or other parameters, such as power consumption, weight or

physical volume, are critical to product feasibility.

Using data compression reduces the total storage requirement, thus effecting a cost

saving. There are also two other positive effects that data compression brings. The

first of these is a reduction in the bandwidth required to transmit a given amount of



data –less data must be transmitted when in compressed form, and hence less

bandwidth is required. This can effect a cost saving in cabling operations, where a

lower bandwidth link will be sufficient to meet demand.

The second effect is that given a fixed bandwidth, the total time required to

transmit compressed data is less than for uncompressed data. This can lead to a

performance benefit, as the bandwidth of a link appears greater when transmitting

compressed data and hence more data can be transmitted in a given amount of

time.

DISADVANTAGES:

The design is a dictionary style compressor based around a dictionary implemented

in the form of a content addressable memory (CAM).

The length of the physical CAM varies with values ranging from 16 to 1024 tuples

(4-byte locations) trading complexity for compression.

Typically, the device complexity increases by a factor of 1.5 each time the

dictionary doubles.

APPLICATIONS:

Lossless data compression is a class of data compression algorithms that allows the

exact original data to be reconstructed from the compressed data. The term lossless

is in contrast to lossy data compression, which only allows an approximation of the

original data to be reconstructed, in exchange for better compression rates.

Lossless data compression is used in many applications. For example, it is used in

the ZIP file format and (e.g. lossless mid/side joint stereo preprocessing by the

MP3 encoder and other lossy audio encoders).


http://en.wikipedia.org/wiki/MP3

http://en.wikipedia.org/wiki/Joint_(audio_engineering)#M.2FS_stereo_coding

http://en.wikipedia.org/wiki/ZIP_(file_format)

http://en.wikipedia.org/wiki/Bit_rate#Bitrates_in_multimedia

http://en.wikipedia.org/wiki/Lossy_data_compression

http://en.wikipedia.org/wiki/Algorithm


Lossless compression is used in cases where it is important that the original and the

decompressed data be identical, or where deviations from the original data could

be deleterious. Typical examples are executable programs, text documents and

source code. Some image file formats, like PNG or GIF, use only lossless

compression, while others like TIFF and MNG may use either lossless or lossy

methods.

Lossless audio formats are most often used for archiving or production purposes,

with smaller lossy audio files being typically used on portable players and in other

cases where storage space is limited and/or exact replication of the audio is

unnecessary.

For storage applications ex : video recording

Security applications ex : military applications

Computer systems.

High performance storage devices & Remote sensing applications.


http://en.wikipedia.org/wiki/Audio_compression_(data)#Lossy_audio_compression

http://en.wikipedia.org/wiki/Audio_compression_(data)#Lossless_audio_compression

http://en.wikipedia.org/wiki/Multiple-image_Network_Graphics

http://en.wikipedia.org/wiki/TIFF

http://en.wikipedia.org/wiki/Graphics_Interchange_Format

http://en.wikipedia.org/wiki/Portable_Network_Graphics


CHAPTER 3

LOSSLESS DECOMPRESSION

SYSTEM



BLOCK DIAGRAM OF DECOMPRESSOR:

The block diagram gives the details about the components of a single 32-

bit compressor / decompressor. There are three components namely COMPRESSOR,

DECOMPRESSOR and CONTROL. The compressor has the following components -

COMPARATOR, ARRAY, and CAMCOMPARATOR. The comparator is used to

compare two 32-bit data and to set or reset the output bit as 1 for equal and 0 for unequal

.

FIG.BLOCK DIAGRAM OF 32 BIT DECOMPRESSOR



Array is of length of 64X32bit locations. This is used to store the unmatched in

coming data and when the next new data comes, that data is compared with all the data

stored in this array. If the incoming data matches with any of the data stored in array, the

Comparator generates a match signal and sends it to Cam Comparator. The last

component is the Cam comparator and is used to send the incoming data and all

the stored data in array one by one to the comparator. Suppose output of

comparator goes high for any input, then the match is found and the corresponding

address (match location) is retrieved and sent as output along with one bit to indicate the

match is found. At the same time, suppose no match is found, then the incoming data

stored in the array is sent as output. These are the functions of the three components

of the XMatchPro based compressor.

The decompressor has the following components – Array and Processing






output to the data out

The Control has the input bit called C/D i.e., Compression / Decompression

indicates whether compression or decompression has to be done. If it has the value 0 then

compressor is stared when the value is 1 decompression is done.



CHAPTER 4

XMATCHPRO ALGORITHM



4.1. DESIGN METHODOLOGY:

The XMatchPro algorithm is efficient at compressing the small blocks of

data necessary with cache and page based memory hierarchies found in computer systems.

It is suitable for high performance hardware implementation. The XMatchPro

hardware achieves a throughput 2-3 times greater than other high-performance

hardware implementation.

The core component of the system is the XMatchPro based Compression /

Decompression system. The XMatchPro is a high-speed lossless dictionary based

data compressor. The XMatchPro algorithm works by taking an incoming four-byte

tuple of data and attempting to match fully or partially match the tuple with the past data.

FUNCTIONAL DESCRIPTION:

The XMatchPro algorithm maintains a dictionary of data previously

seen and attempts to match the current data element with an entry in the

dictionary, replacing it with a shorter code referencing the match location. Data elements

that do not produce a match are transmitted in full (literally) prefixed by a single bit.

Each data element is exactly 4 bytes in width and is referred to as tuple. This feature

gives a guaranteed input data rate during compression and thus also guaranteed data rates

during decompression, of the data mix.

Also the 4-byte tuple size gives an inherently higher throughput

than other algorithms, which tend to operate on a byte stream. The dictionary is

maintained using move to front strategy, where by the current tuple is placed at

the front of the dictionary and the other tuples move down by one location as

necessary to make space.



The move to front strategy aims to exploit locality in the input data. If the

dictionary becomes full, the tuple occupying the last location is simply discarded. A

full match occurs when all characters in the incoming tuple fully match a

dictionary entry. A partial match occurs when at least any two of the characters in

the incoming tuple match exactly with a dictionary entry, with the characters that

do not match being transmitted literally.

The use of partial matching improves the compression ratio when compared with

allowing only 4 byte matches, but still maintains high throughput. If neither a full

nor partial match occurs, then a miss is registered and a single miss bit of ‘1’ is transmitted

followed by the tuple itself in literal form. The only exception to this is the first tuple in

any compression operation, which will always generate a miss as the dictionary begins in

an empty state. In this case no miss bit is required to prefix the tuple.

At the beginning of each compression operation, the dictionary size is reset

to zero. The dictionary then grows by one location for each incoming tuple being placed at

the front of the dictionary and all other entries in the dictionary moving down by

one location. A full match does not grow the dictionary, but the move-to-front rule

is still applied.

The growth of the dictionary means that code words are short during the early

stages of compressing a block. Because the XMatchPro algorithm allows partial matches,

a decision must be made about which of the locations provides the best overall

match, with the selection criteria being the shortest possible number of output bits.



4.2. IMPLEMENTATION OF XMATCHPRO BASED COMPRESSOR:

The block diagram gives the details about the components of a single 32

bit Compressor.There are three components nameiy..,

COMPARATOR

ARRAY

CAMCOMPARATOR

.

The comparator is used to compare two 32-bit data and to set or reset the output bit

as 1 for equal and 0 for unequal. The CAM COMPARATOR searches the CAM

dictionary entries for a full match of the input data given. The reason for choosing a full

match is to get a prototype of the high throughout Xmatchpro compressor with reduced

complexity and high performance. If a full match occurs, the match-hit signal is

generated and the corresponding match location is given as output by the CAM

Comparator.. If no full match ccurs, the corresponding data that is given as input at the

given time is got as output.

USAGE OF XMATCHPRO ALGORITHM:

The Lossless Data Compression system designed uses the XMatchPro

Algorithm. The XMatchPro algorithm uses a fixed-width dictionary of previously

seen data and attempts to match the current data element with a match in the dictionary.

It works by taking a 4-byte word and trying to match or partially match this word with

past data. This past data is stored in a dictionary, which is constructed from a

content addressable memory. As each entry is 4 bytes wide, several types of matches are

possible. If all the bytes do not match with any data present in the dictionary they

are transmitted with an additional miss bit. If all the bytes are matched then the match

location and match type is coded and transmitted, this match is then moved to the

front of the dictionary.



The dictionary is maintained using a move to front strategy whereby a new tuple is

placed at the front of the dictionary while the rest move down one position. When

the dictionary becomes full the tuple placed in the last position is discarded leaving space

for a new one. The coding function for a match is required to code several fields as

follows:

A zero followed by:

1). Match location: It uses the binary code associated to the matching location.

2). Match type: Indicates which bytes of the incoming tuple have matched.

3). Characters that did not match transmitted in literal form.

With the increase in silicon densities, it is becoming feasible for

XMatchPros to be implemented on a single chip. A system with distributed

memory architecture is based on having data compression and decompression

engines working independently on different data at the same time.

This data is stored in memory distributed to each processor. There are

several approaches in which data can be routed to and from the compressors that will

affect the speed, compression and complexity of the system. Lossless compression

removes redundant information from the data while they are transmitted or before they are

stored in memory.

Lossless decompression reintroduces the redundant information to recover

fully the original data. There are two important contributions made by the current

compression & decompression work, namely, improved compression rates and the

inherent scalability.



Significant improvements in data compression rates have been achieved by

sharing the computational requirement between compressors without significantly

compromising the contribution made by individual compressors. The scalability

feature permits future bandwidth or storage demands to be met by adding additional

compression engines.

THE XMATCHPRO BASED COMPRESSION SYSTEM:

The XMatchPro algorithm uses a fixed width dictionary of previously seen

data and attempts to match the current data element with a match in the dictionary. It

works by taking a 4-byte word and trying to match this word with past data. This past data

is stored in a dictionary which is constructed from a content addressable memory. Initially

all the entries in the dictionary are empty & 4-bytes are added to the front of the

dictionary, while the rest move one position down if a full match has not occurred.

The larger the dictionary, the greater the number of address bits needed to identify

each memory location, reducing compression performance. Since the number of bits

needed to code each location address is a function of the dictionary size greater

compression is obtained in comparison to the case where a fixed size dictionary

uses fixed address codes for a partially full dictionary. In the XMatchPro system, the

data stream to be compressed enters the compression system, which is then partitioned

and routed to the compressors.



CHAPTER 5

SOFTWARE IMPLEMENTATION



5.1 OVERVIEW OF VLSI:

Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the

1970s when complex semiconductor and communication technologies were being

developed. The microprocessor is a VLSI device. The term is no longer as common as it

once was, as chips have increased in complexity into the hundreds of millions of

transistors.

The first semiconductor chips held one transistor each. Subsequent advances added

more and more transistors, and, as a consequence, more individual functions or systems

were integrated over time. The first integrated circuits held only a few devices, perhaps as

many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one

or more logic gates on a single device.

It is now known respectively as "small-scale integration" (SSI), improvements in

technique led to devices with hundreds of logic gates, known as large-scale integration

(LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far

past this mark and today's microprocessors have many millions of gates and hundreds of

millions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale

integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But

the huge number of gates and transistors available on common devices has rendered such

fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no

longer in widespread use. Even VLSI is now somewhat quaint, given the common

assumption that all microprocessors are VLSI or better.



As of early 2008, billion-transistor processors are commercially available, an

example of which is Intel's Montecito Itanium chip. This is expected to become more

commonplace as semiconductor fabrication moves from the current generation of 65 nm

processes to the next 45 nm generations (while experiencing new challenges such as

increased variation across process corners). Another notable example is NVIDIA’s 280

series GPU.

This microprocessor is unique in the fact that its 1.4 Billion transistor count,

capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's

transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the

earliest devices, use extensive design automation and automated logic synthesis to lay out

the transistors, enabling higher levels of complexity in the resulting logic functionality.

Certain high-performance logic blocks like the SRAM cell, however, are still

designed by hand to ensure the highest efficiency (sometimes by bending or breaking

established design rules to obtain the last bit of performance by trading stability).

VLSI stands for "Very Large Scale Integration". This is the field which involves

packing more and more logic devices into smaller and smaller areas.

1. Simply we say Integrated circuit is many transistors on one chip.

2. Design/manufacturing of extremely small, complex circuitry using modified

semiconductor material

3. Integrated circuit (IC) may contain millions of transistors, each a few mm in

size

4. Applications wide ranging: most electronic logic devices.



HISTORY OF SCALE INTEGRATION:

late 40s Transistor invented at Bell Labs

late 50s First IC (JK-FF by Jack Kilby at TI)

early 60s Small Scale Integration (SSI)

10s of transistors on a chip

late 60s Medium Scale Integration (MSI)

100s of transistors on a chip

early 70s Large Scale Integration (LSI)

1000s of transistor on a chip

early 80s VLSI 10,000s of transistors on a

chip (later 100,000s & now 1,000,000s)

Ultra LSI is sometimes used for 1,000,000s

ADVANTAGES OF ICS OVER DISCRETE COMPONENTS:

While we will concentrate on integrated circuits , the properties of integrated circuits-

what we can and cannot efficiently put in an integrated circuit-largely determine the

architecture of the entire system. Integrated circuits improve system characteristics in

several critical ways. ICs have three key advantages over digital circuits built from

discrete components:

Size: Integrated circuits are much smaller-both transistors and wires are shrunk to

micrometer sizes, compared to the millimeter or centimeter scales of discrete

components. Small size leads to advantages in speed and power consumption,

since smaller components have smaller parasitic resistances, capacitances, and

inductances.



Speed: Signals can be switched between logic 0 and logic 1 much quicker within a

chip than they can between chips. Communication within a chip can occur

hundreds of times faster than communication between chips on a printed circuit

board. The high speed of circuits on-chip is due to their small size-smaller

components and wires have smaller parasitic capacitances to slow down the signal.

Power consumption: Logic operations within a chip also take much less power.

Once again, lower power consumption is largely due to the small size of circuits on

the chip-smaller parasitic capacitances and resistances require less power to drive

them.

VLSI AND SYSTEMS:

These advantages of integrated circuits translate into advantages at the system level:

Smaller physical size. Smallness is often an advantage in itself-consider portable

televisions or handheld cellular telephones.

Lower power consumption. Replacing a handful of standard parts with a single

chip reduces total power consumption. Reducing power consumption has a ripple

effect on the rest of the system: a smaller, cheaper power supply can be used; since

less power consumption means less heat, a fan may no longer be necessary; a

simpler cabinet with less shielding for electromagnetic shielding may be feasible

Reduced cost. Reducing the number of components, the power supply

requirements, cabinet costs, and so on, will inevitably reduce system cost. The

ripple effect of integration is such that the cost of a system built from custom ICs

can be less, even though the individual ICs cost more than the standard parts they

replace.



Understanding why integrated circuit technology has such profound influence on

the design of digital systems requires understanding both the technology of IC

manufacturing and the economics of ICs and digital systems.

APPLICATIONS:

Electronic system in cars.

Digital electronics control VCRs

Transaction processing system, ATM

Personal computers and Workstations

Medical electronic systems.

APPLICATIONS OF VLSI:

Electronic systems now perform a wide variety of tasks in daily life. Electronic

systems in some cases have replaced mechanisms that operated mechanically,

hydraulically, or by other means; electronics are usually smaller, more flexible, and easier

to service. In other cases electronic systems have created totally new applications.

Electronic systems perform a variety of tasks, some of them visible, some more hidden:

Personal entertainment systems such as portable MP3 players and DVD players

perform sophisticated algorithms with remarkably little energy.

Electronic systems in cars operate stereo systems and displays; they also control

fuel injection systems, adjust suspensions to varying terrain, and perform the

control functions required for anti-lock braking (ABS) systems.



Digital electronics compress and decompress video, even at high-definition data

rates, on-the-fly in consumer electronics.

Low-cost terminals for Web browsing still require sophisticated electronics,

despite their dedicated function.

Personal computers and workstations provide word-processing, financial analysis,

and games. Computers include both central processing units (CPUs) and special-

purpose hardware for disk access, faster screen display, etc.

Medical electronic systems measure bodily functions and perform complex

processing algorithms to warn about unusual conditions. The availability of these

complex systems, far from overwhelming consumers, only creates demand for

even more complex systems.

The growing sophistication of applications continually pushes the design and

manufacturing of integrated circuits and electronic systems to new levels of complexity.

And perhaps the most amazing characteristic of this collection of systems is its variety-as

systems become more complex, we build not a few general-purpose computers but an ever

wider range of special-purpose systems. Our ability to do so is a testament to our growing

mastery of both integrated circuit manufacturing and design, but the increasing demands

of customers continue to test the limits of design and manufacturing.

5.2 OVERVIEW OF VHDL:

VHDL is an acronym for Very High Speed Integrated Circuits Hardware

description Language. The language can be used to model a digital system at many levels

of abstraction ranging from the algorithmic level to the gate level. The complexity of the

digital system being modeled could vary from that of a simple gate to a complete digital

electronic system.



The VHDL language can be regarded as an integrated amalgamation of sequential,

concurrent, net list and waveform generation languages and timing specifications.

HISTORY OF VHDL:

VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware

Description Language. It was developed in the 1980’s as spin-off of a high-speed

integrated circuit research project funded by the US department of defense. During the

VHSIC program, researchers were confronted with the daunting task of describing circuits

of enormous scale (for their time) and of managing very large circuit design problems that

involved multiple teams of engineers.

With only gate-level tools available, it soon became clear that more structured

design methods and tools would be needed. To meet this challenge, teams of engineers

from three companies - IBM, Texas Instruments and Intermetrics — were contracted by

the department of defense to complete the specification and implementation of a new

language based design description method.

The first publicly available version of VHDL, version 7.2 was released in 1985. In

1986, the IEEE was presented with a proposal to standardize the language, which it did in

1987 and academic representatives. The resulting standard, IEEE 1076—1987 is the

basis for virtually every simulation and synthesis product sold today. An enhanced and

updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool

vendors have been responding by adding these new language features to their products.

Although IEEE standard 1076 defines the complete VHDL language, there are

aspects of the language that make it difficult to write completely portable design

descriptions (description that can be simulated identically using different vendor’s tools).



The problem stems from the fact that VHDL supports many abstract data types, but

it does not address the simple problem of characterizing different signal strengths or

commonly used simulation conditions such as unknowns and high impedances. Soon after

IEEE 1076-1987 [3] was adopted, simulator companies began enhancing VHDL with new

non-standard types to allow their customers to accurately simulate complex electronics

circuits. This caused problems because design descriptions entered into one simulator

were often incompatible with another with other environments. VHDL was quickly

becoming a non-standard.

To get around the problem of non-standard data types, an IEEE committee adopted

another standard. This standard numbered 1164, defines a standard package (a VHDL

feature that allows commonly used declaration to be collected into an external library)

containing definition for a standard nine-value data type. This standard data type is called

standard logic, and the IELL 1164 package is often referred to as the standard logic

package.The IEEN 1076-1987 and IEEE 1164 standards together form the complete VHDL

standard in widest use today (IEEE 1076-1993 is slowly working its way into the VHDL

mainstream, but it does not add significant number of features for synthesis users).

In the search for a standard design and documentation tool for the Very High

Speed Integrated Circuits (VHSIC) program the United States Department of Defense

(DOD) in the summer of 1981 sponsored a workshop on HDLs at Woods Hole,

Massachusetts. The conclusion of the workshop was the need for a standard language, and

the features that might be required by such a standard in 1983.DoD established

requirements for a standard VHSIC hardware description language(VHDL), based on the

recommendation of the “Woods Hole” workshop. A contract for the development of the

VHDL language, its environment, and its software was awarded to IBM, Texas

instruments and Intermetrics. VHDL 2.0 was released only six months after the project

began.



The language was significantly improved hereafter and other shortcomings were

corrected leading to the release of VHDL 6.0. In 1985 this significant developments led to

the release of VHDL 6.0. In 1985 these significant development led to the release of

VHDL 7.2 language reference manual. This was later on developed as IEEE 1076/A

VHDL language reference manual.

Efforts for defining the new version of VHDL stated in 1990 by a ream of

volunteers working under the IEEE DASC (Design Automation Standards committee). In

October of 1992, a new VHDL’93 was completed and was released for review. After

minor modifications, this new version was approved by the VHDL balloting group

members and became the new VHDL language standard. The present VHDL standard is

formally referred as VHDL 1076-1993.

LEVELS OF ABSTRACTION (STYLES):

VHDL supports many possible styles of design description. These styles differ

primarily in how closely they relate to the underlying hardware. When we speak of the

different styles of VHDL, then, we are really talking about the differing levels of

abstraction possible using the language. To give an example, it is possible to describe a

counter circuit in a number of ways. At the lowest level of abstraction, you could use

VHDL's hierarchy features to connect a sequence of predefined logic gates and flip-flips

to form a counter circuit.

In a behavioral description, the concept of time may be expressed precisely, with

actual delays between related events, or may simply be an ordering of operations that are

expressed sequentially. When you are writing VHDL for input to synthesis tools, you may

use behavioral statements in VHDL to imply that there are registers in your circuit



It is unlikely, however, that your synthesis tool will be capable of creating

precisely the same behavior in actual circuitry as you have defined in the language. The

highest level of abstraction supported in VHDL is called the behavioral level of

abstraction. When creating a behavioral description of a circuit, you will describe your

circuit in terms of its operation over time. The concept of time is the critical distinction

between behavioral descriptions of circuits and lower-level description.

FIG. LEVELS OF ABSTRACTION

If you are familiar with event-driven software programming languages then writing

behavior level VHDL will not seem like anything new. Just like a programming language,

you will be writing one or more small programs that operate sequentially and

communicate with one another through their interfaces. The only difference between

behavior-level VHDL and a software programming language such as Visual Basic is the

underlying execution platform: in the case of Visual Basic, it is the Windows operating

system; in the case of VHDL, it is a simulator.



An alternate design method, in which a circuit design problem is segmented into

registers and combinational input logic, is what is often called the dataflow level of

abstraction. Dataflow is an intermediate level of abstraction that allows the drudgery of

combinational logic to be hidden while the more important parts of the circuit, the

registers, are more completely specified.

There are some drawbacks to using a purely dataflow method of design in VHDL.

First, there are no built-in registers in VHDL; the language was designed to be general-

purpose, and VHDL’s designers on its behavioral aspects placed the emphasis. If you are

going to write VHDL at the dataflow level of abstraction, then you must first create

behavioral descriptions of the register elements that you will be using in your design.

These elements must be provided in the form of components or in the form of

subprograms.

But for hardware designers, for whom it can be difficult to relate the sequential

descriptions and operation of behavioral VHDL with the hardware that is being described,

using the dataflow level of abstraction can make quite a lot of sense. Using dataflow, it

can be easier to relate a design description to actual hardware devices.

The dataflow and behavior levels of abstraction are used to describe circuits in

terms of their logical function. There is a third style of VHDL that is used to combine such

descripttions together into a larger, hierarchical circuit description.

Structural VHDL allows you to encapsulate one part of a design description as a re-

usable component. Structural VHDL can be thought of as being analogous to a textual

schematic, or as a textual block diagram for higher-level design.



NEED FOR VHDL:

The complex and laborious manual procedures for the design of the hardware

have paved the way for the development of languages for high –level description of the

digital system. This high-level description can serve as documentation for the part as well

as an entry point into the design process. The high level description can be processed

through various boards, or gate array using the synthesis tools of Hardware Description

language us such a language. VHDL was designed as a solution to provide an integrated

design and documentation to communicate design data between various levels of

abstractions.

ADVANTAGES OF VHDL:

VHDL allows quick description and synthesis of circuits of 5, 10, 20 thousand

gates. It also provides the following capabilities. The following are the major advantages

of VHDL over other hardware description languages:

Power and flexibility: VHDL has powerful language constructs which allows

code description of complex control logic.

Device independent design: VHDL creates design that fits into many device

architecture and it also permits multiple styles of design description.

Portability: VHDL’s portability permits the design description to be used on

different simulators and synthesis tools. Thus VHDL design descriptions can be

used in multiple projects.

ASIC migration: The efficiency of VHDL allows design to be synthesized on a

CPLD or an FPGA. Sometimes the code can be used with the ASIC.



Quick time to market and low cost:VHDL and programmable logic pair together

facilitate speedy design process. VHDL permits designs to be described quickly.

Programmable logic eliminates expenses and facilitates quick design iterations

The language can be used as a communication medium between different

Computer Aided Design (CAD) and Computer Aided Engineering (CAE) tools.

The language supports hierarchy, i.e., a digital system can be modeled as a set of

interconnected components; each component, in turn, can be modeled as a set of

interconnected subcomponents.

The language supports flexible design methodologies: Top-Down, Bottom- Up, or

Mixed.

The language is technology independent and hence the same behavior model can

be synthesized into different vendor libraries.

Various digital modeling techniques such as finite-state machine descriptions,

algorithmic descriptions and Boolean equations can be modeled using the

language.

It supports both synchronous and asynchronous timing models.

It is an IEEE and ANSI standard, and therefore, models described using these

languages are portable.

There are no limitations that are imposed by the language on the size of the design.

The language has elements that make large-scale design modeling easier, for e.g.

Components, functions, procedures and packages.



Test benches can be written using the same language to test other VHDL models.

Nominal propagation delays, min-max delays, setup and holding timing,

timingconstraints, and spike detection can all be described very naturally in this

language.

Behavioral models that conform to a certain synthesis description style are capable

of being synthesized to gate-level description.

The capability of defining new data types provides the power to describe and

simulate a new design technique at a very high level of abstraction without any

concern about implementation details.

DESIGN METHODOLOGY USING VHDL:

There are three design methodologies namely: bottom-up, top-down and flat

The bottom-up approach involves the defining and designing the individual

components, then bringing the individual components together to form the overall

design.

In a flat design the functional components are defined at the same level as the

interconnection of those functional components.

A top-down design process involves a divide-and-conquer approach to implement

the design a large system. Top-down design is referred to as recursive partitioning

of a system into its sub-components until all sub-components become manageable

design parts. Design of a component is manageable if the component is available

as part of a library, it can be implemented by modifying an already available part,

or it can be described for a synthesis program or an automatic hardware generator.



ELEMENTS OF VHDL:

Constructs of the VHDL language are designed for describing hardware

components, packaging parts and utilities use of libraries and for specifying design

libraries and parameters. In its simplest form, the description of a component in VHDL

consists of an interface specification and an architectural specification. The interface

description begins with Entity keyword and contains the input-output ports of the

component. An architectural specification begins with the Architectural keyword, which

describes the functionality of a component.

This functionality depends on input-output signals and other parameters that are

specified in the interface description. Several architectural specifications with different

identifiers can exist for one component with a given interface description. VHDL allows

architecture to be configured for a specific technology environment.

In a hardware design environment it becomes necessary to group components or

utilities used for description of components. Components and such utilities can be

grouped by use of packages. A package declaration contains components and utilities to

be come visible by Entities and Architectures. VHDL allows the use of Libraries and

binding of sub-components of a design to elements of various libraries. Constructs for

such applications include a library statement and configurations.

VHDL language features:

The various building blocks and constructs in VHDL which have been used are:

Entity:

Every VHDL design description consists of at least one entity. In VHDL, an entity

declaration describes the circuit as it appears from the "outside", from the perspective of

its input and output interfaces.



An entity declaration in VHDL provides the complete interface for a circuit. Using

the information provided in an entity declaration (the port names and the data type and

direction of each port), you have all the information you need to connect that portion of a

circuit into other, higher-level circuits.

The entity declaration includes a name, compare, and a port statement defining all the

inputs and outputs of the entity. Each of the ports is given a direction (either in, out or

inout).

FORMAL DEFINITION:

It is the hardware abstraction of a digital system. Entity declaration describes the

external view of the entity to the outside world.

SIMPLIFIED SYNTAX:

Entity entity-name is

Port (port-list);

[generic(generic-list);]

end entity-name;

DESCRIPTION:

All designs are expressed in terms of entities. Entity is the most basic building

block in a design. The uppermost level of the design is the top-level entity. If the design

is hierarchical, then the top-level description will have lower-level descriptions contained

in it. These lower-level descriptions will be lower-level entities contained in the top-level

entity description.

ARCHITECTURE:



Every entity in a VHDL design description must be bound with a corresponding

architecture. The architecture describes the actual function of the entity to which it is

bound. Using the schematic as a metaphor, you can think of the architecture as being

roughly analogous to a lower-level schematic pointed to by the higher-level functional

block symbol. The second part of a minimal VHDL source file is the architecture

declaration. Every entity declaration you write must be accompanied by at least one

corresponding architecture.

The architecture declaration begins with a unique name, followed by the name of the

entity to which the architecture is bound. Within the architecture declaration is found the

actual functional description of our comparator. There are many ways to describe

combinational logic functions in VHDL.

FORMAL DEFINITION:

A body associated with an entity declaration to describe the internal organization or

operation of a design entity. An architecture body is used to describe the behavior, data

flow or structure of a design entity

SIMPLIFIED SYNTAX:

Architecture architecture-name of entity-name is

Architecture-declarations

Begin

Concurrent-statements

End [architecture] [architecture-name];

DESCRIPTION



Architecture assigned to an entity describes internal relationship between input and

output ports of the entity. It contains of two parts: declarations and concurrent statements.

First (declarative) part of architecture may contain declarations of types, signals,

constants, subprograms (functions and procedures), components and groups.

Concurrent statements in the architecture body define the relationship between

inputs and outputs. This relationship can be specified using different types of statements:

Concurrent signal assignment, process statement, component instantiation, and concurrent

procedure call, generate statement, concurrent assertion statement, and block statement. It

can be writing in different styles: structural, dataflow, behavioral (functional) or mixed.

The description of a structural body is based on component instantiation and

generates statements.It allows creating hierarchical projects, from simple gates to very

complex components, describing entire subsystems. The Connections among components

are realized through ports.

The Dataflow description is built with concurrent signal assignment statements.

Each of the statements can be activated when any of its input signals changes its value.The

architecture body describes only the expected functionality (behavior) of the circuit,

without any direct indication as to the hard ware implementation. Such description

consists only of one or more processes, each of which contains sequential statements.

The Architecture body may contain statements that define both behavior and

structure of the circuit at the same time. Such architecture description is called mixed.

COMPONENT DECLARATION:



FORMAL DEFINITION:

A component declaration declares a virtual design entity interface that may be used in

component instantiation statement.

SIMPLIFIED SYNTAX:

Component component-name

[generic(generic-list)];

port(port-list);

end component [component-name];

COMPONENT INSTANTIATION:

FORMAL DEFINITION:

A component instantiation statement defines a subcomponent of the design entity in

which it appears, associate signals or values with the ports of that subcomponent, and

associates values with generics of that subcomponent.

SIMPLIFIED SYNTAX:

Label: [component] component-name

Generic map (generic-association-list);

Port map (port-association-list);

CONFIGURATION DECLARATION:



FORMAL DEFINITION:

A configuration is a construct that defines how component instances in a given

block are bound to design entities in order to describe how design entities are put together

to form a complete design.

SIMPLIFIED SYNTAX:

Configuration configuration-name of entity-name is

Configuration declarations.

For architecture-name

For instance-label: component-name

Use entity library-name. Entity-name (arch-name);

End for;

end for;

end configuration-name;

PACKAGE:

FORMAL DEFINITION:

A package declaration defines the interface to a package.

SIMPLIFIED SYNTAX:

Package package-name is

Package –declarations

End [package] package-name;

PACKAGE BODY:



FORMAL DEFINITION:

A package body defines the bodies of subprograms and the values of deferred

constants declared in the interface to the package.

SIMPLIFIED SYNTAX:

Package body package-name is

Package-body-declarations

Subprogram bodies declarations

End [package body] package-name;

ATTRIBUTES:

Attributes are of two types: user defined and predefined.

USER DEFINED:

FORMAL DEFINITION:

A value, function, type, range, signals, or constant that may be associated with one

or more named entities in a description.

SIMPLIFIED SYNTAX:

Attribute attribute-name: type; --attribute declaration

Attribute attribute-name of item: item-class is expression --attribute specification

DESCRIPTION:

Attributes allow retrieving information about named entities: types, objects,

subprograms etc. Users can define mew attributes and then assign them to named entities

by specifying the entity and the attribute values for it.

PREDEFINED:

FORMAL DEFINITION:



A value, function, type, range, signals, or constant that may be associated with one

or more named entities in a description.

SIMPLIFIED SYNTAX: object’s attribute-name

PROCESS STATEMENT:

FORMAL DEFINITION:

A process statement defines an independent sequential process representing the

behavior of some portion of the design.

SIMPLIFIED SYNTAX:

[process-label:] process [(sensitivity-list)];

Process-declarations

begin

Sequential-statements

end process [process-label];

FUNCTION:

FORMAL DEFINITION:

A function call is a subprogram of the form of an expression that returns a value.

SIMPLIFIED SYNTAX:

Function function name(parameters) return type -- function declaration

Function function-name(parameters) return type is --- function definition.

Begin

Sequential statements



End [function] function-name;

PORT:

FORMAL DEFINITION:

A channel for dynamic communication between a block and its environment.

SIMPLIFIED SYNTAX:

Port (po-declaration, port-declaration,-----);

----port declarations:

Port-signal-name: in port-signal-type: =initial-value

Port-signal-name: out port-signal-type: =initial-value

Port-signal-name: in out port-signal-type: =initial-value

Port-signal-name: buffer port-signal-type: =initial-value

Port-signal-name: linkage port-signal-type: =initial-value

SENSITIVITY LIST :

FORMAL DEFINITION :

A list of signals a process is sensitive to.

SIMPLIFIED SYNTAX:

(Signal-name, signal-name, ---)

Formal Definition

STANDARD LOGIC:



FORMAL DEFINITION:

A nine-value resolved logic type.

Std-logic is not a part of the VHDL standard. It is defined in IEEE Std 1164.

SIMPLIFIED SYNTAX:

Type std-ulogic is ( ‘U’, -- Uninitialized

‘X’, -- Forcing Unknown

‘0’, -- Forcing 0

‘1’, -- Forcing 1

‘Z’ -- High Impedance

‘W’--Weak Unknown

‘L’--Weak 1

‘-‘--Don’t Care);

Type std-ulogic-vector is array (natural range <>) of std-ulogic

Function resolved (s: std-ulogic-vector) return std-ulogic;

Subtype std-logic is resolved std-ulogic;

DATA TYPES:

There are many data types available in VHDL. VHDL allows data to be

represented in terms of high-level data types. These data types can represent individual

wires in a circuit, or can represent collections of wires using a concept called an array.

The preceding description of the comparator circuit used the data types bit and bit

vector for its inputs and outputs. The bit data type (bit vector is simply an array of bits)



values of '1' and '0' are the only possible values for the bit data type. Every data type in

VHDL has a defined set of values, and a defined set of valid operations.

Type checking is strict, so it is not possible, for example, to directly assign the

value of an integer data type to a bit vector data type. (There are ways to get around this

restriction, using what are called type conversion functions.) VHDL is rich language with

many different data types.

The most common data types are listed below:

Bit: a 1-bit value representing a wire. (Note: IEEE standard 1164 defines a 9-

valued replacement for bit called std_logic.)

Bit vector: an array of bits. (Replaced by std_logic_vector in IEEE 1164.)

Boolean: a True/False value.

Integer: a signed integer value, typically implemented as a 32-bit data type.

Real: a floating-point value.

Enumerated: used to create custom data types.

Record: used to append multiple data types as a collection.

Array: can be used to create single or multiple dimension arrays.

Access: similar to pointers in C or Pascal.

file: used to read and write disk files. Useful for simulation.

Physical: used to represent values such as time, voltage, etc. using symbolic units

of measure (such as 'ns' or 'ma').

PACKAGES AND PACKAGE BODIES:



A VHDL package declaration is identified by the package keyword, and is used

to collect commonly used declarations for use globally among different design units. You

can think of a package as being a common storage area, one used to store such things as

type declarations, constants, and global subprograms.

A package can consist of two basic parts: a package declaration and an optional

package body. Package declarations can contain the following types of statements:

Type and subtype declarations

Constant declarations

Global signal declarations

Function and procedure declarations

Attribute specifications

File declarations

Component declarations

Alias declarations

Disconnect specifications

Items appearing within a package declaration can be made visible to other

design units through the use of a use statement. If the package contains declarations of

subprograms (functions or procedures) or defines one or more deferred constants

(constants whose value is not given), then a package body is required in addition to the

package declaration. A package body must have the same name as its corresponding

package declaration, but can be located anywhere in the design.

The relationship between a package and package body is somewhat akin to the

relationship between an entity and its corresponding architecture. While the package



declaration provides the information needed to use the items defined within it (the

parameter list for a global procedure, or the name of a defined type or subtype), the actual

behavior of such things as procedures and functions must be specified within package

bodies.

5.3 SOFTWARE:

XLINX software is used by the VHDL designers for performing Synthesis

operation. Any simulated code can be synthesized and configured on FPGA. Synthesis is

the transformation of VHDL code into gate level net list. It is an integral part of current

design flows.

ALGORITHM:

Start the ISE Software by clicking the XILINX ISE icon.

Create a New Project and find the following properties displayed.

Create a VHDL Source formatting all inputs, outputs and buffers if required. which

provides a window to write the VHDL code, to be synthesized.



Check Syntax after finally editing the VHDL source for any errors.

Design Simulation is done after compilation.



Synthesizing starts by creating Timing Constrain Implement Design and Verify

Constraints

Assigning Pin Location Constraints according to the requirement on FPGA board.

Download Design to the Spartan FPGA Board by clicking ‘Configure device’, until a .bit

file is generated showing a message “Program Succeeded”.

DATA COMPRESSION SCHEMATIC:



RTL SCHEMATIC OF DATA COMPRESSION:

DATA DECOMPRESSION SCHEMATIC:



RTL SCHEMATIC OF DATA DECOMPRESSION:



CHAPTER 6

RESULTS & CONCLUSION

DATA COMPRESSION WAVEFORM:



DATA DECOMPRESSION WAVEFORM:



6.1 CONCLUSION:

Since the Compression/Decompression system uses XMatchPro algorithm,

speed of compression throughput is high. The Improved Compression ratio is achieved in



Compression architecture with least increase in latency. The High speed throughput

is achieved. The architecture provides inherent scalability in future .

The total time required to transmit compressed data is less than that of

transmitting uncompressed data. This can lead to a performance benefit, as the bandwidth

of a link appears greater when transmitting compressed data and hence more data can be

transmitted in a given amount of time. It can be applied in Computer systems.

6.2 BIBILOGRAGY:

1. S. Henriques and N. Ranganathan, “High Speed VLSI Design for Lempel-Ziv

Based Data Compression,” IEEE Trans. Circuits and Systems, vol. 40, no. 2,

pp. 90-106, Feb. 1993.

2. .B. Jung and W.P. Burleson, “A VLSI Systolic Array Architecture for

Lempel-Ziv Based Data Compression,” Proc. IEEE Int’l Symp. Circuits and

Systems, pp. 65-68, June 1994.

3. J.A. Storer and J.H. Rief, “A Parallel Architecture for High Speed Data

Compression,” J. Parallel and Distributed Computing, vol. 13, pp. 222-227, 1991.

4. C.Y. Lee and R.Y. Yang, “High-Throughput Data Compressor Designs

Using Content Addressable Memory,” IEE Proc. Conf. Circuits Devices Systems,

vol. 142, pp. 69-73, Feb. 1995.

APPENDIX:

LOSSLESS COMPRESSION CODE:



--COMPARATOR:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_misc.all;

use IEEE.std_logic_unsigned.all;

entity comparator is

port(data1 : in std_logic_vector(31 downto 0);

data2 : in std_logic_vector(31 downto 0);

reset : in std_logic;

eqout : out std_logic);

end comparator;

architecture arch_comp of comparator is

begin

process(reset,data1,data2)

begin

if (reset = '1') then

eqout <= '0';

else

if (data1 = data2) then

eqout <= '1';

else

eqout <= '0';



end if;

end if;

end process;

end arch_comp;

--CAMCOMPARATOR

library IEEE;





entity camcomp is

port ( reset : in std_logic; -- Reset

start : in std_logic; -- Write

h0, h1, h2, h3, h4, h5, h6, h7 : in std_logic;

h8,h9,h10,h11,h12,h13,h14,h15 : in std_logic;



mhit : out std_logic; --Found Match

addr_out : out std_logic_vector(4 downto 0) );

end camcomp;

architecture arch_cam64 of camcomp is

begin



process ( reset,start,h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11, h12, h13,h14,h15,

h16,h17,h18,h19,h20,h21,h22,h23,h24,h25,h26,h27,h28,h29,h30,h31)

begin


mhit <= '0';

addr_out <= "00000";

elsif (start = '0') then

if (h0 = '1') then

mhit <= '1';

addr_out <= "00000";

elsif (h1 = '1') then

mhit <= '1';

addr_out <= "00001";


mhit <= '1';

addr_out <= "00010";


mhit <= '1';

addr_out <= "00011";


mhit <= '1';

addr_out <= "00100";




mhit <= '1';

addr_out <= "00101";


mhit <= '1';

addr_out <= "00110";


mhit <= '1';

addr_out <= "00111";


mhit <= '1';

addr_out <= "01000";


mhit <= '1';

addr_out <= "01001";


mhit <= '1';

addr_out <= "01010";


mhit <= '1';

addr_out <= "01011";


mhit <= '1';

addr_out <= "01100";




mhit <= '1';

addr_out <= "01101";


mhit <= '1';

addr_out <= "01110";


mhit <= '1';

addr_out <= "01111";


mhit <= '1';

addr_out <= "10000";


mhit <= '1';

addr_out <= "10001";


mhit <= '1';

addr_out <= "10010";


mhit <= '1';

addr_out <= "10011";




mhit <= '1';

addr_out <= "10100";


mhit <= '1';

addr_out <= "10101";


mhit <= '1';

addr_out <= "10110";


mhit <= '1';

addr_out <= "10111";


mhit <= '1';

addr_out <= "11000";


mhit <= '1';

addr_out <= "11001";


mhit <= '1';

addr_out <= "11010";


mhit <= '1';



addr_out <= "11011";


mhit <= '1';

addr_out <= "11100";


mhit <= '1';

addr_out <= "11101";


mhit <= '1';

addr_out <= "11110";


mhit <= '1';

addr_out <= "11111";

else

mhit<='0';

addr_out<="00000";

end if;

end if;

end process;

end arch_cam64;

--CAM:

library IEEE;







entity cam is

port ( clk : in std_logic; -- Clock

reset : in std_logic; -- Reset


datain : in std_logic_vector(31 downto 0);-- Tag Data

dataout : out std_logic_vector(31 downto 0);-- Data out

mh0, mh1, mh2, mh3, mh4, mh5, mh6, mh7 : inout std_logic;

mh8,mh9,mh10,mh11,mh12,mh13,mh14,mh15 : inout std_logic;



matchhit : out std_logic; --Found Match

addr_out : out std_logic_vector(4 downto 0)

--addr_out : out integer );

end cam;

architecture arch_cam of cam is

component comparator

port ( data1 : in std_logic_vector(31 downto 0);

data2 : in std_logic_vector(31 downto 0);




eqout : out std_logic);

end component;

component camcomp

port ( reset : in std_logic; -- Reset


h0, h1, h2, h3, h4, h5, h6, h7 : in std_logic;




mhit : out std_logic;

addr_out : out std_logic_vector(4 downto 0) );

end component ;

type ram_array is array (0 to 31) of std_logic_vector(31 downto 0);

signal data : ram_array;

signal sg_matchhit : std_logic;

signal sg_addr_out: std_logic_vector(4 downto 0);

signal Wr_addr :std_logic_vector(4 downto 0):="00000";

begin

-- : std_logic;

-- : std_logic_vector(5 downto 0);

u0 : comparator port map (data1 => datain, data2 => data(conv_integer(0)),

reset => reset, eqout => mh0);





































































u64 : camcomp port map (reset => reset, start => start,

h0 => mh0, h1 => mh1, h2 => mh2, h3 => mh3, h4 => mh4, h5 => mh5, h6 => mh6,h7 => mh7,h8 => mh8, h9 => mh9, h10 => mh10, h11 => mh11, h12 => mh12, h13 => mh13,h14 => mh14, h15 => mh15,h16 => mh16, h17 => mh17, h18 => mh18, h19 => mh19, h20 => mh20, h21 =>mh21, h22 => mh22, h23 => mh23,h24 => mh24, h25 => mh25, h26 => mh26, h27 => mh27, h28 => mh28, h29 =>mh29, h30 => mh30, h31 => mh31,

mhit => sg_matchhit, addr_out => sg_addr_out);

process(start,sg_matchhit,sg_addr_out,clk,reset)

--variable Wr_addr :integer := 0;

--variable Wr_addr :std_logic_vector(4 downto 0):= "00000";

begin

--wait until 'event and = '1';




data <= (others=>(others=>'0'));

--dataout<=(others=>'0');

dataout<="11111111111111111111111111111111";

matchhit <= '0';

addr_out <= "00000";

elsif ( clk'event and clk='1') then

if (start = '0') then

if (sg_matchhit = '1') then

matchhit <= '1';

addr_out <= sg_addr_out;

else

if (wr_addr ="11111") then

--wr_addr := "00000";

wr_addr <= "00000";

else

data(conv_integer(wr_addr)) <= datain;

matchhit <= '0';

dataout <= datain;

--wr_addr := wr_addr + "00001";

wr_addr <= wr_addr + "00001";

end if;

--matchhit <= '1';

--addr_out <= sg_addr_out;

end if;



end if;

end if;

end process;

end arch_cam;

-ds FOR COMPRESSION:

library IEEE;





entity ds is

port ( clk1, reset1 : in std_logic;

start1 : in std_logic;

udata : in std_logic_vector (31 downto 0);

dataout : out std_logic_vector(31 downto 0);

addrout : out std_logic_vector (4 downto 0);

matchhit : out std_logic);

end ds;

architecture arch_ds of ds is

component cam is

port ( clk : in std_logic; -- Clock

reset : in std_logic; -- Reset




datain : in std_logic_vector(31 downto 0);-- Tag Data

dataout : out std_logic_vector(31 downto 0);-- Data out

mh0, mh1, mh2, mh3, mh4, mh5, mh6, mh7 : inout std_logic;




matchhit : out std_logic; --Found Match

addr_out : out std_logic_vector(4 downto 0)

--addr_out : out integer );

end component;

begin

u3:cam port map (clk => clk1,

reset => reset1,

start => start1,

datain => udata,

dataout => dataout,

mh0 => open, mh1 => open, mh2 => open, mh3 => open,










matchhit => matchhit,

addr_out => addrout);

end arch_ds;

LOSSLESS DECOMPRESSION CODE:

library IEEE, STD;





entity de_xmatchpro is

port ( clk : in std_logic;


start_de : in std_logic;

datain : in std_logic_vector(31 downto 0);

addrin : in std_logic_vector(4 downto 0);

matchhit : in std_logic;

dataout : out std_logic_vector(31 downto 0) );

end de_xmatchpro;

architecture arch_de_camcomparator of de_xmatchpro is

type ram_array is array (0 to 31) of std_logic_vector(31 downto 0);



signal data : ram_array;

begin

process(matchhit,datain,addrin,clk, reset, start_de)

variable Wr_addr :integer := 0;

begin


data <= (others=>(others=>'0'));

dataout <= x"00000000";

wr_addr := 0;

elsif (clk'event and clk='1') then

if (start_de = '0') then

if (matchhit = '0') then

if (wr_addr = 31) then

wr_addr := 0;

else

--data(conv_integer(wr_addr)) <= datain;

data(wr_addr) <= datain;

dataout <= datain;

wr_addr := wr_addr + 1;

end if;

else

--sg_data_array <= data(conv_integer(addrin));

--dataout <= sg_data_array;



dataout <= data(conv_integer(addrin));

--dataout <= data(wr_addr);

end if ;

end if;

end if;

end process;

end arch_de_camcomparator;


Documents

Main DCM