Mark Thomson University of Cambridge WP6: L1Calo Upgrade

Mark Thomson University of Cambridge

WP6: L1Calo Upgrade

Mark Thomson 2

This Talk

UK ATLAS Upgrade Review, RAL, 10/5/2011

Introduction: L1Calo now L1Calo Upgrade Plans Towards Phase 1 Phase 2 Design

UK Work / Highlights / Plans /Milestones Simulation Firmware Phase 2 conceptual design High speed technology demonstrator Phase 2 demonstrator slice

Organisation Summary

Mark Thomson 3UK ATLAS Upgrade Review, RAL, 10/5/2011

Features of current L1Calo receives analogue signals from LAr and Tile Calorimeters

• input trigger towers: 0.1 × 0.1 in ( , h f) Digitisation and Bunch-crossing ID (BCID) performed in PPMs EM Clusters (e.g. electrons/photons and taus) and Jet triggers

formed independently (in CPs and JEP) Output = counts above thresholds + RoIs

❶ Introduction: L1Calo now


What can be done to upgrade trigger from physics perspective ?

❷ Upgrading L1Calo

EM Triggers longitudinal sampling from LAr may help higher transverse granularity information may help needs study – we don’t yet know what is most useful only available with new Calorimeter readout at Phase 2

Jets not limited by trigger tower granularity – so no help here but would like to separate jets cleanly from EM triggers

• can be done in CMM++ ~2013 shutdownTopology correlate RoIs to pick out physics signatures e.g.

✔✖

Phase 1 topological processor (also in Phase 2)


Phase-I: CMM++CMM++ (MSU responsibility) Replacement for current merger modules (CMMs)

• Need to run backplane at 160 MHz • Modern FPGA provides processing power• Receives output of Cluster and Jet processors• Backward compatible (provides existing trigger signals)

+ resolve overlap of EM and Jet triggers + potential for limited topological processing

CMM CMM++


Phase-I: TPTopological Processor (interest of Mainz and UK) Receives input from CMM++ Single ATCA crate “State-of-the-art FPGA”-based topological processing Should include signals from L1Muon

TPJet / SET

(JEP)0.2 x 0.2

E/g t/hadclusters(CP)

0.1 x 0.1

Pre-Processor(PPr)

Analogtower sums(0.1 x 0.1)

Jets

ClustersTo CTP

Energy results to CTP?

Muons

Further physics studies needed to demonstrate full impact of TP


Current Vision for Phase 2

Latency impact on Phase 2 design… 3.2 ms latency insufficient for track trigger, needs seeding ~6 ms Current favoured solution is a two stage system L0 and L1

Level 0 (Major UK focus) low latency “traditional” real-time trigger system technologically challenging input to L0Calo goes digital (LAr and Tile) includes Topo processing + muons send RoIs to region-based track trigger L0 accept at ~500 kHz

Level 1 (to be defined) includes calorimeter, muon and track trigger might run asynchronously higher latency possibility of HLT-like algorithms with track-based RoIs

Replacement of entire L1Calo system Driven by physics needs + replacement of Calo electronics

• analogue g digital input to trigger


Phase 2: Level 0/1 Strawman

M. Landon, ACES workshop

System might look something like…

Upgrade Schedule CMM++ Installation/commissioning during 2013 shutdown Integral part of Phase 1 upgrade

Phase 1 Topological processor Ready by 2015 or before Physics case still needs to be established

Phase 2 Slice Develop in parallel with CMM++ and TP Need to coordinate closely with LAr / Tile

Full Phase 2 System Fully tested/partially commissioned system by start of

2021 shutdown

Precise institute responsibility for Phase 1/Phase 2 upgrades not yet fully established – discussions ongoing

Mark Thomson 10

❸ UK Work / Highlights / Plans


Soft

Firm

Hard

① Simulation Understand L1Calo at high luminosity Strong focus on defining design

requirements

② Firmware Significant firmware needed at all stages

• CMM++/Phase 1/Phase 2 Essential part of programme

③ Hardware High speed 5-10 GHz demonstrator System Design Phase 2 demonstrator slice

Mark Thomson 11

① Simulation/Design Studies


Milestones

High Level AimsDetailed understanding of L1Calo at High Luminosities Evolution of the performance of current system? Benefits of topological processing? Physics-based design requirements for Phase-II system

Description Date Status

M6.1 Understand impact of pile-up 3/2011 ~complete

M6.2 Understand topological triggers 9/2011 starting

M6.3 Physics based Phase 2 requirements 3/2013 not started

Description Date Revised

Detailed understanding of current system at high L 3/2011 6/2011

Understand physics impact of upgrade options 6/2012

Deliverables


A lot of progress over last year very much UK driven ! went back to basics rather than simply running existing

ATLAS software unsurprisingly (nobody had looked in detail before) many

“features” uncovered Now starting to understand performance of L1Calo at

high luminosity• one deep-down (Geant 4 ?) feature still being studied

first results presented at Oxford ATLAS upgrade meeting

Simulation: Recent Progress


Starting to understand current L1Calo trigger at high luminosities still caveats – results should be considered preliminary looked at evolution of trigger threshold corresponding to

a fixed rate budget of 20 kHz rate

e.g. EM Triggers (electrons)

e.g. Different MCSettings – underinvestigation

General features understood EM triggers dominated by single physics object ~ logarithmic evolution of threshold reflects underlying pT

distribution in single minimum bias events


For 0.4 x 0.4 jets still dominated by single minimum bias events

Jets at High Luminosity

For 0.8 x 0.8 jets dominated by “pile-up”, thresholds increase more rapidly

4x4 8x8


Current estimates (remember still preliminary)

Single RoI Thresholds

Trigger 1x1034 cm-2s-1 3x1034 cm-2s-1

EM ~ 25 – 35 GeV ~ 35 – 45 GeV

EM Isolated ~ 20 – 30 GeV ~ 30 – 40 GeV

Jet 0.4x0.4 ~ 40 – 60 GeV ~ 50 – 80 GeV

Jet 0.8x0.8 ~ 40 – 70 GeV ~ 100 – 130 GeV

Note: triggers only becomes fully efficient ~10 GeV above notional threshold

Need full study of impact on physics, but already…

Thresholds are highMotivates clear need for upgrade at both Phase 1 and Phase 2

Mark Thomson 16

② Firmware


Milestones

High Level AimsProvide essential firmware for ongoing upgrade programme (UK has the core firmware expertise within L1Calo) Modifications to current system required for CMM++ Firmware for demonstrator slice


M6.4 Operation CPM internal links at 80MHz 6/2012

Deliverables

Nothing explicitly stated (perhaps should be) Timescale depends on precise CMM++ schedule

Mark Thomson 17

Recent Progress


Current CMM modules will be replaced with CMM++ (2013 shutdown) Requires more data to be shipped around current system Significant firmware modifications:

Running backplane at 160 MHz (4 x current) demonstrated

Running CPM (internal links) at 80 MHz (2 x current) signal integrity demonstrated

Significant extensions to internal data formats have two options – depends on physics requirements

Increased FPGA processing spare capacity demonstrated

Mark Thomson 18

③ Hardware/System Design


Milestones

High Level AimsFull system design of L1Calo Phase 1 and 2 upgrades Builds on simulation design studies

Build high speed technology demonstrator Build first stage of Phase 2 demonstrator slice Early connection to Calorimeter digital readout


M6.5 Conceptual design for Topo processor 9/2011 descope

M6.6 Conceptual design for Phase 2 system 3/2013 Started

M6.7 Construction of Phase 2 demonstrator 3/2013 Started design

Description Date Revised

Full definition of Phase 1 and 2 L1Calo systems 3/2013

ATCA-based high-speed hardware demonstrator 3/2013

Deliverables


Progress: conceptual designA lot of progress in developing strawman Phase 2 conceptual design

Very much UK led Considerations

Latency, data volumes, needs of track triggerTwo stage system (level 0 and level 1)


L0Calo (feature extraction): Find EM, Tau, Jet objects and ET sums every BC Insufficient bandwidth/latency to use full Calorimeter readout Assuming “mini-tower” + some depth/transverse information

• details need simulation studies L0Topo: Topological processor: merge L0Calo & L0Muon results

L1Calo: Running asynchronously? Refinement of L0Calo using full calorimeter data Implementation of HLT-like algorithms

• at this stage exactly what this means is an open question Processor-based rather than pipelined real-time system ?

L1Topo: Final topological processor for L1Calo, L1Muon & L1Track

L0 & L1 CTP: Final trigger decisions, interface with detectors

Phase 2: Functionality/Assumptions

Mark Thomson 21

High Speed Demonstrator


Data volumes at Phase 2 luminosities will be high Regardless of details, will require state-of-the-art high speed system operating at 5 – 10 GHz Very limited experience in HEP in operating at these speeds

High frequency dielectric behaviour of PCBs Propagation over signal rise time ~ few mm Inter symbol interference (ISI)

bit response depends on signal history need adaptive equalisation

A new level of channel simulation time domain + statistical analysis

10 GHz = battling against Maxwell

First step is high speed demonstrator ATCA backplane + modern FPGA (Virtex 6) Simple data source/sink Gain expertise in industry standard

systematic methodology Essential to build up this expertise


L1Calo Phase 2 upgrade will need to be ready with commissioned system at start of long “phase 2” shutdown ~2020/2021 Will be more complex than current system L1Calo planning full phase 2 demonstrator slice (UK led initiative)

L1Calo Phase 2 Slice

In this grant period UK plans to develop L0 Calo FEX demonstrator Major part of “L1” trigger upgrade

cutting edge high speed real time system builds on high speed demonstrator R&D

Direct connection to digital calorimeter readout “low risk” – independent of final Phase 2 design development is prerequisite for L0Topo

Need further discussions within L1Calo


Phase 2 Slice

ADChigainADClogainPMT

ShaperIntegratorCharge injection











ADChigainADClogain

ADChigainADClogain

ADChigainADClogain

ADChigainADClogain

ADChigainADClogain

ADChigainADClogain







PMT

PMT

PMT

PMT

PMT

PMT

LASER DRIVERo/e

Receivero/e

Receiver

IntegratorMultiplexor IntegratorADC IntegratorMultiplexorIntegratorADC

121 1

LAr and TileCal intend to install a few prototype digital boards on detector (with backward compatible output)

Use as input to L0Calo FEX demonstrator gain early experience in dealing with Phase 2 like digital signals early connection minimizes technical risk for final system possibility of test beam calorimeter slice has been raised…

Insufficient band-width and latency to use full calo readout for L0 Hence still require summation of cells into “mini-towers” Physics should drive the details (needs simulation) Depth information ? Transverse segmentation in LAr

• 0.1 × 0.1 vs. ??? Extra bits giving fine detail ?

vs.

Design issues:


Topological Processor TP in Original UK Proposal UK to construct major fraction of Phase 1 TP ~2013/2014

TP in Descoped UK Proposal Delay in approval/reduction in resources: descoped UK ambition In discussion with PPRP, focus moved more to Phase 2, with

idea that Phase 2 TP might be prototyped in Phase 1 Depends on simulation of physics impact + Phase 2 concept

TP international Context Mainz interested in Phase 1 TP based on GOLD demonstrator

Current UK position Ultimate balance of UK contribution to Phase 1 & Phase 2 TP and

L0Calo depends on: • balance of resources across L1Calo • R&D – simulation/demonstrators/Phase 2 design

Current UK programme addresses relevant R&D issues • High speed demonstrator/slice test: necessary first steps

❹ WP6 Management Management Overall WP6 management: MT WP6 engineering project manager: Ian Brawn

Regular UK L1Calo upgrade meetings roughly every six weeks meet in person (rotate between RAL/B’ham/Camb/QM) provides effective forum for UK-centric L1Calo upgrade effort

International Context discussion of institute L1Calo upgrade responsibilities ongoing details do not impact our work plan for current grant period

Project planning (see next two slides) maintain gantt chart for current (approved) project also “strawman” for entire L1Calo upgrade – useful sanity check


Mark Thomson 26

Gantt: Current Grant


Mark Thomson 27

Strawman Gantt for overall project


Also maintain gantt based on current best estimate of L1Calo upgrade programme

Despite uncertainties – useful sanity check


We have a well focused UK R&D programme concentrating on the core aspects of L1Calo upgrade Simulation: physics driven specification of upgrade

requirements Firmware: immediate upgrades needed CMM++ Design : conceptual design of Phase 2 system Hardware: high speed technology demonstrator Hardware: first part of Phase 2 slice (L0Calo FEX)

❺ Summary

Have clear programme of work up until Q4 2013 By end of current grant will be in position to move from R&D phase to full project

Documents

Mark Thomson University of Cambridge WP6: L1Calo Upgrade