Master’s Thesis Development of a high-level VHDL-AMS ... · PDF file0 Master’s degree in electrical and electronics engineering Master’s Thesis Development of a high-level VHDL-AMS

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Master’s degree in electrical and electronics engineering

Master’s Thesis

Development of a high-level VHDL-AMS simulation model of an RF transmitter based on a

direct modulation architecture Candidate: Bazungula Ntongo Christian Responsibles: Torsten Mähne, EFPL Frédéric Giroud, CSEM Matteo Contaldo, CSEM Supervisors: Alain Vachoux, EPFL Vincent Peiris, CSEM

Lausanne, 16th January 2009

Swiss Center of Electronic and Microtechnology Swiss Federal Institute of Technology, Lausanne

Microelectronic Systems Laboratory

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Acknowledgment

My special thanks go to M. Alain Vachoux, Torsten Mähne, Frédéric Giroud and Matteo Contaldo, who, despite their multiple occupations have always been available for me, showing patience in my many troubles during the project. My gratitude also goes to M. Alain Vachoux and M. Vincent Peiris, who gave me the opportunity to do this project. Sincere thanks to the almighty God, without whom nothing is possible.

To my mother Betthy, To my brothers Eli and Patrick, To my sister Näomie, I dedicate this work.

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Contents

Chapter 1 Introduction....................................................................................13

1.1 Project objective and description ..........................................................13

1.2 Document organisation.........................................................................14

Chapter 2 RF transmitter basics.....................................................................15

2.1 Principle of the Radio ...........................................................................15

2.2 Principle of RF transmitter ....................................................................16

2.3 Summary ..............................................................................................25

Chapter 3 Development of VHDL-AMS models for an RF transmitter............26

3.1 Introduction...........................................................................................26

3.2 Fractional Σ∆ PLL.................................................................................27

3.3 RF Transmitter, modulation process.....................................................65

3.4 Summary ..............................................................................................90

Chapter 4 Conclusion and Outlook ................................................................92

Appendix.............................................................................................................94

A.1 ModelLib prototyping.................................................................................94

A.2 Model hierarchy of the binary FSK transmitter ..........................................95

A.3 Multi-modulus divider ................................................................................96

A.4 Programmable digital divider.....................................................................99

A.5 Programmable divider with the prescaler control word:

“divider_prog_presc_control”.........................................................................102

A.6 High frequency programmable divider ....................................................106

A.7 Sigma delta MASH..................................................................................108

A.8 Bit stream modulator ...............................................................................111

Bibliography ......................................................................................................115

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List of Tables

Table 1: Ports description ...................................................................................29

Table 2: Multi-modulus divider generics..............................................................30

Table 3: Ports descriptions .................................................................................34

Table 4: Programmable divider generics ............................................................35


Table 6: Programmable divider (with the prescaler control word) generics.........42


Table 8: High frequency programmable divider generics....................................47


Table 10: Σ∆ generics.........................................................................................51

Table 11: Ports description .................................................................................58

Table 12: Bit stream generics .............................................................................59

Table 13: Basic configuration of the transmitter (modulation process)................66

Table 14: Post simulation computation: dimension of Loop filter elements. C1,

C2, C3, R2, R3 are shown in the Figure 8 (loop filter structure) .........................69

Table 15: Transmitter (modulation process) configuration while changing the cut-

off frequency of the loop filter..............................................................................69

Table 16: Post simulation computation: dimensions of Loop filter elements. C1,

C2, C3, R2, R3 are shown in the Figure 8 (loop filter structure) .........................70

Table 17: Spectrum characteristics.....................................................................72

Table 18: Transmitter (modulation process) configuration while changing the

modulation index.................................................................................................74

Table 19: Transmitter (modulation process) configuration while changing the Σ∆

order ...................................................................................................................78

Table 20: Configuration of the transmitter (modulation process) for the simulation

when the VCO output is modulated by rectangular signals and signals with

ramped pulse-shaping ........................................................................................81

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when the VCO output is a transient sinusoidal while changing the modulation

index ...................................................................................................................84


when the VCO output is a transient sinusoidal while changing the MASH order 87

Table 23: Configuration of the transmitter (modulation process) for a good

functioning ..........................................................................................................90

Table 24: Model simulation statistics ..................................................................91

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List of Figures

Figure 1: V-model of the design process of a technical system [2, 18] ...............13

Figure 2: Principle of the radio [2] .......................................................................15

Figure 3: RF Transmitter scheme ......................................................................17

Figure 4: Simple PLL architecture.......................................................................19

Figure 5: Integer PLL architecture. P (count) is the programmable digital divider

............................................................................................................................20

Figure 6: Fractional PLL architecture. P (count) is the programmable digital

divider and presc is the multi-modulus divider or the prescaler ..........................20

Figure 7: sigma-delta MASH modulator (of order three) diagram. ......................24

Figure 8: Loop filter structure, IN = charge-pump output, OUT = VCO input [4] .28

Figure 9: resonance elements of the VCO [4] .....................................................28

Figure 10: Multi-modulus divider interface. f_in = input signal (frequency),

presc_ctrl = control bit, div_out = digital output signal, power = supply voltage..29

Figure 11: Multi-modulus simulation ...................................................................32

Figure 12: Digital programmable divider interface...............................................34

Figure 13: Programmable divider with division ratio generated randomly. The

input division ratio is directly used for division process (without adding an offset)

............................................................................................................................38

Figure 14: Programmable divider with division ratio generated consecutively. The

input division ratio is directly used for division process (without adding an offset)

............................................................................................................................38

Figure 15: Programmable divider with a division ratio generated consecutively.

The input division ratio is not directly used for division process. As an offset, it’s

added to DIV_MIN for division process...............................................................39

Figure 16: Programmable divider, effect of the reset signal................................39

Figure 17: Programmable divider, effect of the enable signal .............................39

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Figure 18: Programmable digital divider (with the prescaler control word)

interface ..............................................................................................................41

Figure 19: Programmable divider with the prescaler control word ......................45

Figure 20: High frequency programmable divider interface ................................46

Figure 21: High frequency divider. Division process of frequency input f_in by a

ratio div_n ...........................................................................................................47

Figure 22: Σ∆ Mash interface..............................................................................49

Figure 23: Diagram of Σ∆ MASH 3 .....................................................................50

Figure 24: Addition and synchronization block of the Σ∆ ....................................51

Figure 25: Σ∆ simulation. EPFL Σ∆ model validation..........................................54

Figure 26: period detection of first order Σ∆........................................................54

Figure 27: period detection of second order Σ∆ ..................................................55

Figure 28: period detection of third order Σ∆ ......................................................55

Figure 29: Noise contribution of the Σ∆ (for MASH order 2 and 3) at the input of

the VCO (output of the low-pass filter). Number of samples (FFT): 1048576 (220)

............................................................................................................................56

Figure 30: Noise contribution of the Σ∆ (for MASH order 2 and 3) at the output of

the VCO. Number of samples (FFT): 1048576 (220) ...........................................56

Figure 31: Bit stream modulator interface ...........................................................58

Figure 32: Response impulse (one side of X axis) of the raised cosine filter. The

rolloff factor α is 0.5 and the data rate D is 100 kHz ...........................................61

Figure 33: Bit stream modulator. Generation of non-random bit stream

(rectangular shaped signals)...............................................................................63

Figure 34: Bit stream modulator. Generation of random bit stream (rectangular

shaped signals)...................................................................................................63

Figure 35: Bit stream modulator. Generation of random bit stream with ramped

pulse-shaping .....................................................................................................63

Figure 36: Bit stream modulator. Sampling of bit stream with ramped pulse-

shaping ...............................................................................................................63

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Figure 37: Bit stream modulator. Generation of rand om bit stream with

raised cosine pulse-shaping. The filter has 41 coef ficients with a rolloff

factor of 0.5 and a data rate of 100 kHz ...........................................................64

Figure 38: Transmitter (without the PA): “One-Point” or “direct” modulation

architecture .........................................................................................................65

Figure 39: VCO modulation. Data are ramp shaped. ..........................................67

Figure 40: Eye diagram of the VCO output .........................................................67

Figure 41: VCO output (frequency signal) FFT ...................................................68

Figure 42: Eye diagram of the VCO output for freq_cut_off = 25 kHz.................70

Figure 43: Eye diagram of the VCO output for freq_cut_off = 50 kHz.................71

Figure 44: Eye diagram of the VCO output for freq_cut_off = 100 kHz...............71

Figure 45: VCO output FFT at 25 kHz (blue), 50 KHz (orange) and 100 kHz

(green) ................................................................................................................72

Figure 46: Modulation of VCO output at different cut-off frequencies. 100 kHz

(green), ...............................................................................................................73

Figure 47: Eye diagram for the modulation index= 2 at cut-off frequency=100 kHz

............................................................................................................................74


............................................................................................................................75

Figure 49: FFT of VCO output with modulation index = 2 at cut-off frequency=100

kHz......................................................................................................................76

Figure 50: FFT of VCO output with modulation index = 1 at cut-off frequency=100

kHz......................................................................................................................77

Figure 51: Eye diagram with Σ∆ order equal to 3 for cut-off frequency=100 kHz79

Figure 52: Eye diagram with Σ∆ order equal to 2 for cut-off frequency=100 kHz79

Figure 53: FFT of the VCO output with Σ∆ order equal to 3 for cut-off

frequency=100 kHz.............................................................................................80

Figure 54: FFT of the VCO output with Σ∆ order equal to 2 for cut-off

frequency=100 kHz.............................................................................................80

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Figure 55: FFT of VCO output when modulated with rectangular (green) signals,

signals with ramped pulse-shaping (orange) and signals with raised cosine pulse-

shaping (blue) .....................................................................................................82

Figure 56: VCO output when modulated with rectangular (green) signals, signals

with ramped pulse-shaping (orange) and signals with raised cosine pulse-

shaping (blue) .....................................................................................................83

Figure 57: FFT of VCO output, which is a transient sinusoidal for modulation

index equal to 2...................................................................................................84


index equal to 1...................................................................................................85


index equal to 0.5................................................................................................85


index equal to 0.25..............................................................................................86

Figure 61: FFTs of VCO output with MASH order equal to 2 (green) and MASH

order equal to 3 (orange) ....................................................................................87

Figure 62: Faster version of the PLL model with transient sinusoidal VCO output

............................................................................................................................88

Figure 63: Frequency VCO output (modulated, orange) and its reduced version

(green) ................................................................................................................88

Figure 64: Transient sinusoidal signal which frequency is modulated around 14

MHz ....................................................................................................................89

Figure 65: VCO output FFT around 14 MHz .......................................................89

Figure 66: User interface of the ModelLib prototype [15] ....................................94

Figure 67: Model hierarchy of the binary FSK transmitter...................................95

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List of Listings

Listing 1: Divide process of the programmable divider........................................37

Listing 2: VHDL-AMS code addition and synchronization block of the Σ∆ ..........52

Listing 3: Output calculation................................................................................53

Listing 4: Random generation of sequence bits (data)........................................62

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Acronymes

AM: Amplitude Modulation

AMS: Analog and Mixed-Signal

CSEM: Centre Suisse d’Electronique et de Microtechnique (French), Swiss Center of Electronic and Microtechnology (English)

CP: Charge Pump

CPU: Central Processing Unit

D-FF: Digital Flip Flop

EPFL: Ecole Polytechnique Fédérale de Lausanne

EPS: Simulator accuracy

FFT: Fast Fourrier Transform

FM: Frequency Modulation

FSK: Frequency Shift Keying modulation

HDL: Hardware Description Language

LP: Low-Pass Filter

MASH: Multi-Stage Noise Shaping

NUMTTP: Number of steps accepted by the simulator and sent to the binary output file

OOK: On-Off Keying Modulation

PA: Power Amplifier

PFD: Phase Frequency Detector

PLL: Phase Locked Loop

PM: Phase Modulation

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PSK: Phase Shift Keying modulation

RC: Resistance-Capacitance

RF: Radio Frequency

RSR: Radio Suisse Romande

RTL: Register Transfer Level

VCO: Voltage Controlled Oscillator

VHDL-AMS: Very-High-Speed Integrated Circuits Hardware Description

language - Analog and Mixed-Signal

XTAL: Abbreviation of crystal

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Symbols

A: Ampere

F: Farad

H: Henry

Hz: Hertz

Σ: Sigma

∆: Delta

D: Data rate

V: Volt

Ω: Ohm

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Chapter 1 Introduction 1.1 Project objective and description The design process of technical systems follows often the “V-model” (Figure 1). This also holds true for Radio frequency (RF) transceivers and others analog and mixed-signal (AMS). The “V-model” also shows the usage of models throughout the top-down and bottom-up design phases.

Figure 1: V-model of the design process of a techni cal system [2, 18] The top-down process consists roughly of architecture exploration and synthesis of system. The system needs to be partitioned into sub-systems/components following a chosen architecture allowing to meet the overall specifications. The system-level specifications need to be distributed and translated into components specifications such as gain, bandwidth or cut-off frequency. The bottom-up process is targeted to verify and validate the assembled system. In this design phase, the system is already defined down-till transistor level but its validation is difficult due to the fact that the system simulation would take too much time because all its all effects would be considered. So the bottom-up design consists on modeling abstract models of implemented transistor netlists to allow the system validation in reasonable computing times.

The context of this work is a joint project between EPFL and CSEM to develop modeling methodologies for RF systems, to accelerate the design process and facilitate model reuse.

The project objective is to implement a high-level simulation model for low-power GHz-range radio frequency transmitters as they are developed at CSEM using the “Hardware Description Language (HDL) VHDL-AMS”. This

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high-level model will allow RF designers to validate different transmitter configurations by doing simulation in reasonable time. The challenge of this project is to model the behavior of the RF components with enough precision to obtain meaningful results but leaving them abstract enough to allow fast simulation. Moreover, another challenge is to develop models, which must be as flexible and reusable as possible for other RF design projects. At last, the system is required to work in high frequency applications. So, its modeling must take into account this constraint.

For the development of the abstract RF components models, VHDL-AMS was chosen as it is a hardware description language (HDL) designed to describe mixed-mode, conservative and digital systems. It allows behavioral modeling of system with more flexibility on the nature of the system to be modeled (mixed-mode, conservative and digital systems). Alternative would have been VERILOG-AMS language.

The project consists of several phases: understanding the basics of the RF transmitter architecture, identifying the important parameters of each sub-block jointly with the RF designers, designing the high-level models using VHDL-AMS, and eventually simulating the entire transmitter. Finally, it is important to notice that the target transmitter architecture is based on a direct modulation scheme, using a sigma-delta fractional PLL that drives directly the output power amplifier (PA).

1.2 Document organisation In Chapter 2 the basic theory of RF transmitter is introduced with a brief description of the different building blocks. General principle of the radio will be presented, and afterwards a discussion will be done on the two main parts of the transmission process: modulation and power amplifying.

Chapter 3 is devoted to the VHDL-AMS modeling of the transmitter modulation part, which is performed by a fractional sigma delta (Σ∆) PLL. Regarding the PLL, only the programmable digital divider, the multi-modulus divider and the Σ∆ blocs will be modeled. This is due to the fact that the other PLL components have already been developed in a previous project [1]. The PLL is augmented with a bit stream modulator generating the control word for the Σ∆ to obtain a transmitter model. Its simulation results are presented. Finally Chapter 4 will present the conclusion of the project and give an outlook.

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Chapter 2 RF transmitter basics This chapter introduces the basic principles of an RF transmitter. First the overall concept of radio will be outlined and then the components modulation, PLL, and power amplifier (PA) will be described in more details.

2.1 Principle of the Radio As described in the Figure 2, to communicate by radio, a radio transmitter and a radio receiver are needed. For transmitting signals, they must first be modulated around a certain frequency called carrier frequency. This carrier frequency determines the channel of transmission. For the modulation, frequency synthesis is first performed by a PLL. Then the synthesized frequency is modulated using a “Σ∆ modulator” (for “one-point modulation” architecture (section 2.2.2.2) or using a “mixer” (for “frequency conversion modulation” architecture). For RF applications, the PLL must be fractional. The modulated signals are amplified by the power amplifier and sent to the antenna, which will transmit them to the receiver. On the reception side, signals are demodulated into the base band. As it was already stated (section 1.1), the project will focus on the transmission phase of radio.

Figure 2: Principle of the radio [2]

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2.2 Principle of RF transmitter

2.2.1 Introduction Transmitting data requires two main processing steps: modulation and power amplifying (Figure 3). The modulation can be defined as the process by which the signal is converted from its original form into a suitable form for transmission channel. The channel is determined by the carrier frequency of transmission. Here are some examples of carrier frequencies according to RF applications [16, 17]:

• For Bluetooth applications e.g. wireless keyboard and mouse, the carrier frequency is 2.45 GHz.

• For broadcasting applications e.g. “Radio Suisse Romande” (RSR), carrier frequencies are between 88 MHz and 108 MHz.

• Medical applications often use 400MHz as carrier frequency. • There are non-regulated frequency bands around at 433MHz and

866MHz in Europe, and 900MHz in the USA.

As sudden frequency changes cause the channel to occupy a wide spectrum, the pulses are shaped by a bit stream modulator before they’re translated to division ratios controlling the Σ∆. With this information, the Σ∆ modulates the integer division ratios of the programmable divider inside the PLL to obtain in the average the desired fractional ratio.

Thereafter, the power amplifying is realized by the power amplifier (PA) block. Its aim is to amplify the power of the modulated signal before transmitting them to the antenna. In the context of this project, the PA is not modeled because of two reasons. Primary reason, first order PA model is just a simple scale factor and does not have any influence on the modulation process and the quality of the data to be transmitted. Secondly, for more elaborated PA model, there is not enough time.

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Figure 3: RF Transmitter scheme N: pre-divider. It is not essential to the function ing of the PLL PFD: Phase frequency detector VCO: Voltage controlled oscillator P (count): programmable digital divider presc: multi-modulus divider or prescaler Σ∆: sigma delta MASH modulator PA: Power amplifier

2.2.2 Modulation The modulation can be done using different approaches and determines the transmitter architecture. There are two main types of modulation techniques: analog modulation and digital modulation.

2.2.2.1 Analog modulation Is a modulation where the signal to be modulated is an analog signal. There are many types of analog modulation.

• Frequency modulation (FM) Conveys information over a carrier wave by varying its frequency. [5, 6] Considering: - Data: SDATA represented by the signal - Carrier (signal): SCARRIER given by:

fc is the carrier frequency ∆f is the maximum carrier frequency deviation

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Then the modulated signal SMODULATED is given by:

(2)

• Amplitude modulation (AM) Works by varying the strength of the transmitted signal in relation to the information being sent. [5, 6]

• Phase modulation (PM) Is a modulation that represents information as variations in the instantaneous phase of a carrier wave. [5, 6]

2.2.2.2 Digital modulation Is a modulation where the signal to be modulated is digital. Let’s introduce three of the most used digital modulations.

• FSK modulation Frequency-shift keying is a frequency modulation scheme in which digital information is transmitted through discrete frequency changes of a carrier wave. In the context of this project, FSK modulation will be used to modulate signals. In our case, this technique makes use of a Σ∆ modulator, which will modulate the programmable divider division ratio of a PLL used to control the frequency output of the VCO. [5, 7]

• OOK modulation On-off keying is a type of modulation that represents digital data as the presence or absence of a carrier wave. In its simplest form, the presence of a carrier for a specific duration represents a binary one, while its absence for the same duration represents a binary zero. [5, 7]

• PSK modulation Phase-shift keying is a digital modulation scheme that conveys data by changing, or modulating, the phase of a reference signal called carrier wave. [5, 7]

For this work, the transmitter is based on a direct modulation scheme because the frequency output of the VCO (voltage controlled oscillator that is the local oscillator) is directly modulated by the sigma-delta. It is also called “one point modulation” due to the fact that the modulation is done at one point, which is the input of the Σ∆ modulator. The Σ∆ modulator receives a control frequency word from a digital bit stream modulator, which generates this control frequency word according to a random or pseudo-random bits sequence of data (test signals) and some parameters as data rate (D), carrier frequency (fc) and modulation index.

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2.2.3 Phase-Locked Loop, PLL

2.2.3.1 Introduction A phase-locked loop or phase lock loop is a feedback system that includes voltage controlled oscillator (VCO), phase frequency detector (PFD), charge pump (CP) and low pass filter (LP) within the loop. It has many purposes depending on application. For applications intended to stabilize or synchronize to a reference frequency (XTAL, crystal), a simple PLL is used (Figure 4). In this PLL, VCO is forced to replicate and tack the frequency and phase at the input when the system is locked [6, 8]. In case of the need to synthesize a stable frequency, an integer PLL is useful (Figure 5) [6, 8, 9]. In this case, the synthesized frequency is multiplied by a certain ratio, which is an integer number. But integer PLLs are less flexible for choosing different channels (carrier frequency) of transmission while using high reference frequency. At last, for RF applications in which there are often many channels to choose while using high reference frequencies, as it is the case in this project, a fractional PLL (Figure 6) is required because it is suitable for choosing different channels of transmission while using high reference frequency. It allows frequency synthesis with a fractional ratio. This architecture makes use of an additional component, which is a Σ∆ modulator. When operating, the Σ∆ modulates the ratio at the reference frequency. So the PLL realizes the frequency synthesis with the average of the numbers generated by the Σ∆. That is why the fractional PLL allows to do frequency synthesis, not only with integer multipliers (as the integer PLL), but with also the fractional numbers. The PLL designed in this project has another particularity. The programmable divider contains two different components: a programmable digital divider and a multi-modulus divider or prescaler. This structure allows the PLL to work in the very high frequency ranges.

Figure 4: Simple PLL architecture

For the simple PLL, FVCO is given by Equation 3 (if the PLL is locked).

(3)

FREF is the reference frequency

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Figure 5: Integer PLL architecture. P (count) is th e programmable digital divider

For the integer PLL, FVCO is given by Equation 4 (if the PLL is locked).

(4)

FREF is the reference frequency P is the ratio of division. It is also the number of cycles of the counter or the divider.

Figure 6: Fractional PLL architecture. P (count) is the programmable digital divider and

presc is the multi-modulus divider or the prescaler

For the fractional PLL, FVCO is given by Equation 5 (if the PLL is locked).

(5)

P = P1 + P2

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P1 and P2 are the numbers of cycles of the counter when the prescaler ratio is respectively N and N+1 FREF is the reference frequency N is the minimum ratio of the prescaler

2.2.3.2 Phase frequency detector, PFD It is a device, which compares the phase of two input signals. It has two inputs, which correspond to two different input signals and generates an error Ve(t), proportional to the phase difference between the two inputs. KD is the gain of the phase detector [V/rad].

There are two types of phase detector: Analog phase detectors (multiplier or mixer) and digital phase detectors. In our case, it’s make use of the digital phase detector. This type of phase detector is also termed a “sequential phase detector”. It compares the leading edges of reference signal (SIGNAL_REF) and the feedback signal SIGNAL_BACK (coming from the output of the programmable divider, if PLL is a fractional/integer PLL or from the VCO, if PLL is a simple PLL). A SIGNAL_BACK rising edge cannot be present without a SIGNAL_REF rising edge. If the rising edge of the SIGNAL_REF leads the SIGNAL_BACK rising edge, the "Up" output of the phase detector goes high while the "Down" output remains low. This causes the SIGNAL_BACK frequency to increase and makes the edges move closer. If the SIGNAL_BACK signal leads the SIGNAL_REF, "Up" remains low while the "Down" goes high. [6, 7, 8, 9]

2.2.3.3 Charge pump, CP and low-pass filter, LP The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter. The loop filter converts these signals to a control voltage that is used to bias the VCO. It filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot [4, 6, 8].

2.2.3.4 Voltage controlled oscillator, VCO Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency.

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In PLL application, the VCO is treated as linear, time-invariant system. Excess phase of the VCO is the system output.

The VCO oscillates at an angular frequency . Its frequency is set to a nominal when the control voltage is zero. The VCO model designed in this project has non-linear KVCO but for estimated approximation, frequency is assumed to be linearly proportional to the control voltage with a gain coefficient KO or KVCO [rad/sec/V] [6, 8, 9].

2.2.3.5 Multi-modulus divider (prescaler) with the programmable divider (digital)

The Multi-modulus is a divider designed to carry out frequency division with different successive ratios. These ratios are at least two and are in a given range [PRESC_MIN … PRESC_MAX]. Even if the multi-modulus model designed in the context of this project allows divisions with more than two ratios, the algorithm (Equations 10-15) provided to use it in link with the programmable digital divider forces us to use it with only two ratios of division. So, in the remaining part of the rapport, it will be called “dual-modulus divider”. Its two ratios are PRESC_MIN and PRESC_MAX with:

PRESC_MAX = PRESC_MIN + 1 In a PLL, the dual-modulus prescaler is used to performed first division of high frequency signal, which requires special implementations. The higher reference frequency gives better frequency stability by supplying more samples per unit time to the phase detector, which results the following properties: [4, 11]

• Filtering of the VCO is easier • The locking time is faster • There is less noise at output • The smaller division ratio used in the programmable divider, makes

the filter calculations easier.

The dual-modulus takes at its inputs the instantaneous value of the VCO output frequency and its output is digital.

The programmable digital divider follows the dual-modulus. It is purely digital (input and output are digital). It consists to a counter by P, which must be programmable with the same number of control bits necessary to generate all consecutive divisions between two given numbers (minimum and maximum). It also needs to change the division value of the dual-modulus during an input

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signal cycle in order to generate all the values of division between PRESC_MIN*P and PRESC_MAX*P. The global division ratio, GLOBAL_RATIO, of the system constituted by the programmable digital divider and the dual-modulus is given by:

(9)

With cycle_min and cycle_max are respectively the minimum and the maximum numbers of cycles, during which the dual-modulus prescaler divides by PRESC_MIN and PRESC_MAX. As the highest division of the dual-modulus (ratio = PRESC_MAX) is often more symmetrical in its structure, it is decided to maximize the number of cycles (cycle_max) when the division ratio is PRESC_MAX. To control the ratio of the dual-modulus, the programmable digital divider makes use of Equations 10-15.

To get the maximum cycles division by PRESC_MAX:

(10)

(11)

(12)

To get the minimum cycles division by PRESC_MAX:

(13)

(14)

(15)

2.2.4 Sigma delta MASH The task of the Σ∆ modulator is to control the global division ratio of the programmable divider plus the dual-modulus prescaler, allows to obtain arbitrary rational division ratios without spurs (due to its long periodicity), and also shape the noise by moving it to higher frequencies, which is later efficiently suppressed through the loop filter of the PLL. [4] The structure of the sigma-delta modulator (of order three) diagram of is presented in Figure 7.

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Figure 7: sigma-delta MASH modulator (of order thre e) diagram.

freq_ctrl, provided as a word of N bits, is the desired fractional ratio to be obtained by the PLL. Its integer and fractional part are respectively freq_integ and freq_fract. The number of bits of freq_fract determines the resolution of the Σ∆. The output sda_out is the result of modulation of freq_ctrl.

• If the Σ∆ is of order one, sda_out is modulated between freq_ctrl and freq_ctrl + 1

• If the Σ∆ is of order two, sda_out is modulated between freq_ctrl – 1 and freq_ctrl + 1

• If the Σ∆ is of order three, sda_out is modulated between freq_ctrl – 3 and freq_ctrl + 4

2.2.5 RF Power amplifier, PA It is used to convert a low-power radio-frequency signal into a larger signal of significant power, typically for driving the antenna of a transmitter. Different power amplifier classes can be divided into two major groups: linear and non-linear power amplifiers. Class A, AB, B and C power amplifier are some of the well-known linear power amplifiers, which are distinguished primarily by their bias condition. Class E and F are the most common classes of non-linear power amplifiers [13].

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2.3 Summary In this chapter, the theoretic background of the radio concept has been presented. It consists of a transmitter and a receiver. Since the transmission part is the main objective of this project, our effort focused mainly on the different blocks of the modulation part of a transmitter. This part is essentially performed by the fractional Σ∆ PLL. Concerning to the power amplifier (PA) block, no development has been done in the context of this project. This is due to the fact that the PA is simply increasing the signal power to be transmitted and therefore does not directly impact in the modulation process.

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Chapter 3 Development of VHDL-AMS models for an RF transmitter

3.1 Introduction This chapter will be devoted to the study of the transmitter modulation part. It is performed by a fractional Σ∆ PLL. It is important to note that the phase detector (PFD), the charge pump (CP), the loop filter (LP) and the voltage controlled oscillator (VCO) are already available from prior project done by M. Torsten Mähne [1]. So they will be only shortly discussed. The report will focus on models developed during this project: dual/multi-modulus divider or prescaler, programmable digital divider, Σ∆ modulator and bit stream modulator. For each developed model, the following aspects will be treated:

• Analysis of the requirements according to the project. • The design of the model. It will be done a discussion on modeling for

each models which effects and how they’re modeled. • The implementation phase of models. For the reasons given in the

previous paragraphs, VHDL-AMS is the chosen language for the implementation. Implementation is presented in more details algorithms used in the models architectures.

• The test bench for each model. In this work, much effort is done to design very elaborate test benches. A lot of time was spent on modeling processes (within the test benches) in order to automate or at least facilitate post-processing of the simulation results. In this part, some simulation results of the models will also be presented and discussed.

For fast simulation, the VCO model directly outputs frequency as it changes less fast than the corresponding transient signal. As it is has been stated in the introduction of the project (section 1.1), for the implementation phase of the transmitter (modulation), the chosen language is VHDL-AMS as it is a hardware description language (HDL) designed to describe mixed-mode, conservative and digital systems.

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3.2 Fractional Σ∆ PLL

3.2.1 Phase detector (PFD): “pdf_digi_diff” Parameters:

• Digital, with a time delay on loop reset • Imperfections: coupling of an input to another, time delay on reset

Description

In of our system, the designed PFD is differential and digital. It implements the transition delays of the D-FFs (digital flip flops) and the reset delays of the AND gate. Its architecture is an “RTL architecture” (register transfer level). No power is currently consumed. [1, 4]

3.2.2 Differential Charge Pump: “charge_pump_diff” Parameters

• Gain KPD: 50 uA • Imperfections: currents up and down are different, spurs occurs

at system startup

Description It is the simplest analog circuit of all the blocks of the PLL because it only consists of two switchable current sources. The detailed architecture of the charge pump implements mismatches of the current mirrors, their internal on/off resistances, slew rates for the change of resistances and currents, and a load on the bias branch. [1, 4]

3.2.3 Loop filter, type II: “loop_filter_diff” Parameters

• Cut-off frequency: 50 kHz • Phase margin: 65° • Sizing of C1, R2, C2 • Second order: R3, C3 • Third order (due to varicap): R4, C4

Description The loop filter type II (Figure 8) consists of two capacitances C1 and C2 and a R2 resistance in series with C2. A second order (R3 C3) in cascade, which cut-off frequency is chosen much higher than the first filter, is added to attenuate the Σ∆ noise by 40 dB/decade.

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Figure 8: Loop filter structure, IN = charge-pump o utput, OUT = VCO input [4]

The loop filter model implements two architectures. One for the top-down design phase, which is called td_detailed and another designed for the bottom-up verification phase, which is called bu_detailed. In the context of this project, the simulation of the PLL will be realized with the top-down architecture. [4]

3.2.4 VCO, tune p-m differential, lom-lop different ial: “VCO_freq_out”

Parameters • Gain KVCO: 60 MHz/V • Ltank : 20 nH • Consumption: 500 uA

Description The synthesized fvco frequency depends on the varicap value Cvtot, the tank capacitor Ctank and the tank inductor Ltank (Figure 9) according to Equation 16.

(16)

Figure 9: resonance elements of the VCO [4]

The designed model has the following architectures: ideal, td_detailed, bu_detailed, ideal_discrete, td_detailed_discrete, bu_detailed_discrete. Our

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system will make use of td_detailed_discrete architecture [1]. The choice of this architecture is determined by the fact that it contains the discrete architecture of the “freq_to_digi” (section 3.2.5) instance, which generates less sampling points during simulation. This improves the simulation speed with acceptable precision.

3.2.5 Frequency to digital converter: “freq_to_digi” This model is designed to convert a continuously changing frequency at its input to a digital signal. It has two architectures, ideal and discrete. Our PLL makes use of the discrete architecture. It takes into account the initial phase PHI_LO_0. [1]

3.2.6 Multi-modulus divider or Prescaler : “multi_modulus_divider_freq_digi”

Figure 10: Multi-modulus divider interface. f_in = input signal (frequency), presc_ctrl = control bit, div_out = digital output signal, power = supply voltage

Table 1: Ports description

Name Class Type Direction Description

f_in non-conservative real in Frequency input signal

div_out digital std_logic out Digital output signal

presc_ctrl digital std_logic_vector in Control word of the division ratio

rst_b digital std_logic in Asynchronous active low reset

enable digital std_logic in Enable signal

power conservative electrical none Power supply terminal

ground conservative electrical none Ground terminal

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3.2.6.1 Requirements analysis The model is designed for frequency division with different successive ratios. These ratios are at least two and are in certain range. As front-end prescaler to the programmable digital divider (which provides the control of the prescaler), it allows the operations with higher input frequencies when it’s designed according to bottom-up methodology (system validation). But it can also operate without the programmable divider to do overall division when it’s designed according to top-down methodology (architecture exploration). As it precedes the division process of the programmable divider, it has the role of prescaler in the PLL. So it must be designed in order to fit the programmable divider requirements. This means that it must output a digital signal because the input of the programmable divider is also digital. There is another reason to the nature of its output, which is digital. When it used without the programmable divider, its output is connected to the PFD, which input is digital. The constraint of fast simulation to permit fast system validation is also taken into account. So this model is designed with a frequency input as high frequency because digital signals would cause considerable simulation slow down. The modeling of this model focuses also on flexible and reusability aspects.

3.2.6.2 Design As shown in the Figure 10, the multi-modulus divider contains the “freq_to_digi” as a sub-block. It converts to a frequency signal a digital signal. This fits the programmable divider requirements, which input is digital. In order to ensure fast simulation, the input frequency input is first divided by the desired ratio and then converted into digital signal. Another technique used to obtain fast simulation is to consider the input as an instantaneous value of a frequency. This avoids having many sampling points generated during simulation because they increase simulation time. The VHDL-AMS model has two architectures: ideal and discrete. This is due to the fact that the sub-model used to the conversion frequency to digital has also two architectures. For the flexibility, the model makes use of the following generics.

Table 2: Multi-modulus divider generics Name Type Range Default Unit Description

PRESC_MAX positive > PRESC_MIN 9 Maximum division ratio

PRESC_MIN positive > 2 8 Minimum division ratio

N_BITS_PRESC integer > 0 2 control word register size

PHI_LO_0 real 0.0 [DEG] Initial phase of the output signal (conversion frequency to digital)

V_POWER_MAX voltage [0.9 … 1.8] 1.8 [V] Maximum supply voltage

V_POWER_MIN voltage > 0.9 0.90001 [V] Minimum supply voltage

DEBUG boolean false Debug interface

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To ensure a consistently parameterized model, checks are made and messages are provided to facilitate the debugging.

• 2N_bits_presc – 1 >= PRESC_MAX – PRESC_MIN Prescaler control word register size must be big enough in order to cover the range [PRESC_MIN….PRESC_MAX]. Severity level: Failure

• div_ratio <= PRESC_MAX Division ratio (div_ratio) must be smaller or equal to the maximum division ratio (PRESC_MAX). Severity level: Failure

• Power must be in the range [V_POWER_MIN... V_POWER_MAX] The default values of V_POWER_MAX and V_POWER_MIN are respectively 1.8[V] and 0.9[V]. Severity level: Warning

It is important to note that the model draws currently no power from the supply.

3.2.6.3 Implementation First there is a process, which allows to choose the correct ratio according to the value of the signal control called "div_ctrl". All the ratios are consecutives integer numbers. Ratios are stored in registers. The reset signal is asynchronous and active low and the enable is asynchronous and active high. When the reset is low, the ratio register takes DIV_MIN as value of ratio. This ensures a division with a ratio, which is always greater or equal to DIV_MIN. The enable has the effect of freezing the system when it is inactive. Then, with the selected ratio, the frequency division is realized. And at last the result of this division is converted into digital using the sub program (Figure 10). Both of the architectures (ideal and discrete) have the same procedure. The difference between them is the fact that ideal architecture uses the ideal architecture of the instance designed for conversion of frequency to digital. And the discrete architecture uses the discrete architecture of that same instance.

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3.2.7 Test bench: “multi_modulus_divider_freq_digi_tb”

In the test bench, the frequency input signal f_in is a constant real number. The presc_ctrl signal is generated asynchronously and synchronously with the output div_out. The user can choose one of the two configurations according to the needs of his experiments. For post processing and validation needs, a process is provided to compute the period of the output signal after simulation. This period is calculated as following: It is generated an auxiliary signal, which changes the value at each rising edge of the output signal. Then, the “last_event” function is used on that auxiliary signal, in order to calculate the time spent since the last event occurred on that signal. As events of the auxiliary signal occur on every rising edge of the output, then the calculated time is the period of the output signal. The test bench also provides the possibility to choose or to bypass the test of enable signal. In the case of testing enable effect, the time for active and the disabled enable signal can be chosen. It’s the same for activating and disabling the reset signal; the active and disable times can be chosen. This is to make the model and its simulation as flexible as possible. The test bench has two configuration files according to ideal and discrete architecture of the model.

Figure 11: Multi-modulus simulation

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In the Figure 11, there are the following signals:

• presc_ctrl: control bit word • div_ratio: division ratio • f_in: an input frequency of 100 kHz • f_in_div: The frequency signal after division • div_out: output signal • div_out_period: output period after simulation

It can be noticed that the div_ratio value changes according to the value of presc_ctrl. For instance:

• if presc_ctrl = 0, then div_ratio = 8 • if presc_ctrl = 1 then div_ratio = 9 • if presc_ctrl = 2, then div_ratio = 10

The value of f_in_div corresponds to division of the f_in by div_ratio:

With f_in = 100 kHz:

• div_ratio = 8, then f_in_div = 12.5 kHz • div_ratio = 9, then f_in_div = 11.111 kHz • div_ratio = 10, then i_in_div = 10 kHz

The output period can also be visualized. Another thing to observe is the value of the output period at the transition of two different ratios. It is the average of the two periods.

• div_ratio = 8, f_in = 100 kHz, div_out_period = 80 us • At the transition div_ratio = 8 and div_ratio = 9, div_out_period = 85 us • div_ratio = 9, f_in = 100 kHz, div_out_period = 90 us • At the transition div_ratio = 9 and div_ratio = 10, div_out_period=95 us • div_ratio = 10, f_in = 100 kHz, div_out_period = 100 us

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3.2.8 Digital programmable divider: “divider_prog”

Figure 12: Digital programmable divider interface

Table 3: Ports descriptions Name Class Type Direction Description

div_in digital std_logic in Digital input signal


div_ratio digital std_logic_vector in Division ratio





3.2.8.1 Requirements analysis The model is targeted for frequency divisions of digital signals. It can be used without the multi-modulus divider. In this case it will increase the simulation time due to the fact the VCO must output a digital signal, which will generate many sampling points and slow down the simulation. So in the context of this project, it’s used with the multi-modulus divider, which allows the VCO to output a frequency signal, which will decrease simulation time. When integrated into the system, it works jointly with the multi-modulus divider and the Σ∆ modulator. So it must be designed in order to fit the multi-modulus and the Σ∆ requirements. Which implies that its input and output must be digital. The modeling of this block focuses also on flexible and reusability aspects.

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3.2.8.2 Design The conception of this model takes into account the fact that it can be used for top-down and bottom-up design flow. If the top-down design flow is chosen as modeling methodology, the division ratio is directly used in the division process without being sampled because the control word from the Σ∆ modulator is already synchronous. So it doesn’t need an additional register. For bottom-up design flow, the ratio must first be sampled and then used in the division process. In the context of this project, the system is designed, using the bottom-up approach. So the ratio is sampled when the divider is integrated in the PLL. The sampling is triggered (or controlled) by the output signal. So, in order to allow the system start if the register ratio is zero, it is decided to make the output equal to the input. However the PLL is modeled in order to avoid division with a ratio smaller than two. The model warns about ratios smaller than two as they’re not reasonable for physical implementation. For the flexibility need, two types of process are implemented in order to get or not at the output a duty cycle of 50 % when the division ratio is odd. The model makes use of the some generics, which increase the degree of the flexibility and reusability:

Table 4: Programmable divider generics Name Type Range Default Unit Description

DIV_MAX natural > DIV_MIN 1023 Maximum division ratio

DIV_MIN natural > 2 2 Minimum division ratio

N_BITS positive > 0 10 ratio register size

EVEN_DUTY_CYCLE boolean true Ensure output duty cycle of 50 %

OFFSET boolean false Consider the input ratio as an offset

DIV_RATIO_SAMPLED boolean true Activates the sampling of the input ratio




To ensure a consistently parameterized model, checks are made and messages are provided to facilitate the debugging.

• 2N_bits – 1 >= range [DIV_MIN….DIV_MAX] Division ratio register size must be big enough in order to cover the range [DIV_MIN….DIV_MAX]. Severity level: Failure

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• DIV_MIN < DIV_MAX The maximum division ratio must be the minimum division ratio Severity level: Failure

• DIV_MIN >= 2 and div_ratio_effective >= 2 This assertion ensures a division by at least 2. Severity level: Warning

• div_ratio_effective < or = DIV_MAX The effective division ratio has to be smaller than the maximum value of the division ratio. Severity level: Warning

• div_ratio_effective >= 2 The effective division ratio has to be at least equal to two Severity level: Warning

• power must be in the range [V_POWER_MIN... V_POWER_MAX] The default values of V_POWER_MAX and V_POWER_MIN are respectively 1.8V and 0.9V. Severity level: Warning

The model has only one architecture named ideal. It doesn’t treat non-ideal effects. It is important to note that the model draws currently no power from the supply.

3.2.8.3 Implementation When a ratio (div_ratio) is provided at the input of the model, it can be sampled or not according to the need of the design. Then the effective division ratio (div_ratio_effective) is calculated as following:

If div_ratio is considered as an offset:

And if div_ratio is not considered as an offset

DIV_MIN is the minimum division ratio. A counter register (count_reg) is counting (at every rising edge of the input div_in) from zero to div_ratio_effective – 1 and after it is reset.

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At the rising edge of the input div_in and when the counter reach the value: div_ratio_effective / 2 + div_ratio_effective_LSB (LSB of div_ratio_effective), then the output (div_out) is set to ‘1’. Otherwise div_out is equal to ‘0’. In the case it’s desired to obtain an output with the duty cycle of 50 %, so div_out is ‘0’ at the falling edge of the input div_in and if count_reg is equal to div_ratio_effective / 2 + div_ratio_effective_LSB. The implementation provides a process to allow the start of the system even if the effective ratio is zero. Listing 1 shows the VHDL-AMS implementation of the division process:

Listing 1: Divide process of the programmable divid er

-- purpose: Input division -- type : sequential -- inputs : div_in, rst_b, enable, EVEN_DUTY_CYCL E, div_ratio_effective -- outputs: count_reg, div_out_reg divide:process(div_in, rst_b, enable) is begin -- process divide if rst_b = '0' then -- asynchronous reset (active low) count_reg <= 0; elsif enable = '0' then null; elsif rising_edge(div_in) then if count_reg < div_ratio_effective - 1 and di v_ratio_effective /= 0 then count_reg <= count_reg + 1; -- increment c ounter else -- reset counter_reg count_reg <= 0; end if; if count_reg < shift_right(div_ratio_effectiv e,1) + resize(div_ratio_effective,1) or div_ratio_effective = 0 then div_out_reg <= '1'; else div_out_reg <= '0'; end if; elsif falling_edge(div_in) and EVEN_DUTY_CYCLE and (div_ratio_effective = 0 or (div_rati o_effective(0) = '1' and count_reg = shift_right(div_ratio_eff ective, 1) + resize(div_ratio_effect ive, 1))) then -- For a duty cyle = 50 % and if division rat io = 0, then the output -- is the same as the input div_out_reg <= '0'; elsif falling_edge(div_in) and not EVEN_DUTY_CY CLE and div_ratio_effective = 0 then -- For a duty cyle /= 50 % and if division ra tio = 0, then the output -- is the same as the input div_out_reg <= '0'; end if; end process divide;

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When the reset signal is low, the ratio register takes DIV_MIN as value of ratio. This to ensure a division with a ratio, which is always greater or equal to DIV_MIN. The enable has the effect of freezing the system when it is inactive.

3.2.8.4 Test bench: “divider_prog_tb” The division ratio is clocked by the output div_out. It is generated in 2 ways: consecutively or randomly using the “UNIFORM” function. For post processing and validation needs, a process is provided to compute the division ratio after simulation. An assertion verifies if the division has been done properly. The ratio is calculated as following: A count is made at every rising edge of the input div_in. Then, at every rising edge of output div_out, the current number of the counter is extracted and reset. This extracted number gives us the ratio between the input and the output. The test bench also provides the possibility to choose or to bypass the test of the enable signal. In the case of testing the enable signal, the time of activate and disable the enable signal can be chosen. It’s the same for activating and disabling the reset signal; the active and disable times can be chosen. This is to make the model and its simulation as flexible as possible.

Figure 13: Programmable divider with division ratio generated randomly. The input

division ratio is directly used for division proces s (without adding an offset)

Figure 14: Programmable divider with division ratio generated consecutively. The input division ratio is directly used for division process (without adding an offset)

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Figure 15: Programmable divider with a division rat io generated consecutively. The input division ratio is not directly used for divis ion process. As an offset, it’s

added to DIV_MIN for division process

Figure 16: Programmable divider, effect of the rese t signal

Figure 17: Programmable divider, effect of the enab le signal

Figure 13 and Figure 14 show the simulation of the programmable divider with the following characteristics:

• div_ratio: Division ratio is generated randomly in the Figure 13 (e.g. div_ratio is equal to: 37, 165, 678…) and consecutively in the Figure 14 (e.g. div_ratio is equal to: 76, 77, 78…). It’s sampled and stored in the div_ratio_reg that is its register. In the Figure 13, div_ratio = 165 and after one cycle div_ratio_reg = 165 and in the Figure 14, div_ratio = 77 and after one cycle div_ratio_reg = 77. The delay of one cycle is caused by the sampling of the div_ratio.

• div_ratio is not considered as an offset. So it is directly equal to the effective ratio of the division. It can be observed that: div_ratio_effective = div_ratio.

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Also, div_out_ratio, which is the division ratio after simulation is exactly equal to the value of div_ratio_reg after each cycle (e.g. div_out_ratio is equal to 340 or 37). This is normal, because it’s computed after getting the output signal. An assertion verifies the division process using div_out_ratio.

Figure 15 illustrates the effect of considering div_ratio as an offset. In this case DIV_MIN is equal to 2, so the effective ratio div_ratio_effective is done by div_ratio_reg + 2, e.g. div_ratio = 77, after one cycle div_ratio_reg = 77 and div_ratio_effective = 79. This simulation was done with a div_ratio generated as consecutive number.

Figure 16 shows the effect of the reset on the system. When the reset rst_b is active (rst_b = ‘0’), then the division ratio register div_ratio_reg is equal to DIV_MIN and the others registers are set to zero. It is important to note that in order to ensure a division at least by two, DIV_MIN is always greater or equal to two. This is verified by an assertion.

At last, Figure 17 shows the effect of the enable signal. When the enable signal is low, then the system conserves its state until the enable gets high.

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3.2.9 Programmable digital divider with prescaler control: “divider_prog_presc_control”

Figure 18: Programmable digital divider (with the p rescaler control word) interface

Table 5: Ports description Name Class Type Direction Description



div_n digital std_logic_vector in Global division ratio

presc_ctrl digital std_logic_vector out Prescaler control word





3.2.9.1 Requirements analysis For higher frequency applications, the combination of the prescaler and the programmable is required. The programmable divider receives at its input the signal generated by the prescaler and the division ratio of the prescaler is controlled by a control word generated by the programmable digital divider. The aim of this model is to generate this control word. So this model contains

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the programmable divider as sub-program (block) and the logic process to generate the control word (Figure 18). Therefore, it has more or less the same requirements as the programmable divider requirements.

3.2.9.2 Design As shown in the Figure 18, this model contains an instance of the programmable digital divider as sub-block and a logic process to generate the control word. This logic process will also provide the current division ratio of the programmable digital divider. The instance of the divider is prepared for multi-modulus prescaler control. However, only a dual-modulus control word is implemented as a starting point. This means that the control word will generate only two ratios for the prescaler division process. This architecture is called “dual-modulus”. For our application, the current ratio of the programmable digital divider is sampled at the rising edge of the output. The model makes use of the following generics to increase the degree of the flexibility and reusability:

Table 6: Programmable divider (with the prescaler c ontrol word) generics Name Type Range Default Unit Description

DIV_MAX natural > DIV_MIN 1023 Programmable divider maximum division ratio

DIV_MIN natural > 2 56 Programmable divider minimum division ratio

PRESC_MAX positive > PRESC_MIN 9 Prescaler maximum division ratio

PRESC_MIN positive > 2 8 Prescaler minimum division ratio

N_BITS_DIV positive > 0 10 Ratio register size

N_BITS_PRESC positive > 0 1 Prescaler control word register size

EVEN_DUTY_CYCLE boolean true Set output duty cycle to 50 %




To ensure correct operation, checks are made and messages are provided to facilitate the debugging.

• DIV_MIN < DIV_MAX The maximum division ratio must be the minimum division ratio Severity level: Failure

• N_BITS_PRESC = 1, and PRESC_MAX = PRESC_MIN + 1 If the multi-modulus operates in dual-modulus mode; This means that the multi-modulus has only two different division ratios, then the multi-modulus control bit word register size (N_BITS_PRESC) must

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be equal to one and PRESC_MAX and PRESC_MIN must be consecutive numbers. Severity level: Failure

• div_n >= PRESC_MIN * (PRESC_MIN - 1) div_n is the global division ratio. This condition must be ensured in order to be able to generate consecutive numbers for div_n and to avoid negative values of cycle_presc_max and cycle_presc_min. Severity level: Error

• div_n >= DIV_MIN The global division ratio must be greater than the minimum value of the division ratio. Severity level: Warning

• div_n <= DIV_MAX The global division ratio div_n has to be smaller than the maximum value of the division ratio. Severity level: Warning

The architecture doesn’t treat non-ideal effects. It is important to note that the model draws currently no power from the supply

3.2.9.3 Implementation As the implementation reuses the programmable digital divider model as an instance and can thus focus on the logic to generate the control word for the prescaler. Equations 20-22 are used in order to calculate the number of cycles of division by PRESC_MIN and PRESC_MAX to obtain global division ratio.

• cycle_presc_min and cycle_presc_max are respectively the minimum and the maximum numbers of cycles during which the prescaler divides by PRESC_MIN and PRESC_MAX.

• div_p is the current division ratio of the programmable divider. • div_n is the global division ratio (of the programmable digital divider

and the prescaler).

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As the division ratio of the programmable divider is sampled within its model, the value of div_p and div_n used in Equations 20-22 in order to generate the cycle_presc_max and cycle_presc_max values, are also sampled in this model (“divider_prog_presc_control”). In the architecture dual_modulus, there is a process, in which a counter register counts at every rising edge of the input div_in. While the counter value is smaller or equal to cycle_presc_max, the control word is set to one (presc_ctrl = 1) and if the counter value is greater than cycle_presc_max, the control word is set to zero (presc_ctrl = 0).

• presc _ctrl = 0 corresponds to the prescaler ratio = PRESC_MIN • presc _ctrl = 1 corresponds to the prescaler ratio = PRESC_MAX

3.2.9.4 Test bench: “divider_prog_hf_presc_control_tb” This test bench is modeled by taking into account the interaction of the following models:

• Programmable divider with the prescaler. • High frequency divider. This model will be discussed in the

section 3.2.10. • The Σ∆ MASH. It will be also discussed later (section 3.2.11).

The division ratio div_n is clocked by the output. It is generated in two ways: consecutively or randomly using the “UNIFORM” function. For the test, only the discrete architecture of the multi-modulus divider is considered, because it generates fewer samples, which make it faster than the ideal one. To avoid negative values of cycle_presc_max and cycle_presc_min, div_n has an offset, which is DIV_MIN, which must be greater than or equal to PRESC_MIN*(PRESC_MIN-1). For our simulation, PRESC_MIN is equal to 8 and PRESC_MAX is equal to 9. Below PRESC_MIN*(PRESC_MIN-1) (which is equal to 56) and considering the default values of PRESC_MAX (i.e. 9) and PRESC_MIN (i.e. 8), some values of div_n generate negative values of cycle_presc_max and cycle_presc_min.

A Boolean flag called SIGMA_DELTA allows to choose the division ratio div_n to be generated by the test bench process (consecutively or randomly) or the div_n to be generated by the Σ∆ model. The test bench provides a boolean flag named TEST_ENABLE, which allows to choose or to bypass the test of the enable signal. In the case of testing the effect of the enable signal, the time of active and disable enable signal can be chosen. The same is possible for activating and disabling the reset signal. This is to make the model and its simulation as flexible as possible. A process is provided to compute the division ratio after simulation. This ratio is implemented using the same method as for the programmable divider

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model (section 3.2.8.4). And an assertion is made in order to verify if the division is done with the correct ratio. There are processes, which aim is to compute the average of the Σ∆ outputs numbers and to verify, if the difference between this average and the excepted fractional division ratio (given by the frequency control, freq_ctrl) is smaller or equal to than the resolution of Σ∆ 1/2N (with the freq_ctrl size).

Figure 19: Programmable divider with the prescaler control word

Generation of the control wrord “presc_ctrl_prog” Figure 19 shows the generation of the prescaler control word presc_ctrl according to the cycle_presc_max and cycle_presc_min values. When:

• cycle_presc_max = 10 and cycle_presc_min = 1, then presc_ctrl =1 during 10 cycles of the input signal (div_in) and presc_ctrl = 0 during 1 cycle of div_in.

• cycle_presc_max = 5 and cycle_presc_min = 7, the presc_ctrl = 1 during 5 cycles of div_in and presc_ctrl = 0 during 7 cycles of div_in.

It can be verified that the global division ratio is given by Equation 9.

• PRESC_MAX = 9 during 10 cycles and PRESC_MIN = 8 during 1 cycle, then div_n = 10*9+1*8=98

• PRESC_MAX = 9 during 5 cycles and PRESC_MIN = 8 during 7 cycle, then div_n = 5*9+7*8=101

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3.2.10 High frequency programmable divider: “divider_prog_hf_freq_digi”

Figure 20: High frequency programmable divider inte rface









3.2.10.1 Requirements analysis This model assembles prescaler and programmable digital divider with prescaler control to provide high-frequency programmable divider with a frequency input and a digital output. It shall facilitate the design task to distribute the specifications of one programmable divider on an architecture involving a prescaler. It needs to expose all parameters of the underlying models.

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3.2.10.2 Design As shown by the Figure 20, this model is built by connecting together the multi-modulus and the programmable divider with the logic instances. Therefore, it contains all characteristics of its constituting models. As the prescaler has two architectures (ideal and discrete), this model has also two architectures. Table 8 shows that the model exposes the generics of the underlying models to allow their full configurations.

Table 8: High frequency programmable divider generi cs

Name Type Range Default Unit Description







PHI_LO_0 real 0.0 [DEG] Initial phase used in sub program (conversion frequency to digital)




3.2.10.1 Implementation and test bench The implementation consists on connecting the prescaler and the programmable divider with the prescaler control word instances using VHDL-AMS syntax. Concerning the test bench, it is already described in section 3.2.8.4. To accelerate the simulation, the discrete architecture of the model is used.

Figure 21: High frequency divider. Division process of frequency input f_in by a ratio div_n

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The Figure 21 represents a frequency signal f_in (100 kHz), which is divided by a ratio (div_n). div_out is the output signal. It can be noticed that with this model, many details that are less interested on a global scope, are not treated. There are only the input, the output and the ratio of division.

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3.2.11 Sigma delta MASH modulator: “sigma_delta_mash”

Figure 22: Σ∆ Mash interface


freq_ctrl digital std_logic_vector in Frequency control word signal

clk digital std_logic in Clock signal

sda_out digital std_logic_vector out Output signal



3.2.11.1 Requirements analysis The purpose Σ∆ modulator is to modulate the global division ratio of the programmable divider with the dual-modulus prescaler. This allows the PLL to lock on fractional ratio frequencies. Its architecture shall follow the structure of the third order Σ∆ MASH shown in the Figure 23. Its modeling takes into account the fact that it must be as parametrisable as possible. So the implementation will allow to choose the Σ∆ order and its resolution. The synchronization of the whole the Σ∆ modulator is ensured by the programmable divider output.

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Figure 23: Diagram of Σ∆ MASH 3

3.2.11.2 Design The Σ∆ is designed as a register transfer level model (RTL). The entire structure of the Σ∆ is not operating during simulation. Depending on the chosen order, only the necessary parts of the overall structure shown in the Figure 23 are generated to speed up model execution by avoiding unnecessary calculations. It means that:

• If the chosen order is one, only the first branch of the Σ∆ will be activated and operates. The remaining part will not work.

• If the chosen order is two, only the two first branches of the Σ∆ will be activated and operate. The third is not operating.

• If the chosen order is three, the whole structure of the Σ∆ will be activated and operate.

The computation of the periodicity the Σ∆ is also treated is the design of this model. Finally, the PLL model will be simulated in order to visualize the noise contribution of the Σ∆ in all the PLL. Power consumption is not considered in this model. The model makes use of the generics shown in the Table 10, which increase the degree of the flexibility and reusability.

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Table 10: Σ∆ generics Name Type Range Default Unit Description

N_BITS_FREQ_CTRL positive > 0 20 Input register size

N_BITS_INTEG positive > 0 7 Register size of the input integer part

N_BITS_FRACT positive > 0 13 Register size of the input fractional part

N_BITS_SDA positive > 0 7 Output register size

MASH_ORDER positive [1 … 3] 3 Σ∆ MASH order


To ensure correct model operation, checks are made and messages are provided to facilitate the debugging.

• N_BITS_FREQ_CTRL = N_BITS_INTEG + N_BITS_FRACT N_BITS_FREQ_CTRL must be the sum of N_BITS_INTEG and N_BITS_FRACT Severity level: Failure

• MASH_ORDER must be in the range [1…3] The Σ∆ order cannot be greater than 3.

Severity level: Failure

3.2.11.3 Implementation The addition and synchronization block of the Σ∆ (Figure 24) is first implemented. As the structure of the Σ∆ contains three of these blocks, a “for generate” construct is used to generate it one, two or three times according to the order chosen by the user (Listing 2). Overflows generated by these blocks are therefore transmitted to the remaining part of the Σ∆ architecture in order to be sampled, added, subtracted or multiplied by two according to the MASH structure illustrated in the Figure 23. The output is computed according to the chosen order of the Σ∆ by using “if generate” constructs (Listing 3).

Figure 24: Addition and synchronization block of th e Σ∆

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For the calculation of the Σ∆ period, an additional model called “sigma_delta_debug” is implemented. It has the same configurations than the standard Σ∆ model but in its interface, there additional signals, which are: fract_1, fract_2, fract_3, fract_1_reg, fract_2_reg, fract_3_reg, sum_1, sum_2, sum_3, overflow_1_reg, overflow_2_reg, overflow_3_reg. These signals allow post processing calculations. The periodicity of the Σ∆ is reached when fract_1, fract_2, fract_3 are equal to zero.

Listing 2: VHDL-AMS code addition and synchronizati on block of the Σ∆

GEN: for i in 1 to MASH_ORDER generate -- Next values of fract and overflows signals signal fract_next : fract_vector(1 to MASH_ORDE R); signal overflow_next : overflow_vector(1 to MAS H_ORDER); begin process (clk, rst_b, enable) is begin if rst_b = '0' then -- asynchronous reset ( active low) fract_reg(i) <= (others => '0'); overflow_reg(i) <= (others => '0'); elsif rising_edge(clk) and enable = '1' then -- rising clock edge fract_reg(i) <= fract_next(i); overflow_reg(i) <= overflow_next(i); end if; end process; fract_sum(i) <= resize(fract(i), N_BITS_FRACT+1 ) + resize(fract_reg(i), N_BITS_F RACT+1); overflow_next(i) <= fract_sum(i)(N_BITS_FRACT d ownto N_BITS_FRACT); fract_next(i) <= fract_sum(i)(N_BITS_FRACT-1 do wnto 0); C1: if i = 1 generate fract(i) <= unsigned(freq_fract); end generate C1; C2: if i > 1 generate fract(i) <= fract_sum(i-1)(N_BITS_FRACT-1 dow nto 0); end generate C2; end generate GEN;

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Listing 3: Output calculation

C3: if MASH_ORDER >= 2 generate -- Delayed value of overflow_2_reg signal delay_reg : unsigned(0 downto 0); signal delay_next : unsigned(0 downto 0); begin -- Overflow in the 2nd branch and its delayed v alue delay_next <= overflow_reg(2); -- Sum of sum_a and overflows sum in the 2nd br anch sum_b <= sum_a + resize(signed(resize(overflow_ reg(2), 2) -resize(delay_re g, 2)),N_BITS_SDA); -- purpose: Generate delay_reg -- type : sequential -- inputs : reg_clk, rst_b, enable, delay_next -- outputs: delay_reg delay_reg_gen: process (clk, rst_b, enable) is begin -- process delay_reg_gen if rst_b = '0' then -- asynchronous reset (active low) delay_reg <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge if enable = '1' then delay_reg <= delay_next; end if; end if; end process delay_reg_gen; end generate C3; C4: if MASH_ORDER < 2 generate sum_b <= sum_a; end generate C4;

C5: if MASH_ORDER >= 3 generate -- 1rst delayed value of overflow_3_reg signal delay_1_reg : unsigned(0 downto 0); signal delay_1_next : unsigned(0 downto 0); -- Delay_1_reg multiplied by 2 signal delay_1_reg_double : unsigned(1 downto 0) ; -- 2nd delayed value of overflow_3_reg signal delay_2_reg : unsigned(0 downto 0); signal delay_2_next : unsigned(0 downto 0); begin -- Overflow in the 3rd branch and its delayed v alues delay_1_next <= overflow_reg(3); delay_2_next <= delay_1_reg; -- Delayed overflow (in 3rd branch) multiplied by 2. delay_1_reg_double <= delay_1_reg & '0'; -- Sum of sum_b and overflows sum in the 3rd br anch sum_c <= sum_b + resize(signed(resize(overflow_ reg(3), 3) - resize(delay_1 _reg_double, 3) +resize(delay_2_ reg, 3)),N_BITS_SDA); -- purpose: Generate delay_1_reg and delay_2_re g -- type : sequential -- inputs : reg_clk, rst_b, enable, delay_1_nex t, -- delay_2_next -- outputs: delay_1_reg, delay_2_reg delay_1_2_reg_gen: process (clk, rst_b, enable) is begin -- process delay_1_2_reg_gen if rst_b = '0' then -- asynchronous reset (active low) delay_1_reg <= (others => '0'); delay_2_reg <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge if enable = '1' then delay_1_reg <= delay_1_next; delay_2_reg <= delay_2_next; end if; end if; end process delay_1_2_reg_gen; end generate C5;

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3.2.1 Test bench: “sigma_delta_mash_tb” To verify the newly developed parametrisable MASH model, the already verified Σ∆ third order MASH of the CSEM could be used. The test bench instantiates therefore both models, “sigma_delta_mash” (newly developed) and “sigma_delta_top” (already developed at the CSEM), simulates them with the same signals and verifies using assertions that the behavior is the same. A process is provided to detect and to calculate the Σ∆ periodicity. This periodicity is detected by monitoring the register values (fract_1_reg, fract_2_reg, fract_3_reg) in addition and synchronization block of the Σ∆ (Figure 23). When fract_1_reg, fract_2_reg, fract_3_reg are equal to zero, then the Σ∆ returns to its initial state and its periodicity is reached. The test bench also allows to choose or to bypass the test of enable signal. In the case of testing enable effect, the time of active and disable the enable signal can be chosen. It’s the same for activating and disabling the reset signal. This is to make the model and its simulation as flexible as possible.

Figure 25: Σ∆ simulation. EPFL Σ∆ model validation

Figure 26: period detection of first order Σ∆

C6: if MASH_ORDER < 3 generate sum_c <= sum_b; end generate C6; ------------------------------------------------- ------------------------------ -- Output contruction ------------------------------------------------- ------------------------------ sda_out <= std_logic_vector(sum_c);

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Figure 27: period detection of second order Σ∆

Figure 28: period detection of third order Σ∆

Figure 25 shows the validation of the Σ∆ developed in this project. It’s can be noticed that epfl_sda_out is equal to csem_sda_out. With epfl_sda_out, the output of the newly developed Σ∆ model and csem_sda_out, the output of the exiting CSEM Σ∆ model. Figure 26, Figure 27 and Figure 28 illustrate the detection the periodicity of the Σ∆ when the order is respectively one, two and three. This detection is done by the signal SIGMA_DELTA_PERIOD_REACHED. After many simulations, it’s concluded that the periodicity of Σ∆ is given by this formulation: When Σ∆ order is equal to one

(23)

When Σ∆ order is equal to two and three

(24)

N_BITS_FRACT is the number of bits of the fractional part of the frequency control word. For our simulations, N_BITS_FRACT is equal to 13, then the periodicity is equal to:

2(13) = 8192 clock cycles when MASH order is equal to 1 2(13+1) = 16384 clock cycles when MASH order is equal to 2 or 3

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Figure 29: Noise contribution of the Σ∆ (for MASH order 2 and 3) at the input of the VCO (output of the low-pass filter). Number of samples (FFT): 1048576 (220)

Figure 30: Noise contribution of the Σ∆ (for MASH order 2 and 3) at the output of the VCO. Number of samples (FFT): 1048576 (2 20)

In the Figure 29 and Figure 30, it can be observed that in the PLL bandwidth (low-pass filter cut-off frequency equal to 100 kHz), the amplitude of noise is

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higher for the second MASH order than for the third MASH order. But in higher frequencies, the noise of the third MASH order is more important than the noise of second MASH order. There are also lobs after every multiples of the reference frequency, which is equal to 13 MHz. This Σ∆ behavior corresponds exactly to the theory. Considering the Σ∆ noise contribution in the PLL, the noise in higher frequencies doesn’t interest us because it will be filtered by the PLL low-pass filter. This is the reason why the third MASH order is better than the second MASH order because its noise contribution in the PLL bandwidth is less important than the noise contribution of the second MASH order.

According to the Figure 29, the third MASH order slope in the PLL bandwidth is equal to 40 dB/decade and the second MASH order slope is equal to 20 dB/decade. This corresponds to the theory. Beyond the cut-off frequency (100 kHz), the third MASH order slope is about of 20 dB/decade and the second MASH order slope is equal to 0 dB/decade. This is due to the fact that the PLL low-pass filter introduces an attenuation of 20 dB/decade. At high frequency, the slope of second and third MASH order is about of -40 dB/decade. This phenomenon is caused by an additional order (R3C3 in Figure 8) of the low-pass filter, which pole is located is higher frequency and increases the noise attenuation to -40 dB/decade. So, in the Figure 29 allows to visualize the effect of the low-pass filter (first order) and its additional pole in high frequency on the noise of the Σ∆.

Figure 30 shows the effect of the low-pass filter, the VCO and the additional order of the low-pass filter. Each of them introduces an attenuation of 20 dB/decade. This can be observed in higher frequencies where the slope of second and third MASH order is about of -60 dB/decade. Just after the cut-off frequency, the slopes of the second and third MASH order are respectively about of -20 dB/decade and 0 dB/decade. This is normal because beyond the cut-off frequency (100 kHz) and below the half value of the reference frequency (6.5 MHz), there is an attenuation of 40 dB/decade caused by the low-pass filter and the VCO. So the second and the third MASH order, which had initially slopes of 20 dB/decade and 40 dB/decade respectively, will have slopes of -20 dB/decade and 0 dB/decade.

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3.2.2 Bit stream modulator: “bit_stream_modulator”

Figure 31: Bit stream modulator interface


data_in digital std_logic in Input data

freq_carrier digital real in Carrier frequency

delta_freq digital real in Frequency deviation

clock_bit_stream_sampling digital std_logic in Sampling clock of the bit stream

clock_ramp_data_sampling digital std_logic in Sampling clock of ramp shaped data

clock_impulse_response_sampling digital std_logic in Sampling clock of the raised cosine filter impulse response

clock_convolution digital std_logic in Sampling of the convolution process

freq_ctrl_out digital std_logic_vector out Output frequency word signal

3.2.2.1 Requirements analysis In the case of the chosen binary FSK one-point Σ∆ PLL modulation architecture, a bit stream modulator model is required translating the ‘0’ and ‘1’ of data stream to corresponding frequencies and finally resulting division ratios to command the PLL executing the modulation. To avoid spurs and

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other out-of-band disturbances due to non-continues frequency changes, the pulse-train resulting from the data stream needs to be shaped.

3.2.2.2 Design There are three architectures in this model. The architecture called “discrete” is designed to modulate the frequency with rectangular shaped data. The second architecture called “ramp” modulates the frequency using the intermediate ramp shaped signal generated from the rectangular shaped data stream. And the third architecture called “raised_cosine” makes use of the raised cosine filter to filter the rectangular shaped data and modulates the frequency with the resulting filtered signal. Non-ideal effects are not taken into account. The concept of power is not considered in this model. For a flexible and reusable model, this model defines the generics listed in the Table 12.

Table 12: Bit stream generics


FREQ_REF_PLL real > 0 13e6 [Hz] Reference frequency

F_CARRIEER real > 0 868.2e6 [Hz] Carrier frequency

DATA_RATE real > 0 100e3 [Hz] Data rate

ALPHA real [0 … 1] 0.5 Rolloff factor of the raised cosine filter

T_RISE real > 0 2e-6 Rise time of ramp shaped data

T_FALL real > 0 2-6 Fall time of ramp shaped data

N_COEFF_FILTER positive > 0 41 Number of raised cosine filter coefficients

N_BITS_FREQ_CTRL positive > 0 22 Frequency control output register size

N_BITS_FREQ_FRACT positive > 0 13 Register size of the Frequency control fractional part

DEBUG boolean False Debug interface

One assertion ensures the consistency of the model parameters:

• 2(N_BITS_FREQ_CTRL-N_BITS_FREQ_FRACT) – 1 >= div_integ (frequency control integer part). The register size of the frequency control integer part (div_integ) must be big enough in order to cover the number div_integ.

* Severity level: Failure

3.2.2.3 Implementation For the both architectures (discrete and ramp) implement the following bit stream parameters:

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• Carrier frequency: fc. As it’s stated before, it is channel center frequency. This means that it is the frequency around which the signal (data) has to be transmitted.

• Data rate: D It represents the number of symbols transmitted or received per time unit.

• Frequency deviation: ∆f It is the deviation of the carrier frequency according to the logic state of the bit to be transmitted. If the bit is '1', fc + ∆f and if it’s '0', fc – ∆f.

• Modulation Index. It is given by Equation 25.

So, according to the parameters given above, the bit stream modulator can provide the value called frequency control (freq_ctrl), intended to control the fractional division ratio generated by the Σ∆ to the programmable divider within the PLL. This value is given by the formulations:

(26)

FREF is the reference frequency of the PLL generated by a crystal oscillator. freq_ctrl_integ and freq_ctrl_frac are respectively the integer and the fractional part of the frequency control freq_ctrl. They are calculated by Equations 28 and 29

(29)

N is the number of bits of the fractional part of the Σ∆. It represents the Σ∆ resolution.

The ramp architecture generates additionally an intermediate analog signal, which allows to shape the pulse in an easy manner using the “’ramp” attribute. In his case, the ramp shaped signal needs to be sampled before passed to the Σ∆ modulator.

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The raised_cosine architecture implements the raised cosine filter, which transfer function and impulse response are given respectively by the Equations 30 and 31. [34]

The f1 parameter and the bandwidth W are linked to the rolloff factor α (Equation 32), which is the excess use of the bandwidth according to ideal solution. Tb is the symbol time and D the data rate (Equation 33). [4]

The sampling of the impulse response (Figure 32) allows to obtain the filter coefficients. And the convolution between this impulse response (filter coefficients) and the bit stream give the filtered signals (data).

Figure 32: Response impulse (one side of X axis) of the raised cosine filter. The rolloff

factor α is 0.5 and the data rate D is 100 kHz

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Finally, by using the filtered signals and according to the Equations 25-29, the output frequency control of the bit stream is calculated.

3.2.2.4 Test bench: “bit_stream_modulator_tb” The test bench for the bit stream modulator generates the necessary input signals to control the bit stream modulator:

• Carrier frequency (fC) • Maximum deviation of the carrier frequency (∆f) • Test data stream (optionally pseudo-random) • Sampling clock of data stream • Sampling clock of ramp shaped signals • Sampling clock of raised cosine filter • Clock of the convolution process

For random generation of data, the function “UNIFORM” is used according to the “data_in_generation” process (Listing 4).

Listing 4: Random generation of sequence bits (data )

-- purpose: data_in generation -- type : sequential -- inputs : clock_bit_stream, RANDOM_DATA_IN -- outputs: data_in data_in_gen: process (clock_bit_stream) is -- Seed values for random generator variable seed1, seed2: positive; -- Random real-number value in range 0.0 to 1.0 variable v_rand: real; -- Decision value variable v_decision: real; begin -- process data_in_gen if rising_edge(clock_bit_stream) then if RANDOM_DATA_IN then v_decision := 0.5; uniform(seed1, seed2, v_rand); if v_rand >= v_decision then data_in <= '1'; else data_in <= '0'; end if; else data_in <= not data_in; end if; end if; end process data_in_gen;

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Figure 33: Bit stream modulator. Generation of non- random bit stream (rectangular shaped

signals)

Figure 34: Bit stream modulator. Generation of rand om bit stream (rectangular shaped

signals)

Figure 35: Bit stream modulator. Generation of rand om bit stream with ramped pulse-

shaping

Figure 36: Bit stream modulator. Sampling of bit st ream with ramped pulse-shaping

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Figure 37: Bit stream modulator. Generation of rand om bit stream with raised cosine pulse-shaping. The filter has 41 coefficients with a rolloff factor of 0.5 and a data rate

of 100 kHz Figure 33 shows the generation of non-random data named data_in. It’s purely digital. The frequency control word named freq_ctrl_out, which will control the frequency control word of the Σ∆ modulator is also calculated. It can be noticed that freq_ctrl_out is changing according to the value of data_in. If data_in is ‘0’, freq_ctrl_out is equal to 68380 and if data_in is ‘1’, freq_ctrl_out is equal to 68395. Figure 34 shows the generation of random data (data_in). In the Figure 35, the data is generated as signals with ramped pulse-shaping. It’s called data_ramp. To be passed to the Σ∆ modulator, data_ramp must be sampled in order to obtain a certain value called freq_carrier_modulated_sampled, which will be used in Equations 27- 29, to calculate the frequency control output (freq_ctrl_out). In the case of signals with ramped pulse-shaping, freq_ctrl_out has many values when data_in is passed from 0 to 1 (Figure 36). The number of those values (freq_ctrl_out value) depends on the resolution of the sampling. Figure 37 shows the filtering of bit stream by using a raised cosine filter of 41 coefficients with a rolloff factor of 0.5 and a data rate of 100 kHz. The filtered signals are used to generate the output frequency control.

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3.3 RF Transmitter, modulation process The Figure 38 shows the modulation process of the transmitter. In red color are the models, which have been developed in the context of this project. The components in green color were already developed [1]. As it is stated before, a model for the PA was not developed in this project. A PA model is not important to study the modulation properties of the chosen binary FSK transmitter as it primarily only amplifies the signal modulated by the PLL. So the transmitter was simulated without the PA. The architecture (called testbench) of the transmitter as illustrated by the Figure 38 contains instances of the models of: PFD, charge pump, loop filter, VCO, dual-modulus prescaler, programmable digital divider, Σ∆ modulator and bit stream modulator. Its aim is to test the interaction of overall the models in order to perform the modulation process. According to the nature of the VCO output, there are three models of the PLL.

• When the VCO output is a frequency signal, the PLL model is called “pll_sigma_delta_freq_tb”. It is the model used for simulation because it allows fast simulation.

• When the VCO output is a sine signal, the PLL model is called “pll_sigma_delta_sine_tb”.

• And when the VCO output is a digital signal, the PLL model is called “pll_sigma_delta_digi_tb”. It is not used in this project.

Figure 38: Transmitter (without the PA): “One-Point ” or “direct” modulation architecture

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3.3.1 Simulations The goal of the transmitter simulations is to study the influence of its parameters on its behavior and thus resulting transient and spectral properties of the RF output signals. Simulations also permit designers to find the correct and the limit configurations for which the system still works. Simulations of high-level models are always faster than the simulation of the transistor level models. Moreover, the adopted strategy in the modeling of the PLL is to simulate the system with the VCO output as instantaneous frequency value. This is to allow the system validation in reasonable time. The Σ∆ MASH order will be equal to two and three. The order one is not considered in our simulations because, the first order Σ∆ is not a MASH structure. MASH means Multi-stage Noise Shaping. So the Σ∆ MASH is designed first to shape the noise. This is not the case if its order is one.

3.3.1.1 Simulations with the VCO output as instanta neous frequency value

Table 13 shows the basic parameters of the transmitter.

Table 13: Basic configuration of the transmitter (m odulation process) Reference frequency 13 MHz

Carrier frequency 868.2 MHz

Kvco (VCO gain) 60 MHz/V

KPD (charge pump current) 50 uA

VCO out_put Instantaneous frequency

Ltank (tank inductor, VCO) 20 nH

Data rate 100 Kbits/sec

Modulation index 2

Cut-off frequency 50 kHz

Phase margin 65 °

Σ∆ order 3

Σ∆ resolution 10 bits

Pulse shaping method for bit stream Data stream with ramped pulse-shaping

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Figure 39: VCO modulation. Data are ramp shaped.

VCO output (green), data (blue), modulated frequenc y (orange)

Figure 40: Eye diagram of the VCO output

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Figure 41: VCO output (frequency signal) FFT

In the Figure 39, it can be observed that the VCO output follows the shape of the modulated frequency but with an overshoot. The Figure 40 shows the eye diagram of the modulation. The eye diagram opening is approximately equal to 200 kHz because modulation index is equal to 2, so ∆f is equal to 100 kHz. As the eye diagram is well open, the demodulation of the transmitted signal in base band will be possible and easy. Figure 41 shows us the “Fast Fourrier Transform” (FFT) of the VCO output, which corresponds to the theoretical result [4]. As the VCO outputs an instantaneous frequency, its FFT will be the same than the FFT of the signal in base band. Moreover, can be clearly observed the harmonics at the multiples of the data rate (D = 100 kHz). According to the choice of the cut-off frequency Freq_cut_off, the reference is the Nyquist criterion, which states that: Freq_cut_off >= D/2 [4] (D is the data rate). Below this frequency, the modulation of data is not assured due to appearing aliasing effects.

Table 14 lists the loop filter RC parameters calculated by its model to obtain the specified cut-off frequency of 50 Hz

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Table 14: Post simulation computation: dimension of Loop filter elements. C1, C2, C3, R2, R3 are shown in the Figure 8 (loop filter structure )

3.3.1.1.1 Cut-off frequency variation The first simulation task consists in the evaluation of the impact of the cut-off frequency on: the eye diagram, the spectral distribution and the shape of the VCO output. Only the cut-off frequency will change, the other configurations will stay the same. Table 15 gives the parameters of simulation:

Table 15: Transmitter (modulation process) configur ation while changing the cut-off frequency of the loop filter

Reference frequency 13 MHz







Modulation index 1 and 2

Cut-off frequency (Changing) 25 kHz, 50 kHz1 and 100 kHz

Phase margin 65 °

Σ∆ order 3



During simulation, dimensions of the loop filter elements are also calculated (Table 16).

1 F_cut_off >= D/2 according to the Nyquist criteria [4]

C1 100.6934 pF

C2 1.948063 nF

R2 7.370413 KΩ

C3 97.40316 pF

R3 7.370413 KΩ

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Table 16: Post simulation computation: dimensions o f Loop filter elements. C1, C2, C3, R2, R3 are shown in the Figure 8 (loop filter structure )

3.3.1.1.1.1 Eye diagram comparison

Figure 42: Eye diagram of the VCO output for freq_c ut_off = 25 kHz

Cut-off frequency [Hz] 25 e3 50 e3 100 e3

C1 [F] 4.027735 e-10 1.006934 e-10 2.517334 e-11

C2 [F] 7.792253 e-9 1.948063 e-9 4.870158 e-10

R2 [Ω] 3.685207 e3 7.370413 e3 1.474083 e4

C3 [F] 3.896127 e-10 9.740316 e-11 2.435079 e-11

R3 [Ω] 3.685207 e3 7.370413 e3 1.474083 e4

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It can be observed in Figure 42, Figure 43 and Figure 44 that, if the cut-off frequency of the PLL loop filter is below the half of the data rate (e.g. freq_cut_off < D/2), the eye diagram is more closed. This makes the demodulation impossible. If the cut-off frequency is at least equal to the half of the data rate value as it is required by the Nyquist criteria [4] (i.e. freq_cut_off >= D/2), the eye diagram is clearly open.

3.3.1.1.1.2 FFT comparison

Figure 45: VCO output FFT at 25 kHz (blue), 50 KHz (orange) and 100 kHz (green)

Figure 45 shows the result of an FFT of the VCO output for the cut-off frequencies 25 kHz, 50 kHz, and 100 kHz. Lower cut-off frequencies attenuate more the signal causing the demodulation to become more difficult, but also limiting the bandwidth consumed by the transmitted signal. The FFT is around 0 Hz as it was done on the instantaneous frequency output of the VCO. The Table 17 shows the characteristics of the spectrum.

Table 17: Spectrum characteristics

Parameter Value


Modulation index 2

Carrier frequency fC 868.2 MHz

Carrier frequency maximum deviation ∆f

100 kHz

Numbers of samples 8192 (213)

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3.3.1.1.1.3 Comparison of VCO output modulation

Figure 46: Modulation of VCO output at different cu t-off frequencies. 100 kHz (green), 50 kHz (orange), 25 kHz (pink)

Figure 46 shows that the VCO output has the more difficulties to follow the modulation for smaller cut-off frequencies of loop filter. This case is especially appeared for the cut-off frequency equal to 25 kHz. It is also noticed that even if the VCO modulation seems to be better for 100 kHz than for 50 kHz, Σ∆ noise is better filtered at 50 kHz than at 100 kHz.

3.3.1.1.2 Modulation index variation For the second simulation, the task is to change the modulation index; firstly it’s one and after it’s two. As the influence of the modulation index variation is the same for the three cut-off frequencies (25 kHz, 50 kHz, 100 kHz), it’s decided to show only the result for 100 kHz. Table 18 shows the simulation parameters.

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Table 18: Transmitter (modulation process) configur ation while changing the modulation index

3.3.1.1.2.1 Eye diagram comparison









Modulation index (changing) 1 and 2


Phase margin 65 °

Σ∆ order 3



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The modulation index has an impact on the variation (delta_freq, ∆f) of the frequency during the modulation (FSK) according to Equation 25. So if:

• The modulation index = 2, then ∆f = D = 100 kHz. It means that the VCO output frequency will vary about 100 kHz around the carrier frequency, which is equal to 862.2 MHz.

• The modulation index = 1, then ∆f = D/2 = 50 kHz. In this case the VCO output frequency will vary about 50 kHz around the carrier frequency.

The impact on the eye diagram is given above (Figure 47 and Figure 48). If the modulation index is equal to two, the eye diagram is more open than for the modulation index equal to one; for the first case (modulation index = 2), the eye diagram is equal to 200 kHz and for the second case (modulation index = 1) it is equal to 100 kHz.

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Figure 49: FFT of VCO output with modulation index = 2 at cut-off frequency=100 kHz

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Figure 50: FFT of VCO output with modulation index = 1 at cut-off frequency=100 kHz

According to spectral distribution in base band, Figure 49 and Figure 50 show no difference in the FFT result. This means that in base band, the variation of the modulation index has no influence on the spectrum of the VCO output frequency. This is due to the fact that even if the modulation index changes, the shape of the signal (VCO output) doesn’t change. So its spectrum will not change.

But there is a difference of 6 dB while considering the amplitude of the signal spectrum. This amplitude difference (amplitude_difference) when modulation index is equal to one and two is calculated as following: amplitude_difference = |20 log(2) – 20 log(1)| = |20 log(2)| = 6.02 dB. This difference can be observed in the Figure 49 and Figure 50, where

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• For the modulation index equal to one, amplitude (at 0 Hz), is about of 70 dB.

• For the modulation index equal to two, amplitude (at 0 Hz), is about of 76 dB.

So the difference of these amplitudes is: |76dB-70dB| = 6 dB.

3.3.1.1.3 Sigma delta order variation The objective of this section is to change the Σ∆ order and to visualize its influence on the system behavior. As for the previous simulations, the other transmitter configurations stay unchanged and it’s decided to work with 100 kHz as cut-off frequency.

Table 19: Transmitter (modulation process) configur ation while changing the Σ∆ order








Modulation index 2


Phase margin 65 °

Σ∆ order (changing) 2 and 3



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Figure 51: Eye diagram with Σ∆ order equal to 3 for cut-off frequency=100 kHz

Figure 52: Eye diagram with Σ∆ order equal to 2 for cut-off frequency=100 kHz

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Figure 53: FFT of the VCO output with Σ∆ order equal to 3 for cut-off frequency=100 kHz

Figure 54: FFT of the VCO output with Σ∆ order equal to 2 for cut-off frequency=100 kHz

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In changing the Σ∆ order, the eye diagram of the Σ∆ of order 3 shows much more noise than the eye diagram of the Σ∆ of order 2 (Figure 51 and Figure 52). In the case of order 3, noise is present primarily in higher frequencies and doesn’t disturb the opening of eye diagram. But if the order is equal to 2, there is some low-frequency noise disturbing the opening of the eye diagram. This is the expected effect of the Σ∆; if its order increases, more noise is introduced but also pushed to high frequency and they are filtered by the loop filter. Due to this behavior of the Σ∆ modulator, the presence of spurs in the spectrum of the modulated signal (VCO output) can be avoided.

The FFTs of the VCO output for different values of the Σ∆ modulator order (2 and 3) are shown in the Figure 53 and Figure 54. There is no visible difference in the spectral distributions because the Σ∆ shifts the noise to high frequencies, which is filtered out by the loop filter.

3.3.1.1.4 Effect of pulse-shaping the bit stream This part of simulation focuses on the shape of data in order to see their impact on the VCO output spectral distribution and VCO output overshoots. The parameters of the simulation are given the Table 20.

Table 20: Configuration of the transmitter (modulat ion process) for the simulation when the VCO output is modulated by rectangular signals and signals with ramped pulse-

shaping







Data rate 100 kbits/sec

Modulation index 2


Phase margin 65 °

Σ∆ order 3


Pulse shaping method for bit stream -Rectangular data stream -Data stream with ramped pulse-shaping -Data stream with raised cosine pulse-shaping

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Figure 55: FFT of VCO output when modulated with re ctangular (green) signals, signals with ramped pulse-shaping (orange) and signals with raised cosine pulse-shaping (blue)

According the spectral distribution of the VCO output (Figure 55), it can be noticed that if the data stream is rectangular shaped, the spectrum of the VCO output is larger (more harmonics) than if data stream is ramp shaped or filtered by the raised cosine filter (less harmonics). This is due to the fact that the pulse-shaping of the bit stream is filtering the high frequencies (sudden variations) of the discrete data. So its spectrum will be less wide (with less harmonics) than in the case of an unshaped bit stream. It is also important to see that the pulse-shaping performed by the raised cosine filter is better than the ramped pulse-shaping because the spectral distribution of the signal in case of ramped pulse-shaping is wider than the spectral distribution of the signal in case of raised cosine filtering.

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3.3.1.1.4.2 Comparison of VCO output modulation

Figure 56: VCO output when modulated with rectangul ar (green) signals, signals with ramped pulse-shaping (orange) and signals with rais ed cosine pulse-shaping (blue)

The Figure 56 shows the signals f_vco_out_rectangular (green) , f_vco_out_ramp (orange) and f_vco_out_raised_cosine (blue), which are the VCO outputs when modulated, respectively, with unshaped signals (rectangular shaped), signal with ramped and raised cosine pulse-shaping. It can be noticed that the overshoot of the VCO output frequency is more important, if it is modulated by rectangular shaped signals. That is why a pulse-shaping is important in order to attenuate sudden variations of the frequency due to rectangular shaped signals. On the Figure 56, it can be observed that the delay of the VCO output is more important in the case of raised cosine filtering than for ramped pulse-shaping. This is due to the fact that the raised cosine filter is more elaborated than the ramped pulse-shaping (filter). But this delay (in case of raised cosine filter) will not damage the quality of modulation because it is not too big. Considering the VCO output frequency overshoot, which is less important in the case of bit stream filtered by the raised cosine filter than for ramp shaped bit stream, it can be concluded that the raised cosine filter is better than the ramped pulse-shaping in the modulation process.

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3.3.1.2 Simulations with transient sinusoidal VCO o utput The objective of this simulation is to visualize the FFT of the VCO output, which must correspond to the FFT expected from theory. This is to validate the transmitter. The disadvantage of this simulation is the fact that it generates many sampling points, which slow down the simulation. Table 21 summarizes the chosen model parameters.

3.3.1.2.1 Modulation index variation

Table 21: Configuration of the transmitter (modulat ion process) for the simulation when the VCO output is a transient sinusoidal while chan ging the modulation index

Reference frequency 13 MHz Carrier frequency 868.2 MHz Kvco (VCO gain) 60 MHz/V KPD (charge pump current) 50 uA VCO out_put Transient sinusoidal Ltank (tank inductor, VCO) 20 nH Data rate 100 Kbits/sec Modulation index 2, 1 and 0.5 Cut-off frequency 100 kHz Phase margin 65 ° Σ∆ order 3 Σ∆ resolution 10bits Pulse shaping method for bit stream Data stream with ramped pulse-shaping

Figure 57: FFT of VCO output, which is a transient sinusoidal for modulation index equal to 2

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Figure 58: FFT of VCO output, which is a transient sinusoidal for modulation index equal to 1

Figure 59: FFT of VCO output, which is a transient sinusoidal for modulation index equal

to 0.5

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Figure 60: FFT of VCO output, which is a transient sinusoidal for modulation index equal

to 0.25 Figure 57 and Figure 58 show the VCO output FFT for the modulation index is respectively equal to 2 and 1. It can be observed harmonics around the carrier frequency, which are exactly at carrier frequency ± frequency deviation.

• If the modulation index is one, then ∆f = 50 kHz and harmonics are at 868.25 MHz and 868.15 MHz as it is shown in Figure 57.

• If the modulation index is two, then ∆f = 100 kHz and harmonics are at 868.3 MHz and 868.1 MHz (Figure 58). There are also others harmonics at multiples of 100 kHz around 868.2 MHz.

Figure 59 shows the VCO output FFT for the modulation index is equal to 0.5. As harmonics around the carrier frequency are too closed, they are not visible. For this case (Figure 59), the demodulation is very difficult to perform. Those results (Figure 57, Figure 58 and Figure 59) correspond to the theory [20]. If the modulation index changes, the spectrum of the VCO output (sinusoidal function) changes also. The lower is the modulation index, closed are the harmonics around the carrier frequency and difficult will be the demodulation. Generally, it is required to have a modulation index equal to 2 for a good demodulation process. The minimum value of the modulation index is limited to 1/4. [20]

3.3.1.2.2 Sigma delta order variation Table 22 gives the transmitter configuration while changing the MASH order. In this case, the different FFTs of the VCO output for the two different MASH orders (two and three) will be compared.

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Table 22: Configuration of the transmitter (modulat ion process) for the simulation when

the VCO output is a transient sinusoidal while chan ging the MASH order Reference frequency 13 MHz Carrier frequency 868.2 MHz Kvco (VCO gain) 60 MHz/V KPD (charge pump current) 50 uA VCO out_put Transient sinusoidal Ltank (tank inductor, VCO) 20 nH Data rate 100 Kbits/sec Modulation index 2 Cut-off frequency 100 kHz Phase margin 65 ° Σ∆ order 2 and 3 Σ∆ resolution 10bits Pulse shaping method for bit stream Data stream with ramped pulse-shaping

Figure 61: FFTs of VCO output with MASH order equal to 2 (green) and MASH order equal

to 3 (orange) Figure 61 shows FFTs of VCO output while changing the MASH order. Normally the difference between the MASH order two and three is the fact that the MASH order three introduces less spurs in the spectrum of VCO output than the MASH order three. But the difference seen in the Figure 61 is probably due to the artifact of the FFT calculation.

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3.3.1.2.3 Faster version of simulation model of a PLL with tr ansient sinusoidal VCO output: “ pll_sigma_delta_sine_faster_version_tb”

In order to decrease simulation time of a PLL model with transient sinusoidal VCO output, an additional model of PLL is designed. As shown in the Figure 62, this model makes use of a PLL with frequency VCO output, which will be reduced by a constant factor and converted to transient sinusoidal. Comparing with a transient sinusoidal signal, which frequency is equal to the VCO output frequency, the generated transient sinusoidal signal of this new PLL model (which frequency is lower than the VCO output frequency) will be simulated in a reasonable short time.

Figure 62: Faster version of the PLL model with tra nsient sinusoidal VCO output

Figure 63: Frequency VCO output (modulated, orange) and its reduced version (green)

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Figure 64: Transient sinusoidal signal which freque ncy is modulated around 14 MHz

Figure 65: VCO output FFT around 14 MHz

Error! Reference source not found. shows the frequency VCO output (f_VCO_out_high_frequency, orange), which is reduced to 14 MHz. The resultant signal (f_VCO_out_low_frequency, green) of this division is converted into transient sinusoidal signal (Error! Reference source not found. ). This new PLL model is the most interesting because it allows to obtain, in a reasonable time and with only one simulation, the characteristics of VCO output in base band (FFT in base band and eye diagram) and in high frequency (FFT in high frequency). The gain of simulation time is given in the Table 24 (section 3.4).

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3.4 Summary In the chapter 3, blocks of the transmitter modulation part were presented. The chapter focused on the modeling of the dual/multi-modulus divider prescaler, programmable digital divider, Σ∆ modulator and bit stream modulator, which simulation results have been discussed. Thereafter the whole transmitter was simulated. It can be concluded that the quality of modulation is determined by parameters such as: the cut-off frequency of the loop filter, the modulation index, the Σ∆ order and the shaping of the bit stream. The simulation allowed to optimize the component parameters listed in Table 23 to achieve the specified 100 Kbits/sec data rate over a channel at 868.2 MHz.

Table 23: Configuration of the transmitter (modulat ion process) for a good functioning Reference frequency 13 MHz Carrier frequency 868.2 MHz Kvco (VCO gain) 60 MHz/V KPD (charge pump current) 50 uA VCO out_put Instantaneous frequency Ltank (tank inductor, VCO) 20 nH Data rate 100 Kbits/sec Modulation index 2 Cut-off frequency 50 kHz and 100 kHz Phase margin 65 ° Σ∆ order 3 Σ∆ resolution 10 bits Pulse shaping method for bit stream Raised cosine filter

Considering the “NUMTTP”, which is the number of steps accepted by the simulator and sent to the binary output file, and the “CPU time”, which is the effective time consuming by the CPU to perform the simulation [29]. Table 24 presents the model simulation statistics. The advantage of a CPU time reduced by a factor of at least 20 for the fractional Σ∆ PLL model using a VCO model, which directly outputs a frequency rather than a transient sinusoidal waveform, is considerable. Comparing with the fractional Σ∆ PLL, which transient sinusoidal VCO output is not previously divided, the fractional Σ∆ PLL which transient sinusoidal VCO output is previously divided by a constant factor allows very short simulation time.

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The high-level VHDL-AMS models simulate also much faster than a full transistor-level model, of which only estimated simulation time exits form comparable PLL project without a Σ∆ and a bit stream modulator.

Table 24: Model simulation statistics

PLL models Type of model

Simulated time

Simulator accuracy (EPS)

CPU Time NUMTTP Computation resources Simulation date

10-7 6mn 16s 650ms 2’443’682 8-Jan-2009

Σ∆ fractional PLL which VCO outputs frequency (pll_sigma_delta_freq_tb)

High-level model (VHDL-AMS)

4 ms

10-8 7mn 19s 320ms

3’355’060

immsunsrv1 (Linux 2.6.9-78.0.8.ELsmp)

04-Feb-2009

10-7 3h 45mn 49s 220ms

69’668’087 14-Jan-2009

Σ∆ fractional PLL which VCO outputs transient sinusoidal (pll_sigma_delta_sine_tb)


4 ms

10-8 8h 49mn 50s 500ms 166’968’960

immsunsrv1 (Linux 2.6.9-78.0.8.ELsmp)

02-Feb-2009

Σ∆ fractional PLL which VCO outputs transient sinusoidal (pll_sigma_delta_sine_fast_version_tb) (F_VCO is divided by 100)


4 ms 10-8 8mn 35s 310 ms

3’055’219 immsunsrv1 (Linux 2.6.9-78.0.8.ELsmp)

04-Feb-2009

PLL without Σ∆ and bit stream modulator (fixed division factor, 800 MHz VCO)

Transistor level 10 us 10-8 ~1 day N/A

Intel(R) Core(TM)2 CPU 6700 @ 2.66GHz

N/A

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Chapter 4 Conclusion and Outlook During this master project, an RF transmitter based on binary FSK was modeled in VHDL-AMS and the focus was put on the modulation process, which is performed (in the context of this project) directly by the Σ∆ fractional PLL. This kind of modulation is called “one-point modulation“. This work was also the opportunity to realize how important are the PLL techniques in telecommunication field. Σ∆ fractional PLL has the following components: The Phase Frequency Detector (PFD), the Charge Pump (CP), the Loop Filter (LP), the multi-modulus divider, the programmable digital divider, and the Σ∆ MASH modulator. Just the multi-modulus divider, the programmable digital divider and the Σ∆ MASH modulator models were designed in this project because the PFD, CP, LP, and VCO were already developed previously [1].

It is important to recall the modulation process, which consists first on frequency synthesis performed by the PLL, and the modulation of the synthesized frequency by the Σ∆ modulator, which is also modulated by an additional component called “bit stream modulator”. The bit stream modulator modulates the Σ∆ modulator according to the following parameters:

• The data rate, which represents the number of symbols to send or to receive per second.

• The carrier frequency, which determines the channel of transmission. • The modulation index, which determines the maximum variation of the

carrier frequency.

The main objective was to develop a high-level simulation model of RF transmitter, which allows fast simulation for system validation in reasonable time. According to this objective, some design approaches were chosen.

• The VCO outputs a frequency signal in order to generate less sampling points during simulation and to avoid slow down the simulation.

• The Σ∆ architecture is implemented as an “RTL” architecture. So according to the chosen MASH order, just the concerning part of the Σ∆ will be generated and operated.

Models were designed according to the requirements of the ModelLib library, which are flexibility and reusability. [15] A particular effort focused on the implementation of elaborated test benches. They provide processes, which facilitate post processing calculations (e.g. calculation of the output signal period after division process, in order to validate the division). The objectives of fast simulation, flexibility and, reusability of models have been reached.

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Therefore, the whole transmitter, which defines the interaction of the modeled components according to the Figure 38, was simulated. The simulations allow to find out the system configuration, which ensures good operation. They were realized while changing the main transmitter parameters, which are: the cut-off frequency, the modulation index, the MASH order and the effect of pulse-shaping the data signal. Finally, data-sheets of modeled components were created according to the ModelLib methodology (see Appendix).

According to future needs, the presented models could further extended to treat certain component effects, such as the power consumption, in more detail. In addition, the algorithm of the control word generation must be completed in order to allow the programmable digital divider to control the multi-modulus divider with a control word, which allows division by more than two different ratios. A power amplifier (PA) must be designed in order to complete the transmitter architecture. Finally, it will be important to design the models of the receiver part. This will allow the designers to have a complete high-level RF transceiver simulation model, in order to facilitate their design tasks by ensuring fast simulations.

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Appendix A.1 ModelLib prototyping One of the most important requirement common to all transmitter component models is to be as parametrisable as possible to allow their reuse in other projects. This also requires a thorough documentation of each model including interfaces, architectures, and implementations. In the scope of the ModelLib project, a standardized way to document the model structure was developed and implemented in form of a web-based application implementing the basic features of a model library [15].

Figure 66: User interface of the ModelLib prototype [15]

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A.2 Model hierarchy of the binary FSK transmitter Figure 67 shows the dependencies between the component models making up the binary FSK transmitter. Blocks and sub-blocks are linked with the arrow.

Figure 67: Model hierarchy of the binary FSK transm itter

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A.3 Multi-modulus divider: “multi_modulus_divider_freq_digi” Description

The multi-modulus divider realizes the division of an instantaneous frequency signals. Its output is digital. According to the presc_ctrl value, the division ratio will take one of the values between PRESC_MIN and PRESC_MAX.

Parameters





PHI_LO_0 real 0.0 [DEG]

Initial phase of the output signal (conversion frequency to digital)




Ports




presc_ctrl digital std_logic_vector in Control word of the division ratio





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Architectures ideal and discrete

Description First there is a process, which allows to choose the correct ratio according to the value of the signal control called presc_ctrl. All the ratios are consecutives integer numbers. Ratios are stored in registers. The reset signal is asynchronous and active low and the enable is also asynchronous and active high. When the reset is low, the ratio register takes PRESC_MIN as value of ratio. This to ensure a division with a ratio, which is always greater or equal to PRESC_MIN. The enable has the effect of freezing the system when it is inactive. Then, with the selected ratio, the frequency division is realized. And at least the result of this division is converted into digital. Both of the architectures (ideal and discrete) have the same procedure. The difference between them is the fact that ideal architecture uses the ideal architecture of the frequency to digital signal converter model. And the discrete architecture uses the discrete architecture of that same model. File Name Design tool Description

multi_modulus_divider_freq_digi.vhd ADVance MS 2007.1 VHDL-AMS interface and architecture definition

Test bench: “multi_modulus_divider_freq_digi_tb”

Description In the test bench, the frequency input signal f_in is a constant real number. The presc_ctrl signal is generated asynchronously and synchronously with the output div_out. The user can choose one of the two configurations according to the needs of his experiments. For post processing and validation needs, a process is provided to compute the period of the output signal after simulation. This period is calculated as following: an auxiliary signal is generated and changes the value at each rising edge of the output signal. Then, the “last_event” attribute is used on that auxiliary signal, in order to calculate the time spending since the last event occurs on that signal. As events of the auxiliary signal, occur on every rising edge of the output, the calculated time is the period of the output signal. The test bench also provides the possibility to choose or to bypass the test of enable signal. In the case of testing enable effect, the time for active and the disabled enable signal can be chosen. It is the same for activating

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and disabling the reset signal; the active and disable times can be chosen. This is to make the model and its simulation as flexible as possible. The test bench has two configuration files according to ideal and discrete architecture of the model. Parameters





PHI_LO_0 real 0.0 [DEG]

Initial phase of the output signal (conversion frequency to digital)

SIMULATION_TIME time > 0 5e-3 [s] Simulation time

PRESC_CTRL_ASYNC_CHANGE time > 0 SIMULATION_TIME/10 [s] Time after which the presc_ctrl_async changes

RESET_START time > 0 SIMULATION_TIME*75/(10^6) [s] Time during which the reset is low

RESET_STOP time > 0 SIMULATION_TIME*125/(10^6) [s] Time during which the reset is high

ENABLE_START Time > 0 SIMULATION_TIME/2 [s] Time during which the enable is low

ENABLE_STOP Time > 0 SIMULATION_TIME*3/5 [s] Time during which the enable is high

ENABLE_TEST boolean false Activates the test of enable

ASYNCHRONOUS_PRESC_CONTROL boolean true Activates presc_ctrl synchronous generation

POWER_TB real > 0.9 0.90001 Supply voltage




File Name Design tool Description

multi_modulus_divider_freq_digi_tb.vhd ADVance MS 2007.1

VHDL-AMS interface and architecture definition

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A.4 Programmable digital divider: “divider_prog” Description The programmable divider is targeted for frequency divisions of digital signals.

Parameters











Ports




div_ratio digital std_logic_vector in Division ratio





Architecture ideal

Description When a ratio (div_ratio) is provided at the input of the model, it can be sampled or not according to the need of the design. Then the effective division ratio (div_ratio_effective) is calculated has following: If div_ratio is considered as an offset:

And if div_ratio is not considered as an offset:

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DIV_MIN is the minimum division ratio. A counter register (count_reg) is counting (at every rising edge of the input div_in) from zero to div_ratio_effective – 1 and after it is reset. At the rising edge of the input div_in and when the counter reach the value: div_ratio_effective/2 + div_ratio_effective_LSB (LSB of div_ratio_effective), then the output (div_out) is set to ‘1’. Otherwise div_out is equal to ‘0’. In this case, to ensure an output with the duty cycle of 50 %, div_out must be equal to ‘0’ at the falling edge of the input div_in and if count_reg is equal to div_ratio_effective / 2 + div_ratio_effective_LSB. The implementation provides a process to allow the start of the system, even if the effective ratio is zero. File Name Design tool Description

divider_prog.vhd ADVance MS 2007.1 VHDL-AMS interface and architecture definition

Test bench: “divider_prog _tb”

Description The division ratio is clocked by the output div_out. It is generated in two ways: consecutively or randomly using the “UNIFORM” function. For post processing and validation needs, a process is provided to compute the division ratio after simulation. An assertion verifies if the division has been done properly. The ratio is calculated as following: A counting is done at every rising edge of the input div_in. At every rising edges of the output div_out, the current number of the counter is extracted and reset the counter register. This extracted number gives us the ratio between the input and the output. The test bench also provides the possibility to choose or to bypass the test of the enable signal. In the case of testing the enable signal, the time of activate and disable the enable signal can be chosen. It is the same for activating and disabling the reset signal; the active and disable times can be chosen.

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Parameters








DIV_IN_PERIOD time > 0 0.5 e-6 [s] Input period

ENABLE_START time > 0 3000 [s] Time during which the enable is low

ENABLE_STOP time > 0 3500 [s] Time during which the enable is high

ENABLE_TEST boolean false Activates the test of enable

RANDOM_DIV_RATIO boolean true Activates random generation of the division ratio






divider_prog_tb.vhd ADVance MS 2007.1 VHDL-AMS interface and architecture definition

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A.5 Programmable divider with the prescaler control word: “divider_prog_presc_control”

Description For higher frequency applications, the combination of the prescaler [A.3] and the programmable divider [A.4] is required. The programmable divider receives at its input the signal generated by the prescaler and the division ratio of the prescaler is controlled by a control word generated by the programmable divider. The aim of this model is to generate this control word. So this model contains the programmable divider as sub program (block) and the logic process to generate the control word.

Parameters








EVEN_DUTY_CYCLE boolean true Set output duty cycle to 50 %




Ports





presc_ctrl digital std_logic_vector out Prescaler control word





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Architecture dual-modulus

Description The architecture contains the programmable divider instance and processes to generate the control word for the prescaler. The following equations have been used in order to calculate the maximum number for cycle division by PRESC_MAX.

• cycle_presc_min and cycle_presc_max are respectively the minimum and the maximum numbers of cycles during which the prescaler divide by PRESC_MIN and PRESC_MAX.

• div_p is the current division ratio of the programmable divider. • div_n is the global division ratio (of the programmable divider and the

prescaler).

As the ratio of the programmable divider is sampled within its model, the value of div_p and div_n used in these equations in order to generate the cycle_presc_max and cycle_presc_min values are also sampled in the model. In the architecture, there is a process, in which a counter register counts at every rising edges of the input div_in. While the counter value is smaller or equal to cycle_presc_max, the control word is set to one (presc_ctrl = 1) and while the counter value is greater than cycle_presc_max, the control word is set to zero (presc_ctrl = 0).

• presc _ctrl = 0 corresponds to the prescaler ratio = PRESC_MIN • presc _ctrl = 1 corresponds to the prescaler ratio = PRESC_MAX

File

Name Design tool Description

divider_prog_presc_control.vhd ADVance MS 2007.1 VHDL-AMS interface and architecture definition

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Test bench: “divider_prog_hf_presc_control_tb”

Description This test bench is modeled by taking into account the interaction of the following models:

• Programmable divider with the prescaler. • High frequency divider. This model will be discussed in the next

paragraph. • The Σ∆ MASH. It will also be discussed after.

The division ratio div_n is clocked by the output. It is generated in two ways: consecutively or randomly using the “UNIFORM” function. For the test, only the discrete architecture of the multi-modulus divider is considered, because it generates fewer samples, which make it faster than the ideal one. To avoid negative values of cycle_presc_max and cycle_presc_min, div_n has an offset, which is DIV_MIN, which must be greater than or equal to PRESC_MIN*(PRESC_MIN-1). For our simulation, PRESC_MIN is equal to 8 and PRESC_MAX is equal to 9. Below PRESC_MIN*(PRESC_MIN-1) (which is equal to 56) and considering the default values of PRESC_MAX (e.g. 9) and PRESC_MIN (e.g. 8), some values of div_n generate negative values of cycle_presc_max and cycle_presc_min.

A Boolean flag called SIGMA_DELTA allows to choose the division ratio div_n to be generated by the test bench process (consecutively or randomly) or the div_n to be generated by the Σ∆ model. The test bench provides a boolean flag named TEST_ENABLE, which allows to choose or to bypass the test of enable signal. In the case of testing the effect of enable signal, the time of active and disable enable signal can be chosen. The same for activating and disabling the reset signal. This is to make the model and its simulation as flexible as possible. A process is provided to compute the division ratio after simulation. This ratio is implemented using the same methodology than for the programmable divider model [A.4]. An assertion is made in order to verify if the division is done with the correct ratio. There are processes, which aim is to compute the average of the Σ∆ outputs numbers and to verify if the difference between this average and the excepted fractional division ratio (given by the frequency control, freq_ctrl) is smaller or equal to than the resolution of Σ∆ 1/2N (with the freq_ctrl size).

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Parameters








MASH_ORDER natural > 0 3 Σ∆ order

N_BITS_FREQ_CTRL positive > 0 17 Input register size of the control word of Σ∆

N_BITS_INTEG positive > 0 7 Integer register size of N_BITS_FREQ_CTRL

N_BITS_FRACT positive > 0 10 Fractional register size of N_BITS_FREQ_CTRL

N_BITS_SDA positive > 0 10 output register size of Σ∆

PHI_LO_0 real 0.0 [DEG] Initial phase of the output signal (conversion frequency to digital)

F_INPUT Real > 0 100 e3 [Hz] Input frequency

CLK_PERIOD time > 0 PRESC_MIN/F_INPUT [s] Minimum of prescaler period



TEST_ENABLE boolean false Activates the test of enable

SIGMA_DELTA boolean true Allows the Σ∆ output to be the input of divider

RANDOM_DIV_RATIO boolean true Activates random generation of the division ratio







divider_prog_hf_presc_control_tb.vhd ADVance MS 2007.1


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A.6 High frequency programmable divider: “divider_prog_hf_freq_digi” Description

This block contains the multi-modulus [A.3] and the programmable divider with the logic word [A.5] instances. It is targeted for higher frequency applications. It facilitates the refinement of a single programmable divider to an archietecture using a programmable divider with the dual/multi-modulus prescaler.

Parameters








PHI_LO_0 real 0.0 [DEG] Initial phase used in sub program (conversion frequency to digital)




Ports









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Architectures ideal and discrete

Description Architectures contain instances of the prescaler and the programmable divider and define their interconnection. File Name Design tool Description

divider_prog_hf_freq_digi.vhd ADVance MS 2007.1 VHDL_AMS interface and architecture definition

Test bench: “divider_prog_hf_presc_control_tb” Refer to test bench of Appendix [A.5].

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A.7 Sigma delta MASH: “sigma_delta_mash” Description The Σ∆ is targeted to modulate a given number freq_ctrl. The modulation depends on the MASH order. The Σ∆ output sda_out is the result of modulation of freq_ctrl.

• If the Σ∆ order is equal to one, sda_out is between freq_ctrl and freq_ctrl + 1

• If the Σ∆ order is equal to two, sda_out is between freq_ctrl – 1 and freq_ctrl + 1

• If the Σ∆ order is equal to three, sda_out is between freq_ctrl – 3 and freq_ctrl + 4

Parameters


N_BITS_FREQ_CTRL positive > 0 20 Input register size

N_BITS_INTEG positive > 0 7 Register size of the input integer part

N_BITS_FRACT positive > 0 13 Register size of the input fractional part

N_BITS_SDA positive > 0 7 Output register size

MASH_ORDER positive [1 … 3] 3 Σ∆ MASH order


Ports


freq_ctrl digital std_logic_vector in Frequency control word signal

clk digital std_logic in Clock signal

sda_out digital std_logic_vector out Output signal



Architecture RTL

Description The addition and synchronization blocks of the Σ∆ are first implemented. As the structure of the Σ∆ contains three times these blocks, the “for generate” construct is used to generate it one, two or three times according to the chosen Σ∆ order.

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Overflows generated by these blocks are thereafter transmitted to the remaining part of the Σ∆ architecture in order to get sampled, added, subtracted or multiplied by two according to the MASH structure. File Name Design tool Description

sigma_delta_mash.vhd ADVance MS 2007.1 VHDL_AMS interface and architecture definition

Test bench: “ sigma_delta_mash_tb ”

Description To verify the newly developed parametrisable MASH model, the already verified Σ∆ third order MASH of the CSEM could be used. The test bench instantiates therefore both models, “sigma_delta_mash” (newly developed) and “sigma_delta_top” (already developed at the CSEM), simulates them with the same signals and verifies using assertions that the behavior is the same. A process is provided to detect and to calculate the Σ∆ periodicity. This periodicity is detected by monitoring the register values (fract_1_reg, fract_2_reg, fract_3_reg) in addition and synchronization block of the Σ∆ (see the MASH structure). When fract_1_reg, fract_2_reg, fract_3_reg are equal to zero, then the Σ∆ returns to its initial state and its periodicity is reached. The test bench also allows to choose or to bypass the test of enable signal. In the case of testing enable effect, the time of active and disable the enable signal can be chosen. It’s the same for activating and disabling the reset signal.

Parameters


MASH_ORDER natural > 0 3 Σ∆ order

N_BITS_FREQ_CTRL positive > 0 17 Input register size of the control word of Σ∆

N_BITS_INTEG positive > 0 7 Integer register size of N_BITS_FREQ_CTRL

N_BITS_FRACT positive > 0 10 Fractional register size of N_BITS_FREQ_CTRL

N_BITS_SDA positive > 0 10 output register size of Σ∆

CLK_PERIOD time > 0 1e-6 [s] Minimum of prescaler period



TEST_ENABLE boolean false Activates the test of enable


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sigma_delta_mash_tb.vhd ADVance MS 2007.1 VHDL-AMS interface and architecture definition

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A.8 Bit stream modulator: “bit_stream_modulator” Description It has two architectures: the first one (discrete architecture) is designed to modulate frequency with rectangular shaped data and the second (ramp architecture) modulates frequency with ramp shaped data. Parameters Name Type Range Default Unit Description









N_BITS_FREQ_FRACT positive > 0 13 Register size of the Frequency control fractional part

DEBUG boolean False Debug interface

Ports


data_in digital std_logic in Input data

freq_carrier digital real in Carrier frequency

delta_freq digital real in Frequency deviation

clock_bit_stream_sampling digital std_logic in Sampling clock of the bit stream

clock_ramp_data_sampling digital std_logic in Sampling clock of ramp shaped data

clock_impulse_response_sampling digital std_logic in Sampling clock of the raised cosine filter impulse response

clock_convolution digital std_logic in Sampling of the convolution process

freq_ctrl_out digital std_logic_vector out Output frequency word signal

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Architectures discrete and ramp

Description The architectures discrete, ramp and raised_cosine implement the following equations:

FREF is the reference frequency of the PLL generated by a crystal oscillator. freq_ctrl_integ and freq_ctrl_frac are respectively the integer and the fractional part of the frequency control freq_ctrl. They are calculated by the following equations:

N is the number of bits of the fractional part of the Σ∆. It represents the Σ∆ resolution. In the ramp architecture, an intermediate representation of bit stream is created to perform simple pulse-shaping using the “’ramp” attribute. Then, for transmitting this analog data to the Σ∆, a sampling is required. According to the raised_cosine architecture, an additional equation is implemented in order to obtain the filter impulse response (p(t)), which is sampled in order to get the coefficients of the filter. Therefore the filtered signals (data) are the convolution result between the filter coefficients and the bit stream.

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The f1 parameter and the bandwidth W are linked to the rolloff factor α according to this Equation:

The rolloff factor α is the excess use of the bandwidth according to ideal solution. Tb is the symbol time and D the data rate.


bit_stream_modulator.vhd ADVance MS 2007.1

VHDL_AMS interface and architecture definition

Test bench: “bit_stream_modulator_tb” Description

The test bench for the bit stream modulator generates the necessary input signals to control the bit stream modulator: carrier frequency (fC), maximum deviation of the carrier frequency (∆f), a (optionally pseudo-random) test data stream, and the clock used to sample the data stream or the intermediate pulse-shaped signal. For random generation of data, the function “UNIFORM” is used.

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Parameters





INDEX_MODULATION real > 0 2 Modulation index




N_OVER_SAMPLING real > 0 10 Number of bit stream samples


N_RAMP_SAMPLE positive > 0 2 Sampling resolution of ramp shaped data


N_BITS_FREQ_FRACT positive > 0 13

Register size of the Frequency control fractional part

PERIOD_CLK_BIT_STREAM time > 0 1/DATA_RATE [s] Bit stream period

T_FILTER time > 0 3/DATA_RATE [s]

Duration of the raised cosine filter impulse response (one side of Y axis)

PERIOD_CLK_FILTER_SAMPLING time > 0 T_FILTER*2/(N_COEFF_FILTER-1) [s] Bit stream period

PERIOD_CLK_RAMP_DATA_SAMPLING time > 0 T_RISE/(2^N_RAMP_SAMPLE) [s] Period of sampling clock

RANDOM_DATA_IN boolean true Activates random generation of data


File

Name Design tool Description

bit_stream_modulator_tb.vhd ADVance MS 2007.1


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