Memory OrganizationMemory Organization

Basic System Memory Architecture View (Functional)

[FFFE]=27h

FFFE: 27Notation:

Basic Characteristics (1/3)Basic Characteristics (1/3) 

• Memory cell registers are one byte wideMemory cell registers are one byte wide

• Memory Word is the contents of the cell, usually in hex notationusually in hex notation.

• Data wider than one byte uses two or more llmemory cells.

• Reading or writing memory words is done through the Data Bus

Basic Characteristics (2/3)Basic Characteristics  (2/3) 

• Each memory cell is identified by an addressEach memory cell is identified by an address– The address is independent from contents!

– The CPU can read/write  the memory cell only if the Address Bus has the address of the cell

– The address of the cell is a physical address

i i di h f ll– Notation: To indicate the contents of a memory cell we write [addr] = contents  (for ex: [0200h] = 8Ah)

– Unless indicated otherwise, hex notation is used (Unless indicated otherwise, hex notation is used ( [0200]=8A )

• Memory segment: A set of memory cells with contiguous addresses.

Basic Characteristics (3/3)Basic Characteristics (3/3)

• The Control Bus carries signals that are usedThe Control Bus carries signals that are used to indicate what type of transactions are done with memory if transaction is done withwith memory, if transaction is done with memory  and so on

Memory Types (1/3)Classification

• Classified according toClassified according to– Storage permanence: how long data is maintained

Write ability: data can be written at normal– Write ability: data can be written at normal running voltage and speed conditions

• Storage permanence classes:• Storage permanence classes:– Volatile memory: looses its contents when power is removedis removed

– Non‐volatile memory: does not loose its contents when power is removedwhen power is removed

Memory Types (2/3):Volatility

• Non‐volatile Examples:Non volatile Examples:– ROM structures: ROM, OPROM, EPROM, EEPROM

Ferro Electric RAM (FRAM FeRAM)– Ferro Electric RAM (FRAM, FeRAM)

– Flash Memory

V l til E l• Volatile Examples– Static RAM (SRAM)

– Dynamic RAM (DRAM)

• Popular non‐volatile in MCU: Flash, FRAM

Memory Types (3/3):Write ability

• Non‐writable Examples:Non writable Examples:– ROM structures: ROM, OPROM, EPROM, EEPROM

Flash– Flash

• Writable Examples( )– Static RAM (SRAM)

– Dynamic RAM (DRAM)

– FRAM

• FRAM memory has both non‐volatility and write‐ability

Comments on memoryComments on memory

• RAM (Random Access Memory) is usually used as aRAM (Random Access Memory) is usually used as a generic term to refer to writable and volatilememory

• The term ROM (Read Only Memory) is used as a generic term to refer to non‐writable and non‐volatile memory independently of the truthness

• Modern non‐writable memory is in fact writable, but d ff l d ll dat different voltages generated internally, and at 

slower speeds

More memory concepts: Physical and Data address. (1)

• Unless otherwise noted, memory words will be one‐Unless otherwise noted, memory words will be onebyte size.

• Physical Address:  Address of a memory celly y

• Data size dictates how many memory words are required:q

– 1 to 8 bits:  1 memory word

– 9 to 16 bits: 2 memory wordsy

• Data is stored in contiguous memory  cells.

• DATA Address: The lowest physical address of theDATA Address:  The lowest physical address of the cells occupied by data.

More memory concepts: Physical and Data address. (2)

• DATA Address:  The lowest physical address of the cells p yoccupied by data.– Example 1:  For  data address  0F208  for  456F,  physical addresses are 

0F208 and 0F2090F208 and 0F209.   

– Example  2: For  data address  0F208  for  456FA2B1,  physical addresses are 0F208, 0F209, 0F20A, and 0F20B

N t ti I di d fi ll t ti ll• Notation: In diagrams and figures, as well as notation, cells may be shown in byte, word, double word sizes. Examples:– 0F208: 2A     or   [F208] = 2A

– 0F208:   2AB9 or    [F208] = 2AB9

– 0F208:   2F1A40CD   or   [F208] = 2F1A40CD

Little endian vs. big endian (1)Little endian vs. big endian (1)

• Little endian: The dataLittle endian: The data address points to the least significant byte of data (i.e., LSB in lowest physical address)

• Big endian: The data address points to the most significant byte ofmost significant byte of data (i.e., MSB in lowest physical address)

[4300]=342B Little endian: [4300]= 2B, [4301]= 34physical address)

Big endian: [4300]= 34, [4301]= 2B

IAR Memory Window (1)IAR Memory Window (1)

To open Memory Windowo ope e o y do

Memory Window

IAR Memory Window (2)IAR Memory Window (2)

T i ifiMemorymenu

Use memory menu to select viewsbyte (1x)

d (2 )To examine specificAddress Zone

menu word (2x)double word (4x)--------- Little Endian or Big Endian

Sixteen bytes per rowASCII value when

Address of firstbyte in row(In HEX)

present

IAR Memory Window (2)(word and double word views)

Word view (Little endian)

Double word view (Little endian)

Program and Data memory

• Data memory is used for storing variables andData memory is used for storing variables and data expected to change during program executionexecution.

• Program memory is used to store  system programs and data that will not change duringprograms and data that will not change during program execution and should not be lost when power is removedwhen power is removed

Von Neumann and Harvard architectures

• Von Neumann (Princeton) architecture: Program and dataVon Neumann (Princeton) architecture: Program and data Memories share the system buses– Example: MSP430, 68HC11, Intel 80x86/Pentium

• Harvard Architecture: Program and data storage have different memory spaces, different buses.– Example: PIC MCU, Intel 8051, AtmelExample: PIC MCU, Intel 8051, Atmel  

Memory MapMemory MapMemory Map: model representation of the usage given to the addressable space

Example: A global Map

Memory Map (2)Memory Map (2)Example of a partial map:

MEMORY INTERFACECPU and Memory Hardware connection

MEMORY INTERFACE

Basic considerationsBasic considerations

• Hardware wise, the memory is distributed in banks.Hardware wise, the memory is distributed in banks.– Usually, these banks constitute a set of byte‐registers (virtually or actually)

– The outputs of these registers are connected via internal buses to the Data Bus.

The selection of a particular register is done through– The selection of a particular register is done through terminals connected to the address bus.

• Interfacing consists in connecting the banks to theInterfacing consists in connecting the banks to the Data, Address and Control buses so that transactions can be made by the CPU

Basic Functional description of a bank

word 2^(n 1)A(n 1)

InternalAddressDecoder ng Q7word 2^(n‐1)A(n-1)

A(n-2) word 2^(n‐2)

Decoder

Y(2n-2)

rite

Rou

tin

QQ6Q5Q4Q3-----

A0 Word  0Y0

---------

Rea

d/ w

r Q3Q2Q1Q0

CS Write Read

Example: ATMEL AT28C256( b )32KB  (256 Kbits) EEPROM

htt // t l /I /d 0006 dfhttp://www.atmel.com/Images/doc0006.pdf

Pin Name  Function

A0 ‐ A14  Addresses

CE Chip EnableCE  Chip Enable

OE  Output Enable

WE  Write Enable

I/O0 I/O7 Data Inputs/OutputsI/O0 ‐ I/O7  Data Inputs/Outputs

NC  No Connect

DC  Don’t Connect

Extract from Data sheet (1)Block Diagram

Extract from Data sheet (2)Operating Modes

Interface Principles for 8‐bit  Data bus  systems

• The eight IO outputs of each bank are connected toThe eight IO outputs of each bank are connected to the Data Bus in the ordered sequence– IO0 with D0, IO1 to D1, etc.

• For each bank the Address bus bits, are divided in two disjoint subsets:– One subset directed toward the selection of internal registers

One s bset in charge of acti ating the bank sing an– One subset in charge of activating the bank  using an address decoder for the bank

Basics of memory interfacingBasics of memory interfacing

ADDRESS BUS N>M BITS

Memory Chip

A0 IO 0A0 IO 0A1 IO 1.. ....

DATA BUS

M bitsfrom Address

.. IO 7

..A(M-1)

AddressBus

A(M-1)

CEAddress

N-M bits fromAddress Bus

DecoderSignals fromControl Bus

Basic Analysis ProcedureBasic Analysis Procedure

• Determine the combination of address bus bits thatDetermine the combination of address bus bits that activates the bank. – This set is fixed for all addresses in the space covered by the bank.

• Vary the  set of Address Bus Bits that determine the b k’ l dd f fbank’s internal address from  from 00..0 to 11…1 to establish the set of addresses

If this set is a least significant group then the bank covers– If this set is a least significant group, then the bank covers a segment

• Do this for each bank. The set of banks may or mayDo this for each bank. The set of banks may or may not define a segment.

Analysis Examples on Blackboard.Analysis Examples on Blackboard.

Basic design Procedure (Data bus 8‐bits) (1/2)

• Specify an appropriate segment or set of addressesSpecify an appropriate segment or set of addresses to be covered by the bank

• Select the set of Address Bus Bits that will determine the bank’s internal address as they change from 00..0 to 11…1– Usually,  this set is the least significant group, 

• If there are many banks involved, select the group of bits that will discriminate among banks

• The rest of the bits are used to activate the whole set f b kof banks.

Basic design Procedure /(Data bus 8‐bits) (1/2)

• An alternative and easy procedure is tu useAn alternative and easy procedure is tu use programmable PLA or ROM’s  as address decoders for banksdecoders for banks

Design examples on blackboardDesign examples on blackboard

Interface Principles for 16‐bit  Data bus  systems

• Two banks are needed to connect to the 16 bits of bus. They ywork by pairs

• One bank is connected to least significant byte, the other to th t i ifi t b tthe most significant byte– A) IO0 with D0, IO1 to D1, … IO7 to D7.

– B) IO0  with D8, IO1 to D9 …. IO7 to D15

– Which one goes to the LSB will determine little or big endianess.

• One bank of the pair works with even addresses (AD. Bus A0=0) and the other with odd addresses (A0=1)A0=0) and the other with odd addresses (A0=1)

• The control bus has a signal the indicates if we work with a bank only (byte operation) or with the pair (word operation)

Memory Interfacing (Data bus width 16 bits)

Note: This is a little endian scheme

IO 0A0US:

1 D

15 –

D8

D7

–D

0

IO 0A0US:

1

Low Bank(Even address)

High Bank(Odd address)

IO 0**

IO 7

A0**

A(K-1)

AD

DR

. BA

K …

A1

ta b

us:

D

ata

bus:

DIO 0

**

IO 7

A0**

A(K-1)

AD

DR

. BA

K …

A1

CE Dat Da

CE

(A0 = 0)(A0=1)

ADDR. Bus A0

Control BusSignalsADDRESS

ADDR. Bus A(N-1)… A(K+1)

ADDRESS DECODER

Basic Principles for 16 bit Data bus(explained with 2KB banks)

Internal Addresses established with AD. Busbits A11 A10 … A2 A1

Address Decoder

7FF7FE********

7FF7FE********

123FE123FC**************

123FF123FD**************

Operation:

1. If byte data andA0 = 0 activate even****

001000

****001000

*******0240202400

*******0240302401

A0 = 0, activate evenaddress bank only.

2. If byte data andA0 = 1 activate oddA0 = 1, activate oddaddress bank only.

3. If word data, activate both banks

Even addressOdd address

Addresses seen by systemactivate both banks

Note: Connection to data bus determines endianness

An example : discriminating among b kbanks in one pair

Use the previous criteria, adding an active low signal Y’ to select the system: Y’ is low, the banks are used and selected according to criteria. If Y’= 1, theM d l b bl dModules cannot be enabled.

Inputs to the system: A0, Y’ and W/B’ (1 if word, 0 if byte)Outputs: OddEn’, EvenEn ‘–both active low

Y’ W/B’ A0 OddEnn’ EvenEn’ 0 0 0 1 00 0 1 0 10 1 0 0 00 1 1 0 01 X X 1 11 X X 1 1

BWAYOddEn '/0'' +=

BWAYEvenEn /0'+=Note: Y’ is controlled by other addressbus bits and/or control bus bits

And for several pairs….And for several pairs….

Y0’ and Y1’ may be, for example, outputs of an active low decoder…..

EXAMPLES ON BLACKBOARDEXAMPLES ON BLACKBOARD

IO SubsystemIO Subsystem

IV Ports and peripherals

IO Subsystem (1)IO Subsystem (1)

• All devices connected to the system busesAll  devices connected to the system buses, other than memory and CPU– Input and output ports (I/O): interface CPU with– Input and output ports (I/O): interface CPU with external world directly

• Input portInput port

• Output port

• Input/Output  port

– Peripherals:  May be only internal to system or may have also external connection

IO Subsystem (2)IO Subsystem (2)

• Input transaction: Information toward CPUInput transaction: Information toward CPU

• Output transaction: Information from CPU

( h i ) i h l• Important (not exhaustive)  peripherals:– Timers: Uses such as measuring time intervals bbetween two events,  generate interrupts at specified and many others.

W t hd Ti (WDT) S f t d i d/– Watchdog Timer (WDT): Safety device and/or timer

ADC and DAC: to deal with analog inputs/outputs– ADC and DAC: to deal with analog inputs/outputs. 

IO Structure

• Data Registers:– Input and Output

• Control Registers:/– Used for  I/O and 

peripheral configuration

• Status registers:• Status registers:– Show information about information transfer or configuration status

• Control registers may contain status bits.

IO Mapped vs Memory MappedIO Mapped vs. Memory Mapped

IO Mapped IO Memory Mapped IOIO Mapped IO- Different sets of addresses- Different instructions for transfers

Memory Mapped IO- Same system of addresses- Same instructions for transfers

IO Mapped vs Memory Mapped (2)IO Mapped vs Memory Mapped (2)

• IO mapped I/O has different sets of addresses forIO mapped I/O has different sets of addresses for memory and for I/O subsystem– CPU distinguishes address with type of instruction

• Example: 8086 uses  MOV for transfers to/from memory,  OUT to transfer to Output  port, and IN from port.

– Routing of address bus is done by control bus according toRouting of address bus is done by control bus according to instruction.

• Memory mapped I/O does not distinguish between types– User must know memory map  (or “names”).

IO Ports: RemarksIO Ports: Remarks

• Input portInput port– Buffered: Readable only at a given moment

– Latched: Readable on demand

Must not be left floating– Must not be left floating

– Interruptible or non interruptiblep

• Output port– “Always” Latched

Important Remark for InputImportant Remark for Input  

Do not leave an input floating:

If necessary use pull up or pulldown resistors

Pulldown Resistor Pullup Resistor

Example: MSP430 General Purpose I/O ports

General Purpose I/O (8 bits)General Purpose I/O (8 bits)

• Named P0 to P10a ed 0 to 0– Number of ports and available bits depends on model– P1 and P2 have interrupt capability

• Bit independently programmable• Edge selectable interrupt capability• Some series have individually programmable pulldown/pull‐up resistors

• Depending on model, pins can be configured for special I/O

B7 B4 B3 B2 B1 B0B7 B4 B3 B2 B1 B0

Simplified Hardware configuration: bl1.  Non interruptible port

DataData Registers

C t lControl Registers

Basic I/O Registers (1/3)Basic I/O Registers  (1/3) 

• Function Selection Register (PxSEL): Selects the connection for the i ith t th t t th i h l( )pin, either to the port or to other peripheral(s)• 0: Connected to port (default)• 1: Connected to  other module(s)• To connect pin 1 2 to port (if necessary since it is connected by• To connect pin 1.2 to port (if necessary, since it is connected by 

default), clear bit 2 of (P1SEL) [bic.b #BIT2, &P1SEL]• To connect pin 1.2 to module ,  set bit 2 of (P1SEL) [bis.b #BIT2, 

&P1SEL]• Direction Register (PxDIR): Selects in or out direction function for 

pin– 1: Output direction

0 I t di ti (d f lt)– 0: Input direction (default)– Example:  mov.b #0xF0, &P1DIR  configures pins 4 to7 as outputs and 

0 to 3 as inputs

Basic I/O Registers (2/3)Basic I/O Registers (2/3)

• Output Register (PxOUT): to write signal toOutput Register (PxOUT): to write signal to output– To output the word 0x2A to port 2:p p

• (P2OUT) #2Ah       [mov.b #0x2A,&P2OUT]

• Input Register (PxIN):  Read only register– Example:  mov.b &P1IN, R6 transfers input to R6– Avoid writing to this register (power consumption and does nothing)

Multiple peripherals pins: (3/3)Multiple peripherals pins:  (3/3)

• Several Function Select Registers (PxSEL ySeveral Function Select Registers (PxSEL y PxSEL2 for 2xx family):  For example , in ‘2xx family– PxSEL ‐‐ PxSEL2:

• 00:   I/O  pin• 01:   Primary peripheral module• 10:  Reserved (device specific)• 11: Secondary peripheral module11:  Secondary peripheral module

• Consult data sheets and user guides for specific information.specific information.

More Examples:More Examples:• To put pins  0, 1 and 6 of Port 3 in output mode and 

ll h h iall the others as input:– (P3DIR) # 01000011b   [ mov.b #0x43,&P3DIR]

T t i 0 1 d 6 f P t 3 i t t d• To put pins  0, 1 and 6 of Port 3 in output mode leaving the others unchanged:

(P3DIR) # 0x43 OR (P3DIR) [ bis b #0x43 &P3DIR ]– (P3DIR) # 0x43 OR (P3DIR)   [ bis.b #0x43,&P3DIR ]

• To check status (high or low) or the input at pin 3 of input port 2:input port 2:– Test bit 3 of port 2    [bit.b  #BIT3,&P2IN]

Interruptible I/O ports (P1 and P2)Interruptible I/O ports (P1 and P2)

• Each pin has individual interrupt capabilityEach pin has individual interrupt capability which can be enabled or disabled independently of other pinsindependently of other pins.

• Has the same registers as non interruptible I/O ports plus three additional registers (allI/O ports, plus three additional registers (all read and write registers)

I bili i l h i i l d• Interrupt capability is lost when pin is selected for peripheral

Simplified Hardware Configuration: blInterruptible port

Control Registersg

Status Register

Interruptible Port RegistersInterruptible Port Registers

• Interrupt Enable Register (PxIE):  enables interrupt capability– 1 enabled, 0 disabled   (0 default)– bis.b #BIT0, &P1IE enables interrupt capability of pin P1.0– Interrupt requests from I/O ports are maskable

I t t bilit i l t if i i d f th d l– Interrupt capability is lost if  pin is used for other module.• Interupt Edge Select Register (PxIES): 

– 1:  high to low, 0 low to high  (0 default)• Interrupt Flags (PxIFG)• Interrupt Flags (PxIFG)

– Automatically set when interrupt is generated– Writable, so interrupt may be generated by software– ATTENTION: I/O IFG Reset only by software (Ex bic b #BIT0 P1IF)– ATTENTION:  I/O  IFG Reset only by software (Ex. bic.b #BIT0,P1IF)– 0:  no interrupt pending,   1:  interrupt pending 

I/O Ports with Pull‐up Pull‐down  Resistor

(Example from MSP430g2211 data sheet. Consult specific information for other models Diagram is not complete)other models. Diagram is not complete)

PSEL PDIR Pout PREn Condition0 0 x 0 IN, no R0 0 x 0 IN, no R0 0 0 1 In, R pull down0 0 1 1 IN, pull up R0 1 - 0 Out 0 1 x 1 Illegal0 1 x 1 Illegal1 ----------------Use with module

RemarksRemarks

• In your launchpad: Check if R‐pull up isIn your launchpad:  Check if R pull up is connected at P1.3 if using push‐button (see next slide)next slide)– If not, connect with software:

• bic b #BIT3 &P1DIR ; verify input statusbic.b #BIT3,&P1DIR   ; verify input status

• bis.b  #BIT3,&P1REN   ; connect resistor and

• bis.b  #BIT3,&P1OUT  ; set it as  pull up, ; p p

• Make an habit to set unused port pins as outputs.outputs.

USB ConnectorUSB Connector

Pull-up Resistors:R34 f k *

Left Port Right Port

Jumper Set J3R34 for user key*and R27 for resetkey

Left PortHeader J1

Right PortHeader J2

MSP430

OptionalpPower Port

* Note: R34 notin later versions

ResetKey

UserKey

JumperSet J5

in later versions.It must be configuredinternally