Micronodes - Indico at ESA / ESTEC (Indico)

1

2017 Thales Alenia Space UK Limited THALES ALENIA SPACE OPEN Ref. =

Ref. Modèle = 83230347-DOC-TAS-EN-004

Micronodes

ADCSS 2017 18th October 2017 @ ESTEC

Harness Reduction Session

[email protected]

18/10/2017

2



Content

18/10/2017

Project Overview

Micronodes Concept

Mission Applicability

Candidate Processors

CANbus Protocol

System Modelling

3



Project Overview

18/10/2017

Follow-on from ESA-funded study

“Smart Microsystems for Space Applications”

Led by Thales Alenia Space in the UK

Thales Alenia Space (France)

AAC Microtec

Cobham Gaisler

Requirements consolidation

Applicability for future missions

Retrospective assessment for past missions

Design & manufacture

Dependency on GR716 programme

Software development

SAVOIR-aligned

Targeted at ATHENA mission

4



Micronodes Concept

18/10/2017

Low power

Standard C&C bus

Microcontroller CPU

Analog/digital IO

Power switching

Heater PWM

Subsystem A

PCDU

LCL

LCL

Subsystem ASubsystem B

Subsystem ASubsystem C

Nominal High V Bus

Redundant High V Bus

uN uN

uN

Nominal Data Bus

Redundant Data BusOBC

uN

uN

5



Micronode Advantages

18/10/2017

Reduced harness mass

Modular/standardised architecture

New functional modes

Semi-autonomous

Partial operation

Simplified AIT

6



Mission Applicability

18/10/2017

Athena

Mission driving the study, high complexity, need decentralized architecture, mass reduction necessary

ExoMars TGO

Deep Space, thermal control based on important number of sensor/actuator, flight proven

NEOSAT

Telecommunications, mass production

TAS Generic RTU

Maturity level high, Earth Observation missions

SAVOIR RTU and OBC

Gather functions expected from such components

OBC for its computing capability, RTU for its interfacing capability

7



Relation to SAVOIR

18/10/2017

Telecommand

Platform

Telemetry

Time

reference

Security

Reconfiguration

Processing

On-Board

Time

Platform

Data Storage

Safe-Guard

MemoryEssential

TC

Cmd & Ctrl

Links

Mission

Data LinksTC

CLTUs

Authentication/

Decryption

Encryption

TM

CADUs

Context data,

Boot report

CLCW

TC Segments

TC

Segments

Essential

TM

TM

packets

X

Enable/

Disable

Alarms

Discrete

signals

System

alarms

Time

and

time

tick

Trig

Time tick

TM

packets

TM packets

TC

Segments

Platform

sensors and

actuators

Platform

commandingPayload

commanding

Data

Concentrator

Sensor and

actuator I/F

Sensor and

actuator I/F

Synchronisation

Payload

Data

Storage

Instruments incl.

ICUs,

Payload I/F Unit

Payload

Data Routing

X

Platform Payload

TC Segments

TM packets,

files

Time tick

Time

TM

frame

sync

Payload

synchronisation

Payload control

Inter

-PM

Platform

synchronisation

Hot redundant operation

Cold redundant operation

Hot or cold redundant operation

Payload

Telemetry TM

CADUs

Security

Encryption

Payload direct monitoring

PIO

PIO

Time & Tick

Context

Data

“The availability of microcontroller (as standalone ASIC or as IP core in a FPGA) could change the avionics architecture of a S/C allowing the decentralization of tasks very often done by the OBC, using an intelligent RTU.”

SAVOIR Functional Reference Architecture

Diagram: ESA

8



Candidate Processors

18/10/2017

GR716

LEON3 @ 50MHz

Baselined for Micronodes

DPC

OpenMSP430 @ 40MHz

SSDP

LEON3 @ 100MHz

Xentium DSP

ARM

ATMEL

Cobham Gaisler

9



Digital Programmable Controller

18/10/2017

40 MHz Maximum Clock Frequency

Rad-hard, ESCC9000 qualified

3 x OpenMSP430 cores

Onboard ADC + DAC + PWM + GPIO

Redundant CANbus + Mil-1553

Onboard 1.8V regulator

Low power consumption

Non-invasive debug facility

Used in many TAS equipments (inc. SB-Neosat SDIU)

Used by space community

DLR (robotics), Onera (Gyros), more to come

Available for ESA projects without restriction

No US content

200+ FM produced

10



Scalable Sensor Data Processor

18/10/2017

100 MHz Maximum Clock Frequency

300 krad

High SEU hardness

1x LEON3FT with High-Performance Floating Point Unit

Up to 64 MB SRAM & PROM

2x Xentium Fixed-Point DSPs

Network-on-Chip Interconnect with DMA Controller

On-Chip ADC, up to 50 Msps

Interface for Off-chip ADC/DAC / Chip-to-Chip

2x SpaceWire with RMAP Target, up to 200 Mbps

11



Performance Spectrum

18/10/2017

12



CANbus Protocol

18/10/2017

CANbus baselined for Micronodes

Determinism may be required

Add scheduling

e.g. TDMA frames

TAS in the UK developing an open CANbus backplane

UKSA funded activity

Protocol based on ECSS-E-ST-50-15C

CANopen compliant

Deterministic

PDO

SDO

Suitable for Micronodes

13



System Modelling

18/10/2017

Protocol validation

Correctness

Robustness

Schedulability

SDL

Graphical language for protocol description

Used in telecoms since 1980s

Formally complete

Human readable

Executable

Provable

14



System Modelling (TASTE)

18/10/2017

SDL integrated in ESA TASTE toolset

OpenGEODE SDL editor

Data modelling via ASN.1

ICD generation

Autogen encoding/decoding

Output as C/Ada code

TASTE VM executes SDL

Message sequence charts (MSC)

Record / replay / editing of message exchanges

Scripting of test cases (Python)

15



Thank you for listening Questions…

18/10/2017

Documents

Micronodes - Indico at ESA / ESTEC (Indico)