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USB 3.0TECHNOLOGY
MINDSHARE, INC.
Donovan (Don) AndersonJay Trodden
MindShare Training Courses
Click here to see a complete list of live and eLearning courses.
[email protected] 1-800-633-1440 www.mindshare.com
Intel Architecture• Intel Haswell Processor• Intel 32/64 Bit x86 Architecture• Intel QuickPath Interconnect (QPI)• Computer Architecture
Big Data• Hadoop• Cassandra• ElasticSearch• MongoDB
Mobile Technology• M-PCIe• UFS• MIPI M-PHY• Intel-Based Mobile (Phone/Tablet)• Intel Atom SoC• Mobile DRAM (LPDDRx)• High Speed/EMI for Mobile Platforms
IO Buses• PCI Express 3.0• PCIe IO Virtualization• USB 3.0 / 2.0• xHCI for USB• USB 3.1 Update
AMD Architecture• AMD Opteron Processor (Bulldozer)• AMD64 Architecture
Virtualization Technology• PC Virtualization• IO Virtualization• ARM Virtualization
Firmware Technology• x86 Firmare (UEFI/BIOS) Architecture• BIOS Essentials
Storage Technology• SAS• Serial ATA• AHCI for SATA• SATA 3.0• NVMe
ARM Technology• ARM Architecture• ARM Virtualization
DRAM Technology• DDRx & LPDDRx• LPDDRx
Programming• x86 Architecture Programming• x86 Assembly Language Basics• OpenCL Programming
High Speed Design• High Speed Design• EMI/EMC
The Ultimate Tool to View, Edit and Verify Configuration Settings of Computers
MindShare Arbor is a computer system debug, validation, analysis and learning tool that allows the user to read and write any memory, IO or configuration space address. The data from these address spaces can be viewed in a clean and informative style. In addition, Arbor checks and flags configuration errors and non-optimal settings.
Arbor’s Software SupportMindShare’s Arbor tool supports DOS, Windows and Linux 32- and 64-bit implementations and OS-X is near-ing completion. In addition, Arbor supports Intel’s JTag debuggers.
View Reference InfoArbor can quickly display standard PCI, PCI-X and PCIe configuration registers and memory structures. All the register and field definitions are up-to-date with the PCI Express 3.0 implementation. Arbor also supports other implementations such as the x86 MSRs, USB”s xHCI Host Controller and SATA’s AHCI Host Bus Adapter. Other implementations are planned including, new x86 features and NVMe registers and data structures.
Decoding Standard and Custom Structures from a Live SystemMindShare Arbor performs a system scan to record the PCI config space data, relevant memory and memory-mapped structures as well as Model Specific Registers (MSRs) and shows them in a clean and intuitive decoded format. MindShare Arbor also allows users to create their own decode files via XML.
Write CapabilityMindShare Arbor provides a very simple interface to directly edit a register in PCI config space, memory address space, IO address space or MSR. This can be done in the decoded view so you see what the mean-ing of each bit, or by simply writing a hex value to the target location.
Scripting CapabilityMindShare Arbor can also be used in a testing environment with compliance test suites, regression testing, system setup for bug evaluation and more. Arbor can run Python scripts which allow users to automate any functionality that can be performed manually from the graphical interface (and even more). MindShare pro-vides several useful python scripts with the purchase of Arbor related to PCIe testing.
Run Rule Checks of Standard and Custom StructuresIn addition to capturing and displaying headers and capability structures from PCI config space, Arbor can also check the settings of each field for errors (e.g. violates the spec) and non-optimal values (e.g. a PCIe link trained to something less than its max capability). MindShare Arbor has scores of these checks built in and can be run on any system scan (live or saved). Any errors or warnings are flagged and displayed for easy evaluation and debugging. Users can also define their own rule checks. These rule checks can be for any structure, or set of structures, in PCI config space, memory space or IO space.
Saving System Scans (XML)After a system scan has been performed, MindShare Arbor allows saving of that system's scanned data (PCI config space, memory space and IO space) all in a single file to be looked at later or sent to a colleague. The scanned data in these Arbor system scan files (.ARBSYS files) are XML-based and can be looked at with any text editor or web browser. Even scans performed with other tools can be easily converted to the Arbor XML format and evaluated with MindShare Arbor.
USB 3.0TECHNOLOGY
MINDSHARE, INC.
Donovan (Don) AndersonJay Trodden
Many of the designations used by manufacturers and sellers to distinguish their prod-ucts are claimed as trademarks. Where those designators appear in this book, and Mind-Share was aware of the trademark claim, the designations have been printed in initialcapital letters or all capital letters.
The authors and publisher have taken care in preparation of this book, but make noexpressed or implied warranty of any kind and assume no responsibility for errors oromissions. No liability is assumed for incidental or consequential damages in connec-tion with or arising out of the use of the information or programs contained herein.
Library of Congress Cataloging-in-Publication Data
Anderson, Don and Trodden, JayUSB 3.0 Technology / MindShare, Inc. Donovan Anderson, Jay Trodden....[et al.]
Includes indexISBN: 978-0-9836465-1-81. Computer Architecture 2. Microcomputers - buses.I. Anderson, Don II. MindShare, Inc. III. Title
Library of Congress Number: ISBN: 978-0-9836465-1-8
Copyright ©2013 by MindShare, Inc.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopy-ing, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America.
Sponsoring Editor: Project Manager: Maryanne DavesCover Design: Greenhouse Creative and MindShare, Inc.
Set in 10 point Palatino Linotype by MindShare, Inc.
First Edition, First Printing,
Table of Contents
About This BookScope............................................................................................................................................. 1The MindShare Architecture Series ....................................................................................... 1Cautionary Note ......................................................................................................................... 3The Standard Is the Final Word .............................................................................................. 3Documentation Conventions................................................................................................... 3
Hexadecimal Notation ........................................................................................................ 3Binary Notation .................................................................................................................... 3Decimal Notation ................................................................................................................. 4Bits Versus Bytes Notation ................................................................................................. 4Bit Fields ................................................................................................................................ 4
Other Terminology and Abbreviations ................................................................................. 4Visit Our Web Site ..................................................................................................................... 5We Want Your Feedback........................................................................................................... 6
Chapter 1: Motivation for USB 3.0Introduction................................................................................................................................. 7USB 3.0 Host Controllers .......................................................................................................... 8Performance................................................................................................................................. 8
USB Bandwidth Comparison ............................................................................................. 8Streaming Video and Audio............................................................................................. 10Mass Storage ....................................................................................................................... 10
Improved Protocols.................................................................................................................. 11End-to-End Protocols ........................................................................................................ 11
Token/Data/Handshake Shortcomings and Improvements................................. 11Token/Data/Handshake is Inefficient. .............................................................. 12Broadcast Bus Increases Power Consumption ................................................ 13Polled Flow Control. ........................................................................................... 13Error Handling and Reporting .......................................................................... 13
Data Bursting............................................................................................................... 14Bulk Streaming............................................................................................................ 14
Port-to-Port Protocols........................................................................................................ 14Link Flow Control....................................................................................................... 15Link Error Detection and Recovery ......................................................................... 15
Power Management ................................................................................................................. 15SuperSpeed Bus Power Management ............................................................................. 15
Broadcast Versus Unicast Bus................................................................................... 15Link Power Management .......................................................................................... 16Function Power Management................................................................................... 16
System Power Improvements .......................................................................................... 16
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USB 3.0 Technology
Chapter 2: USB 2.0 BackgroundMotivations for USB................................................................................................................ 17USB Topologies ........................................................................................................................ 18
USB 2.0 Companion Controllers ...................................................................................... 19Host Controller Registers.................................................................................................. 20USB Hubs ............................................................................................................................ 22
Root Hubs .................................................................................................................... 22External Hubs.............................................................................................................. 23Hub Depth Limits ....................................................................................................... 25
Broadcast Transactions...................................................................................................... 26Device Architecture ................................................................................................................. 28
Endpoints and Buffers....................................................................................................... 29Control Endpoints.............................................................................................................. 30Standard Requests ............................................................................................................. 31Optional Endpoints ........................................................................................................... 32
USB 2.0 Packets and Protocol................................................................................................. 33Token-Data-HandShake Packet Protocol ....................................................................... 33
IN Transactions ........................................................................................................... 34OUT Transactions ....................................................................................................... 35Low-Speed Transaction Variation............................................................................ 35Control Transfer Stages.............................................................................................. 36
Three-Stage Transfers ......................................................................................... 36Two-Stage Transfers............................................................................................ 36
Maximum Payload Sizes ........................................................................................... 37HS Ping Protocol - For OUT Transactions...................................................................... 37HS Split Transaction Protocol .......................................................................................... 39
Transaction Generation and Scheduling............................................................................. 41Transaction Generation..................................................................................................... 42Transaction Scheduling..................................................................................................... 43
Device Power ............................................................................................................................ 45
Chapter 3: USB 3.0 OverviewUSB 3.0 Topology and Compatibility .................................................................................. 47
USB 3.0 Host Controller .................................................................................................... 49Topology ............................................................................................................................. 49USB 2.0/3.0 Compatibility................................................................................................. 50
Receptacle and Plug Compatibility.......................................................................... 50SuperSpeed Device Compatibility ........................................................................... 51Software Compatibility.............................................................................................. 51
The SuperSpeed Physical Layer Environment................................................................... 51
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USB 3.0 Composite Cable ................................................................................................. 51SS Link Models............................................................................................................ 52Shared Bus Power ....................................................................................................... 53
USB 3.0 Compliant Cable Assemblies............................................................................. 54General ......................................................................................................................... 54USB 3.0 Power-B Connections .................................................................................. 54
SuperSpeed Layered Interface and Protocols..................................................................... 56Hub Interface Layers ......................................................................................................... 58
Layers - Hub Forwarding Packets............................................................................ 58Layers - Hub as Target ............................................................................................... 58Layers - Hub Downstream Port (Thin Protocol Layer)......................................... 60
Three Protocols................................................................................................................... 61End-to-End Protocol (Protocol Layer) ..................................................................... 61
USB 2.0 vs SS IN Transaction Comparison...................................................... 62USB 2.0 vs SS OUT Transaction Comparison.................................................. 63
Port-to-Port Protocol (Link Layer) ........................................................................... 64Chip-to-Chip Protocol (Physical Layer) .................................................................. 66
Configuration and Descriptors.............................................................................................. 66Power Management ................................................................................................................. 67
Link Power Management.................................................................................................. 68Function Power Management .......................................................................................... 69
Chapter 4: Introduction to End-to-End ProtocolThe Protocols............................................................................................................................. 71
The Protocol Packet Types................................................................................................ 72The Token Lives On........................................................................................................... 72Bursting ............................................................................................................................... 73Bulk Endpoint Streaming ................................................................................................. 74Endpoint Characteristics for SuperSpeed ...................................................................... 76
Port-to-Port Protocol Influence.............................................................................................. 76Does SuperSpeed Support Parallel Operations? ............................................................... 77
Chapter 5: End-to-End PacketsThree Categories of End-To-End Packets ............................................................................ 79Transaction Packets (TPs)....................................................................................................... 82
ACK Header ....................................................................................................................... 83Downstream Moving ACK........................................................................................ 83 Upstream Moving ACK............................................................................................ 85
NRDY Header..................................................................................................................... 86ERDY Header ..................................................................................................................... 88STATUS Header ................................................................................................................. 89
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USB 3.0 Technology
STALL Header.................................................................................................................... 91Notification Headers ......................................................................................................... 92
Function Wake Header .............................................................................................. 92Latency Tolerance Message Header......................................................................... 94Bus Interval Adjustment Message Header ............................................................. 95
PING and PING RESPONSE Header.............................................................................. 96Data Packet ................................................................................................................................ 99
DATA Packet Moving Downstream ............................................................................... 99DATA Packet Moving Upstream................................................................................... 101
Isochronous Timestamp Packet (ITP) ................................................................................ 103
Chapter 6: Control ProtocolIntroduction to SuperSpeed Control Transfers ............................................................... 105Control Transfer Structures and Examples ....................................................................... 106
Two-Stage Control Transfer Structure.......................................................................... 107Three-Stage Control Transfer Structure........................................................................ 107
Control IN Example — Single Data Packet........................................................... 108Control IN Example — Two Data Packets............................................................ 109Control OUT Example — Two DATA Packets .................................................... 109
Control Transfer Packet Content ........................................................................................ 110The Setup Transaction..................................................................................................... 110
The DATA Header Packet ....................................................................................... 110Data Packet Payload — Setup Data ....................................................................... 111Setup Response — ACK .......................................................................................... 114
DATA Stage ...................................................................................................................... 114Status Stage ....................................................................................................................... 115
General ....................................................................................................................... 115Control Transfer with STALL ................................................................................. 115
Two Stage Control Transfer Example ................................................................................ 116Set Address Request ........................................................................................................ 116
Setup Stage — Set Address ..................................................................................... 116Status Stage — Set Address..................................................................................... 117
Protocol Details for Set Address Request ..................................................................... 117Three Stage IN Control Transfer Examples ...................................................................... 119
The Get Device Descriptor Request Example .............................................................. 119Setup Transaction — Get Device Descriptor ........................................................ 119Data and Status Stages — Get Device Descriptor ................................................ 120Protocol Details — Get Device Descriptor Request ............................................. 120
Control Transfer — Variable-Length Data Example 1 ............................................... 122Control Transfer — Variable-Length Data Example 2 ............................................... 123
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Chapter 7: Bulk ProtocolIntroduction to Bulk Transfers............................................................................................ 125Bulk End-to-End Protocol..................................................................................................... 126
Bulk IN SuperSpeed Transaction Protocol................................................................... 127IN Data Bursting ....................................................................................................... 127
Single DATA Packet Burst Example............................................................... 129Burst IN Example with Four DATA Packets................................................. 130Burst IN Example with Long Burst................................................................. 131
End-to-End Flow Control — Bulk IN Transfers................................................... 132NRDY Flow Control at Start of IN Transfer .................................................. 132IN Burst Flow Control Using EOB.................................................................. 133IN Burst Flow Control Using NRDY .............................................................. 134Short packets ...................................................................................................... 135Data IN Transfer Errors and Retry.................................................................. 136
Bulk OUT SuperSpeed Transaction Protocol............................................................... 137OUT Data Bursting ................................................................................................... 138
Single DATA OUT Burst Example.................................................................. 138Burst OUT Example with Four DATA Packets............................................. 139Burst OUT Example with Long Burst............................................................. 140
End-to-End Flow Control — Bulk OUT Transfers............................................... 141NRDY Flow Control at Start of OUT Transfer .............................................. 142OUT Burst Flow Control Using NumP=0 ...................................................... 143DATA OUT Transfer Errors............................................................................. 144
Timeout conditions and values...................................................................................... 146Standard Bulk Vs. Bulk Streaming Endpoints................................................................. 146Streaming And Endpoint Buffers ....................................................................................... 147
Standard Bulk Endpoint Buffer ..................................................................................... 147Bulk Streaming Endpoint Buffers.................................................................................. 148Stream ID (SID), A Bit More........................................................................................... 148Priming the Bulk Streaming Endpoints........................................................................ 149
Reporting Bulk Endpoint Streaming Capability ............................................................. 149Standard And Bulk Streaming Examples.......................................................................... 150
Standard Bulk Endpoints & SCSI BOT Drive .............................................................. 150UAS Device Endpoints............................................................................................. 151Host Memory Buffers............................................................................................... 152Host Controller (HC)................................................................................................ 152BOT Disk DMA Read Operation ............................................................................ 153
Bulk Streaming Endpoints & UAS Drive ..................................................................... 154UAS Device Endpoints............................................................................................. 155Host Memory Buffers............................................................................................... 156Host Controller (HC)................................................................................................ 157
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USB 3.0 Technology
Example UAS and UASP Commands........................................................................... 157The Non-Data UAS Command............................................................................... 158Non Data UASP Command .................................................................................... 159Read DMA UAS Command .................................................................................... 160Read DMA UASP Command.................................................................................. 162Write DMA UAS Command ................................................................................... 164Write DMA UASP Command................................................................................. 165
Chapter 8: Interrupt ProtocolIntroduction to Interrupt Transfers .................................................................................... 167Interrupt IN SuperSpeed Transaction Protocol ............................................................... 169
Single Interrupt Transaction........................................................................................... 169Burst transaction sequence (two DATA packets)........................................................ 170Interrupt IN — Errors and Retries................................................................................. 173Interrupt OUT SuperSpeed Transaction Protocol....................................................... 176
Interrupt OUT Data Bursting.................................................................................. 176End-to-End Flow Control — Interrupt OUT Transfers....................................... 177
Chapter 9: Isochronous ProtocolIntroduction to Isochronous Transfers .............................................................................. 181Bus Intervals and Isochronous Service Intervals............................................................. 183Flexibility of Scheduling ...................................................................................................... 184Isochronous Timestamp Packet Delivery.......................................................................... 185
General............................................................................................................................... 185The Timestamp Packet .................................................................................................... 186
Delta Value ................................................................................................................ 187Delayed Bit................................................................................................................. 187
Changing the Time Base ....................................................................................................... 187Requirements for Changing the TimeBase................................................................... 187Bus Interval Adjustment Message................................................................................. 188
Ping and Ping Response ....................................................................................................... 189Ping Related Timing Parameters ................................................................................... 190
Maximum Exit Latency (MEL) ............................................................................... 190tPingTimeout............................................................................................................. 190
Ping and Ping Response Header Format...................................................................... 191Isochronous End-to-End Protocol ....................................................................................... 192
General Isochronous IN Protocol Rules ....................................................................... 192Isochronous IN Protocol ................................................................................................. 192
Isochronous IN with Burst of Two......................................................................... 193Isochronous IN Burst of Two with Zero Payload ................................................ 194Isochronous IN Burst Size of 16.............................................................................. 195
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Isochronous OUT Transactions...................................................................................... 196Isochronous OUT with Burst Size of 16................................................................. 196Isochronous OUT Burst with Four Service Intervals........................................... 197
Service Interval N .............................................................................................. 197Service interval N+1 .......................................................................................... 197Service Interval N+2 .......................................................................................... 197Service Interval N+3 .......................................................................................... 197
Smart Isochronous Transaction Scheduling..................................................................... 198Smart Isochronous IN Transaction Example ............................................................... 199Smart Isochronous IN Transactions with No Ping ..................................................... 202Smart Isochronous OUT Transactions .......................................................................... 203
Chapter 10: USB 3.0 HubsIntroduction to SS Hubs ....................................................................................................... 205Hub Attachment ..................................................................................................................... 207Packet Forwarding ................................................................................................................. 207
Packet Forwarding and the Layers................................................................................ 209Packet Routing Across Hub — Link-to-Link........................................................ 209Packet Routing to Hub Controller.......................................................................... 210Packet Routing to Hub Controller with LMP....................................................... 210
Unicast Routing................................................................................................................ 212Packet Forwarding and Buffer Requirements ............................................................. 213
Header Buffers — Store and Forward Model....................................................... 214Data Payload Buffers — The Repeater Model...................................................... 215
Transaction Deferral ........................................................................................................ 216Hub Error Detection and Handling.................................................................................... 218Hub Link Power Management Responsibilities.............................................................. 219Cable Power and Distribution............................................................................................. 220Reset Propagation................................................................................................................... 220
Chapter 11: Introduction to Port-To-Port ProtocolPort-To-Port Protocol And The Link Layer ....................................................................... 221The Big Picture Revisited ..................................................................................................... 222Port-To-Port Protocol: Header Processing ......................................................................... 223
General............................................................................................................................... 223Header Fields, Two Groups ........................................................................................... 223
Link Layer Header Processing Elements ........................................................................... 224Tx HP Processing ............................................................................................................. 225Tx HP Buffers.................................................................................................................... 225Tx Data CRC-32 Generation ........................................................................................... 225Rx HP Checks ................................................................................................................... 226
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USB 3.0 Technology
Rx HP Buffers ................................................................................................................... 226Rx Data CRC-32 Checking.............................................................................................. 226
Link Management Elements ................................................................................................ 227LTSSM Functional Block................................................................................................. 228Tx, Rx Link Commands................................................................................................... 228Link Command Groups .................................................................................................. 228
Packet Acknowledgement Link Commands ........................................................ 229Flow Control Link Commands ............................................................................... 229Power Management Link Commands................................................................... 229Link Up/Link Down Link Commands................................................................... 229
HP Acknowledgement .................................................................................................... 230HP Flow Control .............................................................................................................. 230
Ordered Sets............................................................................................................................ 231Ordered Set Data (D) and Control (K) Symbols .......................................................... 231Four Ordered Set Functional Groups............................................................................ 232
Framing Ordered Sets (Delimiters) ........................................................................ 232Header Packet Framing .................................................................................... 232Data Packet Framing (Valid Data Payload)................................................... 233Data Packet Framing (Nullified Data Payload) ............................................ 234Link Command Framing .................................................................................. 235
Link Training & Retraining Ordered Sets ............................................................. 236TSEQ Ordered Set.............................................................................................. 236TS1 Ordered Set ................................................................................................. 237TS2 Ordered Set ................................................................................................. 238
Clock Compensation Ordered Set (Skip Ordered Set) ........................................ 239Loopback Bit Error Rate Test (BERT) Ordered Sets............................................. 240
General ................................................................................................................ 240BRST Ordered Set .............................................................................................. 241BERC Ordered Set ............................................................................................. 241BCNT Ordered Set............................................................................................. 242
Chapter 12: LTSSM And the SuperSpeed Link StatesTwelve High Level LTSSM States ...................................................................................... 244Why Is The LTSSM Needed?............................................................................................... 245
LTSSM And Link Training And Retraining................................................................. 245Background: USB 2.0 Doesn’t Require Training .................................................. 245LTSSM Coordinates SuperSpeed Link Training .................................................. 245
LTSSM And Link-Level Error Handling ...................................................................... 246Background: USB 2.0 Approach to Bus Errors ..................................................... 246USB 3.0 SuperSpeed Approach To Link Errors.................................................... 247When Does The LTSSM Become Involved?.......................................................... 247
LTSSM And SuperSpeed Link Power Management................................................... 248
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Background: USB 2.0 Power Management ........................................................... 248USB 3.0 SuperSpeed Power Management Enhancements.................................. 248The LTSSM Role In SuperSpeed Link Power Management ............................... 248
LTSSM And SuperSpeed Link Testing ......................................................................... 249Background: USB 2.0 Testing.................................................................................. 249USB 3.0 SuperSpeed Link Testing Features .......................................................... 249
LTSSM State Transitions...................................................................................................... 250General............................................................................................................................... 250What Is A Directed LTSSM Transition?........................................................................ 250Handshake Signaling Locks LTSSMs............................................................................ 250LTSSM Handshake Takes Several Forms..................................................................... 251
LFPS Signaling Events Used In LTSSM Handshake ........................................... 251Ordered Sets Used In LTSSM Handshake ............................................................ 252Link Commands Used In LTSSM Handshake...................................................... 253
LTSSM Time-outs............................................................................................................. 254General ....................................................................................................................... 254Timer Characteristics................................................................................................ 254
LTSSM Reference Section Note .......................................................................................... 256Summary Of LTSSM Operational States .......................................................................... 256
U0 ....................................................................................................................................... 256General Description.................................................................................................. 257Requirements In The U0 State ................................................................................ 257Exit Rules For The U0 State ..................................................................................... 257
U1 ....................................................................................................................................... 259General Description.................................................................................................. 259Requirements In The U1 State ................................................................................ 259Exit Rules For The U1 State ..................................................................................... 260
U2 ....................................................................................................................................... 261General Description.................................................................................................. 261Requirements In The U2 State ................................................................................ 261Exit Rules For The U2 State ..................................................................................... 262
U3 (Suspend) .................................................................................................................... 263General Description.................................................................................................. 263Requirements In The U3 State ................................................................................ 263Exit Rules For The U3 State ..................................................................................... 264
Summary Of LTSSM Link Initialization &Training States .......................................... 265Rx.Detect ........................................................................................................................... 265
General Description.................................................................................................. 265Requirements In The Rx.Detect.Reset Substate.................................................... 266Exit Rules For The Rx.Detect.Reset Substate ........................................................ 266Requirements In The Rx.Detect.Active Substate.................................................. 266Exit Rules For The Rx.Detect.Active Substate ...................................................... 267
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USB 3.0 Technology
Requirements In The Rx.Detect.Quiet Substate ................................................... 267Exit Rules For The Rx.Detect.Quiet Substate........................................................ 268
Polling................................................................................................................................ 268General Description.................................................................................................. 268Requirements In The Polling.LFPS Substate ........................................................ 269Exit Rules For The Polling.LFPS Substate ............................................................. 269Requirements In The Polling.RxEQ Substate ....................................................... 270Exit Rules For The Polling.RxEQ Substate............................................................ 270Requirements In The Polling.Active Substate ...................................................... 271Exit Rules For The Polling.Active Substate........................................................... 271Requirements In The Polling.Configuration Substate......................................... 272Exit Rules For The Polling.Configuration Substate ............................................. 272Requirements In The Polling.Idle Substate........................................................... 273Exit Rules For The Polling.Idle Substate ............................................................... 273
Recovery............................................................................................................................ 274General Description.................................................................................................. 275Requirements In Recovery.Active.......................................................................... 275Exit Rules For Recovery.Active .............................................................................. 275Requirements In Recovery.Configuration ............................................................ 276Exit Rules For Recovery.Configuration................................................................. 276Requirements In Recovery.Idle............................................................................... 277Exit Rules For Recovery.Idle ................................................................................... 277
Hot Reset ........................................................................................................................... 278General Description.................................................................................................. 278Requirements In Hot Reset.Active ......................................................................... 278Exit Rules For Hot Reset.Active.............................................................................. 279Requirements In Hot Reset.Exit.............................................................................. 279Exit Rules For Hot Reset.Exit .................................................................................. 280
Summary Of LTSSM Testing States .................................................................................. 281Compliance Mode............................................................................................................ 281
General Description.................................................................................................. 281Requirements In Compliance Mode ...................................................................... 282Exit Rules For Compliance Mode........................................................................... 282
Loopback ........................................................................................................................... 283General Description.................................................................................................. 283Requirements In Loopback.Active ......................................................................... 283Exit Rules For Loopback.Active ............................................................................. 284Requirements In Loopback.Exit.............................................................................. 284Exit Rules For Loopback.Exit .................................................................................. 284
Summary Of Other LTSSM States ..................................................................................... 285SS.Inactive State................................................................................................................ 285
General Description.................................................................................................. 285
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Basic SS.Inactive Requirements .............................................................................. 285Requirements In SS.Inactive.Quiet Substate......................................................... 286Exit Rules For SS.Inactive.Quiet Substate ............................................................. 286Requirements In SS.Inactive.Disconnect.Detect................................................... 286Exit Rules For SS.Inactive.Disconnect.Detect ....................................................... 286
SS.Disabled State .............................................................................................................. 287General Description.................................................................................................. 287Exit Rules For The SS.Disabled State ..................................................................... 288Requirements For The SS.Disabled.Default Substate.......................................... 288Exit Rules For The SS.Disabled.Default Substate................................................. 288Exit Rules For The SS.Disabled.Error Substate..................................................... 288
Chapter 13: Link CommandsFour Groups Of Link Commands ....................................................................................... 289Link Commands On The SuperSpeed Link ..................................................................... 291For Additional Details On Link Commands .................................................................... 291Link Command Encoding And Use.................................................................................... 292
Packet Acknowledgement: LGOOD_n......................................................................... 292Packet Acknowledgement: LBAD ................................................................................. 293Packet Acknowledgement: LRTY.................................................................................. 294Flow Control: LCRD_x.................................................................................................... 295Power Management: LGO_Ux (The Request) ............................................................. 296Power Management: LAU (Acceptance) ...................................................................... 297Power Management: LXU (Rejection)........................................................................... 298Power Management: LPMA (Acknowledgement)...................................................... 299Link Up/Link Down: LDN.............................................................................................. 300Link Up/Link Down: LUP .............................................................................................. 301
Notes On Link Command Placement................................................................................. 302
Chapter 14: Header Packet ProcessingLink Layer Packet Processing Role..................................................................................... 303Transmitter Packet Processing............................................................................................. 305
Header Sequence Number Assignment ....................................................................... 306Header Link Control Word CRC-5 Generated ............................................................ 307Header CRC-16 Generated ............................................................................................. 308Copy Is Placed In A Header Packet Buffer .................................................................. 309Data Packet Payload CRC-32 Generation..................................................................... 310
General ....................................................................................................................... 310Tx DPP CRC-32 Generation, The Hardware Details ........................................... 311
Framing Added, Packet Sent To Physical Layer ......................................................... 312Receiver Packet Processing .................................................................................................. 313
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Inbound Link Layer Traffic ............................................................................................ 313Key Header Packet Processing Elements ..................................................................... 314Header Packet CRC-16 Checked.................................................................................... 315Header Link Control Word CRC-5 Checked ............................................................... 316Header Sequence Number Checked ............................................................................. 317Header Packet Buffer Accepts The Header.................................................................. 318Data Packet Payload (DPP) CRC-32 Checked ............................................................. 319
General ....................................................................................................................... 319Rx DPP CRC-32 Checking, The Hardware Details .............................................. 320
Chapter 15: Header Packet Flow ControlBackground: Host And Device Flow Control ................................................................... 321
USB 2.0 Flow Control, Very Limited............................................................................. 322The SuperSpeed Flow Control Approach .................................................................... 322
End To End Flow Control........................................................................................ 322Link Level Flow Control Is Also Needed.............................................................. 323
SuperSpeed Link Level Flow Control Basics ................................................................... 324Flow Control Elements.......................................................................................................... 325
Transmitter Elements ...................................................................................................... 326Tx Header Packet (HP) Buffers............................................................................... 326Remote Rx HP Credit Count ................................................................................... 326Credit _HP_Timer..................................................................................................... 326Next Rx LCRD_x....................................................................................................... 327
Receiver Elements ............................................................................................................ 327Rx Header Packet (HP) Buffers............................................................................... 327LCRD_x Generation ................................................................................................. 327
Header Packet Flow Control Link Commands................................................................. 328General............................................................................................................................... 328LCRD_x Link Command Format................................................................................... 328
Flow Control Initialization................................................................................................... 329Flow Control Logic State After Reset............................................................................ 329Flow Control Logic Initialization................................................................................... 330
Flow Control During Normal Operations......................................................................... 331The First Header Is Sent .................................................................................................. 331Header Packet Reaches Rx HP Buffer........................................................................... 332Emptying An Rx HP Buffer ............................................................................................ 333Transmitter Receives LCRD_x ....................................................................................... 334If Tx Receives A Valid LCRD_x ..................................................................................... 335If Tx Receives An Invalid LCRD_x................................................................................ 336
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Chapter 16: Link Errors & Packet AcknowledgementBackground: USB 2.0 Error Handling ................................................................................ 339USB 3.0 SuperSpeed Requires A New Approach ............................................................ 340
SuperSpeed Signaling Affects Bit Error Rates ............................................................. 340Complex USB Topologies A Challenge At 5 Gb/s....................................................... 340Upstream Asynchronous Message Errors.................................................................... 341
Scope Of SuperSpeed Link Errors ...................................................................................... 342Training Sequence Errors................................................................................................ 343Errors Occurring While Link is in U0 ........................................................................... 343
SuperSpeed Link Level Error Correction Approach ....................................................... 343Goals Of Header Packet Acknowledgement ............................................................... 344
Reliable Delivery Of Header Packets..................................................................... 344Hand Off The More Serious Errors ........................................................................ 344
End-To-End Acknowledgement Is Still Needed ......................................................... 345Header Packet Acknowledgement Elements.................................................................... 345
Transmitter Elements ...................................................................................................... 346HDR Seq# Assignment............................................................................................. 346Next Tx HDR Seq#.................................................................................................... 347HDR CRC-5................................................................................................................ 347HDR CRC-16.............................................................................................................. 347Tx HP (Header Packet) Buffers............................................................................... 347Pending_HP_Timer .................................................................................................. 347Next Rx LGOOD_n................................................................................................... 348
Receiver Elements ............................................................................................................ 349HDR CRC-5 And CRC-16 Checks .......................................................................... 349Retries (Retry attempt counter) .............................................................................. 349LBAD Generation ..................................................................................................... 350HDR Seq# Check....................................................................................................... 350Next Rx HDR Seq#.................................................................................................... 350Rx Header Packet (HP) Buffers............................................................................... 351LGOOD_n Generation ............................................................................................. 351
Header Packet Acknowledgement Link Commands ...................................................... 351LGOOD_n Link Command Format .............................................................................. 352LBAD Link Command Format....................................................................................... 353LRTY Link Command Format ....................................................................................... 354
Header Packet Acknowledgement Initialization............................................................. 355HP Acknowledgement Logic After Reset .................................................................... 355HP Sequence Number Advertisement.......................................................................... 356
General ....................................................................................................................... 356Sequence Of Events .................................................................................................. 357
HP Acknowledgement Sequence: No Retry Required ................................................... 357
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First Header Packet Is Sent ............................................................................................. 357Header CRC-5, CRC-16 Checked By The Receiver ..................................................... 359Header Sequence Number Checked By Receiver ....................................................... 360Receiver Accepts And Acknowledges The Packet...................................................... 361Transmitter Checks LGOOD_n Acknowledgement ................................................... 362LGOOD_n Valid: Retire Header Packet ....................................................................... 363
HP Acknowledgement Sequence: Retry Required.......................................................... 364The Header Packet Is Sent .............................................................................................. 364Header CRC-5 or CRC-16 Check Fails, LBAD Sent .................................................... 365Transmitter Receives LBAD, Starts The Retry............................................................. 366Retry Header Packet CRC-5, CRC-16 Checked ........................................................... 367Retry Header Packet Sequence Number Checked...................................................... 368Receiver Acknowledges The Retry Header Packet..................................................... 369Transmitter Checks LGOOD_n Following The Retry ................................................ 370LGOOD_n Valid: Retire The Header Packet................................................................ 371
Chapter 17: Introduction to Chip-To-Chip ProtocolChip-To-Chip Protocol And The Physical Layer ............................................................. 373The Big Protocol Picture, Once More ................................................................................. 374Chip-To-Chip Protocol: PHY Logical Processing............................................................. 375
A Note About D/K Bytes And Symbols........................................................................ 375A Few Common Structure D/K Examples ................................................................... 376
The Physical Layer: PHY Logical Processing.................................................................... 377Tx Scrambling................................................................................................................... 378Tx 8b/10b Encoding ......................................................................................................... 378Tx Serialization................................................................................................................. 378Rx Clock/Data Recovery ................................................................................................. 378Rx De-serialization........................................................................................................... 378Rx Elastic Buffer ............................................................................................................... 379Rx 8b/10b Decoding......................................................................................................... 379Rx De-scrambling............................................................................................................. 379Receiver PHY Forwards Traffic to Link Layer ............................................................ 379
The Physical Layer: PHY Electrical Specifications .......................................................... 379General Topics.................................................................................................................. 381Transmitter PHY Electrical Topics ................................................................................ 381Receiver PHY Electrical Topics ...................................................................................... 381Low Frequency Periodic Signaling (LFPS)................................................................... 381
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Chapter 18: Physical Layer Logical FunctionsPhysical Layer Logic Definitions ........................................................................................ 383Tx Physical Layer (PHY) Logic ............................................................................................ 385
Tx Outbound Bytes And The D/K Flag ........................................................................ 385Data Scrambling ............................................................................................................... 386
General ....................................................................................................................... 386Disabling Scrambling ............................................................................................... 388
8b/10b Encoding............................................................................................................... 388The Purpose Of Encoding........................................................................................ 389Two Key 8b/10b Encoding Rules............................................................................ 390Some 8b/10b Encoding Examples........................................................................... 3908b/10b Encoding And Current Running Disparity.............................................. 391The AC-Coupled SuperSpeed Link........................................................................ 392
Advantages of AC-Coupling ........................................................................... 392Challenges of AC-Coupling ............................................................................. 392
8b/10b Encoding Minimizes Disparity .................................................................. 392Is The Transmitter CRD Choice Correct? .............................................................. 393
Parallel To Serial Data Conversion................................................................................ 394Differential Transmitter .................................................................................................. 395
Rx Physical Layer (PHY) Logic ............................................................................................ 396Differential Receiver And Equalization........................................................................ 396Clock And Data Recovery .............................................................................................. 397
Clock Recovery.......................................................................................................... 398Data Recovery Circuit (DRC).................................................................................. 398
Serial To Parallel Data Conversion................................................................................ 399Serial To Parallel Conversion and COM Symbol Lock ....................................... 400Differential Polarity Inversion (If Needed)........................................................... 401
Elastic Buffer ..................................................................................................................... 402Tx And Rx Clock Requirements ............................................................................. 403
5 GHz Base Clock .............................................................................................. 403Spread Spectrum Clocking............................................................................... 403
Implications Of Tx, Rx Clock Difference ............................................................... 403The Result: Two Rx Clock Domains....................................................................... 404
Receiver PHY Clock Domain Notes................................................................ 405Elastic Buffer Architecture....................................................................................... 406Skip (SKP) Ordered Sets .......................................................................................... 407
8b/10b Decode .................................................................................................................. 408Error Checking At The Decoder ............................................................................. 408Decoded Data (D) And Control (K) Bytes............................................................. 409
Descrambling Of Data (D) Bytes.................................................................................... 410Forwarding Traffic To Link Layer................................................................................. 411
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Chapter 19: SuperSpeed Reset EventsPowerOn Reset ....................................................................................................................... 413
Software May Enable And Disable VBUS.................................................................... 414PowerOn Reset Impact On Device State ...................................................................... 415PowerOn Reset And Self-Powered Devices................................................................. 415
Warm Reset.............................................................................................................................. 416How Warm Reset Is Signaled On The Link ................................................................. 417After Warm Reset Completes......................................................................................... 418
Hot Reset.................................................................................................................................. 418How Hot Reset Is Signaled On The Link...................................................................... 419After Hot Reset Completes ............................................................................................. 420Hot Reset, The LTSSM View .......................................................................................... 420
General Description.................................................................................................. 421Requirements In Hot Reset.Active ......................................................................... 421Exit Rules For Hot Reset.Active.............................................................................. 421Requirements In Hot Reset.Exit.............................................................................. 422Exit Rules For Hot Reset.Exit .................................................................................. 422
Notes About Warm Reset And Hot Reset Latency .......................................................... 423Warm Reset Is Time Consuming, But Thorough ........................................................ 423Hot Reset Is Much Faster, Not As Thorough............................................................... 423
How Does Software Know If Hot Reset Is Possible?...................................................... 423The Two In-Band Reset Hub Requests.............................................................................. 424
SetFeature (BH_PORT_RESET)...................................................................................... 424SetFeature (PORT_RESET) ............................................................................................. 424
Hubs Propagate Resets Downstream ................................................................................. 425General............................................................................................................................... 425Hub Reset Propagation, Key Rules ............................................................................... 426
Chapter 20: Link TrainingLink Training Required Before SuperSpeed Operation ................................................ 427
USB Physical Connections Complicate Link Training ............................................... 428The Long Channel..................................................................................................... 429The Short Channel .................................................................................................... 429
SuperSpeed Link Training Is Adaptive ........................................................................ 429Which Logic Requires Training?......................................................................................... 430
General............................................................................................................................... 430Summary Of Key Link Training Elements................................................................... 431
Receiver Equalization............................................................................................... 431Clock Recovery.......................................................................................................... 432Data Recovery Circuit (DRC).................................................................................. 432
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Serial To Parallel Conversion and Symbol Lock .................................................. 433Differential Polarity Inversion (If Needed)........................................................... 433Elastic Buffer Initialization ...................................................................................... 433
Link Training Is Managed by LTSSM............................................................................... 434The Normal Link Training Sequence ................................................................................ 435
Rx.Detect.Reset ................................................................................................................. 435Normal Exit From Rx.Detect.Reset ........................................................................ 436Other Exits From Rx.Detect.Reset .......................................................................... 436
Rx.Detect.Active............................................................................................................... 437SuperSpeed Receivers Enable & Disable Termination........................................ 438Receiver Common Mode Input Impedance Range.............................................. 438The Detection Method.............................................................................................. 439Normal Exit: From Rx.Detect.Active To Polling .................................................. 441Alternative Exit: From Rx.Detect.Active To Rx.Detect.Quiet............................. 441Other Exits From Rx.Detect.Active ........................................................................ 441
Rx.Detect.Quiet ................................................................................................................ 442Polling.LFPS...................................................................................................................... 443
The Polling.LFPS Burst Format .............................................................................. 443Other Polling.LFPS Requirements And Options ................................................. 444Normal Exit: From Polling.LFPS To Polling.RxEQ.............................................. 444Other Exits From Polling.LFPS ............................................................................... 444
Polling.RxEQ..................................................................................................................... 445Other Requirements In Polling.RxEQ.................................................................... 445The TSEQ Ordered Set ............................................................................................. 446Two Special Symbols In TSEQ................................................................................ 447
Symbol K28.5 (COM) ........................................................................................ 447Symbol 16-31 D10.2 ........................................................................................... 448
Normal Exit: From Polling.RxEQ To Polling.Active ........................................... 449Polling.Active ................................................................................................................... 450
Other Requirements In Polling.Active .................................................................. 450The TS1 Ordered Set................................................................................................. 450Normal Exit: From Polling.Active To Polling.Configuration............................. 451Other Exits From Polling.Active............................................................................. 452
Polling.Configuration...................................................................................................... 452The TS2 Ordered Set................................................................................................. 453Normal Exit: From Polling.Configuration To Polling.Idle ................................. 453Other Exits From Polling.Configuration ............................................................... 454
Polling.Idle ........................................................................................................................ 454General ....................................................................................................................... 454Other Requirements In Polling.Idle ....................................................................... 455
LGOOD_n Advertisement.............................................................................................. 455General ....................................................................................................................... 455
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Format Of LGOOD_n Link Command.................................................................. 456LCRD_x Advertisement.................................................................................................. 457
General ....................................................................................................................... 457Format Of LCRD_x Link Command...................................................................... 458
Port Capability LMP........................................................................................................ 459Port Capability LMP Header Format..................................................................... 460Link Speed Field (DW0, bits 15:9) .......................................................................... 460Num HP Buffers Field (DW1, bits 7:0)................................................................... 460D (Port Direction Support) Field (DW1, bits 17:16) ............................................. 461Tiebreaker Field (DW1, bits 23:20) ......................................................................... 461
Port Configuration LMP ................................................................................................. 462Port Configuration LMP Header Format .............................................................. 463Selected Link Speed Field (DW0, bits 15:9)........................................................... 463
Port Configuration Response LMP................................................................................ 464Port Configuration Response LMP Header Format ............................................ 465Response Code Field (DW0, bits 15:9) ................................................................... 465
Link Training Is Complete, What Now? ........................................................................... 466General............................................................................................................................... 466Life In U0, A Few More Rules ........................................................................................ 466
Chapter 21: Link Recovery and RetrainingReasons For Link Recovery And Retraining..................................................................... 467Recovery And Retraining Managed By The LTSSM ...................................................... 468Recovery Is Speedy................................................................................................................ 469Which Logic Is Retrained In Recovery?............................................................................. 470Entering Recovery: Two Common Examples ................................................................... 471
U1-U3 Exit And Transition To Recovery...................................................................... 471U0 Link Layer Error And Transition To Recovery ..................................................... 472
The Recovery Substate Events............................................................................................. 474Recovery.Active ............................................................................................................... 474
Other Requirements In Recovery.Active............................................................... 474Recovery.Active And The TS1 Ordered Set.......................................................... 475Two Special Symbols In TS1 Ordered Sets ........................................................... 475
Symbol K28.5 (COM) ........................................................................................ 475Symbol 6-15 D10.2 ............................................................................................. 476
Normal Exit: Recovery.Active To Recovery.Configuration ............................... 477Other Exits From Recovery.Active......................................................................... 478
Recovery.Configuration.................................................................................................. 478Recovery.Configuration And The TS2 Ordered Set ............................................ 478Normal Exit: From Recovery.Configuration To Recovery.Idle ......................... 479Other Exits From Recovery.Configuration ........................................................... 479
Recovery.Idle .................................................................................................................... 479
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General ....................................................................................................................... 479Other Requirements In Recovery.Idle ................................................................... 480
LGOOD_n Advertisement.............................................................................................. 480A Simple Example .................................................................................................... 480Format Of LGOOD_n Link Command.................................................................. 481
LCRD_x Advertisement.................................................................................................. 482General ....................................................................................................................... 482A Simple Example .................................................................................................... 482
For More Details On The LTSSM Recovery ..................................................................... 483
Chapter 22: Device ConfigurationOverview.................................................................................................................................. 485Standard Device Requests.................................................................................................... 486Device Detection and Reporting ......................................................................................... 488Device Detection Process — Details................................................................................... 489
Status Change Indicator (Endpoint 1)........................................................................... 489Hub Port Status and Change Indicators ....................................................................... 491Get Port Status Request................................................................................................... 495Clear Port Connection Request ...................................................................................... 496
The Device Configuration Process ..................................................................................... 498Address Device ................................................................................................................ 498Getting the Descriptors ................................................................................................... 499
General ....................................................................................................................... 499Standard Descriptors................................................................................................ 500
Device Descriptor............................................................................................................. 502Descriptor Length and Type ................................................................................... 504DeviceClass/SubClass/Protocol .............................................................................. 504Maximum Payload Size for Endpoint Zero (EP0)................................................ 505String Index Values .................................................................................................. 505
BOS Descriptor ................................................................................................................. 506USB 2.0 Extension ..................................................................................................... 507SuperSpeed USB Device Capability....................................................................... 508Container ID .............................................................................................................. 509
Configuration Descriptor................................................................................................ 510Number of Interfaces................................................................................................ 512Configuration Value................................................................................................. 512Attributes and Maximum Power............................................................................ 512
Interface Association Descriptor.................................................................................... 512Interface Descriptors........................................................................................................ 513
General ....................................................................................................................... 513Interface Number and Alternate Setting ............................................................... 514
Endpoint Descriptors ...................................................................................................... 516
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Endpoint Companion Descriptor .................................................................................. 518String Descriptors ............................................................................................................ 519Setting Device Configuration ......................................................................................... 521Additional Requests ........................................................................................................ 522Class Driver Initialization............................................................................................... 522
Chapter 23: SuperSpeed Hub ConfigurationConfiguring the Hub ............................................................................................................. 523Standard Device Requests.................................................................................................... 524Device Detection and Reporting ......................................................................................... 525
General............................................................................................................................... 525Device Detection Process ................................................................................................ 526
Status Change Endpoint (Endpoint 1) ................................................................... 527Hub Port Status and Change Indicators................................................................ 528Get Port Status Request............................................................................................ 532Clear Port Request .................................................................................................... 533
The Hub Configuration Process.......................................................................................... 534Addressing the Device .................................................................................................... 534Getting Descriptors.......................................................................................................... 535
General ....................................................................................................................... 535Get Device Descriptor .............................................................................................. 538
BOS Descriptor ................................................................................................................. 540USB 2.0 Extension ..................................................................................................... 541SuperSpeed USB Device Capability....................................................................... 541Container ID .............................................................................................................. 543
Configuration Descriptor................................................................................................ 544Configuration Value................................................................................................. 545Bus- or Self-Powered Hub ....................................................................................... 545Maximum Bus Power Consumed .......................................................................... 546
Hub’s Interface Descriptor.............................................................................................. 546Status Change Endpoint Descriptor.............................................................................. 547
General ....................................................................................................................... 547Hub Status Change Endpoint Address/Transfer Direction................................ 548
Status Change Endpoint Companion Descriptor........................................................ 549String Descriptors ............................................................................................................ 549Additional Requests ........................................................................................................ 550
Hub Driver Initialization ..................................................................................................... 550Hub Class Descriptor ...................................................................................................... 550
Power Switching Mode Implemented ................................................................... 553Over-Current Protection Mode............................................................................... 554Maximum Bus Current for Hub Controller .......................................................... 554Device Removable/Non-removable ....................................................................... 554
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Hub-Specific Requests..................................................................................................... 554Set Hub Depth ........................................................................................................... 554Port U1/U2 Timeout ................................................................................................. 556Set Port Remote Wake Mask ................................................................................... 556Port Link State ........................................................................................................... 557Set Port Power ........................................................................................................... 557Port Reset ................................................................................................................... 558BH Port Reset............................................................................................................. 558
Hub Status Change Endpoint Request ......................................................................... 559Reading the Hub Status Field......................................................................................... 559Reading Hub Port Status ................................................................................................ 559
Summary of Hub Feature Selectors .................................................................................... 560
Chapter 24: SuperSpeed Power ManagementPrinciples of SuperSpeed Power Management................................................................ 563
Background....................................................................................................................... 564Power Management Design Goals ................................................................................ 565
Link Power Management ........................................................................................ 565Function Power Management................................................................................. 566Suspend/Resume (U3).............................................................................................. 566
SuperSpeed Link Power Management .............................................................................. 566The Link Power States..................................................................................................... 566 Link-Power Hierarchy.................................................................................................... 568
Software Role in Link Power Management...................................................................... 569Host Software Triggers ................................................................................................... 569Hub Inactivity Timers ..................................................................................................... 570
U1 Inactivity Timeouts............................................................................................. 571U2 Inactivity Timeouts............................................................................................. 572U0 Æ U1 Æ U2 with Silent Transition ................................................................... 573
Device-Specific Inactivity Timers/Algorithms............................................................. 574Upstream and Downstream U1/U2 Triggers............................................................... 575
The Handshake Sequence .................................................................................................... 576Entering The U1 and U2 States ...................................................................................... 576U1 / U2 Handshake and Timer Behavior ..................................................................... 577
Device Suspend — U3........................................................................................................... 578General............................................................................................................................... 578Entering SuperSpeed Suspend....................................................................................... 579
The U3 Handshake ................................................................................................... 579Device Suspend State ............................................................................................... 580
U1/U2/U3 Exit to U0 ............................................................................................................... 580Triggering U1/U2/U3 Exit............................................................................................... 580The Handshake Sequence............................................................................................... 581
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General ....................................................................................................................... 581The LFPS Handshake ............................................................................................... 582
Function Suspend .................................................................................................................. 583General............................................................................................................................... 583The Function Suspend Request...................................................................................... 583
Latency Tolerance Message Reporting .............................................................................. 584
Chapter 25: SuperSpeed Signaling RequirementsPhysical Layer Electrical Signaling Scope......................................................................... 591Normative And Informative Specifications...................................................................... 593Jitter Budgeting (Informative) ............................................................................................. 593
General............................................................................................................................... 593Jitter Budget Allocations ................................................................................................. 594
SuperSpeed Voltage Levels, Some Definitions ............................................................... 595SuperSpeed Transmitter Requirements ............................................................................ 596
Tx Electrical Specifications ............................................................................................. 596Normative Tx Electrical Parameters ...................................................................... 596Informative Tx Electrical Parameters..................................................................... 598
Transmitter Low Power Option..................................................................................... 599Transmitter De-emphasis................................................................................................ 600
Background................................................................................................................ 600Transmitter Signal De-emphasis Helps................................................................. 601
Transmitter Spread Spectrum Clocking (SSC)............................................................. 603SuperSpeed Receiver Requirements .................................................................................. 605
Rx Electrical Specifications ............................................................................................. 605Normative Rx Parameters ....................................................................................... 606Informative Rx Parameters...................................................................................... 607
Rx Equalizer Training...................................................................................................... 608SuperSpeed Receiver Termination ................................................................................ 609
Receiver Common Mode Input Impedance Range.............................................. 610The Detection Method.............................................................................................. 610
Low Frequency Periodic Signaling Requirements .......................................................... 612LFPS Is A Simple Squarewave ....................................................................................... 613Six LFPS Signaling Event Types .................................................................................... 613LFPS Electrical Requirements ........................................................................................ 614
Transmitter And Receiver DC Specifications .................................................................. 615High Impedance Reflections (Normative) ................................................................... 615ESD Protection (Informative) ......................................................................................... 615Short Circuit Requirements (Informative) ................................................................... 616
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Chapter 26: Compliance TestingScope Of USB 3.0 Compliance Testing.............................................................................. 617Key Compliance Testing Documents................................................................................. 618
Compliance Testing Resources: Documentation......................................................... 619Compliance Testing Resources: Hardware/Software ................................................. 619
The Compliance Testing Environment.............................................................................. 620Key Test Suite 1: USB Command Verifier Compliance ................................................. 620
General Approach USB Command Verification Tests ............................................... 621Test Assertions ................................................................................................................. 621
USB Device State Test Assertions........................................................................... 623Generic Device Operation Test Assertions ........................................................... 623USB Device Request Test Assertions ..................................................................... 624USB Descriptor Definition Test Assertions........................................................... 624
Nineteen Tests Used In USB Command Verification ................................................. 624Key Test Suite 2: Link Layer Compliance ......................................................................... 626
General Approach In Link Layer Compliance Tests .................................................. 626Test Assertions ................................................................................................................. 626
Link Management & Flow Control Test Assertions ............................................ 627Link Error Rules & Recovery Test Assertions ...................................................... 628Link Reset Test Assertions....................................................................................... 628LTSSM Test Assertions ............................................................................................ 628Protocol Layer Test Assertions ............................................................................... 629Hub Port Test Assertions......................................................................................... 629
Forty Tests Are Used In Link Layer Testing ................................................................ 629Electrical Compliance Testing ............................................................................................. 632
Factors Affecting USB Electrical Compliance Testing................................................ 632Electrical Compliance And The Varied USB Topology.............................................. 633
The Long Channel..................................................................................................... 633The Short Channel .................................................................................................... 634
USB 3.0 Adds Even More Complexity .......................................................................... 634Electrical Compliance Test Support Is Designed In.................................................... 634LTSSM Compliance Mode: Device Roles ..................................................................... 635Nine Compliance Mode Test Patterns .......................................................................... 636Electrical Compliance Testing And The LTSSM ......................................................... 637
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Chapter 27: Receiver Loopback TestingLoopback Motivation ............................................................................................................ 639Standard Loopback Configuration ..................................................................................... 639
General Master And Slave Loopback Rules................................................................. 640The Loopback Test Pattern BERT Data (BDAT) .......................................................... 641
Optional Loopback Slave Error Counting Support......................................................... 641Loopback BERT Ordered Sets ............................................................................................. 642
BERT Reset (BRST)........................................................................................................... 643BDAT Error Count Request (BERC).............................................................................. 643BDAT Error Count (BCNT) Value................................................................................. 644
Slave BERT Command Processing Rules .......................................................................... 644General............................................................................................................................... 644BRST & BERC If No Slave Error Counting Support ................................................... 645
Loopback And The LTSSM.................................................................................................. 645General............................................................................................................................... 645Loopback LTSSM Substates And Transition Events................................................... 646
Loopback.Active Substate ....................................................................................... 646Loopback.Exit Substate ............................................................................................ 648A Note About Differences In Loopback Exit Latency ......................................... 649
Loopback May Also Be Used In Compliance Testing .................................................... 650
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List of Figures
1-1 SuperSpeed Link Interface ............................................................................................. 91-2 USB 2.0 vs SS OUT Transaction Protocols ................................................................. 122-1 Eight-Port Companion Controller Built into Chipset............................................... 202-2 Companion Controller and Register Sets................................................................... 212-3 Example Companion Controller with Root Hubs .................................................... 232-4 External Full-Speed and High-Speed Hubs............................................................... 242-5 Hub Depth ...................................................................................................................... 252-6 Low-Speed Packet Broadcast ....................................................................................... 262-7 HS Broadcast and HS Split Transactions ................................................................... 272-8 Standard Device Descriptor Tree ................................................................................ 292-9 Device Endpoints and Associated Buffers ................................................................. 302-10 Token-Data-Handshake Packet Types and Elements .............................................. 342-11 Example IN Transaction FS or HS............................................................................... 342-12 Example OUT Transaction FS or HS........................................................................... 352-13 Low-Speed Packet from Host Controller ................................................................... 352-14 Three Stage Control Transfer (Read) .......................................................................... 362-15 Two-Stage Control Transfer......................................................................................... 372-16 OUT Data NAK vs Ping Protocol Solution ................................................................ 382-17 Ping Protocol Sequence................................................................................................. 392-18 Major High-Speed Hub Functions .............................................................................. 402-19 Split Transaction Sequence - Bulk IN Transfer ......................................................... 412-20 Transaction Generation................................................................................................. 432-21 Frames and MicroFrames ............................................................................................. 442-22 Frame Lists Executed by UHCI Controller ................................................................ 443-1 Example USB 3.0 Host Controller and Topology ..................................................... 483-2 Transmit and Receive Differential Pairs..................................................................... 493-3 The USB 3.0 Cable Interface ......................................................................................... 523-4 SS Signaling Environments .......................................................................................... 533-5 Powered B Connection Examples ............................................................................... 553-6 SS Interface Layers and Protocols ............................................................................... 563-7 Hub Bypasses the Protocol Layers When Forwarding Packets .............................. 593-8 Hub as Target Device.................................................................................................... 593-9 Hub as Target Device with LMP Delivery................................................................. 603-10 Example of End-to-End Communication................................................................... 613-11 IN Transaction — Token/Data/Handshake versus End-to-End Protocols............ 623-12 OUT Transaction — Token/Data/Handshake versus End-to-End Protocols........ 643-13 Port-to-Port Protocol Between Link Partners ............................................................ 653-14 SuperSpeed Descriptors................................................................................................ 673-15 USB 2.0 vs USB SS Bus Idle .......................................................................................... 684-1 SuperSpeed Headers Support IN, OUT and Setup Tokens..................................... 734-2 IN Burst Example with Maximum Payload Size of Four ........................................ 744-3 Example UASP Structure.............................................................................................. 75
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5-1 Protocol Layer Overview and Packet Types.............................................................. 805-2 Basic Header Packet ...................................................................................................... 815-3 Transaction Packet - Basic Format .............................................................................. 825-4 ACK Header Fields - Moving Downstream .............................................................. 845-5 ACK Header Fields - Moving Upstream.................................................................... 855-6 NRDY Header Fields..................................................................................................... 875-7 ERDY Header Fields ..................................................................................................... 885-8 Status Header Packet..................................................................................................... 905-9 Stall Header Fields......................................................................................................... 915-10 Function Wake Notification Header — Header Moves Upstream ........................ 935-11 Latency Tolerance Message Header ........................................................................... 945-12 Bus Interval Adjustment Message Header ................................................................ 955-13 PING Header Fields — Header Moving Downstream ............................................ 975-14 PING RESPONSE Header — Header Moving Upstream........................................ 985-15 Data Header and Payload Moving Downstream ................................................... 1005-16 Data Header and Payload Moving Upstream......................................................... 1025-17 Isochronous Timestamp Header ............................................................................... 1046-1 Two-Stage Control Transfer....................................................................................... 1076-2 Three Stage Control Transfer Structure (IN or OUT)............................................. 1086-3 Example Three-Stage Transfer with Single IN Transaction .................................. 1086-4 Example Two-Packet Data Stage............................................................................... 1096-5 Example Two-Packet OUT Data Stage ..................................................................... 1096-6 DATA Header — Setup Request ............................................................................... 1116-7 Setup Data Fields Showing Byte Order of Packet Transmission Across the Link ...1146-8 STATUS Header Format and Content...................................................................... 1156-9 Set Address Request Data .......................................................................................... 1176-10 Control Transfer Protocol — Two-Stage Transfer .................................................. 1186-11 Get Device Descriptor Request Data......................................................................... 1196-12 Three-Stage Get Device Descriptor Protocol ........................................................... 1216-13 Variable Length Data During Control Read Operation (with Short Packet) ...... 1226-14 Variable Length Data During Control Read Operation (No Short Packet)......... 1237-1 Bulk IN Transaction — Burst of One DATA packet............................................... 1297-2 Bulk IN Transfer — Burst of Four DATA Packets .................................................. 1307-3 IN Burst Transaction with Large Transfer ............................................................... 1317-4 NRDY Flow Control at Start of Transfer .................................................................. 1337-5 IN Burst Flow Control Using EOB ............................................................................ 1347-6 IN Burst Flow Control Using NRDY ........................................................................ 1357-7 DATA Header and Payload ....................................................................................... 1367-8 Example Bulk IN Burst with DATA Packet Error .................................................. 1377-9 Bulk OUT Transaction — Burst of One DATA packet........................................... 1397-10 Bulk OUT Burst of Four DATA Packets................................................................... 140
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List of Figures
7-11 OUT Burst with Large Transfer................................................................................. 1417-12 NRDY Flow Control at Start of Transfer .................................................................. 1437-13 OUT Transaction Burst Flow Control Example ...................................................... 1447-14 Example Bulk OUT Burst with DATA Packet Error .............................................. 1457-15 Standard And Bulk Streaming Endpoints ............................................................... 1477-16 BOT Drive Endpoints And System Resources ........................................................ 1517-17 UASP Streaming Drive Endpoints And System Resources .................................. 1557-18 UAS Non-Data Command ......................................................................................... 1587-19 UASP Non-Data Sequence ......................................................................................... 1597-20 UAS Read DMA Sequence ......................................................................................... 1617-21 UASP Read DMA Protocol......................................................................................... 1627-22 UAS Write DMA Sequence ........................................................................................ 1647-23 UASP Write DMA Sequence...................................................................................... 1658-1 Interrupt with Single DATA Packet Per Interval.................................................... 1698-2 Interrupt IN Burst Example with Service Interval of 64 ........................................ 1708-3 Interrupt IN with NRDY ............................................................................................ 1718-4 Interrupt IN Transaction with EOB .......................................................................... 1728-5 Interrupt IN with Retry in Next Service Interval.................................................... 1748-6 Interrupt IN Retry Example ....................................................................................... 1758-7 Interrupt OUT Burst.................................................................................................... 1778-8 Interrupt OUT with NDRY ........................................................................................ 1788-9 Interrupt OUT Burst with End of Burst.................................................................... 1798-10 Interrupt OUT — Retry............................................................................................... 1809-1 Maximum Number of Bursts per Service Interval.................................................. 1829-2 Isochronous Service Interval Examples.................................................................... 1839-3 Scheduling Options for Load Balancing within an Isochronous Service Interval ...1849-4 Isochronous Timestamp Packet Delivery Example ................................................ 1859-5 Isochronous Timestamp Packet Format ................................................................... 1869-6 Bus Interval Adjustment Message ............................................................................ 1899-7 Ping and Ping Response Packet Format................................................................... 1919-8 Isochronous IN Sequence with Bursts of Two ........................................................ 1939-9 Isochronous IN with Burst of Two, Zero Payload, and Burst of One.................. 1949-10 Isochronous IN with Maximum Burst Size.............................................................. 1959-11 Isochronous OUT Burst of 16..................................................................................... 1969-12 Isochronous OUT with Four Service Intervals ........................................................ 1979-13 ACK/DATA Header Fields Used to Manage Smart Isochronous Scheduling ... 1989-14 Isochronous IN Smart Scheduling Example with Pings........................................ 2019-15 Smart Scheduling Associated with Isochronous IN Transfers ............................. 2029-16 Isochronous OUT Transactions with Smart Scheduling Example ....................... 20410-1 Basic Block Diagram of USB 3.0 Hub........................................................................ 20610-2 Hub Connectivity — Downstream and Upstream ................................................. 208
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USB 3.0 Technology
10-3 Packet Routing — Link Layer to Link Layer ........................................................... 20910-4 Transaction Targeting Hub ........................................................................................ 21010-5 Transaction Targeting Hub with Port LMP............................................................. 21110-6 Route String .................................................................................................................. 21210-7 SuperSpeed Unicast Routing Example..................................................................... 21310-8 Buffers Used When Forwarding Packets ................................................................. 21410-9 DATA Payload Buffering Required by Specification............................................. 21510-10 Deferred Transaction Example .................................................................................. 21710-11 Header Bits Set During Deferral................................................................................ 21811-1 Port-To-Port Protocol And Link Layer Role ............................................................ 22211-2 Link Layer Header Packet Processing, Key Fields ................................................. 22311-3 Link Layer Header Processing Elements ................................................................. 22411-4 Link Management Elements ...................................................................................... 22711-5 Header Packet Framing Ordered Set ....................................................................... 23211-6 Good Data Packet Framing Ordered Sets ................................................................ 23311-7 Nullified Data Packet Framing Ordered Sets .......................................................... 23411-8 Link Command Framing Ordered Sets .................................................................... 23511-9 TSEQ Ordered Sets Train Receiver Equalizer ......................................................... 23611-10 TS1 Ordered Set ........................................................................................................... 23711-11 TS2 Ordered Set ........................................................................................................... 23811-12 Skip Ordered Set .......................................................................................................... 23911-13 Loopback BERT Ordered Sets.................................................................................... 24012-1 Link Training And Status State Machine (LTSSM)................................................. 24412-2 LFPS Signaling Used In LTSSM Handshake ........................................................... 25112-3 Ordered Sets Used In LTSSM Transition Handshake............................................ 25212-4 Link Commands Used For LTSSM Power Management Transitions.................. 25312-5 LTSSM U0 State............................................................................................................ 25612-6 LTSSM U1 State............................................................................................................ 25912-7 LTSSM U2 State............................................................................................................ 26112-8 LTSSM U3 State............................................................................................................ 26312-9 LTSSM Rx.Detect State................................................................................................ 26512-10 LTSSM Polling State .................................................................................................... 26812-11 LTSSM Recovery.......................................................................................................... 27412-12 LTSSM Hot Reset ......................................................................................................... 27812-13 LTSSM Compliance Mode.......................................................................................... 28112-14 LTSSM Loopback......................................................................................................... 28312-15 LTSSM SS.Inactive State ............................................................................................. 28512-16 LTSSM SS.Disabled State............................................................................................ 28713-1 Link Command Word Fields ..................................................................................... 29013-2 Framed Link Command On The SuperSpeed Link................................................ 29113-3 LGOOD_n Link Command On The SuperSpeed Link .......................................... 29213-4 LBAD Link Command On The SuperSpeed Link................................................... 293
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List of Figures
13-5 LRTY Link Command On The SuperSpeed Link ................................................... 29413-6 LCRD_x Link Command On The SuperSpeed Link............................................... 29513-7 LGO_Ux Link Command On The SuperSpeed Link.............................................. 29613-8 LAU Link Command On The SuperSpeed Link ..................................................... 29713-9 LXU Link Command On The SuperSpeed Link ..................................................... 29813-10 LPMA Link Command On The SuperSpeed Link.................................................. 29913-11 LDN Link Command On The SuperSpeed Link..................................................... 30013-12 LUP Link Command On The SuperSpeed Link...................................................... 30114-1 Link Layer Tx And Rx Packet Processing Scope..................................................... 30414-2 Key Transmitter Packet Processing Functional Blocks .......................................... 30514-3 Transmitter Assigns Header Packet Sequence Number (HDR Seq#) .................. 30614-4 Transmitter Generates Header Link Control Word CRC-5................................... 30714-5 Transmitter Generates Header CRC-16.................................................................... 30814-6 Header Packet Buffers Hold A Copy Of Each Header........................................... 30914-7 Data Packet Payload Requires CRC-32 Generation................................................ 31014-8 Transmitter’s DPP CRC-32 Generation Logic ......................................................... 31114-9 Transmitter Adds Ordered Set Framing To Outbound Packets........................... 31214-10 Receiver Accepts Inbound Packets And Link Commands.................................... 31314-11 Key Receiver Packet Processing Functional Blocks................................................ 31414-12 Receiver Checks Header Packet CRC-16.................................................................. 31514-13 Receiver Checks Header Link Control Word CRC-5 ............................................. 31614-14 Receiver Checks Header Sequence Number ........................................................... 31714-15 Receiver Header Packet Buffet Accepts Header ..................................................... 31814-16 Receiver Checks Data Packet Payload (DPP) CRC-32 ........................................... 31914-17 Receiver’s DPP CRC-32 Checking Logic .................................................................. 32015-1 Asynchronous Traffic May Contribute To Link Flow Control Problems ........... 32315-2 Elements Of USB 3.0 Link Level Flow Control ....................................................... 32515-3 Format Of LCRD_X Link Command Variants ........................................................ 32815-4 Link Level Flow Control Logic After Reset ............................................................. 32915-5 Flow Control Logic Initialization .............................................................................. 33015-6 The First Header Packet Is Processed And Sent ..................................................... 33115-7 The First Header Packet Arrives At The Receiver .................................................. 33215-8 Rx HP Buffer Is Available, Credit Returned............................................................ 33315-9 Transmitter Receives A Flow Control Credit .......................................................... 33415-10 Transmitter Receives A Valid LCRD_x .................................................................... 33515-11 Transmitter Receives An Invalid LCRD_x............................................................... 33616-1 Link Errors Are Affected By The Channel ............................................................... 34116-2 Upstream Asynchronous Packet Encounters An Error ......................................... 34216-3 Elements Of Link Level Header Packet Acknowledgement ................................. 34616-4 Format Of LGOOD_n Link Command Variants..................................................... 35216-5 Format Of The LBAD Link Command ..................................................................... 35316-6 Format Of The LRTY Link Command...................................................................... 354
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USB 3.0 Technology
16-7 Link Level Header Packet Acknowledgement Logic After Reset ........................ 35516-8 Initial Header Packet Sequence Number Advertisement...................................... 35616-9 The First Header Packet Is Processed And Sent ..................................................... 35816-10 Header Packet CRC-5, CRC-16 Checked.................................................................. 35916-11 Header Packet Sequence Number Is Checked ........................................................ 36016-12 Receiver Accepts And Acknowledges A Valid Header Packet ............................ 36116-13 Transmitter Checks LGOOD_n Link Command .................................................... 36216-14 Transmitter Retires A Header Packet ....................................................................... 36316-15 A Header Packet Is Processed And Sent .................................................................. 36416-16 Header Packet CRC-5, CRC-16 Check Fails, LBAD Sent ....................................... 36516-17 Transmitter Receives LBAD, Starts Retry Sequence............................................... 36616-18 Retry Header Packet CRC-5, CRC-16 Is Checked................................................... 36716-19 Retry Header Packet Sequence Number Is Checked.............................................. 36816-20 Receiver Accepts And Acknowledges The Retry Header Packet......................... 36916-21 Transmitter Validates LGOOD_n Received After Retry........................................ 37016-22 Transmitter Retires The Header Packet After Retry............................................... 37117-1 Chip-To-Chip Protocol And Physical Layer Role................................................... 37417-2 Common Traffic And Data/Control Bytes ............................................................... 37617-3 Physical Layer Logical Processing: Scope................................................................ 37717-4 Physical Layer Electrical Specifications: Scope ....................................................... 38018-1 Physical Layer Tx And Rx Logical Section .............................................................. 38418-2 Transmitter Outbound Bytes And The D/K Flag.................................................... 38518-3 Transmitter PHY Logic Scrambling .......................................................................... 38718-4 TS2 Scrambling Disable Bit ........................................................................................ 38818-5 Transmitter PHY 8b/10b Encoding ........................................................................... 38918-6 8b/10b Encoding Supports Link CRD Scheme ........................................................ 39118-7 Transmitter PHY Parallel To Serial Data Conversion ............................................ 39418-8 The Differential Transmitter ...................................................................................... 39518-9 The Differential Receiver, Termination, And Equalizer ........................................ 39618-10 Receiver PHY Clock And Data Recovery Logic...................................................... 39718-11 Receiver PHY Serial To Parallel Data Conversion.................................................. 39918-12 COM Is Used To Achieve Symbol Lock ................................................................... 40018-13 Receiver PHY Corrects Differential Polarity Inversion.......................................... 40118-14 Receiver PHY Elastic Buffer ....................................................................................... 40218-15 Elastic Buffer Spans Two Receiver Clock Domains................................................ 40418-16 Clocking Symbols Into And Out Of The Elastic Buffer.......................................... 40618-17 Transmitter Inserts Skip (SKP) Ordered Sets .......................................................... 40718-18 Receiver PHY 8b10b Decode...................................................................................... 40818-19 Receiver PHY Decoder Use Of The D/K Flag.......................................................... 40918-20 Receiver PHY Descrambling Hardware Details ..................................................... 41018-21 Receiver PHY Forwards Traffic To Link Layer ....................................................... 41119-1 Enabling VBUS Triggers PowerOn Reset................................................................. 414
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List of Figures
19-2 3.0 Hub Receives A Request To Perform Warm Reset........................................... 41619-3 Warm Reset LFPS Signaling Sent And Received .................................................... 41719-4 3.0 Hub Receives A Request To Perform Hot Reset ............................................... 41919-5 LTSSM Hot Reset State And Substates..................................................................... 42019-6 USB 3.0 Hub Propagates Resets To Downstream Ports......................................... 42620-1 An Example Server System With Short And Long USB 3.0 Channels ............... 42820-2 Link Training & Receiver Physical Layer Logic...................................................... 43020-3 Link Training Sequence And LTSSM States ............................................................ 43420-4 Link Training Is Delayed Until Warm Reset Ends ................................................. 43520-5 Warm Reset LFPS Characteristics ............................................................................. 43620-6 Checking For A Link partner In Rx.Detect.Active.................................................. 43720-7 Receiver Enables & Disables Low-Impedance Termination ................................. 43820-8 SuperSpeed Transmitter Detects Receiver Termination ........................................ 43920-9 Rx Detect Equivalent Circuits .................................................................................... 44020-10 Conserving Power In Rx.Detect.Quiet If Link Partner Isn’t Present.................... 44220-11 Link Traffic Starts With Low Frequency Periodic Signaling (LFPS).................... 44320-12 Characteristics Of The Polling.LFPS Burst Sequence ............................................. 44420-13 Devices Send SuperSpeed TSEQ Ordered Sets For Receiver Equalization......... 44520-14 COM Symbol Bit Pattern Is Easily Recognized By Receiver ................................. 44720-15 Normal Transmitter And Receiver Differential Polarity ....................................... 44820-16 Differential Polarity Inversion Corrected By The Receiver ................................... 44920-17 TS1 Ordered Sets Appear On The Link In Polling.Active ..................................... 45020-18 TS1 Ordered Set Format ............................................................................................. 45120-19 TS2 Ordered Sets In Polling.Configuration Signal End Of Link Training .......... 45220-20 TS2 Ordered Set Format ............................................................................................. 45320-21 Idle Symbols Confirm That The Next State Is U0 ................................................... 45420-22 LGOOD_n Link Command Advertises Header Packet Sequence Number ....... 45520-23 Format Of LGOOD_n Link Command..................................................................... 45620-24 LCRD_x Link Commands Initialize Header Packet Flow Control ...................... 45720-25 Format Of LCRD_x Link Command......................................................................... 45820-26 Devices Exchange First Header Packets, Port Capability LMP ............................ 45920-27 Port Capability LMP Header Format........................................................................ 46020-28 Downstream Facing Port Sends Port Configuration LMP .................................... 46220-29 Port Configuration LMP Header Format ................................................................. 46320-30 Upstream Facing Port Sends Port Configuration Response LMP........................ 46420-31 Port Configuration Response LMP Header Format ............................................... 46521-1 LTSSM Recovery State, Substates, Entry, And Exits .............................................. 46821-2 Receiver PHY Logic Retrained During Recovery ................................................... 47021-3 U1-U3 Exit Followed By A Transition To LTSSM Recovery ................................ 47121-4 U0 Link Layer Error Causes A Transition To LTSSM Recovery ......................... 47321-5 Recovery.Active Employs TS1 Ordered Sets........................................................... 47421-6 COM Symbol Bit Pattern Is Easily Recognized By Receiver ................................. 475
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USB 3.0 Technology
21-7 Normal Transmitter And Receiver Differential Polarity ....................................... 47621-8 Differential Polarity Inversion Corrected By The Receiver ................................... 47721-9 Recovery.Configuration Employs TS2 Ordered Sets ............................................. 47821-10 Logical Idle Symbols Confirm That A Return To U0 Is Next ............................... 47921-11 LGOOD_n Link Command Advertises Header Packet Sequence Number ....... 48121-12 Format Of LGOOD_n Link Command..................................................................... 48121-13 LCRD_x Link Commands Initialize Header Packet Flow Control ...................... 48222-1 Hub Status Change Indicator..................................................................................... 48922-2 Hub Status Change Indicator..................................................................................... 49122-3 SuperSpeed Descriptors.............................................................................................. 50022-4 Descriptor Tree Containing Alternate Interface Settings....................................... 51523-1 Hub and Port Status .................................................................................................... 52823-2 SuperSpeed Descriptors.............................................................................................. 53623-3 Hub Depth Assignment.............................................................................................. 55524-1 All SS Links Remain Powered Without Link Power Management...................... 56424-2 LTSSM and Link Power States and Transitions...................................................... 56724-3 Link Power State Hierarchy ....................................................................................... 56824-4 Inactivity Timers .......................................................................................................... 57024-5 Silent Transitions — LMP........................................................................................... 57324-6 LMP — Inactivity Timeout......................................................................................... 57424-7 Link Partner Handshake - U0 to U1 or U2............................................................... 57724-8 Function Wake Notification Packet .......................................................................... 58124-9 U1/U2/U3 LFPS Exit Signaling .................................................................................. 58224-10 Function Suspend Request — Setup Transaction Data.......................................... 58424-11 PEL and SEL Reported Parameters........................................................................... 58524-12 System Exit Latency Calculation ............................................................................... 58624-13 Latency Tolerance Message Header ......................................................................... 58825-1 Physical Layer Tx And Rx Electrical Section ........................................................... 59225-2 Effects Of Jitter On SuperSpeed Eye ......................................................................... 59325-3 Differential And Single-Ended Voltage Levels ....................................................... 59525-4 SuperSpeed Transmitter Elements............................................................................ 59625-5 Inter Symbol Interference (ISI) Example .................................................................. 60025-6 Transmitter De-emphasis Example (Peak-to-Peak Voltage) ................................. 60225-7 Comparison Of ISI With, Without De-emphasis .................................................... 60325-8 Triangular SSC Modulation Example....................................................................... 60425-9 SuperSpeed Receiver PHY Electrical Elements....................................................... 60525-10 SuperSpeed Receiver Equalization ........................................................................... 60825-11 TSEQ Frequency Spectrum ........................................................................................ 60925-12 Receiver Enables & Disables Low-Impedance Termination ................................. 61025-13 SuperSpeed Transmitter Detects Receiver Termination ........................................ 61125-14 Rx Detect Equivalent Circuits .................................................................................... 61225-15 Transmitter And Receiver LFPS Signaling Logic.................................................... 613
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List of Figures
26-1 Scope Of Three Key USB 3.0 SuperSpeed Compliance Tests................................ 61826-2 Compliance Testing Accounts For Long & Short Channels................................. 63326-3 Compliance Mode Test Configuration ..................................................................... 63526-4 Compliance LTSSM State ........................................................................................... 63727-1 Loopback Master And Slave ...................................................................................... 64027-2 Loopback Ordered Sets & Slave BERT Logic .......................................................... 64227-3 Loopback LTSSM State And Substates..................................................................... 64527-4 Loopback LTSSM Substate Requirements & Transitions ...................................... 64627-5 TS2 Loopback Entry Signaling................................................................................... 64727-6 Loopback Exit Through Recovery............................................................................. 649
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USB 3.0 Technology
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List of Tables
1 PC Architecture Book Series .......................................................................................... 11-1 USB Bandwidth Comparison......................................................................................... 91-2 Download Time Comparison ...................................................................................... 102-1 Motivations for USB ...................................................................................................... 182-2 Standard Device Requests ............................................................................................ 312-3 Standard Features Supported for Get/Set Feature Request..................................... 322-4 USB 2.0 Maximum Payload Sizes................................................................................ 373-1 Plug and Respectable Compatibility........................................................................... 503-2 USB 3.0 Cable Assemblies ............................................................................................ 544-1 Protocol Packet Types and Characteristics ................................................................ 724-2 General Endpoint Characteristics ............................................................................... 765-1 Protocol-Layer Packet Categories and Characteristics............................................. 815-2 Transaction Packet Sub Types ..................................................................................... 825-3 ACK Header Field Descriptions — Header Moving Downstream........................ 845-4 ACK Header Field Descriptions — Header Moving Upstream ............................. 865-5 NRDY Header Field Descriptions — Header Moving Upstream .......................... 875-6 ERDY Header Field Descriptions — Header Moving Upstream ........................... 895-7 STATUS Header Field Descriptions — Header Moving Downstream ................. 905-8 STALL Header Field Descriptions — Header Moving Upstream.......................... 925-9 Wake Notification Header Field Descriptions — Header Moves Upstream........ 935-10 Latency Tolerance Message Header Field Descriptions .......................................... 945-11 Bus Interval Adjustment Header Field Descriptions ............................................... 965-12 PING Header Field Descriptions — Header Moving Downstream....................... 975-13 PING RESPONSE Header Field Descriptions ........................................................... 985-14 DATA Header Field Descriptions — Header Moving Downstream................... 1005-15 DATA Header Field Descriptions — Header Moving Upstream ........................ 1025-16 ISOCHRONOUS TIMESTAMP Header Field Descriptions.................................. 1046-1 Setup Stage Request Data ........................................................................................... 1127-1 SuperSpeed Endpoint Companion Descriptor........................................................ 1277-2 Timing Parameters for IN and OUT Transaction Protocol.................................... 1467-3 Stream ID Values and Descriptions .......................................................................... 1497-4 Endpoint Companion Descriptor Streaming Support ........................................... 1509-1 Descriptions for the Smart Isochronous Fields ....................................................... 19911-1 Control (K) Symbols .................................................................................................... 23111-2 Loopback BRST Ordered Set...................................................................................... 24111-3 Loopback BERC Ordered Set ..................................................................................... 24111-4 Loopback BCNT Ordered Set .................................................................................... 24212-1 LTSSM State Transition Time-outs ........................................................................... 25413-1 Link Command Groups.............................................................................................. 29013-2 LGOOD_n Link Command Information Fields ...................................................... 29313-3 LBAD Link Command Information Fields .............................................................. 29413-4 LRTY Link Command Information Fields ............................................................... 295
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USB 3.0 Technology
13-5 LCRD_x Link Command Information Fields .......................................................... 29613-6 LGO_Ux Link Command Information Fields ......................................................... 29713-7 LAU Link Command Information Fields................................................................. 29813-8 LXU Link Command Information Fields ................................................................. 29913-9 LPMA Link Command Information Fields ............................................................. 30013-10 LDN Link Command Information Fields ................................................................ 30113-11 LUP Link Command Information Fields ................................................................. 30218-1 8b/10b Data And Control Symbol Encoding Examples ......................................... 39018-2 8b/10b Encoder Selects The Best CRD Alternative ................................................. 39318-3 Spread Spectrum Clocking (SSC) Requirements .................................................... 40320-1 TSEQ Ordered Set Symbol Encoding ....................................................................... 44622-1 Standard Device Requests .......................................................................................... 48622-2 Fields Returned During GetPortStatus..................................................................... 49222-3 Port Change Indicator Definition.............................................................................. 49322-4 Port Status Definition.................................................................................................. 49422-5 Setup Stage Request Data for GetPortStatus ........................................................... 49622-6 ClearPortConnection Request.................................................................................... 49722-7 ClearPortConnection Request.................................................................................... 49722-8 Set Address Request.................................................................................................... 49922-9 Get Descriptor Request — Setup Data ..................................................................... 50122-10 SuperSpeed Descriptors.............................................................................................. 50122-11 Get Device Descriptor Request .................................................................................. 50322-12 Device Descriptor Definition ..................................................................................... 50322-13 Get Configuration Descriptor Request ..................................................................... 50622-14 BOS Descriptor Definition.......................................................................................... 50622-15 BOS — USB 2.0 Extension Descriptor....................................................................... 50722-16 BOS — SuperSpeed Device Capability..................................................................... 50822-17 BOS — Container ID ................................................................................................... 51022-18 Get Configuration Descriptor Request ..................................................................... 51022-19 Configuration Descriptor Definition ........................................................................ 51122-20 Interface Association Descriptor Definition ............................................................ 51322-21 Interface Descriptor Definition .................................................................................. 51422-22 Endpoint Descriptor Definition................................................................................. 51622-23 Endpoint Companion Descriptor Definition........................................................... 51922-24 Get String Descriptor Request ................................................................................... 52122-25 String Descriptor Definition....................................................................................... 52122-26 SetConfiguration Request Data ................................................................................. 52223-1 Standard Device Requests .......................................................................................... 52423-2 Fields Returned During GetPortStatus..................................................................... 52923-3 Port Change Indicator Definition.............................................................................. 53023-4 Port Status Definition.................................................................................................. 53023-5 Setup Stage Data for GetPortStatus .......................................................................... 532
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List of Tables
23-6 Clear Port Connection Request.................................................................................. 53323-7 Clear Hub/Port Requests ............................................................................................ 53423-8 Set Address Request.................................................................................................... 53523-9 Get Descriptor Request — Setup Data ..................................................................... 53723-10 SuperSpeed Descriptors.............................................................................................. 53723-11 Get Device Descriptor Request .................................................................................. 53823-12 Device Descriptor Definition ..................................................................................... 53923-13 Get BOS Descriptor Request ...................................................................................... 54023-14 BOS Descriptor Definition.......................................................................................... 54023-15 BOS — USB 2.0 Extension Descriptor....................................................................... 54123-16 BOS — SuperSpeed Device Capability..................................................................... 54123-17 BOS — Container ID ................................................................................................... 54323-18 Get Configuration Descriptor Request ..................................................................... 54423-19 Hub’s Configuration Descriptor................................................................................ 54423-20 Hub Interface Descriptor ............................................................................................ 54623-21 Hub Status Change — Endpoint Descriptor ........................................................... 54723-22 Hub’s Endpoint Companion Descriptor Definition ............................................... 54923-23 Get Hub Class Descriptor Request............................................................................ 55023-24 Hub Class Descriptor .................................................................................................. 55123-25 Set Hub Depth Request............................................................................................... 55623-26 Set Port U1/U2 Timeout.............................................................................................. 55623-27 Set Port Remote Wake Mask ...................................................................................... 55723-28 Set Port Link State........................................................................................................ 55723-29 Set Port Power.............................................................................................................. 55823-30 Set Port Reset State ...................................................................................................... 55823-31 Set BH Port Reset ......................................................................................................... 55823-32 Hub Feature Selectors ................................................................................................. 56024-1 Link Power State Conditions ..................................................................................... 56724-2 Port Link State Transitions ......................................................................................... 56924-3 Set Feature - Port U1 Timeout Request — Setup Data........................................... 57124-4 U1 Inactivity Timeout Value...................................................................................... 57124-5 Set Feature - Port U2 Timeout Request — Setup Data........................................... 57224-6 U2 Inactivity Timeout Values .................................................................................... 57224-7 SetFeature U1 Enable and U2 Enable Requests — Setup Data ............................. 57424-8 Summary of U1/U2 Entry........................................................................................... 57524-9 U1/U2/U3 Exit Timing Parameters ........................................................................... 58324-10 GetStatus Request ........................................................................................................ 58424-11 System Exit Latency Request Data............................................................................ 58725-1 Jitter Budget At Silicon Pads (Informative) ............................................................. 59425-2 Transmitter Electrical Parameters (Normative) ...................................................... 59725-3 Transmitter Electrical Parameters (Informative) .................................................... 59825-4 Spread Spectrum Clocking (SSC) Modulation ........................................................ 604
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USB 3.0 Technology
25-5 Receiver Electrical Parameters (Normative)............................................................ 60625-6 Receiver Electrical Parameters (Informative) .......................................................... 60725-7 Timing Requirements For Six LFPS Event Types ................................................... 61425-8 LFPS Electrical Specifications (Normative) ............................................................. 61526-1 Test Assertion Examples: USB Command Verifier Compliance Test Specification62226-2 List Of Test Descriptions For The USB Command Verifier Compliance Specifica-tion 62526-3 Test Assertion Examples From Link Layer Test Specification.............................. 62726-4 List Of Test Descriptions For The Link Layer Test Specification ......................... 63026-5 Compliance Pattern Sequence ................................................................................... 63627-1 Loopback BDAT Symbols........................................................................................... 64127-2 Loopback BRST Ordered Set...................................................................................... 64327-3 Loopback BERC Ordered Set ..................................................................................... 64327-4 Loopback BCNT Ordered Set .................................................................................... 644
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About This Book
Scope
The USB 3.0 Technology book is intended as a tutorial and to serve as classroommaterials for the training MindShare delivers on this subject. It should be con-sidered a companion to the USB 3.0 specification, helping to clarify and explainthe concepts and motivations for decisions that were made in the creation of thespecification. This book does include limited reference information from thespecification, but in general does not duplicate reference material from the spec-ification. Doing so would potentially introduce errors into information that isrightfully the sole domain of the specification.
The MindShare Architecture Series
The MindShare System Architecture book series includes the publicationsshown in Table 1.
Table 1: PC Architecture Book Series
Category Title Edition ISBN
Processor Architecture
80486 System Architecture 3rd 0-201-40994-1
Pentium® Processor System Architecture
2nd 0-201-40992-5
Pentium® Pro and Pentium® II System Architecture
2nd 0-201-30973-4
PowerPC SystemArchitecture
1st 0-201-40990-9
The Unabridged Pentium® 4 1st 0-321-24656-X
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Bus Architectures
PCI System Architecture 4th 0-201-30974-2
Firewire System Architecture: IEEE 1394
2nd 0-201-48535-4
ISA System Architecture 3rd 0-201-40996-8
USB 3.0 Technology 1st 978-0-9836465-1-8
Universal Serial Bus System Architecture
2nd 0-201-30975-0
PCI-X System Architecture 1st 0-201-72682-3
PCI Express 3.0 Technology 1st 978-0-9770878-6-0
Network Architecture
InfiniBand Network Architec-ture
1st 0-321-11765-4
Other Architectures
PCMCIA System Architecture: 16-Bit PC Cards
2nd 0-201-40991-7
CardBus System Architecture
1st 0-201-40997-6
Plug and Play System Architecture
1st 0-201-41013-3
Protected Mode Software Architecture
1st 0-201-55447-X
AGP System Architecture 1st 0-201-37964-3
Storage Architecture
SAS Storage Architecture 1st 0-977-08780-8
SATA Storage Technology 1st 978-0-9770878-1-5
Table 1: PC Architecture Book Series (Continued)
Category Title Edition ISBN
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Cautionary Note
The reader should keep in mind that MindShare’s book series often deals withrapidly evolving technologies. This being the case, it should be recognized thatthe book is a “snapshot” of the state of the targeted technology at the time thatthe book was completed. We attempt to update each book on a timely basis toreflect changes in the targeted technology, but, due to various factors (waitingfor the next version of the standard to be approved, the time necessary to makethe changes, and the time to produce the books and get them out to the distribu-tion channels), there will always be a delay.
The Standard Is the Final Word
As with all of our books, this book represents the authors’ interpretations of thespecification - in this case the USB 3.0 specification. The authors’ are mindful ofthis fact and attempt to gain clarification from others to minimize this affect. Inany case, the specification must be considered the final word!
Documentation Conventions
The conventions used in this book for numeric values are defined in the sectionsthat follow.
Hexadecimal Notation
This section defines the typographical convention used throughout this book.All hex numbers are followed by an “h.” Examples:
9A4Eh0100h
Binary Notation
All binary numbers are followed by a “b.” Examples:
0001 0101b01b
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1 Motivation for USB 3.0
This Chapter
The Universal Serial Bus (USB) emerged in 1995 to address the many shortcom-ings of the PC peripheral interfaces, including both technical and end-user con-cerns. Improvements since the initial USB implementation have been steady inperformance and capability. This chapter highlights the key motivations thathave led to the latest developments in USB — the SuperSpeed bus.
The Next Chapter
Key elements of the USB 2.0 implementation help in understanding the USB 3.0and SuperSpeed (SS) bus architectures. The next chapter reviews these key ele-ments for those who want to refresh their USB 2.0 knowledge.
Introduction
USB 3.0 introduces a variety of new features that improve performance, reducesystem power consumption, and extend functionality. The key features include:
• Improved performance using new SuperSpeed data rates.• Improved protocols
— End-to-End Protocol (Based on Token/Data/Handshake)– Data Bursting– Bulk Streaming
— Port-to-Port Protocol (also called Link-to-Link Protocol)• Enabling of new host controllers that handle all device speeds and proto-
cols while reducing overall link and system power consumption.
These items summarize the most important elements that led to the develop-ment of USB 3.0 and the SuperSpeed bus. One additional enabling element formoving to the SuperSpeed bus is maintaining backward compatibility to theexisting Low-, Full- and High-Speed devices, and backward compatibility forSuperSpeed devices so they can operate at one or more of the USB 2.0 speeds.
USB 3.0 Technology
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USB 3.0 Host Controllers
In order to support all of the enhancements afforded by the USB 3.0 specifica-tion, a new generation of USB 3.0 host controllers is required. While other USB3.0 host controller implementations are possible, many of the principal USB 3.0host controllers released thus far are compatible with the eXtensible Host Con-troller Interface (xHCI) specification. Key motivations for new controllers suchas xHCI include:
• Combining support for legacy USB 2.0 low speed (LS), full speed (FS), andhigh speed (HS) transactions with the new USB 3.0 SuperSpeed (SS) trans-actions — essential in handling high bandwidth bulk streaming transfers tolarge-capacity mass storage devices.
• Improved power efficiency at both the bus/device and platform levels. Thisis becoming critical with the huge growth of mobile and embedded battery-powered platforms.
• Optional virtualization support. Many platforms now support multipleOS’s running in virtual machine (VM) environments. a host controller (HC)may leverage the PCI Express Single-Root IO Virtualization (SR-IOV)model and add HC hardware support to lessen the burden on VM software.
Performance
There are few applications that require the SuperSpeed performance at thistime. However, solid state drives and video and audio are some of the applica-tions that can currently take advantage of the current SuperSpeed transfer rateof 5 Gigabits/second. In addition, the higher speed enables more demandingapplications for the future.
USB Bandwidth Comparison
First, let’s take a quick look at USB bus bandwidth. Table 1-1 shows the peakbandwidth for USB 2.0’s low-, full-, and high-speed transmission rates alongwith USB 3.0’s SuperSpeed transmission rate. Each of the bandwidth numbersare the peak theoretical maximum with a single differential pair. The Super-Speed bandwidth number can be doubled in some cases as discussed next.
Chapter 1: Motivation for USB 3.0
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Figure 1-1 illustrates the physical link associated with SuperSpeed. The Super-Speed link interface includes two differential pairs; one for transmission andone for reception. This makes the aggregate bandwidth equal to one gigabyteper second. This kind of bandwidth is possible when the host controller sendsan OUT transaction while a previous IN transaction is still returning data.
Table 1-1: USB Bandwidth Comparison
USB Speed Bit Rate Max Bytes/sec Introduced
Low Speed 1.5Mb/sec 187.5KB/s Jan, 1995
Full Speed 12Mb/sec 1.5 MB/sec Jan, 1995
High Speed 480Mb/sec 60MB/sec April, 2000
SuperSpeed 5Gb/sec 500MB/sec Dec, 2008
Figure 1-1: SuperSpeed Link Interface
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2 USB 2.0 Background
The Previous Chapter
The Universal Serial Bus (USB) emerged in 1995 to address the many shortcom-ings of the PC peripheral interfaces, including both technical and end-user con-cerns. Improvements since the initial USB implementation have been steady inperformance and capability. The previous chapter highlights the key motiva-tions that have led to the latest developments in USB — the SuperSpeed bus.
This Chapter
Key element of the USB 2.0 implementation help in understanding the USB 3.0and SuperSpeed bus architecture. This chapter reviews these key elements andis recommended reading for those who need a refresher on USB 2.0.
The Next Chapter
USB 3.0 incorporates the entire USB 2.0 implementation and adds the Super-Speed bus. The next chapter discusses how compatibility is managed betweenUSB 2.0 and SuperSpeed buses, and summarizes the most important features ofthe SuperSpeed bus.
Motivations for USB
An understanding of the motivations for USB are central to understanding thenature of the architecture and why it developed as it did. First, let’s look at theprimary goals of the original implementation listed in Table 2-1 on page 18. Asnew versions of USB have been added, the fundamental architecture and fea-tures listed in Table 2-1 have been created to ensure compatibility with the olderimplementations while extending performance and capabilities.
USB 3.0 Technology
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USB Topologies
While USB started as a peripheral bus for desktop PCs, over time USB found itsway into platforms ranging from laptops and servers to embedded systems.Some embedded systems may be resource constrained and implement a subset
Table 2-1: Motivations for USB
Feature Description
Better Peripheral Inter-face
Lower Cost and Consumer Friendly — including a serial interface with common connectors that allows sharing of a wide range of device types.
Support range of band-width requirements
• Low-speed — 1.5Mb/sec focusing on keyboards, mice,etc.
• Full-speed — 12Mb/sec focusing on.• High-speed — 480Mb/sec focusing on mass storage,
headphones, printers, etc.
Real Hot Insertion/Removal
Allow devices to be plugged and unplugged while power is applied, and provide for automatic detection of device insertion and removal, along with the related software setup and tear-down.
Standard IO Connec-tions
Defines standard connectors for attaching USB devices to a host computer and for attaching to the peripheral devices.
Method to Expand Topology
Expand the topology up to 127 devices via root hub ports and external hub ports, while limiting the number of cable hops between a root port and the furthest down-stream device to no more than six cables (5 hubs).
Eliminate memory, IO and interrupt resource conflicts
Implement a peripheral bus whose attached peripheral devices require no memory, IO or interrupt resources.
Reduce complexity and cost of USB devices
Create a peripheral bus architecture that concentrates complexity within the host controller, thereby reducing the cost of the peripheral devices.
Chapter 2: USB 2.0 Background
Visit MindShare Training at www.mindshare.com 19
of USB features (proprietary host controller and software, restricted speeds,custom connectors, etc.).
The foundation for all USB activity is the Host Controller. There are a variety ofhost controllers, including:
• UHCI (Universal Host Controller Interface) — handles only low- and full-speed devices
• OHCI (Open Host Controller Interface) — handles only low- and full-speeddevices
• EHCI (Enhanced Host Controller Interface) — handles high-speed devicesdirectly and low- and full-speed devices that attach beneath high-speedhubs that implement a transaction translator
These host controllers may be used stand-alone or combined with other control-lers. The most common implementation is an EHCI controller combined withone or more UHCI or OHCI companion controllers as illustrated in Figure 2-1on page 20.
USB 2.0 Companion Controllers
USB 2.0 host controllers typically include a companion controller implementa-tion. These controllers normally have a single EHCI controller for handling allroot ports to which high-speed devices are attached and one or more UHCI orOHCI controllers to handle all root ports to which low- and full-speed devicesare attached. USB host controller implementations vary widely depending onthe number of USB root ports desired. Figure 2-1 depicts a companion control-ler with eight root ports. The four UHCI companion controllers each have twoports to support the possibility of all eight root ports having either low- or full-speed devices attached. EHCI also implements eight ports to handle up to eighthigh-speed devices.
The Port Routing logic is controlled by EHCI software that tests each port todetermine whether a high-speed, full-speed or low-speed device is attached.The EHCI retains all high-speed devices and connects full- and low-speeddevices to the UHCI companion controllers.
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3 USB 3.0 Overview
Previous Chapter
Key elements of the USB 2.0 implementation help to understand the USB 3.0and SuperSpeed bus architecture. The previous chapter reviewed these key ele-ments and is recommended reading for those who do not have a strong back-ground in USB 2.0.
This Chapter
USB 3.0 incorporates the entire USB 2.0 bus implementation along with theSuperSpeed bus. This chapter discusses how compatibility is managed withUSB 2.0 and SuperSpeed buses, and summarizes the features of the new Super-Speed bus. Later sections of this book provide additional detail regarding thesefeatures.
The Next Chapter
The protocol layer and the related End-to-End SuperSpeed protocol is based onthe USB 2.0 Token/Data/Handshake protocol. However, the addition of new fea-tures make the End-to-End protocols very different. The next chapter character-izes the major changes brought about by the SS End-to-End protocols.
USB 3.0 Topology and Compatibility
This section discusses the USB 3.0 topology along with the related system anddevice compatibility issues. Refer to Figure 3-1 on page 48 during the followingdiscussion.
USB 3.0 cables include both the USB 2.0 and SuperSpeed buses. Each 3.0 portsupports either a Low-, Full-, or High-Speed device attached to the 2.0 bus or adevice attached to the SuperSpeed bus. It should be emphasized that the USB2.0 bus and SuperSpeed buses are completely independent of each other. Thisextends to the USB 3.0 hubs that contain a SuperSpeed hub and a USB 2.0 hub.
USB 3.0 Technology
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Figure 3-1: Example USB 3.0 Host Controller and Topology
CPU
Host Bridge DRAM
FS Hub
SS
HS Hub
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HS
HS HS
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Chapter 3: USB 3.0 Overview
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USB 3.0 Host ControllerThe USB 3.0 host controllers support low-speed (1.5Mb/s), full-speed (12Mb/s),high-speed (480Mb/s) and SuperSpeed (5Gb/s) operation, and do so withoutany companion controller requirements. This single controller can performaccesses to both USB 2.0 and USB 3.0 SuperSpeed devices simultaneously. Allaccesses to low- and full-speed devices are handled via a transaction translatorthat is integrated within the host controller. Also, the host controller mayinclude one or more 2.0-only ports. For example, Figure 3-1 on page 48 illus-trates port 1 of the host controller connecting to the HS bus only. All other portssupport both HS and SS connections.
TopologyThe USB 3.0 topology provides for the SS and HS bus to be implemented side-by-side. The topology maintains the same depth considerations as USB 2.0 withup to five hubs allowed in-line between a root hub port and the furthest devicedownstream. The upstream port of all USB SS hubs require connecting to boththe SuperSpeed and high-speed buses simultaneously. These hubs integrate aSS hub and high-speed hub that contains one or more transaction translators.
The SuperSpeed bus consists of a dual simplex implementation (a transmit dif-ferential pair and a receive differential pair) allowing traffic to flow in bothdirections simultaneously. Figure 3-2 illustrates the SS link interface.
Figure 3-2: Transmit and Receive Differential Pairs
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4 Introduction to End-to-End Protocol
Previous Chapter
USB 3.0 incorporates the entire USB 2.0 implementation and adds the Super-Speed bus. The previous chapter discussed how compatibility is managedbetween USB 2.0 and SuperSpeed buses, and summarized the features of thenew SuperSpeed bus.
This Chapter
The protocol layer and the related End-to-End SuperSpeed protocol is based onthe USB 2.0 Token/Data/Handshake protocol. However, the addition of new fea-tures make the End-to-End protocols very different. This chapter characterizesthe major changes brought about by the SS End-to-End protocols.
The Next Chapter
The role of each header packet that is employed by the End-to-End protocol isdescribed in the next chapter. This chapter serves as a reference for these pack-ets and includes an overview of the role each packet plays in the End-to-Endprotocol and details the format and descriptions of the fields within eachpacket. This information is essential for a thorough understanding the opera-tion of the End-to-End protocol.
The Protocols
The End-to-End protocols define a set of protocol layer packets used in transfer-ring information between the host controller and device endpoints. The proto-col varies depending on the type of endpoint being accessed and whether thedata movement is IN or OUT. Subsequent chapters discuss the specific charac-teristics and protocols associated with each endpoint type.
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The Protocol Packet Types
SuperSpeed USB uses a collection of header packets that originate at and arereceived by the Protocol layer. These Protocol layer packets are categorized asfour primary types by the specification. Table 4-1 lists these packet categoriesand lists the number of subtypes that exist in each group. Some SubTypes alsohave additional packet categories that are discussed in the next chapter.
The Link Management Packets (LMPs) originate and terminate at the Protocollayer, but are only exchanged between link partners. Consequently, the End-to-End protocol does not employ the LMPs and are discussed later in the contextof the applications to which they apply. The related LMP functions involve:
• Power Management• Power Budgeting• Port Configuration following certain resets• Vendor Device Testing
The Token Lives On
Every transaction initiated on the USB 2.0 begins with a token packet whosecontent is still used by the SS protocol. The specification calls this informationthe Address Triplet, which uniquely identifies each device endpoint in thetopology. The Address Triplet includes:
• Device Address (assigned by USB configuration software)• Endpoint Number (reported in the device’s endpoint descriptor) • Direction (D) of data flow (D=1, IN and D=0, OUT)
Table 4-1: Protocol Packet Types and Characteristics
Name Type Code Sub-Types
Link Management Packets 00000b 6
Transaction Packets 00100b 8
Data Packet 01000b NA
Isochronous Timestamp Packet 01100b NA
Chapter 4: Introduction to End-to-End Protocol
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The End-to-End protocol uses only ACK and DATA header packets when initi-ating a transaction. Also, the End-to-End protocol uses the IN, OUT and Setuptoken types that are incorporated into the ACK/Header packets listed in Figure4-1. The DATA Header used for OUT transactions is converted to a SETUPheader when the “S” bit in DW1/Bit 15 is set. Figure 4-1 highlights the token-related information.
Bursting
SuperSpeed USB adds a new feature called Data Bursting. Like USB 2.0, the SSEnd-to-End protocol requires that each data packet transferred must be explic-itly acknowledged with an ACK packet. However, Data Bursting allows a lim-ited number of DATA packets to be sent without waiting for an ACK from the
Figure 4-1: SuperSpeed Headers Support IN, OUT and Setup Tokens
31 25 5
Seq NumEpt Num
CRC-16
Data Length
Type
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eob/lp
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NumPSeq Num
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00100b
0001b
DF DL
ACK Header - IN Token
DATA Header - OUT & SETUP (S bit) Tokens
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5 End-to-End Packets
Previous ChapterThe protocol layer and the related End-to-End SuperSpeed protocol is based onthe USB 2.0 Token/Data/Handshake protocol. However, the addition of new fea-tures make the End-to-End protocols very different. The previous chapter char-acterized the major changes brought about by the SS End-to-End protocols.
This ChapterThis chapter describes the role of each packet that is employed by the End-to-End protocol. This chapter serves as a reference for these packets and includesan overview of the role each packet plays in the End-to-End protocol and detailsthe format and descriptions of the fields within each packet. This information isessential for understanding the operation of the End-to-End protocol.
The Next ChapterControl transfers, also known as message pipes, provide a USB-specific mecha-nisms that allow requests to be issued to USB devices. These transfers use thebi-directional endpoint zero (called the default endpoint). The next chapter dis-cusses the transfer protocol and example applications associated with Controltransfers.
Three Categories of End-To-End PacketsFigure 5-1 on page 80 is a reminder of the various interface layers associatedwith the SuperSpeed bus and provides some detail regarding the packet typesused in the End-to-End protocol. The host controller initiates each transactionsequence by sending a token packet (e.g., ACK packet for IN tokens and DATApacket for OUT tokens). The SuperSpeed End-to-End protocol defines thesequence of packets exchanged between the host controller and targeted USBdevice. Three categories of protocol layer packets are used in conjunction withthe End-to-End protocol:
• Transaction Packets (TPs) — these packets are all Header packets andinclude seven SubTypes that in general emulate the token/data/handshakesequence, control data flow and manage End-to-End connectivity.
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• Data Packet — this packet is categorized separately from the TransactionPacket because it consists of both a Header packet and the Data PacketPayload (DPP). In some cases errors may result in the payload beingdropped in which case the End-to-End protocol will detect the missing pay-load and retransmit the Data packet.
• Isochronous Timestamp Packet (ITP) — this header packet is the onlybroadcast packet used in the SuperSpeed protocol and is a replacement forthe Start of Frame (SOF) packet used by the USB 2.0 bus implementation.As its name indicates the ITP carries bus timing information that is broad-cast to all devices in the network that are ready to accept the packet.
Note: Figure 5-1 lists Link Management Packets at the bottom of the ProtocolLayer, but they are not used in the End-to-End protocol even though they aredefined as protocol layer packets. Link Management packets are associatedwith a variety of functions covered later.
Figure 5-1: Protocol Layer Overview and Packet Types
Protocol Layer Headers
USB System Software
Device Driver/Application
Logical Device(Endpoint Zero)
Function Endpoints
Port-to-PortProtocol
Port-to-PortProtocol
Port-to-PortProtocol
Chip-to-ChipProtocol
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Protocol Layer Headers- Transaction Packets
- Data + Data Payload
- Isochronous Timestamp
End-to-End Protocol
- Link Management(Port-to-Port)
Chapter 5: End-to-End Packets
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Table 5-1 lists the four Protocol Layer Header Types and indicates packet direc-tion, type code and number of subtypes. All protocol layer packets consist ofheaders except for the Data Packet Payload. A basic header consists of 12 headerbytes, along with a CRC-16 that covers the 12-byte header and a 16-bit LinkControl Word for a total of 16 Bytes as shown in Figure 5-2. Header packets aresubject to the Port-to-Port protocols that perform two primary functions associ-ated with the Protocol Layer headers:
• Flow Control — verifies that the receive buffer can accept the header• Header Error Detection and Recovery — verifies that all header packets
exchanged between link partners are received without error. Any error con-dition triggers a recovery process resulting in the header being retried untilit is successfully transferred.
Table 5-1: Protocol-Layer Packet Categories and Characteristics
Packet Category Type Code Sub-Types Direction Protocol
Transaction 00100b 8 Sub-Type Specific End-to-End
Data (Header + Payload) 01000b NA Bi-directional End-to-End
Isochronous Timestamp 01100b NA Downstream Only Multicast
Link Management 00000b 6 Mixed Port-to-Port
Figure 5-2: Basic Header Packet
31 5
CRC-16
Type Header Type Specific
Header Type Specific
Header Type Specific
Link Control Word
0
31 0
31 0
31 016
DW0
DW1
DW2
DW3
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6 Control Protocol
Previous Chapter
The role of each packet employed by the End-to-End protocol is described in theprevious chapter. It serves as a reference for these packets and includes an over-view of the role each packet plays in the End-to-End protocol and details theformat and descriptions of the fields within each packet. This information isessential for understanding the operation of the End-to-End protocol.
This Chapter
Control transfers, sometimes called message pipes, provide a USB-specificmechanisms that allow requests to be issued to USB devices. These transfers usebi-directional endpoint zero (called the default endpoint). This chapter dis-cusses the transfer protocol and example applications associated with Controltransfers.
The Next Chapter
Many common devices use the Bulk transfers including printers, scanners, andmass storage devices. The next chapter introduces the capabilities and featuresassociated with the SuperSpeed bulk endpoints, including the new DATABursting feature and Bulk Streaming protocols.
Introduction to SuperSpeed Control Transfers
The first transactions targeting a device, once it has been detected, are controltransfers. SuperSpeed uses the same control transfer scheme as USB 2.0 and isbased on the Token/Data/Handshake sequence. Each SuperSpeed device mustimplement a default control endpoint (always endpoint zero) used for configur-ing devices, controlling device states, and other aspects of the device’s opera-tion. The control endpoint responds to a variety of USB specific requests thatare delivered via control transfers. For example, when a device is detected onthe Universal Serial Bus, host software must access the device’s descriptors todetermine the device type and operational characteristics. The USB specifica-
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tion defines a variety of USB device requests for controlling hub configurationand operation, as well as USB peripheral devices. These requests may be “stan-dard” requests used to perform typical operations required of most devices.Class or vendor-specific requests provide special functionality specific to somedevice types. See “Standard Device Requests” on page 486 for a detailed list ofstandard requests supported by SuperSpeed USB.
Control transfers consist of either two or three stages as described below:
• Setup Stage - control transfers always begin with a setup transaction thatalways delivers 8 bytes of data to endpoint zero. The 8 bytes of data definesthe type of request to be performed (e.g., Getting the contents of a devicedescriptor).
• Data Stage (optional) - this stage is defined only for requests that requiredata transfers to or from endpoint zero. For example, the GetDescriptorrequest requires the host controller to perform an IN transaction to read thecontents of the requested descriptor information.
• Status Stage - this stage reports the result of the requested operation and isalways the final stage of a control transfer.
Following is a list of characteristics implemented by Control Endpoints:
• Max Packet Size - The data packets delivered during the data stage of a con-trol transfer have a maximum payload size of 512 bytes. USB 2.0 restrictsthe maximum payload to 64 bytes.
• Data Bursting - Control transfers do not support Data Bursting.• Error Recovery - Control transfers participate in error detection and recov-
ery mechanisms to provide a “best effort” delivery of data based on theUSB “three strikes and you’re out” policy. In this case, the error is for-warded to software for handling.
• Bus Bandwidth Allocation - control transfer scheduling guarantees at least10% of the bus bandwidth be reserved for control transfer. If additional busbandwidth is available, then more than 10% can be allocated to controltransfers during a given bus interval.
Control Transfer Structures and Examples
All control transfers are performed using either the two-stage or three-stagesequence. This section details the elements and structure of control transfersand provides example applications.
Chapter 6: Control Protocol
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Two-Stage Control Transfer Structure
Two-stage requests commonly deliver commands to a device or hub. Examplesinclude SetAddress, SetConfiguration, SetFunctionWake, and SetPortPower.The two-stage control transfers consist of a Setup and Status Stage as illustratedin Figure 6-1. The Setup Stage is simply a Setup transaction comprising a DATAHeader with the Setup bit set, the 8-byte Data Packet Payload (DPP), both sentby the host controller, and an ACK packet returned from the device. In thisexample, the 8-byte DPP defines a two-stage control transfer (e.g., a SetAddressrequest). After the host controller has delivered the Setup request it sends thenew SuperSpeed Status header to device endpoint zero and the device returnsan ACK header to confirm the request has successfully completed.
Three-Stage Control Transfer Structure
Three stage control transfers consist of the Setup Stage followed by the Datastage that consists of one or more IN or OUT transactions depending on the spe-cific request and ends with the Status Stage (See Figure 6-2). The most commontypes of three-stage control transfer are getting descriptor or status informationfrom peripheral devices and hubs.
The 8-bytes of data associated with a Setup Stage of a three-stage control trans-fer specifies the amount of data to be transferred during the Data Stage. The
Figure 6-1: Two-Stage Control Transfer
Setup Transaction
Setup Stage Status Stage
Status Transaction
StatusSETUP Header
(OUT token)
DATA Payload
(8 bytes)ACK HeaderACK Header
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7 Bulk Protocol
Previous Chapter
Control transfers, sometimes called message pipes, provide a USB-specificmechanisms that allow requests to be issued to USB devices. These transfers usebi-directional endpoint zero (called the default endpoint). The previous chapterdiscusses the transfer protocol and example applications associated with Con-trol transfers.
This Chapter
Many common devices use the Bulk transfers including printers, scanners, andmass storage devices. This chapter introduces the capabilities and features asso-ciated with the SuperSpeed bulk endpoints, including the DATA Bursting andBulk Streaming protocols.
The Next Chapter
Interrupt transactions provide periodic access to an endpoint and limit theamount of data that can be transferred during a bus interval. The next chapterdiscusses the applications, capabilities, and behaviors associated with interrupttransfers.
Introduction to Bulk Transfers
SuperSpeed Bulk endpoint characteristics include several important new fea-tures, but in general have the same characteristics as USB 2.0 Bulk transfers. Theattributes of SuperSpeed Bulk endpoints include:
• End-to-End reliable data transport between the host and device is accom-plished through an error detection and retry mechanism. Three failedattempts to deliver data results in software handling the error recovery.
• No reservation for bus bandwidth is made for bulk transfers. Consequently,there are no latency or bandwidth guarantees.
• Maximum payload size increases from 512 bytes to 1024 bytes
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• Data Bursting provides for up to 16 DATA packets (16 KB) that can be sentor received without having received an ACK. This capability can signifi-cantly reduce data transfer latency.
• Bulk Streaming provides nearly 64K of addressable buffers associated witha single bulk endpoint. This is managed via the 16-bit StreamID field.
Bulk End-to-End Protocol
The End-to-End protocol associated with bulk endpoints involves the exchangeof several Protocol Layer packets and further focusses on several critical fieldswithin these packets. This chapter explains the protocol requirements and pro-vides a number of example transfers for both IN and OUT operations.
Common fields related to both IN and OUT transfers include:
• Route String — Used by hubs to forward packets to the destination device• Address Triple — Device Address, Endpoint Number, and Direction that
uniquely each endpoint within the topology (aka, token information)• Seq Num — End-to-End Sequence Numbers ensure DATA packets arrive
in order• NumP — Number of packet buffers available for receiving or sending
DATA packets• Retry — Indicates failed transfer of a Data Packet that must be retried• PP — Packet Pending bit from host notifies the device that this packet is the
last currently scheduled for delivery
Chapter 7: Bulk Protocol
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Bulk IN SuperSpeed Transaction Protocol
The host issues ACK packets to initiate IN transactions. IN transaction protocolinvolves several areas of focus as listed below:
• Data bursting• End-to-End flow control• Short packets• Data transfer errors and retry• Host and device responses to all valid conditions• Timeout conditions and values
The protocol requirements associated with each of the topics is covered in thefollowing sections.
IN Data Bursting
Whether or not a bulk endpoint supports bursting is reported in the EndpointCompanion descriptor. Table 7-1 shows the first three fields of the descriptorincluding MaxBurst size supported.
Table 7-1: SuperSpeed Endpoint Companion Descriptor
Offset Field Definition
Field Size Description
0 Length 1 Size of the Endpoint Companion Descriptor in bytes
1 Descriptor Type 1 Descriptor Type = 48
2 MaxBurst 1 Maximum number of DATA packets this end-point can send or receive that have not been acknowledged. Values range from 0 to 15 and translate to 1 - 16 packets
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8 Interrupt Protocol
Previous Chapter
Many common devices use the Bulk transfers including printers, scanners, andmass storage devices. The previous chapter introduces the capabilities and fea-tures associated with the SuperSpeed bulk endpoints, including the new DATABursting feature and Bulk Streaming protocols.
This Chapter
Interrupt transactions provide periodic access to an endpoint and limit theamount of data that can be transferred during a bus interval. This chapter dis-cusses the applications, capabilities, and behaviors associated with interrupttransfers.
The Next Chapter
Some devices require constant data delivery normally handled as synchronoustransfers, such as the connection between an MP3 player and headphones.However, USB does not support synchronous transfers, so an alternate solutioncalled isochrony is employed. The next chapter details the application, capabili-ties and characteristics of Isochronous transfers.
Introduction to Interrupt Transfers
SuperSpeed interrupt endpoint characteristics are similar to USB 2.0 interruptendpoint characteristics, but include several new features. The attributes ofSuperSpeed interrupt endpoints include the following:
• Periodic transfers target device endpoints that require occasional access.Classical interrupt devices like keyboards and mice may not be able to senddata to the host any faster than every 10 ms and may not be in use for longperiods of time.
• Interrupt transfers use a reliable transport mechanism to ensure data is suc-cessfully transferred between the host and device. This is accomplishedthrough CRC error detection and end-to-end retry. Three failed attempts todeliver data results in software being notified to handle error recovery.
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• Endpoint descriptors specify a service interval (sometimes called the poll-ing interval) that defines the frame or µframe during which data is trans-ferred. The interval value reported in the endpoint descriptor is based on avalue, ranging from 1-16, that is used as an exponent as follows:
2interval-1
For example, a keyboard with a polling interval of 8ms, requires an intervalvalue of 7.
27-1 → 26 → 64 µframes = 8ms
A polling interval may range from 1 to 32,768 on power’s of 2 boundaries.
• MaxBurstSize is reported in the Endpoint Companion descriptor. Interruptendpoints may have the MaxBurstSize value set as follows:MaxBurstSize = 0; supports 1 DATA packetMaxBurstSize = 1; supports 2 DATA packet burstMaxBurstSize = 2; supports 3 DATA packet burst
• MaxPacketSize is reported in the Endpoint descriptor as follows:— if MaxBurstSize=0; the MaxPacketSize value in the Endpoint descriptor
may be a value from 1-1024— if MaxBurstSize=1 or 2; the MaxPacketSize must be 1024
• Two types of interrupt endpoint transfers exist in SuperSpeed as defined bythe Interrupt Endpoint descriptors:— Standard periodic transfers— SuperSpeed asynchronous notifications (including WAKE, LATENCY
TOLERANCE messages and BUS INTERVAL ADJUSTMENT mes-sages.
• The periodic nature of interrupt transfers requires the host to access theendpoint during the specified service interval. Beyond that difference,Interrupt IN endpoints use the same End-to-End flow control mechanismsthat are used in Bulk transfers. Other variations associated with interrupttransfers are reviewed below:— Following a burst flow control event ERDY notifies the host when the
endpoint is ready to resume transactions. Unlike Bulk transfers the hostmust re-initiate burst transactions within two service intervals.
— The host is not required to retry failed DATA packets during the sameservice interval.
— Interrupt transactions are limited to a MaxBurstSize of three DATApackets.
Chapter 8: Interrupt Protocol
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Interrupt IN SuperSpeed Transaction Protocol
This section illustrates and discusses variations of the Interrupt IN protocol,including:
• Single Interrupt Transaction• Burst transaction sequence (two DATA packet burst)• Transaction with NRDY• Transaction with eob• Burst transaction with DATA packet error and Retry in same interval• Burst transaction with DATA packet error and Retry in next interval
Single Interrupt Transaction
The example in Figure 8-1 illustrates an interrupt transactions that transfersdata during every other µframe. As always, the host issues ACK packets to ini-tiate IN transactions delivered to the target device. The device responds with aDATA header and payload (1024 Bytes) that are returned to the host. In turn,the host delivers an ACK packet to confirm the successful transaction.
Figure 8-1: Interrupt with Single DATA Packet Per Interval
Device Tx Service IntervalHost Tx
ACK Packet
DATA Packet
ACK Packet
Seq=1; NumP=0
Seq=0; NumP=1
Seq=0
Service Interval n
ACK Packet
DATA Packet
ACK Packet
Seq=2; NumP=0
Seq=1; NumP=1
Seq=1
Service Interval n+2
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9 Isochronous Protocol
Previous ChapterInterrupt transactions provide periodic access to an endpoint and limit theamount of data that can be transferred during a bus interval. The previouschapter discusses the applications, capabilities, and behaviors associated withinterrupt transfers.
This ChapterSome devices require constant data delivery that is typically handled as syn-chronous transfers, such as the connection between an MP3 player and ear-plugs. However, the USB bus does not support synchronous transfers, so analternate solution call isochrony is employed. The next chapter details the appli-cation, capabilities and characteristics of Isochronous transfers.
The Next ChapterUSB SuperSpeed hubs support both SuperSpeed and USB 2.0 operation. Thenext chapter covers the detailed operation of the SuperSpeed side of the hub,including the major hub responsibilities.
Introduction to Isochronous Transfers
Isochronous transaction protocols implemented in the SS environment behavevery similar to the USB 2.0 implementation. The primary characteristics of iso-chronous transfers are summarized in the following bullet list.
• Used by devices that require synchronous operation: — USB Headphones— Streaming Video, etc.
Note: USB is not a synchronous bus but Isochrony aids hardware and soft-ware in managing synchronous delivery of data.
• Host provides guaranteed bandwidth and bounded latency per serviceinterval.
• Periodic endpoints (isochronous and interrupt) are allocated up to 90% ofthe available bandwidth.
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• Isochronous data delivery takes priority over the validity of data. Conse-quently, handshake packets are not defined for the Isochronous transferprotocol and no flow control or retries are allowed.
• The Endpoint descriptor defines the Maximum Packet Size (i.e., maximumsize of a DATA payload). This value can vary depending on the MaximumBurst Size supported as defined below:— If bMaxBurstSize = 0; bMaxPacketSize can be any value from 0-1024
bytes— If bMaxBurstSize = 1-15; bMaxPacketSize must be 1024 bytes
• The Maximum Burst Size is defined in the Endpoint Companion descriptoras follows:— 0 = endpoint supports burst of 1 DATA packet— 1-15 = bursts of 2 to 16 DATA packets
• The Multiplier (Mult) field defines the Maximum number of Bursts sup-ported during a service interval. The Mult value is located in the EndpointCompanion descriptor within the bmAttributes field (see Figure 9-1). TheMult field is zero based and has a maximum value of 2. The example showsthe maximum burst size of 16 packets for each of the three multipliers.
• The number of bytes an isochronous endpoint will transfer during a serviceinterval is reported in the wBytesPerInterval field in the SS Endpoint Com-panion descriptor. This value is intended to facilitate Isochronous schedul-ing by reserving the required bus bandwidth.
• The binterval value for an isochronous endpoint defines the number of busintervals contained within a single service interval. The binterval value isreported in the Endpoint descriptor as follows:— The possible values range from 1 to 32,768, and expressed as:
2bInterval-1; where bInterval is a value from 1-16.— Service interval duration ranges from 125µs – 4.096s (power’s of 2).
Figure 9-1: Maximum Number of Bursts per Service Interval
Reserved Mult
7 6 5 4 3 2 1 0
Bits 1:0 - 00b; (Value+1) bMaxBurst = 16 KB
- 01b; (Value+1) bMaxBurst = 32 KB
- 10b; (Value+1) bMaxBurst = 48 KB**
*
Chapter 9: Isochronous Protocol
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Bus Intervals and Isochronous Service Intervals
Some USB 2.0 isochronous endpoints maintain synchronization with the USBbus clocks as a means of delivering data at a constant rate (nominally 1KHz forfull speed or 8KHz for high speed). This synchronization is maintained via theStart of Frame (SOF) or Micro Start of Frame (µSOF) packets that are broadcastat the beginning of every bus interval boundary. SOF packets also report theframe count that increments with each frame and rolls back to zero after 2048frames.
SuperSpeed timing is also based on the same nominal 8KHz timing used inHigh-Speed USB. However, the SS bus uses the Isochronous Timestamp Packet(ITP) rather than µSOF packets to report the host bus interval timing.
Figure 9-2 depicts two isochronous transfers (A and B) with different serviceintervals. Transfer A uses a service interval duration of two bus intervals, whiletransfer B has a service interval spanning four bus intervals. Note in this exam-ple that during each service interval the same amount of data is being trans-ferred. This indicates that the sample clocks associated with both transfer A andB are synchronous to the USB bus clock.
Figure 9-2: Isochronous Service Interval Examples
X = Bus Interval (125μs)
Isochronous Transfer A; Service Interval is 2X (250μs)
Isochronous Transfer B; Service Interval is 4X (500μs)
X X+1 X+2 X+3 X+4 X+5 X+6 X+7
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10 USB 3.0 HubsThe Previous Chapter
Some devices require constant data delivery (sometimes called streaming) nor-mally handled as synchronous transfers, such as the connection between anMP3 player and earplugs. However, the USB bus does not support synchronoustransfers, so an alternate solution call isochrony is employed. The next chapterdetails the application, capabilities and characteristics of Isochronous transfers.
This Chapter
USB SuperSpeed hubs support both SuperSpeed and USB 2.0 operation. Thischapter covers the detailed operation of the SuperSpeed side of the hub, includ-ing the major hub responsibilities.
The Next Chapter
In the three levels of USB 3.0 SuperSpeed protocol, Port-To-Port is the middlelayer. This chapter is an overview of Port-To-Port topics covered in greaterdetail in subsequent chapters: transmitter and receiver header packet process-ing, CRC generation/checking, Link Commands, header packet flow control,and packet acknowledgement.
Introduction to SS Hubs
SuperSpeed hubs contain two separate hub functions: one for SuperSpeed oper-ations and one for the USB 2.0 (i.e., Low-, Full- and High-Speed) operations. TheUSB 2.0 hub functions exactly as it did previously. (Please see MindShare’s USB2.0 book for details). Figure 10-1 on page 206 illustrates a SS Hub implementa-tion showing the primary interconnects.
The upstream port of a hub attaches directly to a root port or to the downstreamport of another hub. The upstream port must attach to both the SuperSpeed busand the high-speed USB 2.0 bus when possible. The USB cable delivers VBUSpower that is shared by the SuperSpeed and USB 2.0 sides of the hub. VBUS con-
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trol logic may be required to manage potential port power conflicts if bothSuperSpeed and USB 2.0 software attempt to change port power simulta-neously or inappropriately.
Hub downstream ports provide the attachment points for connecting USB 2.0devices (Low-, Full- and High-speed devices) and SuperSpeed devices. Adescription of hub upstream port and downstream port connections are dis-cussed later in this chapter.
Figure 10-1: Basic Block Diagram of USB 3.0 Hub
USB 2.0
Hub
VBUS
ControlLogic
Upstream Port
Downstream Ports
Downstream Root or Hub Port
SS
Hub
VBUSincludes
Chapter 10: USB 3.0 Hubs
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This chapter focuses on SuperSpeed hub functionality as listed below:
• Attachment to a downstream root or hub port.• Responding to Software Requests including:
— GetDescriptor (Device, Configuration, String, Hub, etc.)— SetAddress— SetConfiguration— SetPortPower— GetPortStatus, etc.
• Attachment/Detachment to upstream ports of device/hubs.• Forwarding Packet in both directions.• Managing packet routing in the downstream direction.• Managing the link power hierarchy• Transaction Deferral• Hub Error Detection and Handling
Hub Attachment
Hubs like other USB devices cannot attach to a root or other hub port withoutVBUS power being detected. This is true of both the USB 2.0 bus connection andthe SuperSpeed connection. Once power is detected each bus will attempt toestablish a connection to the downstream ports of the link partner.
Attachment to the SS and USB 2.0 buses are completely independent andattachment procedures are very different. Once the connections have beenmade, the buses remain completely independent. Also, when the hub connectsto the USB 2.0 side only, SS Hub functions are disabled. Details associated withthe USB 2.0 bus attachment can be found in MindShare’s USB 2.0 book.
Packet Forwarding
One of the primary functions associated with Hubs is to forward packets inboth directions while performing end-to-end transfers between the root portand target devices. Figure 10-2 on page 208 illustrates this requirement. Packetsmoving in the downstream direction must be routed by the hub to support theSS unicast routing mechanism. When a packet arrives at the upstream hub portthe hub determines the destination of the incoming packet. As highlighted inthe Figure 10-2 example. There are five possibilities:
• the transaction may be routed to one of the four downstream ports• the hub itself may be the recipient (i.e., SS Hub Controller)
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11 Introduction to Port-To-Port Protocol
Previous Chapter
USB 3.0 hubs support both SuperSpeed and USB 2.0 operation. The previouschapter covers the operation and major features of the SuperSpeed side of thehub.
This Chapter
In the three levels of USB 3.0 SuperSpeed protocol, Port-to-Port is the middlelayer. This chapter is an overview of Port-to-Port topics covered in greater detailin subsequent chapters: transmitter and receiver header packet processing, CRCgeneration/checking, Link Commands, header packet flow control, and packetacknowledgement.
The Next Chapter
The next chapter describes the Link Training and Status State Machine (LTSSM)and the twelve SuperSpeed link states it supports. The LTSSM logic resides,conceptually, at the link layer and is used to reduce the traditional USB softwareburden related to managing link connectivity, power management, and testing.The responsibilities of the LTSSM and each of it’s states and substates are sum-marized to provide background for later chapters that refer to the LTSSM’s roleduring reset events, link training/recovery, power management transitions, etc.
Port-To-Port Protocol And The Link Layer
As traffic moves between link partners, the link layer enforces Port-to-Port pro-tocol rules that assure that link integrity is maintained, header packets are pro-cessed and transported between link partners without error, link powermanagement transitions occur transparently, etc.
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The Big Picture Revisited
As indicated in Figure 11-1 on page 222, the link layer functions required of allhost, hub, and peripheral devices to support Port-to-Port protocol fall into twogroups:
• Header Processing• Link Management
Figure 11-1: Port-To-Port Protocol And Link Layer Role
�USB System Software
�Device Driver/Application
Logical Device(Endpoint Zero)
Function Endpoints
Port-to-Port Protocol
Chip-to-ChipProtocol
Chip-to-ChipProtocol
Chip-to-ChipProtocol
Ap
plic
atio
nL
aye
rP
roto
co
lL
aye
rLin
kL
ayer
Ph
ysic
al
La
ye
r
Host Hub Device
End-to-EndProtocol
End-to-EndProtocol
Header Processing- Link Sequence Numbers- CRC Generation/Check- Header Flow Control- Header Retry Buffer
Link Management- Link Commands- Ordered Set Delimiters (Framing Symbols)- Logical Idle Symbol (IS)- Link Error Handling- LTSSM & Link States- Link Power Transitions
Port-to-Port Protocol
Header Processing- Link Sequence Numbers- CRC Generation/Check- Header Flow Control- Header Retry Buffer
Link Management- Link Commands- Ordered Set Delimiters (Framing Symbols)- Logical Idle Symbol (IS)- Link Error Handling- LTSSM & Link States- Link Power Transitions
Port-to-Port Protocol
Header Processing- Link Sequence Numbers- CRC Generation/Check- Header Flow Control- Header Retry Buffer
Link Management- Link Commands- Ordered Set Delimiters (Framing Symbols)- Logical Idle Symbol (IS)- Link Error Handling- LTSSM & Link States- Link Power Transitions
Chapter 11: Introduction to Port-To-Port Protocol
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Port-To-Port Protocol: Header Processing
GeneralHeaders are 16 byte structures that originate at the protocol layer of the trans-mitter and terminate at the protocol layer of the receiver. Some fields in theheader are related to End-To-End protocol, other header fields are managed bythe link layer and related to Port-to-Port protocol. As the headers pass throughthe link layer, CRC and header sequence numbers are generated by the trans-mitter and checked by the receiver to assure that no errors have occurred andthat packets were received in the intended order.
Header Fields, Two GroupsDW3 of each protocol layer packet includes key fields associated with the Port-to-Port protocol; these fields are identified in Figure 11-2 on page 223. The otherfields (within the dashed line) are related to the End-To-End protocol and arepassed through unchanged by the link layer.
Figure 11-2: Link Layer Header Packet Processing, Key Fields
31 25 5
PP
HE SubTypeEpt Num
CRC-16
NumPSeq Num
Type
RtyD
Route String
Stream ID/Reserved
Link Control Word
0
31 48 7 621 026 1516 12
31 028 27
31 016
Device Address
16
DW0
DW1
DW2
DW32527 26 22
R19
CRC-5 Hub Depth Hdr Seq #
00100b
0001b
DF DL
Rsvd R
ReservedRsvd
Rsvd
Port-To-Port Protocol FieldsLink Control Word Hdr Seq#Link Control Word CRC-5DW0-DW2 CRC-16
End-To-End Protocol Fields
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12 LTSSM And the SuperSpeed Link States
The Previous Chapter
In the three levels of SuperSpeed protocol, Port-to-Port is the middle layer. TheUSB 3.0 specification defines Port-to-Port protocol in terms of link layer respon-sibilities of transmitters and receivers. The previous chapter provided an over-view of link layer responsibilities, including header processing, packet framing,flow control, header packet acknowledgement, and the use of link commands.All of these are described in more detail in subsequent chapters in the context oftheir use.
This Chapter
This chapter introduces the Link Training and Status State Machine (LTSSM)and the twelve SuperSpeed link states it supports. The responsibilities of theLTSSM and each of it’s states and substates are summarized here to providebackground for later chapters that refer to the LTSSM’s role during reset events,link training/retraining, power management transitions, etc.
The Next Chapter
The next chapter describes the format and use of each SuperSpeed link com-mand. Collectively, these eight-symbol commands are used for header packetflow control and packet acknowledgement, power management transitionhandshake, and for indicating continued presence in the U0 link state in theabsence of other traffic.
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Twelve High Level LTSSM States
As indicated in Figure 12-1, the Link Training and Status State Machine(LTSSM) resides at the link layer and supports twelve high level states. The USB3.0 specification organizes the twelve high level LTSSM states into four func-tional groups:
• Operational States: U0, U1, U2, U3• Link Initialization & Training States: Rx.Detect, Polling, Hot Reset, Recovery• Testing States: Compliance Mode, Loopback• Other States: SS.Inactive, SS.Disabled
Figure 12-1: Link Training And Status State Machine (LTSSM)
LTSSM
Protocol Layer
TimeoutTimer
Rx.DetectAttempts
Link Layer
LTSSM
Protocol Layer
Termination
LFPS SignalDetect
Equalization
Ordered Sets
Tx LFPS
Detect
TimeoutTimer
Link Layer
Rx
Termination
LFPS SignalDetect
Equalization
Tx
Ordered Sets
Tx LFPS
Detect
Tx
Rx
Upstream (DS) Port
II II
II II
Simplified drawing at the left: LTSSM elements related to upstream and downstream (US/DS) ports are shown.
Directed
Directed
SS.Inactive
U3
RecoveryU0U1
U2
Rx.Detect
Polling
Only selected transitions shown
Loopback
SS.Disabled
ComplianceMode
Hot Reset
LTSSM High Level States
Downstream (DS) Port
Chapter 12: LTSSM And the SuperSpeed Link States
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Why Is The LTSSM Needed?
USB has always relied on software and host controller hardware to manage thecollection of simple hubs and peripherals that reside downstream. For USB 3.0SuperSpeed, addition of the LTSSM helps reduce some of this burden by trans-ferring many responsibilities to hardware. The LTSSM responsibilities include:
• Link training and retraining• Link-level error handling• Link power management• Link test management
The following sections summarize major elements of each of these LTSSMresponsibilities. All are covered in greater detail in other chapters.
LTSSM And Link Training And Retraining
Background: USB 2.0 Doesn’t Require Training
USB 2.0 does not specify a particular initialization sequence when preparing thephysical layer for low speed (LS), full speed (FS), or High Speed (HS) opera-tions. At attachment, the downstream device (upstream facing port) attaches apull-up resistor to either the D- or D+ bus signals indicating to the hub it isattached to whether it is LS or FS/HS capable.
When software polls the hub and discovers the attachment, a bus reset is per-formed. During reset, a high speed device is permitted to negotiate a speedchange from FS to HS using chirp protocol. If chirp is successful, HS termina-tions are switched in by the link partners. That’s it; the electrical specificationsfor the bus, cables, connectors, etc. assure that:
• No receiver equalization is required at any USB 2.0 speed• No attempt is made to establish a continuous bit/symbol lock between link
partner transmitter and receivers. • At the start of a new packet, a special Start Of Packet (SOP) bit transition
sequence is sent to re-establish lock between transmitter and receiver.• At the end of each USB 2.0 packet, the bus returns to electrical idle.
LTSSM Coordinates SuperSpeed Link Training
A number of features of USB 3.0 make the use of the LTSSM essential in the
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13 Link Commands
Previous ChapterThe previous chapter introduced the Link Training and Status State Machine(LTSSM) and the twelve SuperSpeed link states it supports. The LTSSM is usedto reduce the traditional USB software burden related to managing link connec-tivity, power management, and testing. The responsibilities of the LTSSM andeach of it’s states and substates were summarized to provide background forsubsequent chapters that refer to the LTSSM’s role during reset events, linktraining/recovery, power management transitions, etc.
This ChapterThis chapter describes the format and use of each SuperSpeed link command.Collectively, these eight-symbol commands are used for header packet flowcontrol, packet acknowledgement, power management transition handshake,and for indicating continued presence in the U0 link state in the absence ofother traffic.
The Next Chapter
The next chapter presents a conceptual view of transmitter and receiver logicinvolved in link layer processing of outbound and inbound 16-byte headersrequired for each data packet (DP), isochronous timestamp packet (ITP), trans-action packet (TP), and link management packet (LMP). Topics include genera-tion and checking of link sequence number, header CRC-5/CRC-16, and the useof link layer header packet buffers holding a copy of each header packet until itis checked and acknowledged by the receiver.
Four Groups Of Link Commands
Unlike protocol layer End-To-End packets, link commands are part of the Port-to-Port protocol and used for communication between link partners; they arenever routed to other links. They also are not subject to flow control and, whensent by the transmitter link layer, must be accepted by the receiver link layer. Asindicated in Table 13-1 on page 290, there are four link command groups:
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• Packet Acknowledgement — three types, sub-types vary with type. Twotypes are sent by the receiver link layer to inform the transmitter link layerwhether or not a header packet was received without error. The third typeis used by the transmitter link layer to inform the receiver that a headerpacket is being resent due to an earlier failure (also referred to as a retry).
• Flow Control — one type, four sub-types. Sent by the receiver to inform thetransmitter each time a link layer header packet buffer becomes available.
• Power Management — one type, four sub-types. Exchanged by link part-ners during link power management transitions from U0 to U1, U2, or U3.
• Link Up/Link Down — one type, two sub-types. Periodically sent in theabsence of other traffic to inform partner of continued presence in U0 state.
As depicted in Figure 13-1 on page 290, the basic content of a link command iscontained in a 16-bit Link Command Word structure consisting of:
• Link Command Information (LCI) in bits 10:0. Note the three valid LCIfields: Class, Type, and Sub-Type
• A CRC-5 field in bits 15:11 (protecting the LCI)
Table 13-1: Link Command Groups
Packet Category Class Code Type Codes Sub-Types
Packet Acknowledgement 00b 00b, 02b, 3b Varies with Type
Flow Control 00b 01b 4
Power Management 01b 01b 4
Link Up/Link Down 10b 10b 2
Figure 13-1: Link Command Word Fields
Type0 ? ? ?? ?
6 48 715 11
CRC-5Sub-TypeClass
? ?Rsvd
Link Command Information (LCI)
0 0 0
10 9 3 2 1 0
Link Command Word
Chapter 13: Link Commands
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Link Commands On The SuperSpeed Link
As described previously, a link command contains a 16-bit Link CommandWord consisting of the 11-bit Link Command Information (LCI) field and the 5-bit CRC. To assure that link command information is valid at the receiver, twothings are done by the transmitter:
• The 16-bit (2 byte) Link Command Word is replicated--each with its ownLCI and CRC-5. The two Link Command Word copies follow one another.
• The link command is preceded with the 4 “K” symbol LCSTART framingfor a total of 8 symbols.
At the receiver link layer, both copies of the Link Command Word are verifiedto be identical before the link command is processed. Figure 13-2 on page 291illustrates a framed link command on the SuperSpeed link.
For Additional Details On Link Commands
Additional details on the use of link commands may be found in other chapters:
• Refer to Chapter 24, entitled "SuperSpeed Power Management," on page563 for additional details on LGO_Ux, LAU, LXU, LPMA Link commands.
• Refer to Chapter 15, entitled "Header Packet Flow Control," on page 321 fordetails on LCRD_x link commands
• Refer to Chapter 16, entitled "Link Errors & Packet Acknowledgement," onpage 339 for details on LGOOD_n, LBAD, and LRTY link commands
Figure 13-2: Framed Link Command On The SuperSpeed Link
Type0 ? ? ?? ?
6 48 715 11
CRC-5Sub-TypeClass
? ?Rsvd
Link Command Information
Link Command Word
0 0 0
10 9 3 2 1 0
Two byte Link Command Word and it’s replica must be the same
Type0 ? ? ?? ?
6 48 715 11
CRC-5Sub-TypeClass
? ?Rsvd
Link Command Information
0 0 0
10 9 3 2 1 0
Link Command Word
Framed 8-Symbol Link Command
SLCSLCSLCEPF
LCSTART Framing
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14 Header Packet Processing
The Previous Chapter
The previous chapter described the format and use of each SuperSpeed linkcommand. Collectively, these eight-symbol commands are used for headerpacket flow control and packet acknowledgement, power management transi-tion handshake, and for indicating continued presence in the U0 link state in theabsence of other traffic.
This Chapter
This chapter presents a conceptual view of transmitter and receiver logicinvolved in link layer processing of outbound and inbound 16-byte headersrequired for each data packet (DP), isochronous timestamp packet (ITP), trans-action packet (TP), and link management packet (LMP). Topics include genera-tion and checking of link sequence number, header CRC-5/CRC-16, and the useof link layer header packet buffers holding a copy of each header packet until itis checked and acknowledged by the receiver.
The Next Chapter
SuperSpeed USB employs link level header packet flow control to assure thatheader packet transmission is never attempted if link layer buffer space isunavailable at the receiver. The next chapter describes the motivation for linklayer header packet flow control and a conceptual view of the buffers, creditcounters, timers, and link commands required to support it.
Link Layer Packet Processing Role
While the link layer has a wide range of Port-to-Port protocol responsibilities,the focus of this chapter is on the link layer transmitter and receiver roles inheader and data packet processing. The highlighted regions in Figure 14-1 onpage 304 indicate the scope of link layer topics covered here.
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Figure 14-1: Link Layer Tx And Rx Packet Processing Scope
OK?
HDR Seq #?
Rx Physical Layer
Data CRC-32?
HDR CRC-5?
Data
D/K x8
Rx Header Packet Buffers
Rx Header Packet Buffers
HDR CRC-16?
HDR
Data HDR info
Rx Protocol Layer
HDR Seq #
Tx Header Packet Buffers
Tx Physical Layer
CRC-5?
Link CMD?
Data CRC-32
HDR CRC-5
Data
HDR CRC-16
HDR
Data HDR info
Tx Protocol Layer
D-D+D+D-
LTSSM
Ordered Sets
Logical Idle
Ordered Sets
Logical Idle
CRC-5
Link CMD
D/K x8
Flow Control
Flow Control
Chapter 14: Header Packet Processing
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Transmitter Packet ProcessingThe transmitter link layer processes outbound header and data packets thatoriginate at the device protocol layer. Each header for a transaction packet (TP),link management packet (LMP), isochronous timestamp packet (ITP), and datapacket (DPH) arrives at the transmitter (Tx) link layer as a partially completed16-byte structure. The Tx link layer performs the final processing, includingassignment of a link sequence number and generation of two CRCs to protectfields within the header. In cases when a data packet is to be sent, an additionalCRC-32 will generated and appended to the data packet payload (DPP) to pro-tect it.
Before looking at the details, Figure 14-2 on page 305 provides a quick review ofheader packet format and the key Tx link layer header packet processingresponsibilities. In the example, an ACK transaction packet has arrived at thelink layer for final processing buffering before transmission to the link partner.
Figure 14-2: Key Transmitter Packet Processing Functional Blocks
Tx Physical Layer
Tx Protocol Layer
D+D-
HDR Seq #
Tx Header Packet Buffers
Data CRC-32
HDR CRC-5
Data
HDR CRC-16
HDR
Data HDR info
Ordered Sets
Logical Idle
Ordered Sets
Logical Idle
CRC-5
Link CMD
D/K x8
Flow Control
LTSSM
31 25 5
PP
HE SubTypeEpt Num
CRC-16
NumPSeq Num
Type
RtyD
Route String
Stream ID/Reserved
Link Control Word
0
31 48 7 621 026 1516 12
31 028 27
31 016
Device Address
16
DW0
DW1
DW2
DW32527 26 22
R19
CRC-5 Hub Depth Hdr Seq #
00100b
0001b
DF DL
Rsvd R
ReservedRsvd
Rsvd
Example: ACK Packet Header
Key Tx Header Packet Processing Responsibilities:
1 Assign link header packet sequence number (Hdr Seq#)
2 Generate CRC-5 protecting Link Control Word
3 Generate CRC-16 protecting Header DW0-DW2
22 3311
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15 Header Packet Flow Control
The Previous Chapter
The previous chapter presented a conceptual view of transmitter and receiverlogic involved in link layer processing of outbound and inbound 16-byte head-ers required for each data packet (DP), isochronous timestamp packet (ITP),transaction packet (TP), and link management packet (LMP). Topics includedgeneration and checking of link sequence number, header CRC-5/CRC-16, andthe use of link layer header packet buffers holding a copy of each header packetuntil it is checked and acknowledged by the receiver.
This Chapter
SuperSpeed USB employs link level header packet flow control to assure thatheader packet transmission is never attempted if link layer buffer space isunavailable at the receiver. This chapter describes the motivation for link layerheader packet flow control and a conceptual view of the buffers, creditcounters, timers, and link commands required to support it.
The Next Chapter
The next chapter summarizes common SuperSpeed link errors encounteredduring transmission of header packets, data packets, and link commands. Italso describes one of the primary components of link error handling, link levelheader packet acknowledgement and, if necessary, retransmission (referred toas a retry). Topics covered include the use transmitter and receiver counters,timers, header CRC and link sequence number generation/checking, and threelink commands used in the packet acknowledgement handshake.
Background: Host And Device Flow Control
Generally speaking, flow control enables an initiator or target device to pausedata transfers or other traffic, usually because of temporary buffer full/emptyconditions. Flow control by an initiator is often simpler than for the targetbecause it can withhold new requests until it is ready.
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USB 2.0 Flow Control, Very LimitedA number of features associated with the previous generation USB 2.0 severelylimit flow control opportunities for low speed, full speed, and high speedperipheral devices and hubs:
• The simple master-slave broadcast bus requires that all transactions mustbe initiated by the host controller under software control.
• The USB 2.0 physical layer (PHY) is built on a half-duplex interface whichrenders upstream asynchronous messages, for purposes such as device ini-tiated flow control, impossible. This also means that no DMA or peer-to-peer transactions may be initiated.
• While a USB host controller is capable of generating CPU interrupts, thereis no support for peripheral interrupts in any generation of USB.
Given these limitations, the best USB 2.0 can offer in the way of flow control isan endpoint polling scheme in which the host provides the target device end-point an opportunity to return a NAK handshake response to an IN or OUTtoken. The NAK indicates that the endpoint is not ready to start (or continue)with data transactions. When this occurs in USB 2.0, considerable bandwidthmay be wasted because of transaction re-attempts triggered not by errors, butbecause of IN endpoint buffer empty, or OUT endpoint buffer full conditions.
The SuperSpeed Flow Control Approach
End To End Flow Control
While USB 3.0 SuperSpeed protocol is still based on a token-data-handshakemodel, it includes several enhancements that collectively provide far better endto end flow control for both host and devices:
• The USB 2.0 NAK response is replaced with the USB 3.0 SuperSpeedNRDY/ERDY responses. In this scheme, once the device returns a NRDYpacket indicating is not ready to start (or continue) data transfers, the hostcontroller will suspend service to the endpoint until the device later sendsan ERDY packet (this eliminates the repeated NAKs seen in USB 2.0)
• For OUT endpoint flow control, each ACK header packet returned by thedevice endpoint includes a NumP (number of additional packets) field indi-cating its readiness to continue accepting data.
• For IN endpoint flow control, each data packet header returned by thedevice includes the NumP field in the DPH (data packet header) indicating
Chapter 15: Header Packet Flow Control
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its readiness to continue sending data. As long as the host and endpoint areboth ready and willing to proceed, data transfers can continue.
Link Level Flow Control Is Also Needed
USB 2.0 makes no provision for link layer flow control because the master-slavebroadcast bus and half-duplex link means that there can only be one transactionoutstanding at a time beneath the host controller and no possibility that packetscould be moving upstream and downstream at the same time. The host control-ler and current target endpoint simply take over all parts of the topology untilthe transaction is complete.
With the USB 3.0 SuperSpeed dual-simplex links, host packets and asynchro-nous upstream device packets may occur at the same time. A simple example isdepicted in Figure 15-1 on page 323. Here, Device A,B, and D attached to a USB3.0 hub are each sending asynchronous transaction packets upstream. On itsupstream port, the hub must forward the three packets to the host controller.The question of whether the downstream facing port of the host controller canaccept all of them at the highest possible rate depends on the number of receiverbuffers currently available. The remainder of this chapter describes the USB 3.0solution to this type of link level flow control problem.
Figure 15-1: Asynchronous Traffic May Contribute To Link Flow Control Problems
2.0SS
Host Controller
Device DEP
3.0 Hub
NRDY
Enough Buffering?
Device BEP
Device Notification
Device AEP
ERDY
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16 Link Errors & Packet Acknowledgement
The Previous Chapter
SuperSpeed USB employs link level header packet flow control to assure thatheader packet transmission is never attempted if link layer buffer space isunavailable at the receiver. The previous chapter describes the motivation forlink layer header packet flow control and a conceptual view of the buffers,credit counters, timers, and link commands required to support it.
This Chapter
This chapter summarizes common SuperSpeed link errors encountered duringtransmission of header packets, data packets, and link commands. It alsodescribes one of the primary components of link error handling, link levelheader packet acknowledgement and, if necessary, retransmission (referred toas a retry). Topics covered include the use transmitter and receiver counters,timers, header CRC and link sequence number generation/checking, and threelink commands used in the packet acknowledgement handshake.
The Next Chapter
In the three levels of SuperSpeed protocol, Chip-To-Chip resides below End-To-End and Port-to-Port protocols. The USB 3.0 specification defines Chip-to-Chipprotocol in terms of physical (PHY) layer responsibilities of the transmitter andreceiver in each link partner. The next chapter provides an overview of theChip-to-Chip protocol and two key groups of physical layer responsibilities:PHY logical functions and the electrical signaling requirements. Both of theseare described in more detail in subsequent chapters.
Background: USB 2.0 Error Handling
Previous generation USB 2.0 relies heavily on host controller time-outs andtransaction rescheduling to deal with bus level errors. Even if bit errors are
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fairly infrequent, when they do occur a considerable amount of potential band-width is wasted waiting for timeout requirements to be met before correctingproblems and moving on to other transactions. Placing the burden for errorhandling and most other aspects of USB 2.0 protocol on software and the hostcontroller reduces the complexity and cost of USB hubs and peripheral devices,but increases the overall latency in moving packets when errors occur.
USB 3.0 SuperSpeed Requires A New Approach
A number of factors helped drive the move away from the traditional USB 2.0model of host based error detection and correction towards link-level errordetection and handling. A few of the key factors include the following.
SuperSpeed Signaling Affects Bit Error Rates
• Moving from USB 2.0 480 Mb/s High Speed to USB 3.0 5 Gb/s Superspeedresults in a much narrower signal eye. This complicates receiver clock anddata recovery (CDR) and increases the likelihood of bit error rates above theSuperSpeed target bit error rate (BER) of 10-12.
• SuperSpeed transmitter spread-spectrum clocking (SSC), needed to reduceEMI, also adds to the complexity of clock recovery at the receiver.
• Frequency-dependent losses when transmitting at 5 Gb/s further degradesignal quality and the ability of a SuperSpeed receiver to discriminatebetween logic levels. A usable signal eye may not be recoverable withoutaggressive receiver equalization.
• Transmitter de-emphasis (3.5 dB), required to reduce inter-symbol interfer-ence (ISI) at the receiver, also has the general negative effect of lowering sig-nal levels at the receiver.
Complex USB Topologies A Challenge At 5 Gb/s
Over the years, as USB added new speeds, users have maintained high expecta-tions regarding plug-and-play, backward compatibility, and low cost. One of thebiggest challenges of USB 3.0 SuperSpeed design is preserving this user experi-ence while assuring reliable 5 Gb/s operations in the wide range of USB topolo-gies encountered in systems ranging from mobile devices to PCs, workstations,and servers.
Chapter 16: Link Errors & Packet Acknowledgement
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Figure 16-1 on page 341 depicts some extremes of physical connections that arepossible in the point-to-point, USB cabled bus topology (the example shown isbased on a rack-mounted server chassis). The USB 3.0 specification refers toconnection extremes as short channels and long channels.
• Short channel example. As indicated in Figure 16-1, the “dongle” deviceattached at the left is directly connected to the host controller with 4 inchprinted circuit board (PCB) traces.
• Long channel example. The device at the right of Figure 16-1 is at the end ofa very long channel that includes lengthy PCB traces, two cables, and multi-ple connectors.
While both devices in Figure 16-1 may have been designed with great care, real-world differences in USB topologies can, and do, impact signal quality (and thebit error rate) at SuperSpeed receivers.
Upstream Asynchronous Message Errors
Another motivation for moving away from the host-based error handlingemployed in USB 2.0 involves upstream message traffic. While device initiatedupstream traffic is not possible with the half-duplex USB 2.0 physical connec-tions, the USB 3.0 SuperSpeed link is full-duplex and devices are permitted tosend asynchronous protocol layer packets to gain the attention of the host.
Figure 16-1: Link Errors Are Affected By The Channel
Short Channel
Dongle Device
3 Meter USB 3.0 Cable
4” PCBTraces
USB 3.0Host
Controller
Host System Chassis
AFront
Panel Card
Motherboard
A
Internal Cable11” PCB
Traces
Cabled Device
B
Long Channel
FrontPanel
Rear Panel
(Only SS PCB Signals shown)
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17 Introduction to Chip-To-Chip Protocol
Previous ChapterThe previous chapter summarizes common SuperSpeed link errors encounteredduring transmission of header packets, data packets, and link commands. Italso described one of the primary components of link error handling, link levelheader packet acknowledgement and, if necessary, retransmission (referred toas a retry). Topics covered included the use transmitter and receiver counters,timers, header CRC and link sequence number generation/checking, and threelink commands used in the packet acknowledgement handshake.
This ChapterIn the three levels of SuperSpeed protocol, Chip-to-Chip resides below End-To-End and Port-to-Port protocols. The USB 3.0 specification defines Chip-to-Chipprotocol in terms of physical (PHY) layer responsibilities of the transmitter andreceiver in each link partner. This chapter provides an overview of the Chip-to-Chip protocol and two key groups of physical layer responsibilities: PHY logi-cal functions and the electrical signaling requirements. Both of these aredescribed in more detail in subsequent chapters.
The Next ChapterThe next chapter describes logical functions performed by physical layer trans-mitters and receivers during 5 Gb/s SuperSpeed operations. For the transmitter,a description of hardware scrambling, 8b/10b encoding, and serialization is pro-vided. For the receiver, equalization, clock/data recovery, symbol lock, elasticbuffer, 8b/10b decoding, and descrambling are covered.
Chip-To-Chip Protocol And The Physical LayerAs traffic moves between link partners, the physical layer enforces Chip-to-Chip protocol rules that assure that packet, link command, ordered set, and log-ical idle symbols are processed and transported across the 5 Gb/s SuperSpeedlink without error. In addition, the physical layer employs Chip-to-Chip proto-col low frequency periodic signaling for a number of cases when SuperSpeedoperations are not possible on the link.
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The Big Protocol Picture, Once More
As indicated in Figure 17-1 on page 374, the physical layer functions required ofall host, hub, and peripheral devices to support Chip-to-Chip protocol fall intotwo groups:
• Physical layer (PHY) Logical Processing• Physical layer (PHY) Electrical Specifications
Figure 17-1: Chip-To-Chip Protocol And Physical Layer Role
�USB System Software
�Device Driver/Application
Logical Device(Endpoint Zero)
Function Endpoints
Port-to-PortProtocol
Port-to-PortProtocol
Port-to-PortProtocol
Ap
plic
atio
nL
aye
rP
roto
co
lL
aye
rL
ink
La
ye
r
Host Hub Device
End-to-EndProtocol
End-to-EndProtocol
Chip-to-Chip Protocol
Ph
ysic
al
La
ye
r
PHY Logical- Scrambling- 8/10b Symbol Encoding- Serialization- Rx Clock/Data Recover- Elastic Buffer, SKPs
Chip-to-Chip Protocol Chip-to-Chip Protocol
PHY Electrical Specs- Differential Signal Levels- Clock & Jitter Budgets- Spread Spectrum Clocks- Rx Equalization- LFPS Requirements
PHY Logical- Scrambling- 8/10b Symbol Encoding- Serialization- Rx Clock/Data Recover- Elastic Buffer, SKPs
PHY Electrical Specs- Differential Signal Levels- Clock & Jitter Budgets- Spread Spectrum Clocks- Rx Equalization- LFPS Requirements
PHY Logical- Scrambling- 8/10b Symbol Encoding- Serialization- Rx Clock/Data Recover- Elastic Buffer, SKPs
PHY Electrical Specs- Differential Signal Levels- Clock & Jitter Budgets- Spread Spectrum Clocks- Rx Equalization- LFPS Requirements
Chapter 17: Introduction to Chip-To-Chip Protocol
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Chip-To-Chip Protocol: PHY Logical Processing
As the header packets, data packets, and link commands move from the linklayer to the SuperSpeed link, transmitter physical layer (PHY) hardware per-forms logical processing on each data and control byte in a series of pipelinedstages including scrambling, 8b/10b encoding, and serialization before shiftingeach bit onto the 5 Gb/s SuperSpeed link with its differential driver.
At the link partner receiver, similar logical processing is performed in thereverse order to recover each data and control byte as well as the packet or linkcommand structure to which it belongs.
A Note About D/K Bytes And Symbols
The term “data byte” is used loosely in the context of physical layer logical pro-cessing. It includes any byte associated with a header packet, data packet, orlink command that is not a framing symbol. It also includes logical idle (D0.0) aswell as any data (D) bytes within the link training TSEQ, TS1, and TS2 orderedsets. The distinction between data (D) and control (K) bytes is importantbecause physical layer logical processing is different in the two cases.
Another distinction work noting here is the use of the terms “byte” and “sym-bol”. In this book, the difference is:
• A byte is an 8-bit value before it is encoded by the transmitter; dependingon where in the logical processing sequence it is, the byte may or may notbe scrambled. At the receiver, a byte is an 8-bit value after it is decoded;again, it may or may not have been de-scrambled.
• A symbol is the 10-bit value assigned to a byte by the 8b/10b encoder at thetransmitter. The encoded values for data (D) and control (K) symbols aremutually exclusive; a D/K flag bit accompanying each byte into the encoderassures that the 10-bit encoding belongs to either the data symbol group orthe control symbol group.
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18 Physical Layer Logical Functions
The Previous ChapterIn the three levels of SuperSpeed protocol, Chip-to-Chip resides below End-To-End and Port-to-Port protocols. The USB 3.0 specification defines Chip-to-Chipprotocol in terms of physical (PHY) layer responsibilities of the transmitter andreceiver in each link partner. The chapter provides an overview of the Chip-to-Chip protocol and two key groups of physical layer responsibilities: PHY logi-cal functions and the electrical signaling requirements.
This ChapterThis chapter describes logical functions performed by physical layer transmit-ters and receivers during 5Gb/s SuperSpeed operations. For the transmitter, adescription of hardware scrambling, 8b/10b encoding, and serialization is pro-vided. For the receiver, equalization, clock/data recovery, symbol lock, elasticbuffer, 8b/10b decoding, and descrambling are covered.
The Next Chapter
The next chapter describes three reset types defined in USB SuperSpeed: Pow-erOn Reset, Warm Reset, and Hot Reset. PowerOn Reset occurs automaticallywhen VBUS link power transitions to a valid voltage level. Warm Reset and HotReset are referred to as inband resets, occurring when software directs a down-stream facing port to assert reset signaling to its attached device.
Physical Layer Logic Definitions
The SuperSpeed physical layer (PHY) consists of a transmitter and receiverresiding in the same package and supporting two sets of unidirectional AC-cou-pled differential signal pairs. The physical layer can be subdivided into logicaland electrical signaling sections. This chapter covers the logical section of thePHY shown in the highlighted region of Figure 18-1 on page 384. In the illustra-tion, the transmit (Tx) PHY logical section is on the left and the receive (Rx)PHY logical section on the right.
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Figure 18-1: Physical Layer Tx And Rx Logical Section
(Rx)D-D+
Parallel To Serial
Scrambling (D)
(Tx)
x1
D/K x8
x8
x10
D/K8b/10b Encode
LFPSTransmit
Tx
Bit C
lk
Core C
lk
D+D-
Equalization RxTx
De-emphasis
Rx Termination
PLL & Local Clocks
Tx Termination
8b/10b DecodeC
ore Sym
Clk
x8
Descrambling (D)
D/K
x8
Serial To Parallelx1
x10
x10
Elastic Buffer
Rx S
ymC
lk
D10.2K28.5 inverted?
LFPS Detect
Clock Recovery
D/K#R
x Clk
Sym
Lock Data RecoveryCircuit (DRC)
Rx Link Layer
Rx Protocol Layer
Tx Link Layer
Tx Protocol Layer
Chapter 18: Physical Layer Logical Functions
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Tx Physical Layer (PHY) LogicAnytime a link is operating SuperSpeed, The Tx physical layer logic continuallyprocesses outbound packets, link commands, and ordered sets. In the absenceof all other traffic, logical idle symbols are sent in order to maintain reliableclock/data recovery at the receiver of the link partner.
Tx Outbound Bytes And The D/K FlagThe first step in Tx PHY logic processing is shown in Figure 18-2 on page 385.
Figure 18-2: Transmitter Outbound Bytes And The D/K Flag
Parallel To Serial
Scrambling (D)
(Tx)
x1
D/K x8
x8
x10
D/K8b/10b Encode
LFPSTransmit
Local Clks
Tx
Bit C
lk
Core C
lk
Tx Link Layer
Tx Protocol Layer
TxDe-emphasis
Tx Termination
D+D-
(From Tx Link Layer)
SHP
EPF
SHP
SHP
Byte 0
Byte 1
Byte 15
Link CommandHP DPH
DPP
SLC
EPF
SLC
SLC
Byte 0
Byte 1
Byte 2
Byte 3
END
EPF
END
END
Byte 0
Byte n
SDP
EPF
SDP
SDP
SHP
EPF
SHP
SHP
Byte 0
Byte 1
Byte 15
D/K x8
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19 SuperSpeed Reset Events
The Previous Chapter
The previous chapter described logical functions performed by physical layertransmitters and receivers during 5 Gb/s SuperSpeed operations. For the trans-mitter, a description of hardware scrambling, 8b/10b encoding, and serializa-tion was provided. For the receiver, equalization, clock/data recovery, symbollock, elastic buffer, 8b/10b decoding, and descrambling was covered.
This Chapter
This chapter describes three reset types defined in USB SuperSpeed: PowerOnReset, Warm Reset, and Hot Reset. PowerOn Reset occurs automatically whenVBUS link power transitions to a valid voltage level. Warm Reset and Hot Resetare referred to as inband resets, occurring when software directs a downstreamfacing port to assert reset signaling to its attached device. The methods used bysoftware to invoke resets and the impact on device state are also covered.
The Next Chapter
The next chapter covers SuperSpeed link training and port initialization, a pro-cess that starts automatically following a PowerOn or Warm Reset. Chapter top-ics focus on device responsibilities and the handshake sequence required totransition a link from Rx.Detect, through Polling, and into U0. The initializationof device ports upon entry into U0 through the exchange of Header SequenceNumber and Rx Header Buffer Credit Advertisement link commands is alsodiscussed.
PowerOn Reset
PowerOn Reset occurs automatically each time a device attached to a root orexternal hub port detects a VBUS transition to a valid voltage level (a minimumof 4.0 V). Upstream facing ports monitor VBUS continuously and are required toperform an internal PowerOn Reset each time VBUS transitions from invalid tovalid--even if the device is self powered.
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Software May Enable And Disable VBUS
In addition to the PowerOn Reset that occurs automatically each time a devicedetects a VBUS transition to a valid voltage, software may selectively disable orenable VBUS while a device remains physically attached. For external hubs, thisis done by targeting the default control endpoint (EP0) of the hub with theappropriate hub-class request to enable or disable port power.
In the example shown in Figure 19-1 on page 414, software has caused the hub-class request SetFeature (PortPower) to be sent. The 8-byte Setup stage of therequest includes the target hub device address and port number (Device 2, Port1 in this case). Once the Control Transfer Setup and Status stages complete suc-cessfully, the hub port performs the requested action and enables VBUS.
As shown in the example, VBUS transitions to a valid level and PowerOn Resetcommences within the device. This causes a fundamental reset of all internalUSB state and device and partners prepare for SuperSpeed link training.
Figure 19-1: Enabling VBUS Triggers PowerOn Reset
Status Stage
Token/HandshakeSetup Stage
Token/Data/Handshake
Two-Stage Control Transfer
DataType
-NA-
Request
23h 03h(SetFeature)
0000h
Feature Selector Index Length
0001h(Port Number)
0008h(Port Power)
Port Power (VBUS) On
8 Bytes
VBUS On VBUS Off
5 V
0 V
USB 3.0 Host Controller
3.0 Hub
2.0
2.0
1Hub Ports
SS
Dev 2Dev 1
2 3 4
SS
1Hub Ports
2 3 4
3.0Dev n
1
Chapter 19: SuperSpeed Reset Events
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PowerOn Reset Impact On Device StateDetection of PowerOn Reset returns the device USB interface to its initial state.Memory, registers, and other storage elements related to USB Protocol, Link,and Physical layers are restored to default values:
• USB device address returns to 0 and any previously selected configuration/interface information is lost.
• Link layer Tx and Rx header packet buffers, counters, timers are cleared• Once VBUS is again valid and PowerOn Reset completes, a USB 3.0 device
that detects SuperSpeed low impedance receiver terminations for its linkpartner may draw up to 150mA of VBUS current (one unit load). Otherwise,it may only draw up to 100mA of VBUS current as required in the USB 2.0specification.
• If a SuperSpeed link partner was detected, the Link Training and StatusState Machine (LTSSM) transitions to the Rx.Detect state and prepares forlink training. The LTSSM states were introduced in the last chapter.
Note that each device is required to handle its own internal timing when initial-izing itself during PowerOn Reset.
PowerOn Reset And Self-Powered DevicesBus-powered (aka cable-powered) devices are completely powered down whenVBUS is removed. Full initialization is assured because all USB and other hard-ware logic is powered up each time VBUS is reapplied. In addition, bus-powereddevices present a high impedance receiver termination while power is removed,assuring that they are “not visible” to downstream facing hub ports until theport is again powered.
Because self-powered devices have a local supply derived from an AC or DCpower source, they are capable of maintaining some logical state even whileVBUS is off. To help assure consistent USB PowerOn Reset behavior betweenbus-powered and self-powered devices, the USB 3.0 specification includes somerequirements for self-powered devices during and after a PowerOn Reset:
The following rules apply while PowerOn Reset is active (VBUS is invalid):
• Receiver termination must be in the high-impedance state. This means thatwhen a device detects PowerOn Reset is active, it must remove its receiverlow impedance termination and appear as “not visible” on the SuperSpeedlink. High impedance termination, ZRX-HIGH-IMP-DC-POS, must be 25 KΩs ormore.
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20 Link Training
The Previous Chapter
The previous chapter described the three reset types defined in USB Super-Speed: PowerOn Reset, Warm Reset, and Hot Reset. PowerOn Reset occursautomatically when VBUS link power transitions to a valid voltage level. WarmReset and Hot Reset are referred to as inband resets; they occur when softwaredirects a hub downstream port to assert reset signaling to its attached device.The methods used by software to invoke resets and the impact on device statefor each reset type were also covered.
This Chapter
This chapter covers SuperSpeed link training and port initialization, a processthat starts automatically following a PowerOn or Warm Reset. Chapter topicsfocus on device responsibilities and the handshake sequence required to transi-tion a link through LTSSM Rx.Detect and Polling states, and into U0. The initial-ization of device ports upon entry into U0 through the exchange of HeaderSequence Number and Header Buffer Credit Advertisement Link Commands,as well as Port Capability/Configuration LMPs, is also discussed.
The Next Chapter
The next chapter describes link recovery & retraining, a low-latency alternativeto full link training, but only used for links which have previously been in theU0 state. A transition to LTSSM Recovery state followed by retraining isemployed each time an exit is signaled from U1, U2, or U3 power managementstates or to recover from link errors which could not be corrected while in U0.Chapter topics include the impact of retraining on device state and the hand-shake signaling required to enter and exit LTSSM Recovery state.
Link Training Required Before SuperSpeed Operation
Before SuperSpeed links are enabled for 5 Gb/s transfers, an initialization pro-cess called link training is required to establish a reliable connection between
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the physical layer (PHY) transmitters and receivers for each pair of link part-ners. In cases when external hubs are present, all links in the path between ahost controller root hub port and a target device at any level in the topology musthave completed link training before any End-to-End SuperSpeed packets can beexchanged. Full link training occurs automatically, on a link by link basis, eachtime PowerOn Reset or Warm Reset is initiated by a downstream facing port ordetected by an upstream facing port.
USB Physical Connections Complicate Link Training
USB is found in systems ranging from embedded platforms to PCs, worksta-tions, and servers. In addition to the usual high speed serial bus concernsrelated to signal quality and clock/data recovery, SuperSpeed USB 3.0 presentssome additional challenges. It is an IO bus that can be easily extended withhubs and permits a wide range of physical connections between devices,including combinations of cables, connectors, and chip-to-chip pc board traces.The goal of link training is to assure that a reliable 5 Gb/s signal is delivered bytransmitters to receivers across the full range of permitted physical interfaces.
USB 3.0 refers to the connection between link partners as the channel. A channelis often described as long or short, and the term has both physical and electricalimplications. Because of variations in motherboard layout, location of USB con-nectors, and the presence of user supplied cables, hubs, and peripherals, mostreal-world systems have a mix of long and short channels.
Figure 20-1: An Example Server System With Short And Long USB 3.0 Channels
Short Channel
Dongle Device
3 Meter USB 3.0 Cable
4” PCBTraces
USB 3.0Host
Controller
Host System Chassis
AFront
Panel Card
Motherboard
A
Internal Cable11” PCB
Traces
Cabled Device
B
Long Channel
FrontPanel
Rear Panel
(Only SS PCB Signals shown)
Chapter 20: Link Training
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Figure 20-1 on page 428 illustrates long and short channel extremes which maybe encountered in systems such as rack-mounted servers. In the server exampleshown, USB 3.0 connectors are exposed at both the back and front of the chassis.A brief discussion of the long and short channel depicted in the example systemfollows.
The Long Channel
The device at the right in Figure 20-1 on page 428 is connected to the front panelof the server system chassis by a 3 meter USB 3.0 cable. A front panel pc cardinside the chassis then connects to the motherboard using an internal cable.Because of the location of the USB 3.0 host controller on the motherboard in thisexample, 11” of PCB traces are then required to attach to the host controller andthe internal connector. In a long channel such as this, which includes multiplecables and connectors, frequency-dependent losses at SuperSpeed rates resultin poor signal quality at the receiver and a signal eye that may or may not berecoverable.
The Short Channel
By contrast, the USB “dongle” device at the left in Figure 20-1 on page 428 isdirectly attached to a rear panel motherboard USB 3.0 connector and routed tothe USB 3.0 Host Controller using only 4” of PCB trace length. In a short chan-nel such as this, signal losses are less of a problem than signal reflections.
SuperSpeed Link Training Is Adaptive
Designers of USB peripherals and hubs generally have no idea of the actualtopologies where the device will be used. Because of hot plug, a device may beswapped between long and short channels without warning. For the most part,the same uncertainty applies to the host controller. While the motherboard lay-out establishes fixed connections between host controller root hub ports andUSB connectors, the topology beyond the connector is unknown and may bechanged by the user at any time).
The variability in USB channel characteristics is handled automatically byrequiring that full link training is performed if any of the following occurs:
• VBUS transitions from invalid to valid (4.0 V minimum). This typicallyoccurs at attachment or when hub is commanded to apply port power
• On any Warm Reset invoked by software• In the event of certain LTSSM timeout conditions
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21 Link Recovery and Retraining
The Previous ChapterThe previous chapter covered SuperSpeed link training and port initialization, aprocess that starts automatically following a PowerOn or Warm Reset. Chaptertopics included device responsibilities and the handshake sequence required totransition a link through LTSSM Rx.Detect and Polling states, and into U0. Theinitialization of device ports upon entry into U0 through the exchange ofHeader Sequence Number and Header Buffer Credit Advertisement Link Com-mands, as well as Port Capability/Configuration LMPs, was also discussed.
This ChapterThis chapter covers link recovery & retraining, a lower-latency alternative tofull link training for links that have previously been in the U0 state. Transitionsto recovery occur for a variety of reasons, primarily related to related to powermanagement exits and the handling of serious link errors. Chapter topicsinclude the impact of retraining on device state as well the handshake signalingrequired to enter and exit recovery.
The Next Chapter
The next chapter discusses the detection and configuration of USB devices thatare attached to a USB port of any speed. Device descriptors and other character-istics and features that relate to configuring a device are also discussed.
Reasons For Link Recovery And Retraining
There are a number of events which may cause a SuperSpeed link transition tothe Recovery LTSSM state. These events fall into the three groups listed hereand described in the sections that follow:
• Recovery transitions required on each return to U0 from link power man-agement states U1, U2, or U3. The link must exit electrical idle and enterRecovery to retrain the physical layer (PHY) for 5 Gb/s operations.
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• Recovery transitions required to correct link layer or physical layer errorconditions which can’t be repaired while the U0 state. In this case, the tran-sition to LTSSM Recovery is used to exchange training sequences, confirmreceiver “bit lock” and “symbol lock”, and re-initialize elastic buffer levels.If the sequence is successful, then a return to U0 is negotiated followed bythe re-advertisement of link layer flow control credits and header sequencenumber information. Various LTSSM Recovery time-outs handle the caseswhere a link partner is unresponsive; if so, the link may transition to theinactive state (SS.Inactive).
• Transitions to LTSSM Recovery as an intermediate step in a subsequenttransition to Hot Reset, Loopback mode, or to disable link data scrambling.
Recovery And Retraining Managed By The LTSSMFigure 21-1 on page 468 depicts the twelve high-level states of the USB 3.0SuperSpeed Link Training and Status State Machine (LTSSM). Recovery is oneof the high level LTSSM states and its relationship to the other high level statescan be seen at the left in the illustration.
Figure 21-1: LTSSM Recovery State, Substates, Entry, And Exits
Enter from: U0, U1, U2, U3
Polling
U0
SS.DisabledSS.Inactive
Rx.Detect
U3
U1
SS.DisabledSS.Disabled
U2
Loopback
Recovery
Hot Reset
Recovery State
Recovery SubstatesCompliance
Exit to: Rx.Detect
Exit to: Hot Reset
Exit to: SS.Inactive
Recovery.Idle
Recovery.Configuration
Recovery.Active
Exit to: SS.Disabled
Exit to: U0
Exit to: Loopback
Chapter 21: Link Recovery and Retraining
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On the right of Figure 21-1 on page 468 is a more detailed illustration showingthe three LTSSM Recovery substates as well as the entry path from U0, U1, U2,or U3 states. After entering LTSSM Recovery, there are six possible exit paths toother states--depending on the reason for entering LTSSM Recovery, theresponse of the link partner, time-outs, etc. The exit paths are:
• To Rx.Detect state if a timeout or other condition requires full link trainingto be performed again.
• To the SS.Inactive state if the link is non-operational.• To the Loopback state for bit error rate (BER) testing• To the Hot Reset state to force initialization of most device USB 3.0 logic to
the default state.• To the SS.Disabled state for ports not permitted to operate at SuperSpeed • To the U0 state for a return to normal 5 Gb/s SuperSpeed link operations
Recovery Is Speedy
As mentioned previously, a transition to LTSSM Recovery as a way to re-estab-lish reliable 5 Gb/s transport is extremely fast when compared to full link train-ing. The primary reason for this is because link partners entering LTSSMRecovery are required to retain (and apply) receiver equalization parametersestablished earlier during the last full link training.
Receiver equalizer training is, by far, the most time-consuming part of the fulllink training sequence. During this process, devices exchange 64K TSEQordered sets, each 32 symbols in length. On the 5 Gb/s SuperSpeed serial link,this requires approximately 4.2 ms. If this process was repeated for each exitfrom a U1 or U2 link power management state, much of the benefit associatedwith link level power management would be lost. Instead, receiver equalizersare trained and parameters are reused in all cases except errors or other condi-tions requiring full link training to be repeated.
The following discussion describes link recovery events related to the two mostcommon reasons for entering the LTSSM Recovery state: exits from link powermanagement states U1-U3 and handling link layer errors that could not be cor-rected with three attempts at header packet retry. Note that the handshakerequired to enter LTSSM Recovery is different in the two cases and is describedin the following sections. On the other hand, events within the LTSSM Recoverysubstates are much the same for both cases.
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22 Device Configuration
The Previous Chapter
The previous chapter covered link recovery & retraining, a lower-latency alter-native to full link training for links that have previously been in the U0 state.Transitions to recovery occur for a variety of reasons, primarily related torelated to power management exits and the handling of serious link errors.Chapter topics include the impact of retraining on device state as well the hand-shake signaling required to enter and exit recovery.
This Chapter
This chapter discusses the detection and configuration of USB devices that areattached to any USB port. The process is virtually the same for devices of anyspeed. Device descriptors and other characteristics and features that relate toconfiguring a device are also discussed.
The Next Chapter
Hub devices must be configured like any other device attached to a USB port.Hub configuration differs from other devices in that it involves reportingwhether or not other devices are attached to the downstream ports. The nextchapter reviews the hub configuration process and discusses the role of the hubclient driver in performing the setup and initialization for normal hub opera-tion.
OverviewPlease note that many of the actions associated with Device configuration mustbe performed exactly as described herein, while other operations can be per-formed in a variety of ways.
During system initialization, all devices (including hubs) will be detected, con-figured and initialized. Following configuration and initialization, devices maybe removed or new devices may be connected. It is the hub client software thatchecks USB hub ports to detect device attachment or removal. If a status change
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results from a new device having been attached, the configuration process istriggered for that device. Similarly when device removal is detected resourcesassociated with the device are released.
This chapter discusses the primary operations performed during a typical con-figuration sequence. SuperSpeed device configuration is typically performedone device at a time, similar to the USB 2.0 approach. Configuration begins withdetection of an attached device and ends with the device having been config-ured and initialized. The primary operations include:
• Device Detection and Reporting• Assigning a unique Device address• Determining Device Capabilities (via Device Descriptors)• Reporting User Information (via String Descriptors)• Configuring Device (via SetConfiguration Request)• Locating and loading associated Client (Device Class) Software• Client-specific device initialization
Standard Device Requests
Almost all of the Configuration process involves Device Requests and are in theform of control transfers. The setup transaction of a Device Request includes the8 bytes of data that specifies the action to be performed. Table 22-1 lists theStandard Requests including the setup data. The last column (Data) indicatesthe type of data being transfered to or from the device, resulting in a 3-stagecontrol transfer. When “None” is reported a 2-stage control transfer is per-formed. (See “Control Transfer Structures and Examples” on page 106 toreview the control transfer process.)
Table 22-1: Standard Device Requests
RequestType Request Value
(2 bytes)Index
(2 bytes)Length
(2 bytes)Data
100000000B100000001B100000010B
GetStatus (00h)
Zero ZeroInterfaceEndpoint
Two DeviceInterface, orEndpointStatus
00000000B00000001B00000010B
ClearFeature(01h)
Feature Selector
ZeroInterfaceEndpoint
Zero None
Chapter 22: Device Configuration
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00000000B00000001B00000010B
SetFeature(03h)
FeatureSelector
ZeroInterfaceEndpoint
Zero None
00000000B SetAddress(05h)
DeviceAddress
Zero Zero None
10000000B GetDescriptor(06h)
Descriptor Type and Descriptor Index
Zero or Language ID
Descriptor Length
Descriptor
00000000B SetDescriptor(07h)
DescriptorType andDescriptorIndex
Zero or LanguageID
DescriptorLength
Descriptor
10000000B GetConfiguration(08h)
Zero Zero One Configuration Value
00000000B SetConfiguration(09h)
Configuration Value
Zero Zero None
100000001B GetInterface(10h)
Zero Interface One Alternate Interface
00000001B SetInterface(11h)
AlternateSetting
Interface Zero None
10000010B SyncFrame(12h)
Zero Endpoint Two FrameNumber
00000000B SetSEL(48h)
Zero Zero Six Exit Latency Values
00000000B SetIsochDelay(49)
Delay in ns Zero Zero None
Table 22-1: Standard Device Requests (Continued)
RequestType Request Value
(2 bytes)Index
(2 bytes)Length
(2 bytes)Data
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23 SuperSpeed Hub Configuration
The Previous Chapter
The previous chapter discussed the configuration of USB devices that areattached to any USB port. The process is virtually the same for devices of anyspeed. Device descriptors and other characteristics and features that relate toconfiguring the device were also detailed and discussed.
This Chapter
Hub devices are configured like any other device attached to a USB port. Hubconfiguration differs in that it involves reporting whether or not other devicesare attached to the downstream ports. This chapter reviews the hub configura-tion process with the focus on the issues related to extending the bus throughthe hub’s downstream facing ports.
The Next Chapter
The SuperSpeed bus implements a high-speed serial bus that requires constanttransmission of information (logical idle) to ensure the link between devices areready to deliver packets with very low latency. However, this constant transmis-sion of logical idle creates constant power consumption. Consequently, theSuperSpeed bus is architected to manage link power aggressively during logicalidle by entering an electrical idled state. It must also be able to recover back tothe operational state with relatively low latencies. The next chapter describesthe various features and mechanisms used to reduce power consumption.
Configuring the Hub
Hubs are the only USB device types that connect to both the SuperSpeed busand the USB 2.0 bus. This discussion focuses only on the SuperSpeed bus andhub configuration. The USB 2.0 configuration is covered in MindShare’s USB 2.0book.
Hubs must be configured like any other device. When a hub is attached to a rootor other hub port software does not know the nature of the device until the
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device descriptors are read. These descriptors reveal to software the device’sfunction, or class. Consequently, hubs go through the same process as any otherdevice during the initial stages of configuration. This process consists of the fol-lowing events and includes the associated device states. The device in the fol-lowing bullet list is a hub.
• Device is attached to hub port (Attached State) • Power is applied to device (Powered State)• Power triggers device Reset Assertion and Deassertion• Attachment detected and Link Training is performed (Default State)• Software assigns device Address (Address State)• Software determines device characteristics via Descriptors• Software reports user information via String descriptors• Device features are enabled• Device is Configured (Configured State)
This chapter focuses on the hardware and software interactions associated witha root hub port detecting a device (a hub in this case) and software configuringit for normal operation. Once configuration software has configured a device,class-specific software completes the initialization. From a hub perspective thismeans preparing hub features and downstream ports for normal operation.
Standard Device RequestsAlmost all of the configuration process involves Device Requests performed viacontrol transfers. For reference purposes, Table 23-1 lists the standard requestsincluding the 8 bytes of setup data that defines each request. The shaded rowsindicate the request is not supported by Hubs.
Table 23-1: Standard Device Requests
RequestType Request Value
(2 bytes)Index
(2 bytes)Length
(2 bytes)Data
100000000B100000001B100000010B
GetStatus (00h)
Zero ZeroInterfaceEndpoint
Two DeviceInterface, orEndpointStatus
00000000B00000001B00000010B
ClearFeature(01h)
Feature Selector
ZeroInterfaceEndpoint
Zero None
00000000B00000001B00000010B
SetFeature(03h)
FeatureSelector
ZeroInterfaceEndpoint
Zero None
Chapter 23: SuperSpeed Hub Configuration
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Device Detection and Reporting
General
Note: The reader may prefer to skip this section because it is virtually identicalto the discussion covered in the previous chapter. This discussion is includedhere in the event the previous chapter was skipped. See “The Hub Configura-tion Process” on page 534 to skip this section.
00000000B SetAddress(05h)
DeviceAddress
Zero Zero None
10000000B GetDescriptor(06h)
Descriptor Type and Descriptor Index
Zero or Language ID
Descriptor Length
Descriptor
00000000B SetDescriptor(07h)
DescriptorType andDescriptorIndex
Zero or LanguageID
DescriptorLength
Descriptor
10000000B GetConfiguration(08h)
Zero Zero One Configuration Value
00000000B SetConfiguration(09h)
Configuration Value
Zero Zero None
100000001B GetInterface(10h)
Zero Interface One Alternate Interface
00000001B SetInterface(11h)
AlternateSetting
Interface Zero None
10000010B SyncFrame(12h)
Zero Endpoint Two FrameNumber
00000000B SetSel(48h)
Zero Zero Six Exit Latency Values
00000000B SetIsochDelay(49)
Delay in ns Zero Zero None
Table 23-1: Standard Device Requests (Continued)
RequestType Request Value
(2 bytes)Index
(2 bytes)Length
(2 bytes)Data
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24 SuperSpeed Power Management
The Previous Chapter
Hub devices are configured like any other device attached to a USB port. Hubconfiguration differs in that it involves reporting whether or not other devicesare attached to the downstream ports. The previous chapter reviews the hubconfiguration process with the focus on the issues related to extending the busthrough the hub’s downstream facing ports.
This Chapter
The SuperSpeed bus implements a high-speed serial bus that requires constanttransmission of information (logical idle) to ensure the link between devices areready to deliver packets with very low latency. However, this constant transmis-sion of logical idle creates constant power consumption. Consequently, theSuperSpeed bus is architected to manage link power aggressively during logi-cal idle by entering an electrical idled state. It must also be able to recover backto the operational state with relatively low latencies. This chapter describes thevarious features and mechanisms used to reduce power consumption.
The Next Chapter
The next chapter discusses the SuperSpeed link electrical interface and signal-ing. Major topics include SuperSpeed clocks and transmitter/receiver electricalspecifications as well as Low Frequency Periodic Signaling (LFPS).
Principles of SuperSpeed Power Management
This section provides background information, concepts and principles associ-ated with Link Power Management. Later chapter discuss the various mecha-nisms defined by the specification for managing link and device power.
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BackgroundThe primary goal of SuperSpeed bus power management is to conserve asmuch power as possible without adversely affecting responsiveness and perfor-mance. It is obvious that battery-powered systems require the greatest empha-sis on power savings, but with today’s high energy costs, systems of all typescome under scrutiny. Like many high-speed serial bus implementations (e.g.,PCI Express, Serial Attached SCSI, and InfiniBand), SuperSpeed USB can sup-port a large number of links in the topology, and these high-speed linksnatively require constant transmission to maintain synchronization needed forlow-latency transmission of packets. This means that every SuperSpeed link inthe topology continuously consumes power if there is no method for placingthese links into low power states. See Figure 24-1.
Figure 24-1: All SS Links Remain Powered Without Link Power Management
CPU
Host Bridge DRAM
FS Hub
SS
LS
HS Hub
SS
FS
LSFS
HS
USB Host Controller
HS
LS
SSHS
HS
HSSS
SS
SS
1
1
2
2
3
3 4
1 2 3
Chapter 24: SuperSpeed Power Management
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Power Management Design Goals
This section focuses on three features associated with SuperSpeed power man-agement provide improved power management over the USB 2.0 solutions.These features include:
1. Link Power Management2. Improved Suspend/Resume3. Function Power Management.
Link Power Management
The SuperSpeed bus includes features that allow aggressive link power man-agement by placing links into low-power states as often as possible and for thelongest duration possible without significantly impacting performance. Clearly,this approach involves trade-offs between conserving power and maintainingshort latencies. The approach to conserving link power may depend upon plat-form characteristics. Two extremes come to mind:
• Server platforms requiring low latencies and high performance may favorperformance over power conservation.
• Battery powered systems may manage power very aggressively, therebyfavoring power savings over low latencies and high performance.
Link power management relies on bus idle time, during which links can beplaced into low-power states and then recover quickly when a packet must bedelivered. Several features introduced by SuperSpeed USB help to create morebus idle time, including:
• Unicast transactions — only links between the root port and target deviceare active, while all other links remain idle.
• Fast completion of transactions (5 Gb/s) — higher transmission rates meansthe links are active for shorter periods of time.
• More efficient transaction protocols — protocol improvements lead to morebus idle time.
• Improved end-to-end flow control — the SuperSpeed bus is not polled.Instead devices notify the host when they are ready to be accessed, therebyreducing bus traffic and increasing idle time.
The USB 3.0 specification defines the mechanisms used to trigger link transi-tions to the low power states and are discussed later in this chapter.
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25 SuperSpeed Signaling Requirements
The Previous Chapter
The previous chapter described link and platform level power enhancementsintroduced in USB 3.0.
This Chapter
This chapter discusses the SuperSpeed link electrical interface and signaling.Major topics include SuperSpeed clocks and transmitter/receiver electrical spec-ifications as well as Low Frequency Periodic Signaling (LFPS).
The Next Chapter
The next chapter describes key features of compliance testing, a collection ofchecks designed to verify conformance with USB 3.0 Specification protocol,link, and physical layer requirements. Compliance testing is slightly differentfor hosts, hubs, and peripherals and is required in order to assure device interoperability and to receive USB certification.
Physical Layer Electrical Signaling Scope
The SuperSpeed physical layer (PHY) can be divided into a logical and electricalsignaling sections. This chapter covers the transmitter and receiver electricalspecifications for the signaling elements in the highlighted region at the bottomof Figure 25-1 on page 592, including:
• Jitter budgeting• SuperSpeed transmitter requirements• SuperSpeed receiver requirements• Low frequency periodic signaling (LFPS)
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Figure 25-1: Physical Layer Tx And Rx Electrical Section
(Rx)D-D+
Parallel To Serial
Scrambling (D)
(Tx)
x1
D/K x8
x8
x10
D/K8b/10b Encode
LFPSTransmit
Tx
Bit C
lk
Core C
lk
D+D-
Equalization RxTx
De-emphasis
Rx Termination
PLL & Local Clocks
Tx Termination
8b/10b DecodeC
ore Sym
Clk
x8
Descrambling (D)
D/K
x8
Serial To Parallelx1
x10
x10
Elastic Buffer
Rx S
ymC
lk
D10.2K28.5 inverted?
LFPS Detect
Clock Recovery
D/K#R
x Clk
Sym
Lock Data RecoveryCircuit (DRC)
Rx Link Layer
Rx Protocol Layer
Tx Link Layer
Tx Protocol Layer
Chapter 25: SuperSpeed Signaling Requirements
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Normative And Informative SpecificationsThe USB 3.0 specification and related support documents define SuperSpeedtransmitter and receiver electrical requirements as well as the testing methodsto be used to verify compliance. A distinction is made between normative andinformative requirements.
• Normative specifications must be observed and are intended to assure com-ponent inter-operability.
• Informative specifications are optional and intended to “assist productdesigners and testers in understanding the intended behavior of the Super-Speed bus”.
Jitter Budgeting (Informative)
GeneralAs indicated in Figure 25-2 on page 593, when serial data moves across theSuperSpeed link at 5 Gb/s, a number of factors affect the signal eye quality at thereceiver inputs and the receiver’s ability to recover a stable clock for samplingthe incoming bit stream. These factors include:
• Deterministic jitter (Dj) cause by transmission line effects• Data-dependent random jitter (Rj) caused by data patterns• Noise induced into the channel by other signal sources• Frequency-dependent attenuation of the channel
Figure 25-2: Effects Of Jitter On SuperSpeed Eye
Eye Width (min)
Eye Height (min)
300
250
200
150
100
50
0
-50
-100
-150
-200
-250
DifferentalV
oltage (mV
)
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26 Compliance Testing
The Previous Chapter
The previous chapter discussed the SuperSpeed link electrical interface and sig-naling. Major topics included clocks and transmitter/receiver electrical specifi-cations, as well as Low Frequency Periodic Signaling (LFPS).
This Chapter
This chapter describes key features of compliance testing, a collection of testsdesigned to verify conformance with USB 3.0 Specification protocol, link, andphysical layer requirements. Compliance testing is slightly different for hosts,hubs, and peripherals and is required in order to assure device inter operabilityand receive USB certification.
The Next Chapter
The next chapter covers receiver loopback and link bit error rate testing (BERT),including loopback master generation of the test pattern and re-transmission bythe slave. In addition, the LTSSM view of loopback and optional BERT statemachine and slave error counting/reporting protocol are also described.
Scope Of USB 3.0 Compliance Testing
The term compliance testing in the context of USB 3.0 is sometimes used in a veryrestricted way to refer to electrical compliance testing. Electrical compliancetesting defines methods for verifying SuperSpeed voltage and timing parame-ters are within the limits imposed by the USB 3.0 specification, but it is actuallyjust one component in a larger suite of compliance tests.
The USB Implementers Forum (USBIF) website, usb.org, provides a set of sup-plementary specifications and white papers covering the full range of compli-ance testing. Generally speaking, the compliance test specifications describeitems to be verified, procedures used to test them, and the outcome required todemonstrate compliance with the USB 3.0 Specification.
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Key Compliance Testing DocumentsCompliance testing is based on requirements in the base USB 3.0 Specification.Test criteria and procedures for checking SuperSpeed compliance of host, hub,and peripherals are contained in the three key compliance testing specificationsidentified in Figure 26-1. For clarity, the USB 2.0 interfaces and the separatespecification defining compliance testing for USB 3.0 cables are not shown.
Figure 26-1: Scope Of Three Key USB 3.0 SuperSpeed Compliance Tests
Host
USB 3.0 Peripheral
USB 3.0 Hub
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Protocol LayerLink Layer
PHY (Electrical)PHY (Logical)
Electrical Compliance Test Specification
USB Command Verifier Compliance Test Specification
Link Layer Test Specification
11
33
22
11
33
22
11
33
22
Chapter 26: Compliance Testing
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Compliance Testing Resources: Documentation
Compliance testing specifications, white papers, and other documents are avail-able from the usb.org website. These include:
• USB Command Verifier Compliance Test Specification, SuperSpeed USB• USB 3.0 Link Layer Test Specification• USB 3.0 Electrical Compliance Test Specification• USB 3.0 Cable and Connector Compliance Document
If you are working with a stand-alone or integrated xHCI-compliant host con-troller, additional compliance checks are required and the following documentsmay also be useful:
• xHCI Inter operability Test Procedures For Peripherals, Hubs, and Hosts• xHCI Backwards Compatibility Test Procedures For Hosts
Compliance Testing Resources: Hardware/Software
Check the usb.org website and USB-IF eStore to view a wide range of hardwareand software products related to SuperSpeed USB compliance testing.
Some examples:
• USB30CV, the USB 3.0 Command Verifier, is the official software used torun device and hub framework tests that are required for certification.USB30CV includes compliance drivers and other software for xHCI hostcontrollers.
• Lists of known good devices (KGD) and known good hubs (KGH) are alsoavailable to help during the compliance testing process.
• Signal Test (Sigtest) Tool is available for download. The is the official toolused during voltage and jitter electrical compliance testing. It may be usedin conjunction with the SuperSpeed electrical test fixture available in theUSB-IF eStore.
• Several Peripheral Development Kits (PDKs), including xHCI-based kits.• USB Low Speed, Full Speed, High Speed, and SuperSpeed devices which
are certified as compliant. The devices are very useful when checkingdownstream facing port compliance of a USB 3.0 host controller root hub oran external USB 3.0 hub.
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27 Receiver Loopback Testing
The Previous Chapter
The previous chapter described key features of compliance testing, a collectionof checks designed to verify conformance with USB 3.0 specification protocol,link, and physical layer requirements. Compliance testing is slightly differentfor hosts, hubs, and peripherals and is required in order to assure device interoperability and to receive USB certification.
This Chapter
This chapter covers receiver loopback and link bit error rate testing (BERT),including loopback master generation of the test pattern and re-transmission bythe slave. In addition, the LTSSM view of loopback and optional BERT statemachine and slave error counting/reporting protocol are also described.
Loopback Motivation
The target bit error rate (BER) for each USB 3.0 SuperSpeed link is 10-12. Becauseof the dual simplex signaling, it is certain that errors will occur in each directionof the link. Loopback provides a standard way to quantify the actual bit errorrate and isolate errors occurring on the 5GT/s link itself from those related tointernal device hardware problems, protocol violations, etc. The USB 3.0 specifi-cation includes a special LTSSM Loopback state for performing the bit error ratetest (BERT) and defines the role of each link partner when loopback is in use.
Standard Loopback Configuration
There is one master and one slave in a loopback configuration. The master,often a protocol exerciser or other test fixture, sources the loopback data testpattern symbols, checks for errors in symbols “looped back” (retransmitted) toit by the slave, and accumulates an error count that may then be correlated tothe target link BER of 10-12.
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Figure 27-1 on page 640 is a conceptual diagram depicting the general loopbackconfiguration. In this case, the slave does not support the optional BERT statemachine and error counting/reporting capability.
General Master And Slave Loopback Rules
• While in loopback, devices maintain the same transmitter and receiver elec-trical specifications as for U0 (low impedance receiver termination, etc.)
• The master uses normal rules in sending 10 bit symbols, including SKPordered sets.
• Receiver loopback requires the slave to re-time (reclock) the incoming BERTdata test pattern (BDAT) symbols before returning them to the master. Asmentioned previously and illustrated in Figure 27-1 on page 640, the loop-back path in the receiver resides completely at the Physical Layer.
Figure 27-1: Loopback Master And Slave
De-serializerSerializer
TxRx
Physical Layer
Elastic Buffer
8/10b Encoder 10/8b Decoder
Descrambler
Loopback Path
SKP
Loopback Slave (Device Under Test--DUT)
Link Layer
Protocol Layer
Loopback Master (Test Fixture)
RxTx
BDATError Check
BDAT BDAT
BDAT BDAT SKP
SKP
LoopbackControl
Reset LFPS
LFPSDetect
LTSSM
Chapter 27: Receiver Loopback Testing
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• The specification indicates that “Loopback must occur in the 10-bitdomain”, meaning that the receiver must deserialize BDAT stream and per-form loopback operations using 10-bit symbols. This also implies thereceiver disables or bypasses its own 8b/10b encoder/decoder and scram-bler/descrambler logic for the transmit side of the BDAT loopback datapath.
• Other than differential signal polarity inversion, the loopback slave doesnot attempt to correct any errors. Symbols are sent as received, except forSKPs which may be added or dropped as needed by the slave in the man-agement of its elastic buffer.
The Loopback Test Pattern BERT Data (BDAT)
BDAT, the bit error rate test (BERT) data test pattern, consists of scrambled andencoded NOPs as shown in Table 27-1. The duration of the BDAT transmitsequence is implementation specific but, because of the 16-stage LFSR Scram-bler, an extended BDAT pattern is pseudo-random and repeats every 64K sym-bols.
Optional Loopback Slave Error Counting Support
A limitation of the standard BERT loopback scheme is that the test pattern isonly sourced and checked by the loopback master, making it difficult for thetest fixture to determine whether the outbound, inbound, or both directions ofthe SuperSpeed dual simplex link are encountering bit errors.
The specification provides an option for loopback slaves to perform a localcheck of received test pattern symbols as they are retransmitted to the master.To this end, a slave BERT state machine is defined as is a collection of ordered
Table 27-1: Loopback BDAT Symbols
Symbol Number Encoding Description
All <0:n> D0.0(NOP)
BDAT symbols. Bit Error Rate Test (BERT) protocol uses scrambled and encoded NOP symbols as loopback data.
Compliance Tesng
