Studies on Channel Coupling and Floating Body Effects and Their Impacts on Device

Performance and Reliability in SOI MOSFET

Presenter: Franklin L. DuanPh.D. Advisor: Prof. D.E. Ioannou

Department of Electrical & Computer EngineeringSchool of Information Technology and Engineering

George Mason UniversityFairfax, Virginia

• MOSFET• SOI MOSFET• SOI Advantages• SOI Basic Features/Problems• Five Topics Studied • Summary of the Results

Outline

S I T E

IT: Information Technology

Soft

Circuit

MOSFET

Solid

Device

Information Technology

Others

Tree of Information Technology

Silicon

Source Drain

Gate

Metal

Oxide

MOSFET (Metal Oxide Silicon Field Effect Transistor)

Scale factor (K>1)What to scale down Surface dimension 1/K

Vertical dimension 1/KOperating voltage 1/K

Results of the scaling down Delay time 1/K

Power dissipation 1/K2

Power-delay product 1/K3

Scaling-down Rule of MOSFET

Moore’s Law of VLSI

0

100

200

300

400

500

600

0 40 80 120 160 200 240 280

Year

Tra

ns

isto

rs p

er

Die

1970 74 868278 94 9890103

109

108

107

106

105

104

DRAM

4K

4M

1M

256K

64K16K

256M

64M

16M

• Hot carrier degradation due to the increased electric field and hot carrier injections

• Lowered circuit speed due to the lower driving current and higher capacitance

Side Effects of Scaling-down

BOX

G1 DS

G2

N+ N+PSi

Si

SOI (Silicon On Insulator) MOSFET

• Radiation hardness • Low power/high speed

– Reduction in parasitic capacitance– Improved subthreshold slope

• Improved short channel effect • CMOS latch-up free• Increased ULSI packing density• Simplified fabrication

SOI Advantages

SOI Three Basic Features in Device Physics

• Dual Gate control • Channel Coupling • Floating Body Effect

G1

G2

Three Basic Features of SOI

1

23

Five Topics Studied in the Thesis

• Dual gate control: – Opposite channel based-hot-carrier injection (OCBI)

technique, unique tool for hot carrier study in SOI • Channel coupling:

– trade-off between hot carrier degradation and FBE• Floating Body Effect (FBE):

– abnormally higher impact ionization rate at the edges• Two modes of operations in FD SOI:

– a new mixed mode structure • Bulk technology integration:

– performance and reliability trade-off

Methodology/ Characterization

• Experimentally• hot carrier stressing • substrate current (as

a monitor of degradation) measurement

• single transistor latch up voltage characterization

• By simulation• map:

• electric potential

• electric field, • current path,

• calculate :• hot carrier generation • hot carrier injection

current

1. OCBI Technique(Opposite Channel Based Injection)

-N+ N+P - +

VG2= -30 V

VS= 0 V VG1= 1 V VD= 7 V

Ih

1E-16

1E-15

1E-14

1E-13

1E-12

1E-11

0 1 2 3 4 5VG1 (V)

Ie2=0

Ih2

10-16

10-12

10-14

(A/m)

Pure Hole Injection Into the BOX

Ih2: hole injection current

Ie2: electron injection current

VD=7V, VG2= -30V.

Shift of Characteristics After Hole Injection

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

20 25 30 35 40

VG2

I D (

A)

Original

10 hrs stressing

ID-VG2

0

2

4

6

8

10

12

10 100 1000 10000

Time(S)

V

T2(V

)

Standard SIMOX

With a supplemental O2 implantation

Back Threshold Voltage Shift ( ) as a

Function of Stress Time

- VT2

-2

-1

0

1

0 0.05 0.1ts(m)

Eg

(eV

)-30 V 0 V +5 V____Series4Series6

VG2={

Ec

Ev

2. Channel Coupling

Channel C

oupling Effect on H

ot C

arrier Tem

perature, Impact

Generation and E

lectric Field

Substrate Current Dependence on the Back Gate Bias in FD SOI MOSFET

1E-12

1E-10

1E-08

1E-06

1E-04

1E-02

-1 0 1 2 3

VG1 (V)

-30V

0V

+5V

Series4Series5Series6

ID

ISUB

Substrate Current Dependence on the Back Gate Bias in PD SOI MOSFET

0E+00

2E-06

4E-06

6E-06

8E-06

0 2 4 6

VG1 (V)

I SU

B (

A)

0V

10V

20V

30V

40V

50V

60V

Channel Coupling Effect onHot Carrier Degradation

1

10

100

1E+1 1E+3 1E+5Time (s)

I D (1

0-5A

)-30V

0V

+5V

Power(+5V)Power(0V)Power (-30V)

Channel Coupling Effect on Single Transistor Latch-up

7.0

7.4

7.8

8.2

8.6

-70 -50 -30 -10 10

VG2 (V)

VD

LU (

V)

Impact Generation Rate as a Function of Silicon Film Thickness

0.8um (bulk)0.4um

0.3umTs=0.25um

3. Study of Floating Body Effect (FBE) its Edge and Width Effect

SiO2

p

VE

VC

W

n+

n+

0.05

0.1

1 53 752515

W=2m W=10m W=50m

(m)

2525 25

25 25 25

1515 15

Contour Plot of Impact Generation Rate for Different Channel Width

0

5

10

15

20

25

0 0.5 1

X/W

log

G (

1/[

cm3.s

])m

mm

W=

Abnormally Higher Impact Generation Rate at the Edges

1E+00

1E+04

1E+08

1E+12

1E+16

1E+20

0 0.5 1X/W

Lo

g (

G (

1/cm

3 .s))

W=2W=10

Impact Generation Rate at the Edges When the Body is Grounded

umum

6

7

8

0 10 20W (m)

VD

LU (

V)

Body Floating

Body Grounded

Single Transistor Latch-up Voltage as a Function of Device Width

0.01

0.10

1.00

10 100 1000 10000 100000

10

5

3.5

Power(3.5)Power(10)Power(5)

W=10m

W=5.0m

W=3.5m

ID/I D

Time (s)

Hot Carrier Degradation of Three Deviceswith Different Width

0.0000

0.0001

0.0002

0.0003

0 2 4 6

W=5.6

W=3.6

VD (V)

W=3.6m

W=5.6m

0

100

200

300I D

/W (A

/m

)

VG=4 V

VG=3 V

VG=2 V

VG=1 V

Kink Effect Dependence on Channel Width

4. A New FD SOI MOSFET Structure

N+ N+P

Two existing FD SOI MOSFETs

N+ N+N-

N+ P+

INV: inversion mode ACC: accumulation mode

Potential Profiles of the Inversion and Accumulation Mode FD SOI MOSFET

-0 .4

-0 .2

0

0.2

0.4

P ot (V )

Invers ion M ode

-0.4

-0.2

0

0.2

0.4

Pot (V)

Accumulation Mode

-0.2

-0.1

0.0

0.1

0.8 1.20 0.4

n-type n+n+

p-polyspacer

p-type

BOX

(m)

(m)

Virtually Fabricated New SOI Device (by SUPREM)

1E-16

1E-13

1E-10

1E-7

1E-4

0 4 8 12

VD (V)

I D (

A/

m)

ACCMIX

INV

Comparison of Transconductance and Latch-up Voltage of the Three Devices

0E+0

1E-5

2E-5

3E-5

0 2 4 6

VG1 (V)

Gm (

A/V

.m

)

ACCMIXINV

1.01E+001.51E+002.01E+002.51E+003.01E+00

0.0E+0

6.0E-15

1.2E-14

1.8E-14

0 1 2 3 4

VG1 (V)

Ie1

(x1

0-15 A

/m

)accinvmix

18

12

6

0

0.0E+00

5.0E-15

1.0E-14

1.5E-14

0 1 2 3 4VG1 (V)

Ie3

(x1

0-15 A

/m

)

accinvmix

15

10

5

0 0.0E+0

1.0E-18

2.0E-18

3.0E-18

4.0E-18

0 1 2 3 4 5VG1 (V)

Ih3

(x1

0-18 A

/m

)

accinvmix

4

3

0

2

1

0.0E+00

3.0E-16

6.0E-16

9.0E-16

0 1 2 3 4

VG1 (V)

Ih1

(x1

0-16 A

/m

)

accinvmix

9

6

3

0

Comparison of the Hot Carrier Injection of the Three Devices

Ie2

Ih1

Ih2

Ie1

A

LDD Implant S/D Implnat

N+ N N-(A)

(B)

(C)

Si

BOX

Gate-OX

SpacerPoly-Si(p+)

5. LDD Design Tradeoff in SOI MOSFET

(A)

(C)

(B)

Experimental Results:Tradeoff Between Performance and Reliability)

C

B

A

3

3.5

4

LDD Design

Latc

h-up

Vol

tage

(V

)

C

BA

1E+05

1E+06

1E+07

1E+08

1E+09

LDD Design

Life

time

(s)

Contours of Im

pact Generation R

ate of the T

hree LDD

Designs

Structure Impact Rate Integral (1/cm2 s) Latch-up

Voltage (V)

Top Middle Bottom Average

A 8.5x1020 1.7x1022 2.9x1022 1.6x1022 3.40

B 8.0x1020 8.2x1021 2.3x1022 1.1x1022 3.55

C 7.9x1020 1.5x1021 1.8x1021 1.4x1021 3.80

Comparison of Impact Generation Rate and Latch-up Voltage

Summary of the Results

• Opposite channel based injection can happen by the aid of dual gate control and this phenomenon can be used as a tool to study the hot carrier degradation

• Channel coupling imposes a trade-off between the hot carrier reliability and single transistor latch-up in SOI MOSFET

• The rate of carrier generation rate is higher at the edge of SOI MOSFET and more so for wider devices. Wider devices have lower breakdown voltages.

• A new structure was proposed which holds the weaknesses of the current FD SOI MOSFETs and is more resistant to hot carrier injections

• Optimized bulk LDD technology faces a tradeoff between hot carrier reliability and single transistor latch-up in SOI MOSFET