Structural Modeling:EntitiesPortsArchitecturesPackages

Ports and configurations, structures

VHDL Structure DescriptionVHDL Structure Description describes basic

hardware components and their interconnections via ports

the basic features which should be defined:

– component instantiation (includes regular structures),

– ports interconnection and unconnected ports,

– configuration (which entities and architectures are used to define components).

Our goal is in next slides to explain the Component instantiation

PortsPorts ports in entity declarations

– only signals are allowed of mode in, out, inout, buffer, an example

• ports in component declarations- only signals are allowed of mode in, out, inout, buffer,• an example

Component Instantiation StatementComponent Instantiation Statementlabel-identifier : component-mark

generic map association-list

port map association-list ;

• an example

Child : And2 port map (S1, S2, S3);

• component instantiation statement performs association between local and actual port and checks the following rules:- the actual must be an object of class signal;

» it can be defined as a signal declaration or may be a formal port declared in entity declaration,

- the type of actual must be the same as the type of the local; if types are not the same a type conversion must be used.

- signal modes must follow given requirements.

• examples of a simple ALU, a decoder and a data bus.

Default Component BindingDefault Component Binding

And-or structure build from standard NANDs

Structural Architecture for and_or: Structural Architecture for and_or: an examplean example

The correct code is this

In next slide we will see the circuit

Let us compare the block diagram with the VHDL description

In your homeworks, draw a diagram with all your names and explain the role of your gates and components

Structural Architecture for and_or: an Structural Architecture for and_or: an example: example: ARCHITECTURE STRUCTURE 2ARCHITECTURE STRUCTURE 2

Architecture structure2

Circuit in next slide

Fast component for all

Non-Default Component BindingNon-Default Component Binding

Structural Architecture for and_or: Structural Architecture for and_or: an examplean example

Architecture structure3

Circuit in next slide

Fast only for G3

Default and Non-Default and Non-Default Port Default Port

BindingBinding

Structural Architecture for and_or: Structural Architecture for and_or: an examplean example

Architecture structure4

Use of component inside an architecture structure4

Configuration Specification: Configuration Specification: New ExampleNew Example

A new example:

configuration

For U0

Configuration SpecificationConfiguration Specification allows the designer to specify the selection of entity declaration and architecture body for each component in-stance, the general form of the configuration specification

Non-Default Component BindingNon-Default Component Binding

Default ValuesDefault Values if the signal is of a scalar subtype,

– then the implicit default value of each driver is defined to be T'LEFT, where

– T denotes the scalar subtype of the signal.

– type ThreeValue is ('X', '0', '1');

if the signal is of a composite subtype, – then each scalar subelement of the composite is a signal,

– and each driver of each of these scalar subelements is defined to have an implicit default value by the previous rule.

default value can be specified explicitly in the declaration of the signal or port

Default ValuesDefault Values

Unconnected PortsUnconnected Ports any port of mode

out, inout, or buffer may be unconnected provided its type is not an unconstrained array type; a port of mode in may be unconnected only if its declaration includes an explicit default expression.

the reserved word open indicates that a port is unconnected.

an example.

Configuration DeclarationConfiguration Declaration allows the designer to collect all of the binding information for the

model into a single place- configuration specification.

Structural Structural Architecture Architecture for and_or: for and_or: an examplean example

configuration

Architecture structure5 has fast nand only for G3 and standard nand for G1 and G2

Configuration DeclarationConfiguration Declaration an example

You can test behavior of various ready commercial chips working together

Regular StructuresRegular Structures useful for describing hardware which is build of multiple instances of the same

subcomponent connected in some regular pattern– it is done by the use of a generate statement

label-identifier : generation-scheme generate

concurrent-statements end generate identifier ;

– generation schemes:

for identifier in discrete-range if boolean-expression rules

– the generate parameter (in for statement) acts as a constant, however, the generic parameter can be used,

– there are no concurrent statements analogous to the sequential exit-statement and next-statement.

Regular Regular Structures- Structures- An ExampleAn Example

Regular Structures- An ExampleRegular Structures- An Example Generated Counter

ConfigurationsPackages

Do not be lost Do not be lost

SourcesSources

Prof. K. J. Hintz, Department of Electrical and Computer Engineering, George Mason University

Prof. John Wakerly, CISCO Systems and Stanford University. Dr. Jose Nelson Amaral, University of Alberta Krzysztof Kuchcinski More information on ECE 271 class of Marek Perkowski.