NAND Flash Failure Behavior

NAND Flash Failure NAND Flash Failure BehaviorBehavior

Sponsored By Micron Technology IncSponsored By Micron Technology Inc

Group Members and TopicsGroup Members and Topics

Rob WellsRob Wells Project IntroductionProject Introduction System Integration System Integration

Jeremy HamblinJeremy Hamblin Firmware DesignFirmware Design

Roger WhiteRoger White NAND DUT InterfaceNAND DUT Interface NAND Controller & TimingNAND Controller & Timing

David ChuDavid Chu Host GUI Interface & ApplicationHost GUI Interface & Application ConclusionsConclusions

Robert WellsRobert Wells

Project IntroductionProject Introduction

System IntegrationSystem Integration

Introduction to NAND FlashIntroduction to NAND Flash

What NAND Flash Memory IsWhat NAND Flash Memory IsNAND Flash Memory ApplicationsNAND Flash Memory ApplicationsWhat NAND Flash Memory Is NotWhat NAND Flash Memory Is NotProject ConceptProject Concept

An Affordable PlatformAn Affordable PlatformCustomizable Usage/Programming PatternsCustomizable Usage/Programming PatternsCharacterization/Analysis of NAND BehaviorCharacterization/Analysis of NAND Behavior

System IntegrationSystem Integration High Level ViewHigh Level View FPGA SystemFPGA System

Block Diagram InterfaceBlock Diagram Interface SOPC Builder OverviewSOPC Builder Overview

Component GenerationComponent Generation HAL (Hardware Abstraction Layer) – NIOS IIHAL (Hardware Abstraction Layer) – NIOS II HDL (Hardware Description Language) – Quartus IIHDL (Hardware Description Language) – Quartus II

Quartus II OverviewQuartus II Overview Integration of the FPGA systemIntegration of the FPGA system

Controller DevelopmentController Development

NIOS II OverviewNIOS II Overview Device DriversDevice Drivers FirmwareFirmware

Firmware to Controller IntegrationFirmware to Controller Integration Host PC to Firmware IntegrationHost PC to Firmware Integration

High Level ViewHigh Level View

SOPC

Components:• NIOS II Processor• SDRAM• USB• On-Chip Memory• LCD Display

HAL (Hardware Abstraction Layer)• C Code• API (Application Programming Interface)

HDL (Hardware Description Language)• Verilog CodeNAND Flash Controller• Custom Verilog Code (Roger)

Firmware• Custom C Code(Jeremy) Quartus II

NIOS IIApplication GUI Interface• Program the NAND Flash• Analyze/Display Results(David)

SOPC Builder(System On a Programmable Chip)

High Level ViewHigh Level View

Application GUI Interface• Program the NAND Flash• Analyze/Display Results(David)

• Configure Memory Usage• Memory Range• Data Pattern• Number of Cycles

• Analyze PerformanceWill NAND Flash Work Over the Lifespan of a Given Device?








FPGA development systemFPGA development system

NAND FlashController

(Roger)

SOPC BuiltSystem

(Jeremy)

ResetDelay

ClockGeneration








Example FPGA System With SOPCExample FPGA System With SOPC






















Firmware to Controller IntegrationFirmware to Controller Integration

Firmware

C Code

NIOS II

Controller

Verilog

Quartus II

Buffer

SOPC Builder








Host PC to Firmware IntegrationHost PC to Firmware IntegrationPhillips ISP1362

(USB)

SOPC Builder (HAL)

NIOS II (Device Driver)

WinDriver (Device Driver)

ConclusionsConclusions

System ComponentsSystem Components Custom Hardware Design (Verilog)Custom Hardware Design (Verilog) Custom Firmware Design (C)Custom Firmware Design (C) Powerful Design ToolsPowerful Design Tools Custom Built Application GUI InterfaceCustom Built Application GUI Interface

Inexpensive Platform for TestingInexpensive Platform for Testing Analysis of NAND Wear-Out From a Customizable Memory Analysis of NAND Wear-Out From a Customizable Memory

Usage ModelUsage Model Allows Developers to Determine if NAND Flash is a Viable Allows Developers to Determine if NAND Flash is a Viable

Solution for a Given ApplicationSolution for a Given Application Evaluate Other Aspects of NAND FlashEvaluate Other Aspects of NAND Flash

QuestionsQuestions

Jeremy HamblinJeremy Hamblin

Firmware DesignFirmware Design


SOPC BuilderSOPC BuilderSystem ComponentsSystem Components

Firmware Design (NIOS II)Firmware Design (NIOS II)Reset NAND OperationReset NAND OperationUSB InterfaceUSB Interface

Op-Code/AlgorithmOp-Code/AlgorithmNAND Flash AddressingNAND Flash AddressingExample Algorithm LayoutExample Algorithm Layout

Command TransferringCommand Transferring

SOPC BuilderSOPC Builder(System On a Programmable Chip)(System On a Programmable Chip)

NIOS II Processor

SDRAM

•Instruction & Data•Block Mapping & Status

Displays

Global Reset

USBBuffer

Read Enable







Reset NAND OperationReset NAND OperationFirst Operation After NAND Power UpFirst Operation After NAND Power UpOccurs During System InitializationOccurs During System InitializationPlaces NAND DUT (Device Under Test) in a Places NAND DUT (Device Under Test) in a

Known StateKnown State







USB InterfaceUSB InterfaceGenerates IRQ (Interrupt ReQuest)Generates IRQ (Interrupt ReQuest) ISR (Interrupt Service Routine) Receives Data ISR (Interrupt Service Routine) Receives Data

Sent From Host PC and Parses DataSent From Host PC and Parses Data

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

00 00 00 00 - Byte0

Padding

Algorithm

OP Code

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

Start Address – 3 Bytes

End Address – 3 Bytes

Padding – 1 Byte

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

# Cycles – 3 Bytes

Padding – 5 Bytes


Op-Code TypesOp-Code TypesRead IDRead IDWriteWriteReadRead

Algorithm TypesAlgorithm TypesContinuousContinuousChecker BoardChecker BoardRandomRandom


NAND Flash AddressingNAND Flash Addressing

Blocks

Bytes

Pages


NAND Flash AddressingNAND Flash Addressing

Algorithm ExampleAlgorithm Example

Continuous Cycle I Cycle II

Checker Board

Block-0

Block-1

…

Block N-1

Block N

Pag

e N

Pag

e N-1…

Pag

e 1

Pag

e 0

Erased

Programmed







Command TransferringCommand TransferringCommands & Data Transferred Through BufferCommands & Data Transferred Through Buffer

Different Data and Command RequirementsDifferent Data and Command Requirements Write- 2119 Bytes Transferred to NAND, 0 ReturnedWrite- 2119 Bytes Transferred to NAND, 0 Returned Read- 7 Bytes Transferred to NAND, 2112 ReturnedRead- 7 Bytes Transferred to NAND, 2112 Returned Erase- 5 Bytes Transferred to NAND, 0 ReturnedErase- 5 Bytes Transferred to NAND, 0 Returned Read Status- 1 Byte Transferred, 1 ReturnedRead Status- 1 Byte Transferred, 1 Returned

Each NAND Command Type Has its Own Buffer FunctionEach NAND Command Type Has its Own Buffer Function

Removes All NAND Device Timing Constraints Removes All NAND Device Timing Constraints From the FirmwareFrom the FirmwareFirmware Too SlowFirmware Too Slow

Firmware Design ConclusionFirmware Design Conclusion

Command Received Over USBCommand Received Over USBParsed in USB ISRParsed in USB ISR

Execution of Op-CodeExecution of Op-CodeCommand and Data are Passed to NAND Command and Data are Passed to NAND

Controller Through the BufferController Through the BufferCommand is Executed From Start Address to Command is Executed From Start Address to

End AddressEnd AddressRepeated for # of Cycles Given in Command Repeated for # of Cycles Given in Command

From HostFrom HostBlock Status Returned Over USBBlock Status Returned Over USB

QuestionsQuestions

Roger WhiteRoger White

NAND DUT InterfaceNAND DUT Interface

NAND Controller & TimingNAND Controller & Timing


Daughter CardDaughter CardOur Own??Our Own??Boise State’sBoise State’s



Pins to NAND ChipPins to NAND ChipOperationsOperations


Pins to NAND chipPins to NAND chip CLE (Command Line Enable)CLE (Command Line Enable) CE# (Chip Enable)CE# (Chip Enable) WE# (Write Enable)WE# (Write Enable) ALE (Address Line Enable)ALE (Address Line Enable) R/B (Ready/Busy)R/B (Ready/Busy) RE# (Read Enable)RE# (Read Enable) WP# (Write Protect)WP# (Write Protect) I/Ox (Input/Output)I/Ox (Input/Output)


Pins to NAND ChipPins to NAND ChipOperationsOperations


OperationsOperationsReadReadProgramProgramEraseEraseRead StatusRead StatusResetResetRead IDRead ID

Program OperationProgram Operation

NAND Controller & timingNAND Controller & timing


Erase OperationErase Operation


Reset OperationReset Operation

ConclusionsConclusions

NAND DUT InterfaceDaughter Card

NAND Controller & TimingPinsOperations

Questions?Questions?

User Interface, USB, and User Interface, USB, and Conclusions Conclusions

By: David Chu By: David Chu

OverviewOverview

User InterfaceUser Interface Command InterfaceCommand Interface

Functionality and Scripting InformationFunctionality and Scripting Information Results InterfaceResults Interface

Functionality, Database Information, and XML File DescriptionFunctionality, Database Information, and XML File Description Charts InterfaceCharts Interface

FunctionalityFunctionality

USB USB Functionality and Bit OrganizationFunctionality and Bit Organization

Conclusions Conclusions Methods, Results, and Future ImprovementsMethods, Results, and Future Improvements

Three Parts to the UIThree Parts to the UI

Command Interface - Allows the user to Command Interface - Allows the user to specify the method and method specify the method and method parameters that are sent to the controller. parameters that are sent to the controller.

Results Interface - Allows the user to view, Results Interface - Allows the user to view, store, load, and search through the results store, load, and search through the results stored in a databasestored in a database

Charts Interface - Allows the viewer to Charts Interface - Allows the viewer to visually see the results in graphical formvisually see the results in graphical form

Command InterfaceCommand Interface

Command Interface FunctionalityCommand Interface Functionality

Allows the user to easily construct Allows the user to easily construct commands and send them to the controllercommands and send them to the controller

Allows the user to load in scripts to Allows the user to load in scripts to automate the controllerautomate the controller

Allows the user to link to the Results Allows the user to link to the Results Interface Interface

Script FilesScript Files

Allow the user to automate the NAND Allow the user to automate the NAND Flash test application through a comma Flash test application through a comma delimited file.delimited file.Script files are written in the following manner:Script files are written in the following manner:

Read,000000000101111001000000,000000000110000111000000,Full,200

Results InterfaceResults Interface

Results Interface FunctionalityResults Interface Functionality

Allows the user to easily visualize data that is Allows the user to easily visualize data that is stored in the database.stored in the database.

Allows the user to sort items in the table by Allows the user to sort items in the table by columnscolumns

Allows the user to search the data for specific Allows the user to search the data for specific results or a range of resultsresults or a range of results

Allows the user to load or save database Allows the user to load or save database information into or from an XML fileinformation into or from an XML file

Allows the user to link to the Charts InterfaceAllows the user to link to the Charts Interface

Database InformationDatabase Information

Uses SQL and runs on Microsoft SQL Uses SQL and runs on Microsoft SQL Server 2005Server 2005

Contains one table with the following Contains one table with the following elements: ID, Cycle, MemoryAddress, elements: ID, Cycle, MemoryAddress, FunctionName, Status, and AlgorithmFunctionName, Status, and Algorithm

Contains the following stored procedures: Contains the following stored procedures: FindID, RemoveID, RemoveAll, InsertID, FindID, RemoveID, RemoveAll, InsertID, and UpdateIDand UpdateID

XML FilesXML Files<?xml version="1.0" standalone="yes" ?> <?xml version="1.0" standalone="yes" ?> - <NewDataSet>- <NewDataSet>- <FlashStatusTable>- <FlashStatusTable> <ID>1</ID> <ID>1</ID> <Cycle>1</Cycle> <Cycle>1</Cycle>

<MemoryAddress>6</MemoryAddress> <MemoryAddress>6</MemoryAddress> <FunctionName>Write</FunctionName> <FunctionName>Write</FunctionName> <Status>Bad</Status> <Status>Bad</Status> <Algorithm>Checker</Algorithm><Algorithm>Checker</Algorithm>

</FlashStatusTable></FlashStatusTable>- <FlashStatusTable>- <FlashStatusTable> <ID>2</ID> <ID>2</ID> <Cycle>15</Cycle> <Cycle>15</Cycle>

<MemoryAddress>4</MemoryAddress> <MemoryAddress>4</MemoryAddress> <FunctionName>Write</FunctionName> <FunctionName>Write</FunctionName> <Status>Bad</Status> <Status>Bad</Status> <Algorithm>Checker</Algorithm> <Algorithm>Checker</Algorithm>

</FlashStatusTable></FlashStatusTable>- <FlashStatusTable>- <FlashStatusTable>

Generated from Generated from database when the database when the user selects the save user selects the save buttonbutton

Allows the user to Allows the user to manipulate the results manipulate the results to their specific needsto their specific needs

Allows the user to Allows the user to import data into other import data into other applications that applications that support XMLsupport XML

Charts InterfaceCharts Interface

Chart Interface FunctionalityChart Interface Functionality

Allows the user to visually represent the Allows the user to visually represent the total number of failures over cyclestotal number of failures over cycles

Allows the user to turn on and off Allows the user to turn on and off horizontal and vertical gridshorizontal and vertical grids

OverviewOverview







USB InformationUSB Information

Connection: USB 2.0 connectionConnection: USB 2.0 connectionTransfer Rate: USB Full-Speed Transfer Transfer Rate: USB Full-Speed Transfer

Rate (12 Mbps)Rate (12 Mbps)Transfer Method: USB Interrupt TransfersTransfer Method: USB Interrupt TransfersPnP CompatiblePnP Compatible

Bit OrganizationBit Organization

USB InterfaceUSB InterfaceSends 16-BytesSends 16-BytesBytes are Transferred Using Big EndianBytes are Transferred Using Big Endian

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

00 00 00 00 - Byte0

Padding

Algorithm

OP Code

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

Start Address – 3 Bytes

End Address – 3 Bytes

Padding – 1 Byte

00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes

# Cycles – 3 Bytes

Padding – 5 Bytes

OverviewOverview







Project SynopsisProject Synopsis

Method – used the Altera Method – used the Altera DE2 development board DE2 development board to create a system to create a system consisting of a memory consisting of a memory module, a processor, and module, a processor, and an FPGA controller in an FPGA controller in order to enable order to enable communication between communication between a host PC test application a host PC test application and NAND Flash. and NAND Flash.

FPGA/ProcessorDev System

Host PC

USB ver 2.0

Simple GUI

DUT

Project Synopsis Cont.Project Synopsis Cont.

Results – created an Results – created an affordable and easy affordable and easy to use application that to use application that allows developers to allows developers to run multiple tests on run multiple tests on NAND Flash and NAND Flash and easily visualize the easily visualize the results through results through tabular and graphical tabular and graphical methodsmethods

Future ImprovementsFuture Improvements

Redesign the GUI to work with multiple Redesign the GUI to work with multiple operating systemsoperating systems

Configure the NAND Flash controller to Configure the NAND Flash controller to operate with NAND Flash from other operate with NAND Flash from other manufacturersmanufacturers

Use caching methods to improve the Use caching methods to improve the performance of the NAND Flash test performance of the NAND Flash test application application

QuestionsQuestions

Thank You:Thank You:

Ken StevensKen StevensDennis ZattieroDennis ZattieroDean KleinDean KleinKen KoenigKen Koenig

Documents

NAND Flash Failure Behavior