PowerPoint Presentation

Nanoelectromechanical Systems (NEMS)Power ManagementVasantham Sudheer Kumar Meen Chan Winston SeoSECTION TITLE | 2History

http://undergrad.research.ucsb.edu/wp-content/uploads/AFM_laser.gifRichard Feynmans Theres Plenty of Room at the Bottom 1959, Caltech

Issued two challenges: Operational nanomotor (W. McLellan, 1960) and writing letters on a nanoscale (T. Newman, 1985)

Considered implications of mechanical atomic manipulation: denser computer circuitry, atomic and sub-atomic microscopes

Latter realized by AFM and STM

Modern NEMS

Nanoelectromechanical Systems (M. L. Roukes , Caltech)Key functions and applications:

SensorsCommunicationsBiotechnologyRobotics

High fundamental frequenciesHigh mechanical responsivityHigh levels of sensitivity

Needed for novel modes of efficient actuation

Modern NEMS

Example: SEM image Tuning fork geometry nanoelectromechanical switch

Venumbaka, 2010, U. of Utah

Modern NEMS

Example: SEM image High-frequency resonator

Represents a new class of ultra-sensitive magnetometers for DC and low frequency AC magnetic fields.

Easily integrate-able into CMOS technologyVenumbaka, 2010, U. of Utah

Power Consumption and Management in NEMS

Efficient power and thermal management is the biggest limiting factor of further downscaling of electric devices:

Power leakage constitutes nearly 50% of a chips total power usage beyond the 65nm CMOS technology

Exponential increase of power leakage is a top concern, especially in memory systems; decreases robustness of read/write operations

Venumbaka, 2010, U. of Utah

Power Consumption and Management in NEMS

Power density: W cm^-2

Cm dominates, exponentially increasing power density

Standard 10nm chips: 95W cm^-2

R&D chips: 1000W cm^-2 reportedSung, M. K.; Mudawar, I. (2009). "Single-phase and two-phase hybrid cooling schemes for high-heat-flux thermal management of defense electronics"Parallelism to the Rescue

Parallelism allows slower, more efficient coresWhile maintaining overall throughputWorks well (if you can parallel program), but

Novel power management architecture

Motivation : 3D Stacked Integrated Circuits Technique : Through Silicon Vias based integration technology

Addressed technological developments

(i) A Nano-ElectroMechanical (NEM) device, the Suspended Gate FET (SGFET) as sleep transistor

(ii) Make use of the 3D potential by placing the sleep transistor (the entire power management infrastructure) on a dedicated tier of the 3D stacked Integrated Circuit.Focus: NEMS utilization as sleep transistor in CMOS power gated integrated circuitsDedicated tier in the stack for the sleep transistors

3D Stacked SG-FET Based Power Management Architecture.3D STACKED ICSTo achieve tight chip integration

Through Silicon Vias (TSVs) as interconnectsbetween the stacked diesSUSPENDED GATE FET

Operation of Electromechanical SwitchResponse to the bias Voltage levelsPull in Effect and Pull out effectWhats new in Power Gating Architectures Existing Power gating Architectures use STs as ring or columns around gated blockNEMS technology dies containing SG-FET STs placed between dies containing the actual power gated circuits

Precious AreaReduction in Interconnect lengths between gated blocksAdvantagesConclusion & Future ScopeReferencesJames E. Hughes Jr;Massimiliano Di Ventra; Stephane Evoy (2004).Introduction to Nanoscale Science and Technology (Nanostructure Science and Technology). Berlin: Springer.ISBN1-4020-7720-3.G. Panic, Z. Stamenkovic, and R. Kraemer, Power gating in wireless sensor networks, in Wireless Pervasive Computing, 2008. ISWPC 2008. 3rd International Symposium on, 2008, pp. 499503.In Summary, Novel Suspended GateFET (SG-FET) based power management architecture for 3D Through Silicon Vias based integration technology. Our

3D integration is an effective way to make use of the SG-FET characteristics, i.e., abrupt switching and extreme low leakage, in effective NEMS-based power/energy/thermal management.