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Non-isolated High gain DC-DC converter by Quadratic boost converter and voltage Multiplier cell Divya Navamani.J 1 , Vijayakumar.Ka 2 and Lavanya.Ab 3 13 Asst professor, EEE dept, SRM university,kattankulathur-603203, India [email protected] 2 Professor, EEE dept, SRM university,kattankulayhur-603203, India January 8, 2018 Abstract A novel non- isolated DC-DC converter is proposed by combining quadratic boost converter with voltage multiplier cell. The proposed converter has low semiconductor devices voltage stress and switch utilization factor is high. The superiority of the converter is voltage stress of the semi- conductor devices depends on voltage multiplier (VM) cell. By increasing the VM cell the stresses across the devices reduces drastically. The Proposed converter has same num- ber of components compared to certain voltage lift convert- ers taken for comparison. A detailed comparative study is made on the proposed converter with few voltage lift con- verters in literature, conventional boost with VM cell and quadratic boost converter. A 40W prototype is constructed with 12V input voltage and 96V output voltage to verify the performance and validate the theoretical analysis of the proposed converter. Key Words : High gain; Quadratic;Multiplier;CCM; DCM;Voltage stress;Efficiency. 1 International Journal of Pure and Applied Mathematics Volume 118 No. 17 2018, 413-434 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu 413

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Page 1: Non-isolated High gain DC-DC converter by …Non-isolated High gain DC-DC converter by Quadratic boost converter and voltage Multiplier cell Divya Navamani.J1, Vijayakumar.Ka2 and

Non-isolated High gain DC-DCconverter by Quadratic boost converter

and voltage Multiplier cell

Divya Navamani.J1, Vijayakumar.Ka2

and Lavanya.Ab3

1 3Asst professor, EEE dept,SRM university,kattankulathur-603203, India

[email protected], EEE dept,

SRM university,kattankulayhur-603203, India

January 8, 2018

Abstract

A novel non- isolated DC-DC converter is proposed bycombining quadratic boost converter with voltage multipliercell. The proposed converter has low semiconductor devicesvoltage stress and switch utilization factor is high. Thesuperiority of the converter is voltage stress of the semi-conductor devices depends on voltage multiplier (VM) cell.By increasing the VM cell the stresses across the devicesreduces drastically. The Proposed converter has same num-ber of components compared to certain voltage lift convert-ers taken for comparison. A detailed comparative study ismade on the proposed converter with few voltage lift con-verters in literature, conventional boost with VM cell andquadratic boost converter. A 40W prototype is constructedwith 12V input voltage and 96V output voltage to verifythe performance and validate the theoretical analysis of theproposed converter.

Key Words : High gain; Quadratic;Multiplier;CCM;DCM;Voltage stress;Efficiency.

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International Journal of Pure and Applied MathematicsVolume 118 No. 17 2018, 413-434ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

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1 Introduction

High gain dc-dc converter topologies are derived for MEA (MoreElectric Aircraft), Micro and Nano satellite Electric Thrusters dur-ing last decades. Introduction of electric propulsion system needa dedicated dc-dc converter to convert the solar energy for elec-tric thruster [1-3]. Electric thruster requires a high DC voltage ofaround tens of kV depending on the type of electric thruster used[4]. Recent trend in power distribution in MEA is the use of highvoltage DC system. Certain values of system voltage under researchare 270, 350 and 540V [5]. Bidirectional DAB (Dual Active Bridge)dc-dc converter is introduced in [6] to meet the power demands ofaircraft electric loads. Boosting type converters are required boost-ing low level voltage from PV to the desired level of voltage. Usingconventional boost converter, voltage step up can be obtained byincreasing the duty cycle nearer to unity. By increasing the dutycycle the conduction loss, switching loss are increased which resultsin low efficiency [7][8].Series connection of multiple boost converterresults in high voltage gain. However, cost of the converter is in-creased due to too many components [9].By escalating the turnsratio of the transformer in isolated DC-DC converter, large volt-age conversion ratio can be obtained. However the diode stressvoltage and voltage spikes across the switches should be consideredwith certain remedial measures [10-13][30].Large voltage gain can beachieved with coupled inductor in the converters [14][16]. However,they suffer with similar disadvantages of isolated DC-DC convert-ers. By incorporating switched capacitor or switched inductor inthe converter the voltage conversion ratio can be increased. More-over, voltage regulation is poor [17].Based on 3SSC (three stateswitching cell) high voltage gain converter is introduced. However,the circuit weight and volume is high due to the presence of au-totransformer. Soft switching techniques are incorporated in highstep up topologies to improve its performance [31].

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2 High voltage gain converters with volt-

age multiplier cell

The notable application of voltage multiplier cells are Travellingwave tube amplifier and capacitor charge transference [18][19]. Inboth the applications, it step ups the voltage to very high levelwithout the use of magnetic components. Incorporation of voltagemultiplier to DC-DC converter is not new and many articles werepublished in literature. High voltage gain converter is introducedwith capacitor voltage stacking cell [20]. However, the current stressresults in the circuit. Four switch high gain converter is introducedby employing cockroft- walton voltage multiplier cell [21].The con-ducting state of the switches are very complicated in that topology.The advantages of Voltage multiplier based step up converters arefollows:

• Diode-capacitor multiplier (VM cell) can be added to thetopology without modifying the original topology.

• No additional switch is needed apart from the main switch ofthe circuit which simplifies the gate drive circuit.

• Main switch, multiplier and output diode voltage stress de-pends on the number of multiplier cell. As a result of thisswitch with low on-state resistance can be used that mini-mize the losses and improves the converters efficiency.

Table 1 gives the comparison of different topology with voltagemultiplier. Several topologies are derived by integrating voltagemultiplier with voltage lift or coupled inductor or 3SSC or D-C-Lunit. It is found from the comparison that there is no promisingtopology which satisfies both voltage gain and voltage stress acrossthe switch with less number of components. The proposed converteroperating principle is given in section 3.Steady state (DC) analysisis made in section 4. Section 5 describes about the componentdesign and power losses of the converter. A comparative studyis made in the section 6. Section 7 presents the simulated andhardware results of the proposed converter.

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Table 1 Comparison of different topology with voltage multiplier inliterature

3 Operating principle of the proposed

converter in CCM mode

Fig.1 illustrates the topology of the proposed converter, which con-sists of main switch SW, two inductors (L1 , L2), Diode (D1 , D2

) and a Voltage multiplier cell consist of two capacitance (CM1

, CM2 ),two diode (DM1 , DM2) and one resonance inductor Lr.There are five main modes during one switching cycle. The Modesof operation with current flow path are shown in Fig 2. Fig 3demonstrates some typical waveforms obtained during continuousconduction mode (CCM).

Figure 1: Proposed converter

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(a) (b)

(a) (b)

Figure 2: Equivalent circuit representing five operating modeswith current flow path in CCM operation. (a) Mode I. (b) ModeII. (c) Mode III (d) Mode IV (e) Mode V

Mode I [0, t0 ]: The switch SW is conducting at this mode.The input inductor L1 is charged by the input DC source Vg andthe inductor L2 is charged in parallel by the capacitor C1. Thecapacitor CM1 and CM2 are charged to the output voltage of thequadratic boost converter with VM cell (VgM/[1D]2) through thediode DM2. The average voltage of CM1 and CM2 are equal.

Mode II [t0, t1 ]: During this mode the switch SW is on state.At this instant (t0)diode DM2 turns off. The input inductor L1 ischarged by the input DC source V g and the inductor L2 is chargedin parallel by the capacitor C1 .It is similar to Quadratic boostconverter with switch in conducting state. The inductors L1, L2

stores energy until the switch SW turns off at the instant (t1).Mode III, V, VII [t1, t2 ]: At this instant (t1), switch SW

turns off, Diode D2, DM1 and D0 turns on and the energy accumu-lated in the inductors L1, L2 are transmitted to the output capacitorC0 through the diode D0. It is also transmitted to the capacitorCM2 through the diode DM1 and to the capacitor C1 through thediode D2 . This mode is just similar mode 5 and 7.

Mode IV [t2, t3 ]: During this mode the switch SW is off state.At this instant (t2) diode DM1 turns off. The energy accumulated

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in the inductors L1, L2 is transmitted to the output capacitor C0

through the diode D0. At the end of this mode (t3) diode DM1

turns on again and enters in to the mode similar to mode 3.Mode IV [t4, t5 ]: At this instant (t4) diode D0 turns off.

The energy accumulated in the inductors L1, L2 is transmitted tothe output capacitor CM2 through the diode DM1 .At the end ofthis mode (t5) diode D0 turns on again and enters in to the modesimilar to mode 3.

Figure 3: Current waveforms of the proposed converter

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4 Steady state performance analysis of

proposed converter

To simplify the analysis only stages 1 and 3 are considered for CCMoperation because the time durations of mode 4 and 6 are short.Mode 3, 5 and 7 are similar. At mode 1, the main switch SW is inON condition, the inductor L1 is charged by the input dc source Vg

, and the inductors in the switched inductor cells are charged bythe voltage across C1. The following equations are obtained fromfig 2(a)

VL1 = Vg (1)

VL2 = VC1 (2)

During mode 3, the main switch SW is turned OFF, the induc-tors L1 , L2 are discharged. The voltages across the inductor L1and LS1, LS2 can be

VL1 = Vg−VC1 (3)

VL2 = VC1−VCM1 (4)

During the mode 1 Capacitor CM2 is charged with the outputvoltage of quadratic boost converter with voltage multiplier cell.After mode 4, the load voltage is equal to two times of capacitorvoltage CM2 for one multiplier cell [M=1] similar to the converterin [19].

VO = 2VCM2.......M = 1 (5)

Administering a volt-second balance on the inductor L1 , L2

produces

∫ DTs

0Vgdt+

∫ Ts

DTs(Vg−VC1)dt (6)

∫ DTs

0VC1dt+

∫ Ts

DTs(VC1−VCM1)dt (7)

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Solving equation (6) yields

VC1 = Vg

1−D (8)

By substituting (8) in to (7) respectively, VCM2 and VO can beobtained as

VCM1 = Vg

(1−D)2(9)

GV−CCM = VO

Vg= [m+1]

[1−D]2(10)

Table 2 Component stresses and average values of introduced con-verter

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5 Design and paper analysis of proposed

converter

Based on the analytical expression of the operation of converter,the design values of the components are selected.

5.1 Design of inductor L1 and L2

In case of switch ON condition, inductor current i L1 and i L2 peakto peak ripple relation is obtained as follows,

∆iL1 = iL1(DT ) = VgDT

L1(11)

∆iL2 = iL2(DT ) = VC1DTL2

= VgD/1−DL2fs

(12)

At the boundary condition,

IOB = ∆iL1

2(13)

L1min = [1−Dmin]2RLmax

2[1+Dmin]fs(14)

L2min = [1−Dmin]DminRLmax

2[1+Dmin]fs(15)

From (14) and (15) L1 and L2 are selected as 0.119mH and0.239mH respectively.

Resonant inductor limits the current variation and minimizesthe commutation losses. It depends on di/dt (maximum currentvariation) at turn on time. The value of resonant inductor is se-lected as 0.5uH

5.2 Design of capacitor

The input and output capacitors minimum value depends on out-put voltage, load resistance and the operating frequency.

Cmin = VODmax

RLminfs(16)

From (16) input and output capacitor are selected as 22uF. Thevoltage multiplier capacitors minimum value depends on maximum

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power, multiplier capacitor voltage and operating frequency.

CM1min = POmax

VCM12fs

(17)

From (17) voltage multiplier capacitor is selected as 0.5uF

5.3 Power loss analysis

Table 2 gives the average and maximum voltage of the semiconduc-tor devices and other components in the proposed converter.

RMS Current through the switch SW is

iSWrms =√

1T

∫ DT

0[iL1 + iL2]2dt (18)

Hence, ohmic power loss in switch is

PSW = iSW2rDS = io2[2−D]2D

[1−D]6rDS (19)

The RMS current through the diode can be given as

iD1rms =√

1T

∫ DT

0iL1

2dt = io√D

[1−D]3(20)

iD2rms =√

1T

∫ T

DTiL1

2dt = io√

1−D[1−D]3

(21)

iDM1rms =√

1T

∫ T

DT[iL1 − iLr]2dt = ioD

√1−D

[1−D]2(22)

iDM2rms =√

1T

∫ DT

0iL1

2dt = io√D

1−D (23)

iD0rms =√

1T

∫ T

DTiL1

2dt = io√1−D (24)

The power loss in forward resistance R F of the diode is given as

PRF = [iD1rms2+iD2rms

2+iDM1rms2+iDm2rms

2+iD0rms2]RF (25)

The average current through the diode can be given by

iD1avg = 1T

∫ DT

0iL1dt = i0D

[1−D]3(26)

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iD2avg = 1T

∫ T

DTiL1dt = i0

[1−D]2(27)

iDM1avg = 1T

∫ T

DT[iL1−iLr]dt = i0D

1−D (28)

iDM2avg = 1T

∫ T

DTiLrdt = i0D

1−D (29)

The power loss due forward voltage drop in diode is given by

PV F = VF [iD1avg+iD2avg+iDM1avg+iDM2avg+iD0avg] (30)

From (25),( 30) total power loss in diode is obtained as

PD = PRF+PV F (31)

RMS value of the inductor current can be derived as

iL1rms = i0[1−D]3

;

iL2rms = i0[1−D]2

;

iLrrms = i01−D (32)

Power loss associated with inductor can be derived using (32)

PL = iL1rms2rL1 + iL2rms

2rL2 + iLrrms2rLr (33)

Capacitor current RMS values can be given by

iC1rms = ioD[i−D]2

; iCM1rms = io[1−2D]1−D (34)

Capacitor power losses can be derived from (34)

PC = iC1rms2rC1 + iCM1rms

2rCM1 (35)

Total power loss in the converter is

PLOSS = PSW +PD +PL +PC (36)

The efficiency of the proposed high step up converter is givenby

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Efficiency = η = P0

Pin= 1

1+(PLOSS/P0)(37)

6 Comparison of proposed converter with

other high voltage gain converter

Two different comparisons were done in order to highlight the ad-vantage of the proposed converter. The Four converters taken forcomparison in terms of voltage gain and voltage stress are quadraticboost converter, Boost converter with voltage multiplier cell [7], Hy-brid POEL converter with self switched inductor cell and double selfswitched inductor cell [15]. The reason for selecting POEL Switchedinductor (SI) converter for comparison is the similarity in the num-ber of inductors and diodes in the proposed converter. Proposedconverter is the modified version of quadratic boost converter byvoltage multiplier (VM) cell. Thus quadratic boost converter andBoost converter with VM cell [7] are taken for comparison.

Table 3 Comparison of proposed converter with few high voltagegain converters

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Voltage gain versus duty cycle of proposed converter and comparedwith converters in [15], quadratic and boost converter with VM cell[7].

Semiconductor devices voltage stress versus voltage gains of pro-posed converter and compared with converters in [15], quadraticand boost converter with VM cell[7].

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Table 4 Comparison of component utilization of proposed converterwith conventional converter

The comparison in Table 3 and Table 4 are performed withP=40W, V g =12V, V O =96V and f s = 60kHz and the results ofthe comparison are concluded as follows:

6.1 Static gain

Table 3 shows the comparison of proposed converter with Voltagelift converter [15], Quadratic boost and Boost converter with volt-age multiplier cell [7]. Fig 4 shows the graphical comparison ofvoltage gain between converters. One can see the proposed con-verter has high voltage gain compared to other converters taken forcomparison. It is found that voltage conversion ratio is about 22times that of the line voltage for the duty cycle 0.7.

6.2 Main switch and output diode voltage stress

From the table 3 comparative study on voltage stress on switch andoutput diode for proposed converter with other converters are made.Fig 5 presents the graphical comparison of switch voltage, multi-plier and output diode voltage stress of the proposed converter.The switch and output diode voltage stress depends on number ofmultiplier cell. By increasing the multiplier cell, the voltage stress

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on the semiconductor devices can be reduced severely.

6.3 Switch/Diode utilization factor

Table 4 illustrates the comparison of switch and diode utilizationfactor of proposed converter with quadratic boost converter andboost converter with voltage multiplier cell [7]. Switch utilizationfactor is found to be high in the proposed converter. Due to in-crease in number of diode, total diode utilization factor slightlyless compared to boost converter with voltage multiplier cell. Totalenergy volume of inductor of the proposed converter is slightly highcompared to other converter.

7 Simulated and experimental results

The proposed converter is tested with 40W prototype to verify thetheoretical analysis. The electrical specifications are PO = 40W,Vg = 12V, VO = 96V, fS = 50kHz and RL = 230Ω. Inductor L1 ,L2 and Lr is chosen as 0.119mH, 0.239mH and 0.5uH respectively.Input and output capacitors are selected as 22uFas per equation 16.Voltage multiplier capacitor is selected as 0.5uf from the equation17. Fig 6 is the photograph of the converter implemented in thelaboratory. Simulation is carried out in nl5 simulator. Fig 7(a)-(d)shows the simulated waveform of the voltage across the multiplierdiode, output diode, multiplier capacitor voltage and inductor cur-rent. Fig 8(a) shows the main switch stress voltage is 47V for theoutput voltage of 95V. Fig 8(b) presents the voltage across the mul-tiplier diode which is equal to 49V for the output voltage of 95V.Fig 8(c) shows experimental output diode stress voltage of 49Vwhich is very less compared to quadratic boost converter where theswitch and output diode stress voltage is equal to output voltage.Fig 8(d) presents the multiplier capacitor voltage and is equal toVO / M + 1 . From Fig 8(a)-(c) one can see that the voltage stressacross switch and other diodes depend on the number of multipliercell and the expression to the maximum voltage stress on differentcomponents in the converter is given in table 2 which matches withthe experimental results.

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Figure 6 : Photograph of the hardware implementation of the in-troduced converter

(a) (b)

(c) (d)

Figure 7: Simulated results (a) Multiplier diode and Outputdiode stress voltage (b) output voltage (c) multiplier capacitor volt-age (d) Inductor current.

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(a) (b)

(c) (d)

Figure 8 Experimental results. (a) Output voltage and switchvoltage for D=0.5 (X-scale: 10us/div, CH1 : Y-scale: 30V/div,CH2 : 100V/div) (b) Voltage multiplier diode voltage stress andoutput voltage for D=0.5 (X-scale: 10us/div, CH1 : Y-scale: 30V/div,CH2 : 45V/div) (c) Output diode voltage stress (X-scale: 10us/div,Y-scale: 45V/div) (d) Voltage Multiplier capacitor voltage(X-scale:10us/div, Y-scale: 25V/div)

8 Conclusion

A non-isolated DC - DC converter is constructed by integratingquadratic boost converter with voltage multiplier cell. The pro-posed converter possesses an input inductor so the input current isripple free. And, hence such a converter is suitable for fuel cell ap-plication where the ripple free input current is needed. The featuresof this converter include high voltage conversion ratio, low voltage

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stress on the semiconductor devices and high efficiency. This con-verter employs just a single active switch, can operate with simplecontrol circuit and structure of the converter is simple. The mea-sured efficiency is found to be 88% at half-load.

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