Chapter 11Operational Amplifiers and Applications

Chapter Goals

• Understand the “magic” of negative feedback and the characteristics of ideal op amps.

• Understand the conditions for non-ideal op amp behavior so they can be avoided in circuit design.

• Demonstrate circuit analysis techniques for ideal op amps.• Characterize inverting, non-inverting, summing and

instrumentation amplifiers, voltage follower and first order filters.

• Learn the factors involved in circuit design using op amps.• Find the gain characteristics of cascaded amplifiers.• Special Applications: The inverted ladder DAC and successive

approximation ADC

Differential Amplifier Model: Basic

Represented by:

A = open-circuit voltage gain

vid = (v+-v-) = differential input signal voltage

Rid = amplifier input resistance

Ro = amplifier output resistance

The signal developed at the amplifier output is in phase with the voltage applied at the + input (non-inverting) terminal and 180° out of phase with that applied at the - input (inverting) terminal.

LM741 Operational Amplifier: Circuit Architecture

Current Mirrors

Ideal Operational Amplifier

• The “ideal” op amp is a special case of the ideal differential amplifier with infinite gain, infinite Rid and zero Ro .

and

– If A is infinite, vid is zero for any finite output voltage.– Infinite input resistance Rid forces input currents i+ and i- to be zero.

• The ideal op amp operates with the following assumptions:– It has infinite common-mode rejection, power supply rejection,

open-loop bandwidth, output voltage range, output current capability and slew rate

– It also has zero output resistance, input-bias currents, input-offset current, and input-offset voltage.

Aov

idv = 0

idvlim =

∞→A

The Inverting Amplifier: Configuration

• The positive input is grounded.

• A “feedback network” composed of resistors R1 and R2 is connected between the inverting input, signal source and amplifier output node, respectively.

Inverting Amplifier:Voltage Gain

• The negative voltage gain implies that there is a 1800 phase shift between both dc and sinusoidal input and output signals.

• The gain magnitude can be greater than 1 if R2 > R1

• The gain magnitude can be less than 1 if R1 > R2

• The inverting input of the op amp is at ground potential (although it is not connected directly to ground) and is said to be at virtual ground.

0ov22

i1

isv =−−− RRs

1

svsi R=∴

But is= i2 and v- = 0 (since vid= v+ - v-= 0)

and

1

2

svov

R

RvA −==

Inverting Amplifier: Input and Output Resistances

€

Rin =vsis

= R1 since v− =0

Rout is found by applying a test current (or voltage) source to the amplifier output and determining the voltage (or current) after turning off all independent sources. Hence, vs = 0

11i

22ixv RR +=

But i1=i2

)12

(1ixv RR +=∴

Since v- = 0, i1=0. Therefore vx = 0 irrespective of the value of ix .

0=∴ outR

Inverting Amplifier: Example

• Problem: Design an inverting amplifier

• Given Data: Av= 20 dB, Rin = 20k ,

• Assumptions: Ideal op amp

• Analysis: Input resistance is controlled by R1 and voltage gain is set by R2 / R1.

and Av = -100

A minus sign is added since the amplifier is inverting.

€

Av dB ⎛ ⎝ ⎜ ⎞

⎠ ⎟=20log

10Av ⎛

⎝ ⎜

⎞

⎠ ⎟, ∴ Av =1040dB/20dB=100

Ω== k201 inRR

€

Av =−R

2R1

⇒ R2

=100R1

=2MΩ

The Non-inverting Amplifier: Configuration

• The input signal is applied to the non-inverting input terminal.

• A portion of the output signal is fed back to the negative input terminal.

• Analysis is done by relating the voltage at v1 to input voltage vs and output voltage vo .

Non-inverting Amplifier: Voltage Gain, Input Resistance and Output Resistance

Since i-=0 and

But vid =0

Since i+=0

211

ov1

vRR

R+= 1

vid

vsv =−

1vsv =∴

1

211

21

svov

121

svov

R

R

RRR

vA

RRR

+=+

==∴

+=

∞=+

=i

svinR

Rout is found by applying a test current source to the amplifier output after setting vs = 0. It is identical to the output resistance of the inverting amplifier i.e. Rout = 0.

Non-inverting Amplifier: Example

• Problem: Determine the output voltage and current for the given non-inverting amplifier.

• Given Data: R1= 3k , R2 = 43k , vs= +0.1 V

• Assumptions: Ideal op amp

• Analysis:

Since i-=0,

€

Av =1+R

2R1

=1+ 43kΩ3kΩ

=15.3

vo= Avvs =(15.3)(0.1V)=1.53V

A3.33k3k43

V53.1

12ov

oi μ=Ω+Ω

=+= RR

Finite Open-loop Gain and Gain Error

21

1

ovov

21

11

v

RR

R

RR

R

+=

=+

=

β

β

is called the feedback factor.

β

β

AA

vA

AAA

+==

−=−==

1svov

)ovsv()1

vsv(id

vov

Aβ is called loop gain.

For Aβ >>1,

€

Av≅1β

=1+R

2R1

This is the “ideal” voltage gain of the amplifier. If Aβ is not >>1, there will be “Gain Error”.

Gain Error

• Gain Error is given by

GE = (ideal gain) - (actual gain)

For the non-inverting amplifier,

• Gain error is also expressed as a fractional or percentage error.

)1(1

11

ββββ AAAGE

+=

+−=

€

FGE =

1β

− A1+ Aβ1β

= 11+ Aβ

≅ 1Aβ

PGE≅ 1Aβ

×100%

Gain Error: Example

• Problem: Find ideal and actual gain and gain error in percent

• Given data: Closed-loop gain of 100,000, open-loop gain of 1,000,000.

• Approach: The amplifier is designed to give ideal gain and deviations from the ideal case have to be determined. Hence,

.

Note: R1 and R2 aren’t designed to compensate for the finite open-loop gain of the amplifier.

• Analysis:

€

β= 1

105

€

Av = A1+ Aβ

= 106

1+106

105

=9.09x104

PGE=105 −9.09x104

105×100%=9.09%

Output Voltage and Current Limits

Practical op amps have limited output voltage and current ranges.

Voltage: Usually limited to a few volts less than power supply span.

Current: Limited by additional circuits (to limit power dissipation or protect against accidental short circuits).

The current limit is frequently specified in terms of the minimum load resistance that the amplifier can drive with a given output voltage swing. Eg:

€

io = 5V500Ω

=10mA

)21

(

ov

12

ovovFiLioi

RRLREQ

R

EQRRR

LR

+=

=+

+=+=

For the inverting amplifier,

2RLR

EQR =

Example PSpice Simulations ofNon-inverting Amplifier Circuits

The Unity-gain Amplifier or “Buffer”

• This is a special case of the non-inverting amplifier, which is also called a voltage follower, with infinite R1 and zero R2. Hence Av = 1.

• It provides an excellent impedance-level transformation while maintaining the signal voltage level.

• The “ideal” buffer does not require any input current and can drive any desired load resistance without loss of signal voltage.

• Such a buffer is used in many sensor and data acquisition system applications.

The Summing Amplifier

• Scale factors for the 2 inputs can be independently adjusted by the proper choice of R2 and R1.

• Any number of inputs can be connected to a summing junction through extra resistors.

• This circuit can be used as a simple digital-to-analog converter. This will be illustrated in more detail, later.

11

v1i

R=

22

v2

iR

=3ov

3i

R−=

Since the negative amplifier input is at virtual ground,

Since i-=0, i3= i1 + i2,

€

∴vo=−R

3R1

v1

−R

3R

2

v2

The Difference Amplifier

• This circuit is also called a differential amplifier, since it amplifies the difference between the input signals.

• Rin2 is series combination of R1 and R2 because i+ is zero.

• For v2=0, Rin1= R1, as the circuit reduces to an inverting amplifier.

• For general case, i1 is a function of both v1 and v2.

1v

1

2-v

1

21)-v1

v(

1

2-v

21i-v

22i-vov

R

R

R

RR

R

R

RR

−+

=−−

−=−=

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

=

€

v+=R

2R1

+R2

v2

Also,

Since v-= v+)

2v

1(v

1

2v −−=R

Ro

For R2= R1)

2v

1(vv −−=o

Difference Amplifier: Example

• Problem: Determine vo

• Given Data: R1= 10k , R2 =100k , v1=5 V, v2=3 V

• Assumptions: Ideal op amp. Hence, v-= v+ and i-= i+= 0.

• Analysis: Using dc values,

€

Adm

=−R

2R1

=−100kΩ10kΩ

=−10

Vo = Adm

V1

−V2

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟=−10(5−3)

Vo =−20.0 V

Here Adm is called the “differential mode voltage gain” of the difference amplifier.

Finite Common-Mode Rejection Ratio (CMRR)

A(or Adm) = differential-mode gain

Acm = common-mode gain

vid = differential-mode input voltage

vic = common-mode input voltage

A real amplifier responds to signal common to both inputs, called the common-mode input voltage (vic). In general,

€

vo= Adm

vid

+Acmv

icA

dm

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

= Adm

vid

+vic

CMRR

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

CMRR =A

dmAcm

and CMRR(dB)=20log10

(CMRR)

An ideal amplifier has Acm = 0, but for a real amplifier,

21id

v

icvv +=22id

v

icvv −=

€

vo = Adm

(v1

−v2

)+ Acmv1

+v2

2

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

vo = Adm

(vid

)+ Acm(vic)

Finite Common-Mode Rejection Ratio: Example

• Problem: Find output voltage error introduced by finite CMRR.• Given Data: Adm= 2500, CMRR = 80 dB, v1 = 5.001 V, v2 = 4.999 V• Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in dB

of 80 dB corresponds to a CMRR of 104.• Analysis:

The output error introduced by finite CMRR is 25% of the expected ideal output.

€

vid

=5.001V−4.999V

vic = 5.001V+4.999V2

=5.000V

vo = Adm

vid

+vic

CMRR

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟=2500 0.002+ 5.000

104 ⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟V=6.25V

In the "ideal" case, vo = Adm

vid

=5.00 V

€

% output error= 6.25−5.005.00

×100%=25%

uA741 CMRR Test: Differential Gain

Differential Gain Adm = 5 V/5 mV = 1000

uA741 CMRR Test: Common Mode Gain

Common Mode Gain Acm = 160 mV/5 V = .032

CMRR Calculation for uA741

€

CMRR =Adm

Acm

=1000

.032= 3.125x104

CMRR(dB) = 20log10 CMRR( ) = 89.9 dB

Instrumentation Amplifier

Combines 2 non-inverting amplifiers with the difference amplifier to provide higher gain and higher input resistance.

)b

va(v

3

4v −−=R

Ro

bv

2i)

1i(2

2iav =−−− RRR

12

2v

1v

iR

−=

)2

v1

(v

1

21

3

4v −+−=∴⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

R

R

R

Ro

Ideal input resistance is infinite because input current to both op amps is zero. The CMRR is determined only by Op Amp 3.

NOTE

Instrumentation Amplifier: Example

• Problem: Determine Vo

• Given Data: R1 = 15 k , R2 = 150 k , R3 = 15 k R4 = 30 k V1 = 2.5 V, V2 = 2.25 V

• Assumptions: Ideal op amp. Hence, v-= v+ and i-= i+= 0.

• Analysis: Using dc values,

€

Adm

=−R

4R

3

1+R

2R1

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

=−30kΩ15kΩ

1+150kΩ15kΩ

⎛

⎝

⎜ ⎜

⎞

⎠

⎟ ⎟=−22

Vo= Adm

(V1

−V2

)=−22(2.5−2.25)=−5.50V

The Active Low-pass Filter

Use a phasor approach to gain analysis of this inverting amplifier. Let s = j .

€

Av =˜ v o( jω)

˜ v ( jω)=−

Z2

( jω )

Z1( jω )

€

Z1

jω( ) = R1

€

Z2( jω)=R

21

jωC

R2

+ 1jωC

=R

2jωCR

2+1

€

Av =−R

2R1

1(1+ jωCR

2)=

R2

R1

ejπ

(1+ jωωc

)

€

ωc =2πfc = 1R

2C

∴ fc = 12πR

2C

fc is called the high frequency “cutoff” ofthe low-pass filter.

Active Low-pass Filter (continued)

• At frequencies below fc (fH in the figure), the amplifier is an inverting amplifier with gain set by the ratio of resistors R2 and R1.

• At frequencies above fc, the amplifier response “rolls off” at -20dB/decade.

• Notice that cutoff frequency and gain can be independently set.

€

Av =R

2R1

ejπ

(1+ jωωc

)

⎛

⎝

⎜ ⎜ ⎜ ⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟ ⎟ ⎟ ⎟

=R

2

R1

12 + ωωc

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

2e

jπ

ejtan−1(ω/ωc )

⎛

⎝

⎜ ⎜ ⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟ ⎟ ⎟

=R

2

R1

1+ ωωc

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

2e

j[π −tan−1(ω/ωc )]

magnitude phase

Active Low-pass Filter: Example

• Problem: Design an active low-pass filter• Given Data: Av= 40 dB, Rin= 5 k , fH = 2 kHz• Assumptions: Ideal op amp, specified gain represents the desired low-

frequency gain.• Analysis:

Input resistance is controlled by R1 and voltage gain is set by R2 / R1.The cutoff frequency is then set by C.

The closest standard capacitor value of 160 pF lowers cutoff frequency to 1.99 kHz.

100dB20/dB4010 ==vA

Ω== k51 inRR

€

Av =R

2R1

⇒ R2

=100R1

=500kΩ

€

C = 12πf

HR

2= 1

2π (2kHz)(500kΩ)=159pF

and

Low-pass Filter Example PSpice Simulation

Output Voltage Amplitude in dB

Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)

Cascaded Amplifiers

• Connecting several amplifiers in cascade (output of one stage connected to the input of the next) can meet design specifications not met by a single amplifier.

• Each amplifer stage is built using an op amp with parameters A, Rid, Ro, called open loop parameters, that describe the op amp with no external elements.

• Av, Rin, Rout are closed loop parameters that can be used to describe each closed-loop op amp stage with its feedback network, as well as the overall composite (cascaded) amplifier.

Two-port Model for a 3-stage Cascade Amplifier

• Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-port model.

€

vo=AvA

vsR

inBR

outA+R

inB

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

AvB

RinC

RoutB

+RinC

⎛

⎝

⎜ ⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟ ⎟

AvC

vCAvBA

vAAvA ==

svovSince Rout= 0

Rin= RinA and Rout= RoutC = 0

A Problem: Voltage Follower Closed Loop Gain Error due to A and CMRR

ovsvid

v −=2

ovsvic

v+

=

€

vo=A vs−vo( )+vs+vo( )

2(CMRR)

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

Av =vovs

=

A1+ 12(CMRR)

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

1+ A1− 12(CMRR)

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

The ideal gain for the voltage follower is unity. The gain error here is:

€

GE=1− Av =1− A

CMRR

1+ A1− 12(CMRR)

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

Since, both A and CMRR are normally >>1,

€

GE≅1A

− 1CMRR

Since A ~ 106 and CMRR ~ 104 at low to moderate frequency, the gain error is quite small and is, in fact, usually negligible.

Inverted R-2R Ladder DAC

• A very common DAC circuit architecture with good precision.

• Currents in the ladder and the reference source are independent of digital input. This contributes to good conversion precision.

• Complementary currents are available at the output of inverted ladder.

• The “bit switches” need to have very low on-resistance to minimize conversion errors.

Successive Approximation ADC• Binary search is used by the SAL to determine vX. • n-bit conversion needs n clock periods. Speed is limited by the time taken by the DAC output to settle within a fraction of an LSB of VFS , and by the comparator to respond to input signals differing by small amounts.• Slowly varying input signals, not changing by more than 0.5 LSB (VFS /2n+1 ) during the conversion time (TT = nTC) are acceptable.• For a sinusoidal input signal with p-p amplitude = VFS,

• To avoid this frequency limitation, a high speed sample-and-hold circuit is used ahead of the successive approximation ADC.• This is a very popular ADC with fast conversion times, used in 8- to 16- bit converters.

€

fo≤fc

2n+2(n+1)π

SAADC: Block Diagram

SAADC: Method of Operation