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5/26/2018 Opamp Razavi
1/33
Ching-Yuan Yang
National Chung-Hsing UniversityDepartment of Electrical Engineering
Operational Amplifiers
(3349) - 2004
9-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Overview
Reading
B. Razavi Chapter 9.
Introduction
Operational amplifiers (op amps) are an integral part of many analog and
mixed-signal systems. Op amps with vastly different levels of complexity are
used to realize functions ranging from dc bias generation to high-speed
amplification or filtering.This lecture deals with the analysis and design of CMOS op amps.
Following a review of performance parameters, we describe simple op amps
such as telescopic and folded cascode topologies. Next, we study two-stage
and gain-boosting configurations and the problem of common-mode
feedback. Finally, we introduce the concept of slew rate and analyze the
effect of supply rejection and noise in op amps.
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9-2 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Performance parameters
Gain
Example: the circuit is designed for a nominal of 10, i.e.,
1 + R1/R
2=10.
Discussion
The close-loop gain:
1
2
21
1
2
21
1
21
2
1
1 AR
RR
A
R
RR
ARR
R
A
V
V
in
out
++
+
=
++
=
If A1
>> (R1
+ R2)/R
2, then
+
+
12
21
2
1 111AR
RR
R
R
V
V
in
out
The term (R1
+ R2)/(R
2A
1) = (1 + R
1/R
2)/A
1represents the relative error.
To achieve a gain error less than 1%, we must have A1
> 1000.
Simple CS stage an open-loop implementation:
10== Dmin
out RgV
V
However, it is difficult to guarantee an error less than 1%.The variations in the mobility and gate oxide thickness of the transistor and
the value of the resistor typically yield an error greater than 20%.
9-3 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Performance parameters (contd)
Small-signal bandwidth
Large-signal bandwidth slew rate
unity-gain
dB
Gain roll-off with frequency
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9-4 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Performance parameters (contd)
Output swing Most systems employing opamps require large voltage swings to
accommodate a wide range of signal amplitudes.
Linearity Open-loop op amps suffer fromsubstantial nonlinearity. For example, the input
pair M1M
2exhibits a nonilinear relationship
between its differential drain current and input
voltage. In many feedback circuits, the linearity
requirement, rather than the gain error
requirement, governs the choice of the open-loop
gain.
Noise and offset The input noise and offset ofop amps determine the minimum signal level that
can be processed with reasonable quality.
Supply rejection Op amps are often employedin mixed-signal systems and sometimes
connected to noise digital supply lines. Thus, the
performance of op amps in the presence of supply
noise is quite important. For this reason, fullydifferential topologies are preferred.
9-5 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
One-stage op amps
Simple op amp topologies
Differentialinput & single-endedoutput Differentialinput & differentialoutput
For small-signal:
Low frequency gain = gmN(roN||roP). In general, this value hardlyexceeds 20 in submicron devices with typical current levels.
The bandwidth is usually determined by the load capacitance, CL.
The circuits suffer from noise contributions of M1-M4. In all op amp
topologies, at least four devices contribute to the input noise: two
input transistors and two load transistors.
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9-6 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Unit-gain buffer
VCSS
Input common-mode voltage range
Vin,min= VCSS+ VGS1Vin,max= VDD |VGS3| + VTH1
If each device has a threshold voltage of 0.7V and an overdrive
of 0.3V, then Vin,min= 1.3V, and Vin,max= 2.7V. Thus, the inputCM range equals 1.4V with a 3-V supply.
Output impedance
( ) mNoNoPmNoNoP
openv
openoutout
grrg
rr
A
RR
1
11 ,
, +
=+
=
The close-loop output impedance is relatively
independentof the open-loop output impedance.
Allowing us to design high-gain op amps by increasing
the open-loop output impedance while still achieving a
relatively low close-loop output impedance.
9-7 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Telescope cascode op amps
In order to achieve a high gain, the differential cascode topologies can be used.
Low-frequency gain Av= gmN[(gmNroN2) || (gmProP2)], but at the cost of output
swing and adding poles.
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9-8 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
(a): The circuit providing a single-ended output suffers from a mirror pole at
nodeX, creating stability issues.
(b): Fully differential topology, the output swing is given by
2[VDD (VOD1 + VOD3 + VCSS+ |VOD5| + |VOD7|)]
where VODjdenotes the overdrive voltage ofMj.
Another drawback of telescopic cascodes is the difficult in shorting their inputs
and outputs, e.g., to implement a unity-gain buffer.
9-9 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Telescope cascode op amps (contd)
Cascode op amp with input and output shorted
unit gain feedback topology
Output swing: M2 and M4 in saturation:
244
4
2
THGSboutTHb
THbout
THXoutVVVVVV
VVV
VVV+
+
the voltage range VmaxVmin= VTH4 (VGS4VTH2)
Since the op amp attempts to force Voutto be equal to
Vin, for Vin< VbVTH4, we have VoutVinand M4 is in
triode region while others are saturated. Under this
condition, the open-loop gain of the op amp is reduced.
As Vinand Vouthence exceed VbVTH4, M4 enters
saturation and the open-loop gain reaches a maximum.
For VbVTH4
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9-10 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Design of fully differential telescope op amp
Specifications:
VDD= 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume nCox= 60 A/V2, pCox= 30 A/V2, n= 0.1V1, p= 0.2V1 (for an
effective channel length of 0.5 m), = 0, VTHN
= |VTHP
| = 0.7V.
Power budget:
IM9 = 3mA, IMb1 + IMb2 = 330A Output swing:
Node X(Y) swing = 1.5V, M3-M6 in saturation.
For M9,
|VOD7| + |VOD5| +VOD3 +VOD1 +VOD9 = 1.5VSinceM9 carrying largest current,
VOD9 0.5V is chosen.|VOD5| = |VOD7| 0.3V,VOD1 =VOD3 0.2V.
W/L
By ID= (1/2)Cox(W/L)(VGSVTH )2, we have(W/L)14 = 1250, (W/L)58 = 1111, (W/L)9 = 400.
9-11 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Gain:
Avgm1[(gm3ro3ro1)|| (gm5ro5ro7)]. In order to Increase the gain,
we recognize
where 1/L. We can therefore increase the width or length.Choose (W/L)58 = 1111m/1m,
thenAv 4000.
CM level & bias:
Min. allowable input CM level= VGS1 +VOD9 = 1.4V.
Vb1,min = VGS3 +VOD1 +VOD9 = 1.6V.
Vb2,max = VDD (|VGS5 |+|VOD7|) = 1.7V.
DDDoxom IWLIILWCrg /)/()/(2 =
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9-12 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded cascode op amps
In order to alleviate the drawbacks
of telescopic cascode op amps. The
primary advantage of the folded
structure lies in the choice of the
voltage levels because it does not
stack the cascode transistor on the
top of the input device.
9-13 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded cascode op amps (contd)
Two important differences between the two circuits:
In Fig.(a), one bias current, ISS, provides the drain current of both the input
transistors and the cascode devices.
In Fig.(b), the input pair requires an additional bias current, ISS1 = ISS/2 + ID3.
In Fig.(a), the input CM level cannot exceed Vb1 VGS3 + VTH1,whereas inFig.(b), it cannot be less than Vb1 VGS3 + |VTH1|.
In Fig.(b), it is possible to tie the n-well of M1 and M2 to their common source point.
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9-14 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded cascode op amps (contd)
Folded cascode op amp with cascode PMOS loads
Max. output voltage swing: With proper choice of Vb1 and Vb2,
Peak-peak swing = [VDD (|VOD7| + |VOD9|)] (VOD3 + VOD5 ) for one side.
The swing is lager by the overdrive of the tail current source in the telescopic
cascode.M5 and M6 may require a high overdrive voltage if their capacitance
contribution to nodesXand Yis to be minimized.
9-15 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded cascode op amps (contd)
Small-signal voltage gain
Half circuit
|Av| = Gm Rout
Equivalent circuit with
output shorted to ground
Since (gm3+gmb3)1||ro3
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9-16 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded cascode op amps (contd)
Effect of device capacitance on the nondominant pole in telescopic and folded cascode
op amps
Ctot= CGS3 + CSB3 + CDB1 + CGD1 Ctot= CGS3 + CSB3 + CDB1 + CGD1 + CGD5 + CDB5
The pole at the folding point, i.e., the sources of M3 and M4, is quite closer to the
origin than that associated with the source of cascode devices in a telescopic
topology.
9-17 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
A high-gain folded cascode op amp
The circuit provides a higher gain because of the greater mobility of NMOS
devices, but at the cost of lowering the pole at the folding point,
p,X (gm3 + gmb3) / Ctot,X.
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9-18 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Telescopic- & folded-cascode op amps: Discussion
The overall voltage swing of a folded-cascode op amp is only slightly higher than that of a
telescopic configuration. This advantage comes at the cost of higher power dissipation,
lower voltage gain, lower pole frequencies, and higher noise.
Folded-cascode op amps are used quite widely, even more than telescopic topologies,
because the input and outputs can be shorted together and the choice of the input
common-mode level is easier. In a telescopic op amp, three voltages must be defined carefully: the input CM level
and the gate bias voltages of the PMOS and NMOS cascode transistors, whereas in
folded-cascode configurations only the latter two are critical.
In folded-cascode op amps, the capability of handling input CM levels are close to
one of the supply rails.
9-19 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Design of folded-cascode op amp
Specifications:
VDD= 3V, differential output swing = 3V,
power dissipation = 10mW, voltage gain = 2000.
Assume nCox= 60 A/V2, pCox= 30 A/V2, n= 0.1V1, p= 0.2V
1 (for an
effective channel length of 0.5 m), = 0, VTHN= |VTHP| = 0.7V.
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9-20 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Power budget: IM11 = 1.5mA, IM9 +IM10 = 1.5mA, IMb1 +IMb2 +IMb3 = 330A.
Output swing: one side o/p swing = 1.5V, M3-M10 in saturation.
Choose |VOD5,6| 0.5V, |VOD3,4| 0.4V, VOD7,8 =VOD9,10 0.3V.
W/LBy ID= (1/2)Cox(W/L)(VGSVTH )2, we have
(W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)710 = 555. O/p CM level: CMmin = 0.6V, CMmax= 2.1V, thus CMopt= 1.35V.
9-21 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Determine (W/L)1,2: min. input CM level = VGS1 +VOD11.
If input and output are shorted, then VGS2 +VOD11 = 1.35V,
and VGS1 = 0.95V VOD1,2 = 0.25V (W/L)1,2 = 400.
The maximum dimensions of M1,2 are determined by the tolerable input
capacitance at nodesXand Y.
Gain: gm= 2ID/(VGSVTH), we havegm1,2 = 0.006 A/V,gm3,4 = 0.0038 A/V,gm7,8 = 0.05 A/V.
For L= x m, findro.
Note |Av|gm1{[(gm3 + gmb3)ro3(ro1|| ro5)] || [(gm7 + gmb7) ro7ro9]}
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9-22 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Cascode op amps with single-ended output
Fig(a): VX= VDD |VGS5| |VGS7|,
limiting the maximum value of
VouttoVDD |VGS5| |VGS7|
|VTH6| and wasting one PMOS
threshold voltage in the swing.
Fig(b): To solve above issue, M7 and
M8 are biased at the edge of
the triode region.
Disadvantages: (1) it provides only half the output voltage swing.
(2) it contains a mirror pole at nodeX, thus limiting the speed
of feedback systems employing such an amplifier.
It is preferable to use the differential topology, although it requires a feedbackloop to define the output CM level.
9-23 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Triple-cascode op amp
The triple cascode topology provides
a gain on the order of (gmro)3/2 but
further limits the output swings. With
six overdrive voltages subtracted fromVDDin this circuit, it is difficult to
operate the amplifier from a supply
voltage or lower while obtaining
reasonable output swings.
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9-24 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Two-stage op amps
The gain of one-stage topologies is limited to the input pair transconductance
and the output impedance.
Two-stage op amps consist of first stage providing a high gain and the second
providing large swing. The first stage incorporates various amplifier topologies,
but the second stage is typically configured as a simple common- source
stage to allow maximum output swings.
Can we cascade more than two stages to achieve a higher gain?
Each gain stage introduces at least one pole in the open-loop transfer function,
making it difficult to guarantee stability in a feedback system using such an op
amp. For this reason, op amps having more than two stages are rarely used.
9-25 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Simple implementation of a two-stage op amp
Gain:Av,1st stage = gm1,2(ro1,2||ro3,4)
Av,2nd stage = gm5,6(ro5,6||ro7,8)
Overall gain Av= Av,1st stageAv,2nd stage
Output swing = VDD |VOD5,6| VOD7,8
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9-26 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Two-stage op amp employing cascoding
To obtain a higher, the first stage incorporate cascode devices. The overall voltage gain is
Av
{gm1,2
[(gm3,4
+ gmb3,4
)ro3,4
ro1,2
] || (gm5,6
+ gmb5,6
)ro5,6
ro7,8
]} [gm9,10
(ro9,10
||ro11,12
)]
9-27 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Two-stage op amp with single-ended output
Note that if the gate of M1 is shorted to Voutto form a unity-gain buffer,
then the minimum allowable output level is equal to VGS1 + VISS, severely
limit the output swing.
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9-28 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Gain boosting
Increasing the output impedance by feedback
Rout= gm2ro2ro1
M1 operates as a degeneration resistor.
The voltage variations at the drain of M2 effect VX to a
lesser extent because A1 regulates this voltage. (VX= Vb)
With smaller variations at X, the current throughro1 and
hence the output current remains more constant,
yielding a higher output impedance.
RoutA1gm2ro2ro1,
Rout is booted substantially without stacking morecascode devices on top of M2.
9-29 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Gain boosting in cascode stage
For small-signal operation, Vb is set to zero.
regulated cascode
Gain:
|Av| gm1 (gm2ro2ro1) (gm3 ro3)
Min. output swing:
Since VX= VGS3, the min.value ofVoutis VOD2 + VGS3. The auxiliary
amplifier limits the output swing.
Note: Min. output swing is VOD2 +
VOD1 in a simple cascode.
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9-30 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Boosting output impedance of a differential cascode stage
The minimum level at the drain of M3 is
equal to VOD3 + VGS5 + VISS2.
The voltage swing limitation results the fact
that the gain-boosting amplifier incorporates
an NMOS differential pair.
9-31 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Folded-cascode circuit used as auxiliary amplifierHalf circuit
If nodesXand Yare sensed by a PMOS pair, the minimum value of VXand
VY is not dictated by the gain-boosting amplifier.
The minimum allowable level of VXand VY is given by VOD1,2 + VISS1.
Output impedance: Since 15 outmX
P RgV
V=
where Rout1 [gm7ro7(ro9||ro5)] || (gm11ro11ro13), Routgm3ro3ro1gm5Rout1.
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9-32 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Gain boosting applied to both signal path and load devices
Regulated cascodes can also be utilized in the load current sources of a
cascode op amp.
9-33 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Comparison of performance of various op amp topologies
Gain
Medium
Medium
High
High
Output
Swing
Medium
Medium
Highest
Medium
Speed
Low
Medium
Highest
High
Low
Medium
Medium
High
Power
DissipationNoise
Low
Medium
Low
Medium
Telescopic
Folded-Cascode
Two-stage
Gain-Boosted
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9-34 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Common-mode feedback (CMFB)
Full differential circuits have many advantages over their single-ended
counterparts such as greater output swings, avoiding mirror poles, higher
closed-loop speed. However, high-gain differential circuits require common-
mode feedback.
Simple differential pair
Input & output common-mode
level is equal to VDDISS RD /2
9-35 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
High-gain differential pair with inputs shorted to outputs
What is the common-mode level at nodesXand Y?
Since each of the input transistors carries a current ISS/2, the CM level depends on
how close ID3 and ID4 are to this value.
Effect of current mismatches: Mismatches in the PMOS and NMOS current mirrors
defining ISSand ID3,4 create a finite error betweenID3,4 and ISS/2.
IfID3,4 >ISS/2, then both M3 and M4 must enter the triode region so that their drain
currents fall toISS/2. Conversely, IfID3,4
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9-36 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Simplified model of high-gain amplifier
In high-gain amplifiers, we wish ap-type current source to balance an n-type current
source.
( )( )NPNP RRIIV =
Since the current error depends on mismatches and RP||RN is quite high, the voltageerror may be large, thus driving thep-type or n-type current source into triode region.
As a general rule, if the output CM level cannot be determined by visual inspection
and requires calculations based on device properties, then it is poorly defined.
In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a
CMFB network must be added to sense the CM level of the two outputs and
accordingly adjust one of the bias currents in the amplifier.
9-37 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Conceptual topology for CMFB
In high-gain amplifiers, the output CM level is quite sensitive to device properties and
mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB
network must be added to sense the CM level of the two outputs and accordingly adjust
one of the bias currents in the amplifier.
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9-38 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
CMFB with resistive sensing
Output CM level: Vout,CM= (Vout1 + Vout2)/2
Resistive divider level: Vout,CM= (R1Vout2 + R2Vout1)/(R1 + R2)
= (Vout1 + Vout2)/2, ifR1 = R2.
R1 and R2 must be much larger than the output impedance of the op ampso as to avoid lowering the open-loop gain.
9-39 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
CMFB using source followers
Current starvation of source followers for large swings
This technique produces a CM level
that is lower than the output CM
level by VGS7,8, but this shift can be
taken into account in the
comparison operation.
R1 and R2 or I1 and I2 must be large
enough to ensure that M7 or M8 is
not starved when a large differential
swing appears at the output.
If Vout2 is quite higher than Vout1, then I1must sink both IX (Vout2Vout1)/(R1 + R2)and ID7. Consequently, if (R1 + R2) or I1 is
not sufficiently large, ID7 drops to zero
and Vout,CMno longer represents the true
output CM level.
This sensing method limits the differential
output swings. The swing at each output is
reduced by approximately VTH, a significant
value in low-voltage design.
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9-40 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
CMFB using MOSFET operating in deep triode region
( ) ( )
( )THoutoutoxn
THoutoxnTHoutoxn
ononP
VVVL
WC
VVL
W
CVVL
W
C
RRR
2
1
11
21
21
87
+=
=
=
RP is a function of Vout1 + Vout2 but independent of
Vout2Vout1.
The use of M7 and M8 limits the output voltage swings, Vout,min= VTH7,8, which is
relatively close to two overdrive voltages, but the difficulty arises from the assumption
above that both M7 and M8 operate in deep triode region. If Vout1drops from the
equilibrium CM level to one threshold voltage above ground and Vout2 rises by the same
amount, then M7 enters the saturation region, thus exhibiting a variation in its on-resistance that is not counterbalanced by that of M8.
Identical transistors M7 and M8 operate in deep triode region,
9-41 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Sensing and controlling output CM level
We employ a simple amplifier to detect the difference between Vout,CMand a reference
voltage, VREF, applying the result to the NMOS current sources with negative feedback.
If the loop gain is large, the feedback network forces the CM level of Vout1 and Vout2 to
approach VREF.
Also, the feedback may control only a fraction of the current to allow optimization of the
settling behavior. For example, each M3 and M4 can be decomposed into two parallel
devices, one biased at a constant current and the other driven by the error amplifier.
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9-42 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Alternative method of controlling output CM level
In a folded-cascode op amp, the CM feedback may control the tail current
of the input differential pair. This method increases the tail current if Vout1and Vout2 rise, lowering the drain currents of M5M6 and restoring the output
CM level.
9-43 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
CMFB using triode devices
The output CM level sets Ron7||Ron8 such thatID5 and ID6 exactly balance ID9 and ID10, respectively.
Assuming ID9 = ID10 = ID,
RP= Ron7||Ron8 = (VbVGS5)/(2ID ), and also
( )THoutoutoxnP
VVVL
WC
R
2
1
12
8,7
+
=
where( ) 55
5/
2TH
oxn
DGS V
LWC
IV +=
Drawbacks:
1.The value of the output CM level is a function of device
parameters.
2.The voltage drop across Ron7||Ron8 limits the output voltage swing.
3.To minimize this drop, M7 and M8 are usually quite wide devices, introducing
substantial capacitance at the output.
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9-44 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Alternative method of controlling output CM level
If Vb is higher than expected, the tail current of M1 and
M2 increases and the output CM level falls. Since the
feedback through M7 and M8 attempts to correct this
error, the overall change in Vout,CMdepends on the loop
gain in the CMFB network.
Determine the sensitivity dVout,CM/dVb:M7,8 in triode region: gm7,8 = nCox(W/L)7,8VDS7,8Feedback factor:
( )( )THGS
DSononmm
I VV
VRRgg
V
V
=+==
= 8,7
8,78787
01
2
2
Thus,8,7
8,7, 1
DS
THGS
b
CMout
V
VV
dV
dV =
Since VGS7,8 (i.e., the output CM level) is typically
in the vicinity of VDD
/2, the above equation
suggests that VDS7,8 must be maximized.
9-45 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Modification of CMFB for more accurate definition of output MC level
The idea is to define Vb by a current mirror arrangement such that ID9 tracks I1 and IREF.
Suppose (W/L)15 = (W/L)9 and (W/L)16 = (W/L)7 + (W/L)8.
Thus, ID9 = I1 only if Vout,CM= VREF.
The circuit produces an output CM level equal to a reference but it requires no resistors in
sensing Vout,CM.
In practice, since VDS15VDS9, channel-length modulation results in a finite error.
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9-46 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Modification to suppress error due to channel-length modulation
Transistors M17 and M18 reproduce at the drain of M15 a voltage equal to the
source voltage M1 and M2, ensuring that VDS15 = VDS9.
9-47 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Another CM feedback topologies
Differential pair using diode-connected loads
The input CM level, VDDVGS3,4, is relativelywell-defined, but the voltage gain is quite low.
Resistive CMFB
To increase the differential gain, the PMOS
device must operate as current sources for
differential signals.
For differential change at Vout1 and Vout2, node
Pis a virtual ground and the gain can be
expresses as
Av= gm1,2(ro1,2||ro3,4||RF)
For CM levels, M3 and M4 operate as diode-
connected devices.
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9-48 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Input range limitations
Limitation: While the differential input swings are usually much smaller, the input
common-mode level may need to vary over a wide range in some applications.
Unity-gain buffer
The voltage swings are limited by the input differential pair rather than the
output cascode branch. Specifically, Vin,minVout,min = VGS1,2 + VISS, approximatelyone threshold voltage higher than the allowable minimum provided by M5-M8.
If Vin < Vin,min: The MOS transistor operating as ISS enters the triode region,
decreasing the bias current of the differential pair and hence lowering thetransconductance.
9-49 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Extension of input CM range
Variation of equivalent transconductance withthe input CM level.
A simple approach to extending the
input CM range is to incorporate
both NMOS and PMOS differential
pairs such that when one is dead,
the other is alive. This idea is to
combine two folded-cascode op amps
with NMOS and PMOS input
differential pairs.
As the input CM level approaches the
ground potential, the NMOS pairs
transconductance drops, eventually
falling to zero. Nonetheless, the PMOS
pair remains active, allowing normal
operation. Conversely, if the input CM
level approaches VDD, M1Pand M2Pbegin to turn off but M1 and M2 function
properly.
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9-50 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slew rate
Response of a linear circuit to input
step
dVout/dt: Since Vout= V0[1 exp(t/)], where = RC, we have
tV
dt
dVout = exp0
dVout/dtV0; if we apply a larger input step, the output rises more rapidly.
9-51 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slew rate (contd)
Response of a linear op amp to step response
Assume op amp is linear,
sCVRR
V
RVA
RR
RVV Lout
out
out
outoutin ++=
+
2121
2 1
Assume R1 + R2 >> Rout, we have
( )
( )
+++
++
sRRAR
CRRR
RA
As
V
V
Loutin
out
21221
2
111
The step response is given by
( )
( )tu
RRAR
RC
t
RR
RA
AVV
outLout
++
++
=
21221
20
1
exp1
1
indicating that the slope is proportional to the final value.
This type of response is called linear settling.
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9-52 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slew rate (contd)
Slewing in an op amp circuit
( )
( )tu
RRAR
RC
t
RR
RA
AVV
outLout
++
++
=
21221
20
1
exp1
1
The response to sufficiently small inputs follows the exponential of Eq.(A), but
with large input steps, the output displays a linear ramp having a constant slope.
Under this condition, we say the op amp experiences slewing and call the slop ofthe ramp the slew rate.
..(A)
9-53 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Small-signal operation of a simple op amp
Assuming that R1 + R2 is quite large.If Vin experiences a change of V, the total small-signal current providedby the op amp equals gmV. This current begins to change CL, but as Voutrises, so does VX, reducing the difference between VG1 and VG2 and hence
the output current of the op amp.
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9-54 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slewing during large signal transition
Slewing during low-to-high transition
M1 absorbs all of ISS and M2 turns off.
So long as M2 remains off, the feedback
loop is broken and the current charging
CL
is constant and independent of the
input level.
Slewing during high-to-low transition
Slope =ISS /CL
9-55 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Discussion of slew rate
While the small-signal bandwidth of a circuit may suggest a fast time-domainresponse, the large-signal speed may be limited by the slew rate simplybecause the current available to charge and discharge the dominantcapacitor in the circuit is small.
Since the input/output relationship during slewing is nonlinear, the output ofa skewing amplifier exhibits substantial distortion.
For example, if a circuit is to amplify a sinusoid V0sin0t(in the steadystate), then its slew rate must exceed V00.
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9-56 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slewing in telescopic op amp
Vout1 and Vout2 appear as a ramps with slopes equal to ISS /(2CL), and
consequently Vout1Vout2 exhibits a slew rate equal to ISS /CL.
9-57 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slewing in folded-cascode op amp
If IPISS, the slew rate is equal to ISS /CL, independent of IP.
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9-58 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slewing in folded-cascode op amp (contd)
If ISS > IP, then during slewing M3 turns off and VX falls to a low level such that M1and the tail current source enters the triode region. Thus, for the circuit to return to
equilibrium after M2 turns on, VXmust experience a large swing, slow down the
settling.
9-59 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Slewing in folded-cascode op amp (contd)
Clamp circuit to limit swings atXand Y
The difference between ISS and IPflows through
M11, or M12, requiring only enough drop in VXor
VYto return on one of these transistors.
M11 and M12 clamp the two nodes directly to VDD.
Since the equilibrium value VXand VYis usually
higher than VDDVTHN, M11 and M12 are offduring small signal-signal operation.
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9-60 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Power supply rejection
If the circuit in the figure is perfectly symmetric, Vout= VX.
Since the diode-connected device clamps nodeXto VDDVX and hence Voutexperience approximately the same
change as does VDD. In other words, the gain from VDD to
Vout is
1
DD
out
V
V
The power supply rejection ratio (PSRR) is defined as
the gain from the input to the output divided by the gain
from the supply to the output. At low frequencies:
( )oNoPmNDDout
inout rrgVV
VVPSRR
=
9-61 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Noise in a telescopic op amp
Guide: With many transistors in an op amp, it may seem difficult to intuitively identify
the dominant sources of noise. A simple rule for inspection is to change the gate
voltage of each transistor by a small amount and predict the effect at the output.
At relatively low frequency, the
cascode devices contribute negligible
noise, leaving M1-M2 and M7-M8 as the
primary noise sources.
The input-referred noise voltage per unit bandwidth is given by
( ) ( ) 22,1
28,7
8,72,12
2,1
8,7
2,1
222
3
22
3
224
m
m
ox
P
ox
N
m
m
mn
g
g
fCWL
K
fCWL
K
g
g
gkTV ++
+=
where KNand KPdenote the 1/fnoise coefficients of NMOS
and PMOS devices, respectively.
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9-62 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Noise in a fold-cascode op amp
The noise of the cascode devices is negligible at low frequencies,
leaving M1-M
2, M
7-M
8, and M
9-M
10as potentially significant sources.
Thermal noise:
= 22 8,7
8,7
8,7
2
,3
242 outm
m
Moutn Rgg
kTV
= 22 10,9
10,9
10,92,
3
242 outm
m
Moutn Rgg
kTV
= 22 2,1
2,1
2,12,
3
242 outm
m
Moutn Rgg
kTV
andAv
= gm1,2
Rout
.
Total input-referred thermal noise:
++==2
2,1
10,9
22,1
8,7
2,12
2,,2
,3
2
3
2
3
28
m
m
m
m
mv
totoutn
inng
g
g
g
gkT
A
VV
, (uncorrelated noise)
where the factor 2 accounts for noise of M7 and M8, and
Routdenotes the open-loop output resistance of the op
amp.
9-63 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Noise in a fold-cascode op amp (contd)
( )
= 22 8,7
8,7
8,7
2
,
12 outm
ox
PMoutn Rg
fWLC
KV
( )
= 22 10,9
10,9
10,92,
12 outm
ox
NMoutn Rg
fWLC
KV
( )
= 22 2,1
2,1
2,12,
12 outm
ox
NMoutn Rg
fWLC
KV
( ) ( ) ( ) 2 2,1
28,7
8,72
2,1
210,9
10,92,1
2
2,,2
,
12112
m
m
ox
P
m
m
ox
N
v
totoutn
inn
g
g
WLfC
K
g
g
WLWLfC
K
A
VV
+
+=
=
andAv= gm1,2Rout.
Total input-referred flicker noise:
Flicker noise:
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9-64 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Noise in a fold-cascode op amp (contd)
The overall noise:
( ) ( ) ( ) 22,1
2
8,7
8,72
2,1
2
10,9
10,92,1
22,1
10,9
22,1
8,7
2,1
2,
12112
3
2
3
2
3
28
m
m
ox
P
m
m
ox
N
m
m
m
m
m
inn
g
g
WLfCK
g
g
WLWLfCK
g
g
g
g
gkTV
+
++
++=
Discussion:
The noise contribution of the PMOS and NMOS
current sources increases in proportion to their
transconductance. This trend results in a trade-off
between output voltage swings and input-referred
noise: for a given current, as implied by
gm = 2ID /(VGSVTH), if the overdrive voltage ofthe current sources is minimized to allow large
swings, then their transconductance is maximized.
9-65 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design
Noise in a two-stage op amp
( )( )( )231
25
21
752
2
75752
3
161
3
242
85
oomm
mm
v
oommMnrrgg
ggkT
ArrggkTV
+=+=
In the 1st stage:2
1
312
3
242
41
m
mmMn
g
ggkTV
+=
Total input-referred thermal noise: ( )
+++= 2
312
5
753121
2,
1
3
16
oom
mmmm
m
totnrrg
ggggg
kTV
Note the noise resulting from the second
stage is usually negligible because it is
divided by the gain of the first stage when
referred to the main input.
Total voltage gain: Av= gm1(ro1||ro3)gm5(ro5||ro7).
In the 2nd stage: The noise current of M5 and M7 flows through ro5||ro7.