PDR – Preliminary Design Review

Gilad Tsoran

Benny Fellman

Advisor: Shahar Kvatinsky

Continuous FlowMulti-Threading

FPGA Implementation

HHHSSS DDDSSSLLL

Winter 2013

Background

Advances in memory technology inspire new architectures

Memristor based elements deliver large, fast, on die memory

Many ways to use this memory- “Memory Intensive Computing”

Current trend- MultiThreading

Switch on Event (SoE)

Fine grained (interleaved)

SMT

Switch on Event Advantages:

− Less logic than SMT − Better utilization of pipeline than fine

grained

Problem:− Flushing the pipe upon switch reduces

performance and increases power

Solution:− CFMT architecture: keep pipe state

nearby upon switch

5

CacheMiss22

1121 12 123 1234 12345 123456

2

Memory unit

6 5 4 3

1 12 123 1234 12345

End ofMemory

Operation

2

123456 234567

6 5 4 3

345678

Concept Illustration

Project Goals

Analyze CFMT performance

Requires:

Implementing on FPGA

Developing verification environment

Running benchmarks

Previous Project accomplishments

Simulation Level Verilog Implementation

Support for most of Alpha ISA

Initial analysis based on reduced benchmark running on simulation

High Level Design

Pipe Line

Execution Unit Controller (EUC)

Fetch Dependancy

check

Addr calc.

Exe. unit

route

int

Write Back

FP

FP

Mem

Memristor Thread Memory

Thread memory controller (TMC)Thread Switch Controller (TSC)

Thread State Table (TST)

Pipe control

Decode

Development Environment Design and simulation using

ModelSim

Synthesis would be done with the FPGA specific tools

Analysis using Excel

Gantt Chart

1 Adapt old project to FPGA environment

1.1 Adjusting Verilog code for synthesis correctness.

1.2 Coding necessary elements for FPGA.

1.3 Develop FPGA interface

1.4 Verification

1.5 run Dhrystone benchmark

2 Run Benchmark

2.1 Coding missing ops from Ispec 2006 benchmark

2.2 Run Ispec2006

2.3 performance analysis

3 Summary

3.1 Finalize Project Book

3.2 Prepare Presentation

14-Jan 21-Jan 28-Jan26-Nov 3-Dec 10-Dec 17-Dec

2013Objectives

24-Dec 31-Dec 7-Jan12-Nov 19-Nov

2014

11

Pipeline Stage Connector

Stage i

Stage i+1

Memristor Memory

En

RST

Select data