7
Physically Unclonable Function Using CMOS Breakdown Position K.-H. Chuang 1,2 , E. Bury 2,3 , R. Degraeve 2 , B. Kaczer 2 , G. Groeseneken 2,3 , I. Verbauwhede 1 and D. Linten 2 1 imec-COSIC, KU Leuven, Belgium 2 imec, Leuven, Belgium 3 ESAT, KU Leuven, Belgium Email: [email protected] Abstract—A novel physically unclonable function (PUF) utilizing the intrinsic randomness of oxide breakdown (BD) positions in CMOS transistors is presented. The advantages of this approach are studied and validated by measurements on test-chips fabricated in a commercial 40nm CMOS process. Experiments show that the required soft BDs can be reliably generated in a sufficiently short period. The randomness of the utilized mechanism shows excellent properties, required for PUF applications: an overall bias of 0.498 and inter-chip hamming distance (HD) of 0.501. Further analysis of the current distributions reveals a dependence of operating voltage on readout resolution and window. Finally, dedicated experiments with external heating and embedded poly-heaters show that these soft BDs are stable and show no read-out errors up to operating temperatures of 600K. Index Terms—Hardware security, cryptography, physically unclonable function, reliability, oxide breakdown I. INTRODUCTION A physically unclonable function (PUF) is an essential building block for hardware security applications. A PUF implemented in commercial silicon technology enables chip level cryptographic functions such as secret key generation, entity authentication and IP protection [1]-[4]. Ideally, a silicon PUF utilizes intrinsic sources of variation on devices or interconnections, to extract a unique data pattern which is unpredictable and reproducible in various noisy environments. In reality however, a silicon PUF suffers from entropy loss and bit instability due to problems like systematic mismatch and noise sensitivity. In this work we focus on the PUFs for key generation applications [5], before generating a useful secret key, a non- ideal PUF requires additional post-processing such as error correction, de-biasing and compression [6]. These processes introduce not only extra logic circuits but also necessitates the presence of helper data to support these operations. The helper data are normally stored in a separate non-volatile memory (NVM), which signifies an additional cost (in contrast to the case where it can be stored in regular core devices) and security issue: the unencrypted helper data may leak information that makes PUF less unpredictable. In order to cope with these weaknesses, we propose a novel BD-PUF (Fig.1) using the randomness of breakdown positions in CMOS devices. This paper is organized as the follows: In Section II, we discuss the concept of using CMOS breakdown positions as entropy source for PUF. In Section III, we show a PUF array designed in a commercial 40nm CMOS process and the feasibility of creating soft BD. Section IV discusses the electrical properties of the PUF cells after breakdown generation. In Section V, we statistically evaluate the key properties of PUF data, such as the performance indices. In Section VI, the stability of BD-PUF is evaluated. Conclusions are stated in Section VII. This work is supported in part by the European Commission through the Horizon 2020 research and innovation program under grant agreement No 644052 HECTOR. Fig. 1. (a) Unit cell of BD-PUF, consisting of two minimum sized nFET (120nm x 40nm) and a pFET selector. BD can be generated on one of the nFETs. (b) The test array with 60 cells, which has been fabricated in a commercial CMOS process. (b) Stress (V DD ) 5 x 12 devices WL 1 WL 2 WL 12 BL 1 BL 1 BL 2 BL 2 BL 5 BL 5 WL BL BL Stress (a)

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Page 1: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

Physically Unclonable Function Using CMOS Breakdown Position

K.-H. Chuang1,2, E. Bury2,3, R. Degraeve2, B. Kaczer2, G. Groeseneken2,3, I. Verbauwhede1 and D. Linten2 1imec-COSIC, KU Leuven, Belgium

2imec, Leuven, Belgium

3ESAT, KU Leuven, Belgium

Email: [email protected]

Abstract—A novel physically unclonable function (PUF) utilizing the intrinsic randomness of oxide breakdown (BD) positions in CMOS transistors is presented. The advantages of this approach are studied and validated by measurements on test-chips fabricated in a commercial 40nm CMOS process. Experiments show that the required soft BDs can be reliably generated in a sufficiently short period. The randomness of the utilized mechanism shows excellent properties, required for PUF applications: an overall bias of 0.498 and inter-chip hamming distance (HD) of 0.501. Further analysis of the current distributions reveals a dependence of operating voltage on readout resolution and window. Finally, dedicated experiments with external heating and embedded poly-heaters show that these soft BDs are stable and show no read-out errors up to operating temperatures of 600K.

Index Terms—Hardware security, cryptography, physically unclonable function, reliability, oxide breakdown

I. INTRODUCTION

A physically unclonable function (PUF) is an essential building block for hardware security applications. A PUF implemented in commercial silicon technology enables chip level cryptographic functions such as secret key generation, entity authentication and IP protection [1]-[4]. Ideally, a silicon PUF utilizes intrinsic sources of variation on devices or interconnections, to extract a unique data pattern which is unpredictable and reproducible in various noisy environments. In reality however, a silicon PUF suffers from entropy loss and bit instability due to problems like systematic mismatch and noise sensitivity.

In this work we focus on the PUFs for key generation applications [5], before generating a useful secret key, a non-ideal PUF requires additional post-processing such as error correction, de-biasing and compression [6]. These processes introduce not only extra logic circuits but also necessitates the presence of helper data to support these operations. The helper data are normally stored in a separate non-volatile memory (NVM), which signifies an additional cost (in contrast to the case where it can be stored in regular core devices) and security issue: the unencrypted helper data may leak information that makes PUF less unpredictable. In order to cope with these

weaknesses, we propose a novel BD-PUF (Fig.1) using the randomness of breakdown positions in CMOS devices.

This paper is organized as the follows: In Section II, we discuss the concept of using CMOS breakdown positions as entropy source for PUF. In Section III, we show a PUF array designed in a commercial 40nm CMOS process and the feasibility of creating soft BD. Section IV discusses the electrical properties of the PUF cells after breakdown generation. In Section V, we statistically evaluate the key properties of PUF data, such as the performance indices. In Section VI, the stability of BD-PUF is evaluated. Conclusions are stated in Section VII.

This work is supported in part by the European Commissionthrough the Horizon 2020 research and innovation program under grantagreement No 644052 HECTOR.

Fig. 1. (a) Unit cell of BD-PUF, consisting of two minimum sized nFET (120nm x 40nm) and a pFET selector. BD can be

generated on one of the nFETs. (b) The test array with 60 cells, which has been fabricated in a commercial CMOS process.

(b)Stress(VDD)

5 x 12 devices

WL1

WL2

WL12

BL1 BL1 BL2 BL2 BL5 BL5

WL

BL BL

Stress(a)

Page 2: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

II. PUF AND BREAKDOWN IN CMOS

A. Bit instability in PUFs

In CMOS technologies, the widely discussed SRAM PUF reads out the power-up patterns, which are ideally random and unique for different cells and dies [4],[7]. The entropy source of the SRAM PUF is process variations in a pair of matched invertors, resulting in the different pull-up and pull-down strengths. A well-known problem of this approach is that the powered-up SRAMs always experience an inherent metastable state while generating the PUF data. Since the circuits are especially sensitive to noise in the metastable state, the SRAM PUF suffers from a higher quantity of unstable bits. The same problem can be found in several implementations using other kinds of sequential logics such as latch PUF [8] and sense-amplifier PUF [9].

As a solution towards better stability, there exists an interesting link between security and reliability physics. Several strategies using burn-in reinforcement have been reported to enhance the stability of the PUF cells [9]-[11]. These methods increase the mismatch between the two competing units by applying an intentional aging stress after first readout, which introduces biased-temperature instability (BTI) or hot carrier injection (HCI) degradation. The increment of mismatch keeps the following readout more immune to noise and thus will be more similar to the first readout. However, as reported in these studies, these techniques require a long aging period (few seconds to hours) for a sufficient enhancement, which is not feasible for all application.

B. Concepts of breakdown positions

The time-dependent dielectric breakdown (TDDB) is a well-studied reliability issue in modern silicon technologies. In deep sub-micron CMOS processes, the gate oxide thickness is strongly reduced, resulting in a higher risk for the circuit to suffer from the detrimental breakdown issues [12]. When applying high voltage stress to the gate of MOSFETs, it randomly generates defects within the gate oxide [13]. After being stressed for a sufficient time, some defects may form one or more percolation paths [14]. Therefore, the positions of these paths will also be randomly distributed between the source and the drain of the FET. In the case that only one breakdown path exists in the FET, the lateral position of this breakdown can be determined based on voltage and current behavior [14]-[17].

The underlying randomness of the CMOS breakdown positions makes it a promising candidate as a highly stable entropy source. The breakdown is physically generated which introduces variations with stronger magnitude comparing to the intrinsic process variations used by conventional PUFs. The readout of a such entropy source tends to be more robust and may require less complex post-processing. Consequently, we propose this novel PUF implementation utilizing the position of oxide breakdown in CMOS, which we will prove to suffice the key PUF figure-of-merits, including randomness, uniqueness and stability at elevated temperatures.

C. Volatile PUFs and nonvolatile PUFs

Before showing the design details and experimental results of the BD-PUF, we first discuss the pros and cons of two PUF

categories according to the volatility. Table 1 shows a brief comparison between these two. A volatile PUF such as the SRAM PUF will generate readable data only when powered on. This property makes it less stable since the PUF data have to be regenerated every on/off cycles, and will introduce higher leakage current to keep the data; on the other hand the PUF data is unreadable without proper setup, which makes it more difficult to attack. For the nonvolatile PUFs such as RRAM PUFs [18] or the proposed BD-PUF, the data is stored like FLASH or OTP memories, which tends to be more stable but have higher risk to be attacked. It should be noted that the BD-PUFs rely on only “soft” breakdown [12] to avoid the possible visibility of breakdown positions, which may cause security breaches.

Table. 1. Comparison of volatile and nonvolatile PUFs

PUF Type Example Bit

stability Leakage current

Risk of attacking

Volatile SRAM Low High Low

Nonvolatile BD-PUF High Low High

III. TEST STRUCTURE DESIGN AND FEASIBILITY PROOF

A. Test structure overview

A dedicated test structure for the proposed PUF is developed, with the unit cell consisting two minimum-sized nFETs and a pFET selector as shown in Fig. 1(a). This structure requires an additional step called “forming” before operating as a PUF, i.e. creating breakdown on one of the nFETs. Forming is done by applying a high positive voltage across the unit cell The on-state pFET selector allows this high voltage to fall on the nFET gates with negligible voltage drop. As soon as a breakdown occurs on either one of the nFETs, breakdown current through the broken oxide will induce a higher voltage drop on the pFET selector, which then acts as a compliance transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken nFET is

Fig. 2. Time-to-breakdown distribution for single BD-PUF cell

under different stress voltages in Weibull scale. The slope is varying for different stress conditions. The dark dashed lines show the approximation using the maximum Weibull slope

(βmax) at 4V and the red dashed line shows the approximation using the minimum Weibull slope (βmin) at 3.6V.

Page 3: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

sufficiently released from stress and the breakdown path will stop growing as the current reaches its limit. Consequently, only one “soft” breakdown will occur in this unit cell and the breakdown hardness, which is controlled by the current level, will be relatively similar.

In order to statistically verify the concept of BD-PUF, the test structure is designed into an array configuration as shown in Fig. 1(b). The array consisting twelve rows and five columns with totally 60 BD-PUF cells in each array. The shared control lines can be connected to the equipment directly, allowing precise voltage and current measurements. This test structure is designed and fabricated in a commercial 40nm CMOS technology using only core devices.

B. Forming Analysis

The fundamental requirement of forming step is to produce soft breakdowns in a reliable way within a sufficiently short time. In order to prove its feasibility, we individually stress 300 PUF cells (i.e. over multiple dies) under different voltages and measured the corresponding time-to-breakdown (tBD). The resulting tBD-distribution is plotted in Fig. 2. It can be clearly observed that the Weibull-slope (β) increases with elevated stress voltages. We attribute the variations on slopes to the competition of breakdown in a bilayer dielectric stack, consisting of SiO2 and high-k [20]-[21]. Note that the traditional Weibull fitting is not applicable with this varying slopes, and the limited number of samples is not sufficient to characterize the bimodal distribution.

In order to have a good estimation on forming time of higher percentile, which is set as 99.9% in this case, we make the extrapolation from zero Weibit using two extreme values of slopes βmax and βmin shown in Fig. 2. The results are plotted in Fig. 3 which shows that the forming time for all cells can be

pushed below 0.1s at 4.5V, even with the ‘worst-case’ slope βmin.

It should be noted that over-stressing can be detrimental for the BD-PUF. Although the oxide of two nFETs experience the highest stress during forming process, the pFET selector is also inherently stressed by a lower voltage as well as the parasitic P/N junctions of all FETs. These parts can also breakdown with a sufficient long period as illustrated in Fig. 3. An array stressed under 4.5V for about 0.5 second (equipment limitation) was found to have failures, showing the fatality above this stress condition. This issue can be avoid by a controlled stress pulse, or implementing an in-situ breakdown sensor to stop stressing. The breakdown sensing can be simply determined by monitoring the voltage drop at the pFET source and drain.

C. Breakdown Position Readout

Techniques to determine the lateral position of a breakdown spot within a single FET have been studied and developed in several earlier works [15]-[17]. Considering the case of two separated nFETs used here, the issue is efficiently binarized. A straightforward method to distinguish the binary breakdown position is to compare the current between BL and BL (Fig. 4(b)), which is similar to the s-ratio technique [15]-[17]. Fig.4 shows the extracted breakdown position under three different supply voltages (VDD), indicating the occurrence of soft breakdown on one of the nFETs. For positions below 0.5 the breakdown occurs on the left nFET, which is represented by bit “0”; conversely the breakdown occurs on the right nFET and represented by bit “1”. Note that the readout become more challenging when lowering VDD below 1V, the reason will be discussed in the following paragraph.

IV. POST-BREAKDOWN CURRENT ANALYSIS

In order to further study the voltage dependence of breakdown position readout, we first distinguish the broken and non-broken nFETs of each PUF cells based on the current level at 1.5V which shows a binary-like distribution. The separated current distribution under different VDD are plotted in Fig. 5,

Fig. 3. Approximated array forming time at CDF of 99.9%. The blue-colored region shows the tBD is too low to be measured by

our equipment. The dark red-colored region shows the fatal voltages and times that will damage at some PUF cells, this fatal

zone is confirmed by observing short circuits within an array stressed by 4.5V for minimum stress time (~0.5s). The two reasons for this issue are BD occurs at pFET selector or P/N

junctions, both follows different tBD relation which will result in an intercepting region as shown with light-red color

(unconfirmed illustration).

Fig. 4. (a) CDF of the extracted position under three VDD values

using the equation in inset. The result at the elevated VDD is binary as expected, but the distribution at VDD below 1V is not well separated. (b) BD-PUF cell under measurement (readout)

condition, BD position is extracted by s-ratio formula [15]-[17].

Elevated VDD= 1.2V and 1.5V

(a)

(b)

Page 4: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

clearly showing different distribution shape and voltage dependence. The current through breakdown spot (BD current) has significant stronger voltage dependence than the current through the unbroken oxide (leakage current). This is the cause of overlap of two distributions at low VDD, making some of the extracted positions close to 0.5. The breakdown position readout at low VDD has thus more uncertainty since the readout process with actual circuit is noisy and the points close to middle are vulnerable to fluctuation.

Moreover, it can be observed that the leakage current distributions of the unbroken oxides shows three distinct modes (Fig. 6). This behavior can be attributed to the dominating trap-assisted tunneling (TAT) leakage path formed by different numbers of traps [14],[22]. In addition to the pre-existing defects, the forming stress could potentially activate defects in the unbroken nFET, resulting in higher probability to have multiple defect conduction path. The TAT current through three-defect conduction paths causes the high-current tail of the unbroken FETs. This tail overlaps with the tail of the distribution of the broken FETs at low VDD.

The current-voltage behavior of a soft breakdown path can be described by the quantum point contact (QPC) [23]-[24]. Within the measured VDD range of our interest, BD current follows approximately exponential voltage dependence. This explains the strong impact on the extracted breakdown position (Fig. 4) at elevated VDD. Besides the exponential voltage dependence, the breakdown current distribution is in the first approximation lognormal (Fig. 5). This can be attributed to the normal distribution of shape and size variations of the breakdown filament, as the soft breakdown current has exponential sensitivity to these variations.

The current distributions show that the overlapping of the leakage current and BD current at low VDD (below 0.9V) is inevitable with the targeted (soft) breakdown hardness. Since two current distributions are affected by different mechanisms, there is no correlation on the measurement data. The estimated probability of a PUF cell to have leakage and BD current within the overlapped region at VDD=0.9V is below 0.1%, showing negligible loss if masking out all these cell that may introduce readout uncertainty. Therefore, masking those cells is a possible

solution to operate the BD-PUF below nominal VDD conditions. On the other hand, the robustness of the BD position readout can be significantly increased by elevating VDD.

V. STATISTICAL PERFORMANCE

In order to generate a secret key for cryptographic usage, the data extracted from a PUF array need to suffice the requirements on having enough randomness and uniqueness. This will be discussed in the subsequent paragraphs.

A. Randomness

A simplified definition of randomness can be understood as the probability to successfully predict the output of a certain PUF cell. The ideal case of PUF, which is being unpredictable, results from the equal probability of generating “0” and “1” bits, leading to the minimum success rate of 0.5. To examine the quality of PUF data, the binarized readouts of BD-PUF arrays are plotted as a bitmap in Fig. 7, which shows no repeating pattern. The distribution of “1”-bits per array (bias) of 68 measured arrays is plotted in Fig. 8. The result fits well with the mathematical ideal case—a binomial distribution with n=60 and p=0.5. This represents the result obtained from PUF arrays constructed by cells with well-defined probability of “1”-bit equals to 0.5. Also the average bias among all measured PUF cells is 0.498, this value obtained from 4080 PUF cells is clearly within ±σ of a binomial distribution with n=4080 and p=0.5.

Fig. 5. Breakdown current and leakage current distributions

under VDD of 0.9V and 1.5V. The gap between two distribution narrows at lower VDD, affects read-out resolution.

BDleakage

Fig. 6. Leakage current in three VDD (left to right: 0.9V, 1.2V and 1.5V). The different modes in the distribution corresponds to various number of defects. With three or more defects, TAT

can induce much higher current as observed.

Elevated VDD

from 0.9V to 1.5V

Fig. 7. (a) Binarized readout from a single array and (b)

combined results from 60 arrays.

Page 5: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

Both results show that the BD-PUF is equally probable to produce “0” and “1” bits with a high confidence.

B. Uniqueness

The uniqueness for a PUF indicates the correlation between different PUF arrays (chips), ideally the PUF data from any two selected arrays should be uncorrelated. As such, a PUF array with perfect uniqueness is still unpredictable, even if data from other PUF arrays are already known. The uniqueness can be strongly degraded by systematic variations, making a specific cells or regions to be more likely to produce “0” or “1” bits. In order to evaluate the uniqueness, the inter-chip hamming distance (HD) is computed by counting numbers of different bits between two arrays. The distribution of HD is shown in Fig. 9, which can also be well fitted by a binomial distribution of n=60 and p=0.5. The obtained data matches excellently with the ideal case as shown in Fig. 9. The average computed HD equals to 0.501 also close to its ideal value of 0.5.

Both the result of bias and inter-chip HD proves that the proposed PUF cell has the desired randomness and uniqueness, indicating that the soft breakdown generation is a purely

random behavior with no favors of any side and is not affected by systematic variations of process or measurement equipment.

VI. DATA STABILITY

The most critical requirement for a PUF nowadays is to reproduce the same output data at different operating time and environmental conditions. For the proposed BD-PUF, when one soft breakdown is generated, it’s not possible to create a stronger conduction path with limitation set by the pFET selector. Also the soft breakdown is physically generated which is nonvolatile in terms of normal device lifetime. These two properties show that a BD-PUF cell is stable over time, the stability of extracted PUF data is solely determined by the readout circuit or equipment which is out of scope in this paper. Therefore, the remaining scope of the stability can be narrowed down to the thermal stability.

A. Embedded Poly-Heaters

In order to heat the devices up to a relatively high temperature, a part of the test chip contains standalone PUF cells surrounded by dedicated poly-resistor based heaters as shown in Fig. 10. The heater is designed to dissipate large power for heating up the device almost instantaneously to several hundred degrees above room temperature [25]. The actual device temperature can be sensed by a dedicated diode placed next to the targeted device. The temperature is measured based on the ratio of diode voltage while injecting two constant currents, this ratio is linearly proportional to device temperature [25]. Finally, the diode output voltages are calibrated with a thermo-chuck as shown in Fig. 10(b-c). The standalone PUF cell can be heated 300K above room temperature before reaching the breakdown voltage of poly-resistors.

Fig. 8. Histogram of bias within the 68 arrays (each of them consisting of 60 devices). (b) The binomial distribution of

N=4080, showing the average bias of 0.498 is close to the ideal bias of 0.5 with high confidence.

Fig. 9. Inter-chip hamming distance between 68 arrays (i.e. the

uniqueness of each chip), the result can be fitted well in the ideal binomial distribution.

Binomial distributionMeasured Inter-HD

Fig. 10. (a) Illustration of resistive poly-heaters in which (b) the

current flow will induce Joule heating that (c) raises the temperature of the standalone BD-PUF cells as power increases.

Page 6: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

B. Instantaneous High Temperature Meassurement

We measured the breakdown position of 15 standalone PUF cells heated up by poly-heaters to several temperatures as shown in Fig. 11. The distribution of extracted position under 0.9V VDD stays almost unchanged from 300K to 600K, implying that the BD-PUF output has no temperature dependence. Moreover, the characteristic of a PUF cell stays intact after being heated up to 600K, which also implies that this temperature does not physically change (e.g. anneal) properties of breakdown and leakage path.

C. Full-array and Long-term Measurement

In order to obtain more statistics to support the above conclusion, the PUF arrays were heated up entirely by thermo-chuck within a smaller temperature range. Fig. 12 shows the scattering plots of extracted positions at room temperature, 325K and 345K after several hours of heating. The result shows

no temperature dependence on the readouts, there is also no cell turns out to produce opposite data indicated by the colored region in Fig. 12. Although we observe some fluctuation in different temperatures, it does not imply instability since the measurement environment changes when repeating for different temperatures, e.g. contacts between probes and pads are different. Both results from full-array and standalone PUF cells prove that the BD-PUF is resistant to high temperature.

VII. CONCLUSIONS

We have demonstrated a novel PUF implementation that can harvest entropy from the intrinsic randomness of oxide BD positions in MOSFETs. The experimental results and analysis support the feasibility of implementing the BD-PUF idea in the real-world hardware security designs. The statistical performance on randomness and uniqueness has proven that breakdown position is a promising entropy source. Based on the analysis of oxide physics and the experiment on various temperatures, we show that BD-PUF is robust with an elevated supply voltage and is stable over temperature. Our results prove that the BD-PUF is a highly reliable and cheap building block for the on-chip key generation in CMOS technologies.

REFERENCES [1] R. Maes, “Physically unclonable functions: Construction, properties and

applications”, PhD Thesis, KU Leuven, 2012. [2] G. E. Suh and S. Devadas, “Physical Unclonable Functions for Device

Authentication and Secret Key Generation,” in Proc. Design Automation Conference, 2007, pp. 9–14.

[3] S. K. Mathew et al., "16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 278-279.

[4] R. Maes, V. Rozic, I. Verbauwhede, P. Koeberl, E. van der Sluis, and V. can der Leest, “Experimental evaluation of physically unclonable functions in 65 nm CMOS,” in Proc. Eur. Solid State Circuit Conf. (ESSCIRC), 2012, pp. 486–489.

[5] J. Guajardo, S. Kumar, G. J. Schrijen and P. Tuyls, "FPGA intrinsic PUFs and their use for IP protection." International workshop on Cryptographic Hardware and Embedded Systems, Springer Berlin Heidelberg, 2007.

[6] Y. Dodis, L. Reyzin and A. Smith “Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data.” in Advances in Cryptology – EUROCRYPT 2004. Lecture Notes in Computer Science (LNCS), vol. 3027. Springer, 523–540. pages 82, 140, 154, 167, 172, 173

[7] D. E. Holcomb, W. P. Burleson and K. Fu, "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers," in IEEE Transactions on Computers, vol. 58, no. 9, pp. 1198-1210, Sept. 2009.

[8] Y. Su, J. Holleman and B. P. Otis, "A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations," in IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 69-77, Jan. 2008.

[9] M. Bhargava and K. Mai, "An efficient reliable PUF-based cryptographic key generator in 65nm CMOS," 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2014, pp. 1-6.

[10] R. Maes and V. van der Leest, "Countering the effects of silicon aging on SRAM PUFs," 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, 2014, pp. 148-153.

[11] S. Mathew et al., “A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2016, pp. 1–2.

[12] B. Kaczer, R. Degraeve, M. Rasras, K. Van de Mieroop, P. J. Roussel and G. Groeseneken, "Impact of MOSFET gate oxide breakdown on

Fig. 11. CDF of standalone devices with BD heated to different

temperatures measured under 0.9V VDD. Heating does not affect read-out even for temperatures way above normal

operation requirements, i.e. high temperature does not physically change BD path.

Standalone BD-PUF cells

300 K

600 K

T ↑

Fig. 12. The relation between extracted position of the test

arrays under room temperature and 325 K and 345 K at VDD=0.9V. No device is observed within gray-colored region which may cause different readout at elevated temperatures,

which proves that BD-PUF is stable over temperature.

Page 7: Physically Unclonable Function Using CMOS Breakdown Position · transistor in saturation [18]. As a result, both the stress voltage and current are limited by this pFET, the non-broken

digital circuit operation and reliability," in IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 500-506, Mar 2002.

[13] R. Degraeve et al., "New insights in the relation between electron trap generation and the statistical properties of oxide breakdown," in IEEE Transactions on Electron Devices, vol. 45, no. 4, pp. 904-911, Apr 1998.

[14] B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, V. Simons and G. Groeseneken, "Consistent model for short-channel nMOSFET after hard gate oxide breakdown," in IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 507-513, Mar 2002.

[15] R. Degraeve, B. Kaczer, A. De Keersgieter and G. Groeseneken, "Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications," in IEEE Transactions on Device and Materials Reliability, vol. 1, no. 3, pp. 163-169, Sep 2001.

[16] M. A. Alam, D. Varghese and B. Kaczer, "Theory of Breakdown Position Determination by Voltage- and Current-Ratio Methods," in IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3150-3158, Nov. 2008.

[17] E. Bury et al., "Study of (correlated) trap sites in SILC, BTI and RTN in SiON and HKMG devices," Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Marina Bay Sands, 2014, pp. 250-253.

[18] P. Y. Chen, R. Fang, R. Liu, C. Chakrabarti, Y. Cao and S. Yu, "Exploiting resistive cross-point array for compact design of physical unclonable function," 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, 2015, pp. 26-31.

[19] B. P. Linder et al., "Gate oxide breakdown under Current Limited Constant Voltage Stress," 2000 Symposium on VLSI Technology. Digest of Technical Papers, Honolulu, HI, USA, 2000, pp. 214-215.

[20] R. Degraeve et al., "Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress," IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest., Washington, DC, 2005, pp. 408-411.

[21] T. Nigam, A. Kerber and P. Peumans, "Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks," 2009 IEEE International Reliability Physics Symposium, Montreal, QC, 2009, pp. 523-530.

[22] R. Degraeve, B. Govoreanu, B. Kaczer, J. Van Houdt and G. Groeseneken, "Measurement and statistical analysis of single trap current-voltage characteristics in ultrathin SiON," IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual., pp. 360-365.

[23] E. Miranda et al., "Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics," in IEEE Transactions on Electron Devices, vol. 47, no. 1, pp. 82-89, Jan 2000.

[24] A. Cester, L. Bandiera, J. Sune, L. Boschiero, G. Ghidini and A. Paccagnella, "A novel approach to quantum point contact for post soft breakdown conduction," International Electron Devices Meeting. Technical Digest, Washington, DC, USA, 2001, pp. 13.6.1-13.6.4.

[25] J. Franco, B. Kaczer and G. Groeseneken, “Poly -Si heaters for ultra -fast local temperature control of on -wafer test structures”, Microelectronic Engineering, Vol. 114, pp. 47 -51, (2014)