Planarization coating for polyimide substrates used in roll-to-roll

fabrication of active matrix backplanes for flexible displays

Marcia Almanza-Workman, Albert Jeans, Steve Braymen, Richard E. Elder, Robert A. Garcia,

Alejandro de la Fuente Vornbrock, Jason Hauschildt, Edward Holland, Warren Jackson, Mehrban Jam,

Frank Jeffrey, Kelly Junge, Han-Jun Kim, Ohseung Kwon, Dan Larson, John Maltabes, Ping Mei, Craig

Perlov, Mark Smith, Dan Stieler, Carl P. Taussig, Steven Trovinger, Lihua Zhao

HP Laboratories

HPL-2012-23

Keyword(s): Planarization coating; plastic substrate; self-align imprint lithography; flexible displays; active matrix

backplane; roll-to-roll fabrication

Abstract: Good surface quality of plastic substrates is essential to reduce pixel defects during roll-to-roll fabrication of flexible

display active matrix backplanes. Standard polyimide substrates have a high density of “bumps” from fillers and

belt marks and other defects from dust and surface scratching. Some of these defects could be the source of shunts in

dielectrics. The gate dielectric must prevent shorts between the source/drain and the gate in the transistors, resist

shorts in the hold capacitor and stop shorts in the data/gate line crossovers in active matrix backplanes fabricated by

self-aligned imprint lithography (SAIL) roll-to-roll processes. Otherwise data and gate lines will become shorted

creating line or pixel defects. In this paper, we discuss the development of a proprietary UV curable planarization

material that can be coated by roll-to-roll processes. This material was engineered to have low shrinkage, excellent

adhesion to polyimide, high dry etch resistance, and great chemical and thermal stability. Results from PECVD

deposition of an amorphous silicon stack on the planarized polyimide and compatibility with roll-to-roll processes to

fabricate active matrix backplanes are also discussed. The effect of the planarization on defects in the stack, shunts

in the dielectric and curvature of finished arrays will also be described.

External Posting Date: February 6, 2012 [Fulltext] Approved for External Publication

Internal Posting Date: February 6, 2012 [Fulltext]

Copyright 2012 Hewlett-Packard Development Company, L.P.

Planarization coating for polyimide substrates used in roll-to-roll fabrication of active matrix backplanes for flexible displays

A. Marcia Almanza-Workman*a, Albert Jeansb, Steve Braymenc, Richard E. Elderb, Robert

A. Garciab, Alejandro de la Fuente Vornbrockb, Jason Hauschildtc, Edward Hollandb, Warren Jacksonb, Mehrban Jamb, Frank Jeffreyc, Kelly Jungec, Han-Jun Kimb, Ohseung Kwona, Dan

Larsonc, John Maltabesb, Ping Meib, Craig Perlovb Mark Smithb, Dan Stielerc, Carl P. Taussigb, Steven Trovingerb, Lihua Zhaob

aPhicot Inc, 1501 Page Mill Rd, Palo Alto, CA 94304, USA;

bHewlett-Packard Laboratories, 1501 Page Mill Rd, Palo Alto, CA 94304, USA; cPowerfilm Inc, 2337 230th St, Ames, IA 50014, USA.

ABSTRACT

Good surface quality of plastic substrates is essential to reduce pixel defects during roll-to-roll fabrication of flexible display active matrix backplanes. Standard polyimide substrates have a high density of “bumps” from fillers and belt marks and other defects from dust and surface scratching. Some of these defects could be the source of shunts in dielectrics. The gate dielectric must prevent shorts between the source/drain and the gate in the transistors, resist shorts in the hold capacitor and stop shorts in the data/gate line crossovers in active matrix backplanes fabricated by self-aligned imprint lithography (SAIL) roll-to-roll processes. Otherwise data and gate lines will become shorted creating line or pixel defects. In this paper, we discuss the development of a proprietary UV curable planarization material that can be coated by roll-to-roll processes. This material was engineered to have low shrinkage, excellent adhesion to polyimide, high dry etch resistance, and great chemical and thermal stability. Results from PECVD deposition of an amorphous silicon stack on the planarized polyimide and compatibility with roll-to-roll processes to fabricate active matrix backplanes are also discussed. The effect of the planarization on defects in the stack, shunts in the dielectric and curvature of finished arrays will also be described.

Keywords: Planarization coating, plastic substrate, self-align imprint lithography, flexible displays, active matrix backplane, roll-to-roll fabrication

1. INTRODUCTION

Recently there has been increasing demand for lightweight, low-cost, and rugged displays. Fabricating devices on flexible webs is one way to meet these requirements, with the added advantage that a web can be roll-to-roll (R2R) processed. This could result in dramatically lower fabrication costs since R2R processing is steady-state and avoids many of the transients and handling complications associated with traditional batch processing of silicon wafers and flat panels, thus enabling higher throughput. In addition, a rolled up web is impervious to particle contamination so that clean room requirements are substantially reduced. The ideal substrate for R2R electronics fabrication has not yet emerged. Material choice is highly dependent on application and process compatibility. Stainless steel and flexible glass can support high process temperatures and are impermeable, but the former has a rough surface, is opaque, is prone to “kinking” on impact due to its lower yield strain relative to plastic films and requires a dielectric isolation layer, and the latter is notch sensitive. Polyethylene naphthalate (PEN), and polyethylene terephthalate (PET) have good transparency and relatively low cost but are limited to low process temperature ceilings and have high coefficients of thermal expansion (CTE) which are incompatible with typical inorganic thin film transistor materials. Processing PEN or PET at moderate temperature results in increased surface roughness due to migration of oligomers to the surface. This roughness degrades optical and electrical device performance. Planarization coatings act as a barrier to this cyclic oligomer migration.1,2 Polyimide can be processed at temperatures in excess of 300°C and has excellent mechanical properties but has poor transparency. Table 1 summarizes some of the important properties of the common substrate options. In

general these substrates all have anisotropic properties due to the R2R processes used in their manufacture. From a product form-factor perspective, plastics have the best combination of mechanical toughness, light weight and low cost; however, their poor mechanical stability and high permeability make device fabrication challenging. Thin glass can be made flexible and it provides an excellent impermeable interface for device fabrication, but it is still notch-sensitive. Tiny imperfections or damage at the edge of the web can lead to catastrophic failure.

Table 1. Substrate Options for R2R Manufacturing

Polyimide PEN PET

Stainless steel

Flexible glass

Max process Temp [°C] 350 180 150 1000 600 Modulus [GPa @20°C] 9 5 4 200 70 transparency Low Good Good Opaque Exc. Surface roughness Med. Med. Med. Poor Exc. CTE [ppm/°C] 16 40 ~20 10 5 Moisture absorption Low Med. Med. None None cost Med. Med. Low Moderate High?? issues Yellow High CTE Low process temp

Conductive Stiff

Brittle

The surface quality of the substrate is essential to reduce pixel defects to an acceptable level on active matrix backplanes fabricated by roll-to-roll processes using SAIL technology. Typical polyimide substrates have a high density of “bumps” from fillers and belt marks and other defects from dust and surface scratching (Figure 1). It is believed that some of these bumps could be the source of shunt defects in our dielectric. A composite substrate built up from a plastic film with a thin planarization coating is an attractive option. The polymer will make up the bulk of the material and will dominate the mechanical behavior. A thin, smooth coating will serve as a clean, impermeable interface on which to build high performance thin film electronics. Some of the main requirements of the planarization coating are listed in Table 2. In this paper, we report the development of a new proprietary UV curable material (4Mp) that can be coated using a 13” wide gravure coater. The right SEM image in Figure 1 shows that the surface of 4Mp is very smooth and does not replicate defects on the surface of the polyimide. The PECVD deposited thin film stack on the planarized polyimide is very smooth whereas the stack on the non-planarized polyimide conforms to defects on the surface.

Figure 1. Polyimide planarization coating

Planarization coating 

50 um Polyimide substrate

Particle contamination (dust) Scratch or defect

Fillers embedded in substrate

Belt mark

3‐5 um

Uncoated Polyimide Coated Polyimide

2 um 2 um

2 um

Thin film stack (with planarization)Thin film stack (without planarization)

2 um

Table 2. Planarization coating requirements

CH

EM

ICA

L

• Fast UV curing (<0.5 sec) • No oxygen inhibition during UV curing • Low shrinkage during polymerization • No oligomer migration • High resistance to solvents, acids and bases • Low swelling in water • No outgassing during PECVD thin film deposition • Low trace elements content

SU

RF

AC

E

CH

EM

IST

RY

• Planar with low surface roughness • Strong adhesion to polyimide • Stable interface during wet etching of metals • Low stiction to backside

ME

CH

AN

ICA

L

• Flexible, rollable, foldable • High softening temperature • High fracture toughness • High abrasion and scratch resistance

HP and Phicot have developed a process for R2R manufacturing of active matrix backplanes using Self-Aligned Imprint Lithography (SAIL).3-5 We start with a polyimide web on which a stack of uniform layers of materials necessary for fabricating thin film transistors is R2R PECVD deposited before any of the patterning steps. The multiple patterns required to create the backplane are encoded in the different heights of a 3D masking structure that is molded on top of the thin film stack once before any of the etching steps. By alternately etching the masking structure and the thin film stack the multiple patterns required for the backplane are transferred to the device layers. Because the mask distorts with the substrate perfect alignment is maintained regardless of process induced distortion. Imprint lithography is ideally suited for R2R implementation because of its high resolution, compatibility with flexible substrates, high throughput and ability to reproduce complex 3-D structures. The high level process flow for SAIL is shown in Figure 2.

Figure 2. Sequential flow of SAIL, where the one step imprinting process separates film deposition and etching modules

2. PLANARIZATION COATING REQUIRMENTS AND FORMULATION

The effects of materials selection on some of the main properties of the planarization coating are described below: 2.1. Shrinkage

It is important to have a low shrinkage formulation to prevent curling of the polyimide substrate that can introduce stresses and curvature to the finished active matrix backplanes. Therefore, the polyimide coated with a planarization layer of <5 microns should be flat. Shrinkage can be reduced by selecting oligomers with high equivalent weight. The oligomer also needs to have high chemical resistance, high dry etch resistance and good adhesion to polyimide. Shrinkage was evaluated by the curvature of spin coated films of different thicknesses on 4 inch diameter polyimide samples. The curvature of the free standing sample was evaluated after UV curing and after baking at 250°C for 1 hr in partial vacuum. Figure 3(a) shows curling of the polyimide substrate as a function of 4Mp thickness of a formulation with high shrinkage. Figure 3(b) shows coating curvature of modified 4Mp formulation with a high equivalent weight oligomer.

(a) High shrinkage (b) Low shrinkage

Figure 3. Effect of planarization coating shrinkage and thickness on polyimide curling

2.2. Chemical compatibility and adhesion

Chemical stability of the 4Mp backbone was evaluated by exposing patterned 4Mp containing different low shrinkage oligomers on a chrome coated web, pre-coated with adhesion promoter, to the most corrosive etchant in our SAIL processing (Aluminum etchant Al12S from Cyantek at 45°C). The components in the formulation of 4Mp were adjusted until it could withstand at least 20 min in the Al etchant. It should be mentioned that our process only requires a 3 min exposure to the Al etchant but it is important to have a wide processing window. Table 3 shows observations from optical microscopy of the integrity of 3 different low shrinkage oligomers when exposed to Al etchant for different periods of time until failure by detach or delamination occurred. Oligomers A and B had very low stability. Oligomer C had great stability and was chosen as one of the components in 4Mp.

Table 3. Stability of planarization coating in aluminum etchant Al12S

3.3 um

5.3 um

6.5 um

1.8 um

Adhesion of 4Mp to polyimide was evaluated in accordance with the ASTM D3359 cross-cut/tape test based on the amount of 4Mp removed from the grid area by mechanical peel-off with four different tapes: (i) acrylic adhesive (Scotch Magic tape), (ii) super strong hot melt rubber resin adhesive (3M Premium Heavy Duty Packaging Tape 3750), (iii) silicone adhesive (HISCO 2345) and (iv) thermosetting rubber (Intertape LA26, ASTM).The tape was applied on the surface with a 2 kg roller and peeled gently in a continuous way. The surface was inspected with a magnifying glass. Table 4 shows adhesion cross-cut results based on a 0 to 5 scale; where 5 indicates excellent adhesion and 0 specifies full delamination. Adhesion experiments showed problems when 4Mp was coated directly on the as-received polyimide but had excellent adhesion when coated on polyimide with a proprietary surface treatment. Post-baking at high temperature enhanced adhesion which is a process required prior to any thin film deposition by PECVD.

Table 4. Dry adhesion of planarization coating to untreated and treated polyimide

2.3. Thermal stability

High quality device films may require to be deposited at temperatures above 250°C. The current formulation of 4Mp starts degrading at 250°C with major decomposition at 425°C; therefore, thermal stability of this coating has been enhanced by adding a compatible proprietary oligomer with high temperature ceiling. Thermal stability of cured 4Mp with different amounts of proprietary oligomer was determined by Thermogravimetric analysis (TGA). The cured samples were heated from room temperature to 650°C at 10°C/min in an Argon environment; followed by heating in air up to 900°C. The left image in Figure 4 shows that the onset degradation temperature shifted to higher temperatures as the amount of proprietary oligomer was increased in 4Mp. The right image in Figure 4 shows extracted weight loss data from the TGA curves on the left as a function of the amount of proprietary oligomer at 250, 300, 325 and 350°C. The amount of material lost at 250°C corresponds to outgassing of the photoinitiators which are not required in the cured film. The effect of the proprietary oligomer on enhancing thermal stability can clearly be seen at temperatures above 300°C. The amount of the required oligomer will be selected depending on thermal requirements for thin film transistor threshold voltage stability.

250 300 350 400 450 5000

20

40

60

80

100

%w

t c

ha

ng

e

Temperature [°C]

% wt Proprietary oligomer in 4Mp 0% 9.4% 17.4% 25.3% 31.1% 39.5% 50.4% 100% (uncured)

0 10 20 30 40 50 600

1

2

3

4

5

6

350°C

325°C

300°C

250°C

%w

t lo

ss

%Proprietary oligomer in 4Mp

Figure 4. Thermal stability enhancement of 4Mp

3. THIN FILM DEPOSITION AND ARRAY FABRICATION

Metals were put down on the planarized polyimide using a roll-to-roll multiple sputtering coater and the Silicon thin films were deposited using a custom made roll-to-roll PECVD drum coater. Figure 5(a) shows an SEM cross section of the full thin film stack on top of the planarization coating showing that the surface of the stack is very smooth, the planarization coating survived all the high temperature processes, and no delamination was observed on the coating/polyimide and coating/thin film stack interfaces. The adhesion of the thin film stack to planarized and non-planarized polyimide was measured using a pull-off tester that measures the amount of force required to separate the TFT stack from the web material. This test follows the standard procedure described in ASTM 4541. The test determines the greatest perpendicular force (in tension) that a surface area can bear before a plug of material is detached. The failure point for the thin film stack deposited on non-planarized and planarized polyimide was 2.1 and 2.2 MPa, respectively. In both cases failure occurred in the SiNx/a-Si interface of the TFT stack. These results indicate that the planarization coating does not affect adhesion of the thin film stack to the coated polyimide. A higher magnification cross-section of the stack on planarized polyimide was obtained by TEM and is shown in Figure 5(b). The thin film stack lays flat on the planarization coating.

(a) SEM

(b) TEM

Figure 5. SEM and TEM cross-sections of a-Si TFT stack deposited onto 4Mp

SAIL process compatibility of the planarized sample with the full TFT stack was carried out by processing it through the entire roll-to-roll wet and dry etch processes. No issues were found during any of the R2R processing steps. The left image in Figure 6(a) shows a finished active matrix backplane pixels with the standard R2R procedure, and the one on the right is an image of the curvature of finished 120 x 160 TFT arrays for samples with and without planarization coating. The sample with the planarization coating was very flat, whereas the sample without a planarization coating had an upward curvature from residual stresses on the thin film stack. Removal of this curvature is beneficial for processing.

(a) (b)

Figure 6. R2R processed array with standard R2R processes

Electrical testing of the finished arrays on planarized substrate showed that these samples had a higher percentage of open gate lines as compared to samples without a planarization coating. One of the arrays was fully inspected under optical microscope to determine root cause of these breaks. Figure 7 shows examples of these breaks after processing which verified by removing the top metal where broken bottom metal lines (aluminum) can easily be observed through the translucent Si stack as blue regions. The main defects that caused gate line breaks were associated with particles. We are working on understanding and reducing the source of these particles.

Figure 7. Particle defects that break gate lines

4. SHUNT MEASUREMENTS

4.1. Capacitor shunt density measurement

Shunt density measurements were performed on planarized (run 5099) and non-planarized (run 5093) samples with standard TFT stack deposited on them. The sample preparation for the shunt density measurements begins by cutting a 100 mm square sample from the web and mounting it to a 6” Si wafer. The top Cr layer is then removed using a commercial ceric ammonium nitrate based etchant, and a shadow mask was used to redeposit an array of 1 mm circular

chrome dots on the n+ microcrystalline layer of the TFT stack. The Cr dots were then used as an etch mask and the stack between the dots was etched down to the dielectric layer using a fluorine based plasma etch. Following sample preparation, the devices were subjected to electrical breakdown tests using an HP 4155C parameter analyzer and a Signatone semi-automatic wafer prober. Three arrays of 64 devices each were tested from each run using a 0V to -100V sweep with a 10 μA current compliance. Figure 8 shows typical data from both runs. Virtually all of the devices on the non-planarized sample reached the current compliance of 10 μA with less than 10V of applied voltage indicating that there was at least one shunt in each 0.75 mm2 area. The planarized run displayed very different behavior. Only about 30% of the devices reached current compliance during the test, and those devices broke down at voltages between 10 and 50V as opposed to less than 10V in the other runs. However, many other devices in the planarized run broke down but only passed around 2 μA of current. Clearly the planarization layer has had a positive impact on reducing both the density and severity of shunts.

. Figure 8. Current vs. applied voltage for planarized with 4Mp (5099) and non-planarized (5093) samples

4.2. SEM contrast characterization

The direct electrical characterization method to determine shunt paths between TFT stack layers used in the previous section has several drawbacks: (i) sample area must be large, typically 1mm dots for ease of probe contact; (ii) sample must be processed to remove top metal and deposit isolated test pads; (iii) limited number of sample areas in each specimen; (iv) no correlation to stack defects is possible and (v) data requires interpretation of I-V curves.

An alternative method which addresses some of the issues listed above has been developed. It relies on the change in contrast observed in relation to changing surface voltage when materials are inspected in a scanning electron microscope.7 The secondary electrons produced by the probe beam are most commonly used to derive a video signal since there is contrast between different materials. The secondary electron yield from a given surface is also a function of its electric potential. Additionally, the electron beam has the ability to impart charge to insulators or isolated structures, providing the means to apply voltage without the requirement to make physical contact. Making use of these properties, it is possible to infer the presence or absence of electrical leakage paths in supposedly isolated structures by visual comparison of their grey scale appearance after exposure to certain electron beam conditions (see Figure 9). In the figure, two small islands of thin film material are shown, with a common ground connection via the bottom metal layer. In the good stack, the top metal is isolated by the dielectric, and charges under the electron beam of the SEM. This charging increases the number of secondary electrons liberated from the surface, and the appearance of the island brightens until equilibrium between beam current and secondary emission is reached. In the second island, a shunt provides a path for direct current between the top and bottom metal. In this case no charging can occur, and thus no change in brightness is observed.

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0-12

-10

-8

-6

-4

-2

0

2 x 10-5 I1X 10 -6

Cur

rent

[A]

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0-12

-10

-8

-6

-4

-2

0

2 x 10-5 I1X 10 -6

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -12

-10

-8

-6

-4

-2

0

2x 10

-5 I1

X 10 -6

Voltage [V]

Figure 9. Illustration of the mechanism by which an electrical shunt path derives contrast

Application of these principles to the examination of thin film metal/insulator/semiconductor stacks used to build TFT structures requires many multiples of small isolated structures (islands) in which the top metal and lower semiconductor layers are subdivided to create isolated capacitor structures having a common ground plane. This yields many sample “islands” which can be inspected readily for differences in contrast. In the Full SAIL layout, this is possible using some of the incidental “fill” patterning in certain areas of the display panel. These are expressed as squares of approximately 20 m which extend for relatively large areas, thus providing a very large potential sample size for measurements. Imprinted and etched material harvested at the appropriate stage of processing yields the desired structure of capacitive islands all sharing a common lower (ground) electrode. In use, small specimens are mounted to an SEM stub, and a predetermined sample area is exposed to standardized beam conditions to impart a charge dose. The region is then inspected, and islands with a dark appearance, assumed to contain a shunt or leakage path, are counted. Since the sample areas are small and easily viewed at high magnification in situ, it is possible to inspect individual islands to reveal features that might be correlated to the presence of shunt paths. Figure 10 shows micrographs that give a typical view from web materials with high and low instances of dielectric shunts as determined independently via conventional electrical methods. The high incidence of squares with dark contrast in the left image indicates the great density of shunt defects, while in the right image the region under interrogation shows uniform charging of the capacitive islands and good dielectric isolation in between TFT stack layers.

Figure 10, High (left) and low (right) shunt incidence

Closer inspection of shunted islands will often reveal a feature or defect that could be associated with the anomalous electrical performance. An example of this is presented in Figure 11. The shunted square shown in this figure has an anomalous “nodule” defect within the stack. Similar defects have been associated with breaches in the dielectric via other means.

Figure 11. Close up micrograph of a sample square containing a shunt

This method has been adopted as one of 3 techniques used to assess the properties of TFT stack material. In general, while none gives a definitive picture in isolation, there is broad agreement between the methods. Typically several areas containing approximately 1400 capacitive islands are viewed, and the incidence of shunts (as indicated by dark contrast) is counted to yield an estimate of shunt defects per square millimeter. Several runs of recent web material have been assessed in this manner, and the results are presented in Figure 12. The lowest shunt density has been found on thicker dielectric (5107B) and planarized (5113) runs.

Figure 12. Tracking shunt incidence across material batches

5. CONCLUSIONS

Significant progress has been made in understanding the requirements of a planarization coating and developing a compatible UV curable formulation with all SAIL processes. Reduction of particles and defects in the incoming polyimide and during thin film deposition are key to successfully eliminate shunts in our dielectric. Clearly the planarization coating has had a positive impact on reducing both the density and severity of shunts. It is hoped that further improvements will be made as the application process for the planarization material is developed.

6. ACKNOWLEDGEMENTS

We would like to thank the Army Research Lab for helping to support this work under grant number W911NF-08-2-0063.

Shunt incidence in different web batches measured by SEM

0

10

20

30

40

50

60

70

5114

5113

5107

C

5107

B51

0551

0251

0150

88

Inc

ide

nc

e /

mm

2

REFERENCES

1. W. A. MacDonald, M. K. Looney, D. MacKerron, R. Eveson, R. Adam, K. Hashimoto and K. Rakos, J. SID, 2007, 15/12, 1075 2. W. A. MacDonald, M. K. Looney, D. MacKerron, R. Eveson and K. Rakos, Plastics, Rubber and Composites, 2008, 37 (2/3/4), 41 3. A. Jeans, M. Almanza-Workman, R. Cobene, R. Elder, R. Garcia, R. F. Gomez-Pancorbo, W. Jackson, M. Jam, H.-J. Him, O. Kwon, H.

Luo, J. Maltabes, P. Mei, C. Perlov, M. Smith and C. Taussig, Proc. SPIE, 2010, 7637, 763719. 4. H.-J. Kim, M. Almanza-Workman, B. Garcia, O. Kwon, F. Jeffrey, S. Braymen, J. Hauschildt, K. Junge, D. Larson, D. Stieler, A. Chaiken,

B. Cobene, R. Elder, W. Jackson, M. Jam, A. Jeans, H. Luo, P. Mei, C. Perlov and C. Taussig, J. Soc. Inf. Disp., 2009, 17(11), 963. 5. W. B. Jackson, M. Almanza-Workman, A. Chaiken, R. Garcia, A. Jeans, H.-J. Kim, O. Kwon, H. Luo, P. Mei, C. Perlov, C. Taussig, M. S.

Shur and A. Koudymov, ECS Trans., 2007, 8(1), 199. 6. M.-C. Cheon, Y. Kim and C.-S. Ha, Prog. Polym. Sci. , 2008, 33, 581 7. M. Matsui, T. Odaka, H. Nagashi and K. Sakurai, J. Micro/Nanolith, MEMS and MOEMS, 2010, 9, 041304