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OverviewSynopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance and power of multicore systems and next-generation SoC architectures.

Platform Architect enables system designers to explore and optimize the hardware-software partitioning and the configuration of the SoC infrastructure, specifically the global interconnect and memory subsystem, to achieve the right system performance, power and cost.

Its efficient turnaround time, powerful analysis views, and available IP models make Platform Architect the premier choice for system-level analysis and optimization of Arm AMBA®-based SoCs.

Workload and Platform Authoring

Performance and Power Analysis/Optimization

Figure 1: Graphical platform assembly, configuration, performance and power analysis, and optimization of AMBA-based SoC designs in Synopsys Platform Architect

Architecture analysis and optimization for performance and power

Platform Architect

Platform Architect is a production- proven solution used by leading systems OEMs and semiconductor companies worldwide.

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Highlights• Address the architecture challenges of Artificial Intelligence (AI)-enabled SoCs and multi-chip systems

• Hardware-software partitioning and optimization of multicore systems

• SoC interconnect and memory subsystem performance and power optimization

• Efficient exploration using traffic generation and cycle-accurate TLM interconnect models

• Unified view of activity, performance and power for root-cause analysis

• Parameter sweeping and sensitivity analysis

• Hardware-software validation using cycle-accurate TLM processor models

• Compliant with IEEE 1666-2011 SystemC and TLM-2.0 as well as IEEE 1804 UPF 3.0 for system level power analysis

Problem: Predicting System Performance and Power Predicting the dynamic system performance and power of today’s multi-function, multi-application SoCs requires simulation. This impacts both system OEMs and semiconductor companies, and creates an opportunity for information sharing and collaboration within the supply chain.

Challenges with Traditional Methods

Discovering problems with system performance and power consumption late in the development cycle can be catastrophic to project schedules and product competitiveness, causing failure in the market. Accurate architecture analysis must be done earlier in the design cycle:

• While spreadsheets are good for aggregating data, static spreadsheet calculations are not accurate enough to estimate performance and power and make design decisions. Dynamic simulation is needed.

• Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition, the RTL may simply not be available

• Risks include over-design, under-design, cost increases, schedule delays, and re-spins

Solution: Dynamic System-Level Architecture Simulation and AnalysisSynopsys Platform Architect provides system designers with the dynamic transaction-level simulation of performance and power, rapid turnaround time, and powerful system-level visibility they need to greatly improve the analysis and decision-making process.

Address the Architecture Challenges of AI SoCs and Multi-Chip Systems

Easily map AI workloads to different SoC architectures to resolve AI power and performance design challenges with Platform Architect. Quickly address challenges of evolving algorithms, highly parallel compute and high memory requirements, with

• A library of configurable AI operators for modeling Convolutional Neural Networks (CNNs)

• Automated import of workloads from AI frameworks via prototxt and ONNX

• An example NVDLA performance model to rapidly represent custom AI accelerators

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AI Operator library NVDLA performance model exampleCNN workload model Analysis results

Figure 2: AI Exploration Pack for performance analysis of AI accelerators

Hardware-Software Partitioning and Optimization of Multicore Systems Platform Architect enables architects to create task-based workload models of the end-product application for early architecture analysis.

Product trends requiring analysis

� Dynamic workloads generated by multiple initiators and software stacks

� Highest processing and memory bandwidth requirements by AI applications

� Complex interconnect topologies with hierarchical arbitration and advanced QoS capabilities

� Complex memory hierarchies with caches, on-chip SRAM, off-chip DDR

Results with Platform Architect

� Quantitative analysis results on Key Performance Indicators like effective operations per second, frame-rate, etc.

� Fast turn-around time for architectural 'what-if' experiments

� Measurable improvement in product performance and power

� Reduced schedule risk vs. traditional RTL-based methods

Figure 3: SoC performance analysis challenges and the benefits of using system-level methods for performance and power analysis in Synopsys Platform Architect

Generic task models are easily configured to create a SystemC performance model of the application, called a task-graph.

• Using a task-graph, the performance workload of parallel application tasks are mapped onto Virtual Processing Unit (VPU) task-driven traffic generators

• Simulation and task analysis enables hardware/software partitioning to be optimized for best system performance and power well before the application software is available

• Task graphs also model the traffic generated by the initiators enabling performance optimization of the interconnect and memory subsystem

• Platform Architect includes a Task Graph Generator (TGG) tool that generates application task graphs from sofware execution traces, like VDK software analysis, Linux ftrace, Android atrace, or QNX kernel trace. The TGG can be customized to generate task graphs from custom software trace formats.

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Task Trace

Resource Utilization

Power Consumption

Interconnect Throughput

Figure 4: Application task analysis for early optimization of multicore systems

Interconnect and Memory Subsystem Performance Optimization Using Synthetic and Trace-Driven Traffic Generation Platform Architect focuses on architecture design challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem:

• Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance and power before software is available

• Simulation sweeping enables analysis data to be collected parametrically, exploring all traffic scenarios against a wide range of architecture configurations

• Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable identification of performance and power bottlenecks, determine their root-cause, and examine the sensitivity that system performance may have to individual or combined parameter settings

The result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support the latency, bandwidth, and power requirements of all relevant SoC components, under all operating conditions.

Hardware/Software Performance Validation Using Processor Models and Critical SoftwareAfter exploration, the model of the candidate architecture can be refined to replace the task-based workload model with cycle- accurate processor models. This enables architects to validate the architecture candidate using the available performance critical software.

Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure performance and power, and to confirm goals are met.

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Software Function Trace

Neural Network Graph Trace

Address Trace

AI Accelerator Utilization

DDR Utilization

Interconnect Throughput

Figure 5: Software-driven performance analysis of AI accelerators, based on DesignWare Embedded Vision Subsystem

Complete IEEE 1666-2011 SystemC TLM-2.0 Standards-Based EnvironmentSynopsys Platform Architect is a SystemC-based environment fully compatible with the IEEE 1666-2011 SystemC and TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction, including:

• Standards-based SystemC transaction-level models using IEEE 1666-2011 TLM-2.0 and Accellera Systems Initiative (ASI) TLM industry standards, and the open Synopsys SystemC Modeling Library (SCML) API library for highly reusable TLM-2.0 based peripheral modeling

• Support for the IEEE 1804 UPF standard for the creation of system level power models. These can be connected to the TLM performance models to analyze the system-level power consumption based on dynamic activity.

• Mixed SystemC/HDL co-simulation with Synopsys VCS and other third-party HDL simulation environments enabling reuse of RTL memory controllers and other IP components

• An Eclipse-based Integrated Development Environment for development and integration of SystemC based models, including a TLM Creation perspective for development and testing of SCML-based peripheral models and custom task models, as well as a TLM Debug perspective for SystemC aware source code debugging, tracing and analysis

Getting Started with Available Architecture IP ModelsPlatform Architect supports the broadest commercially available portfolio of pre-instrumented SystemC TLM IP models for architecture exploration and validation.

Task-based and Software-based Workload Modeling

• Generic Virtual Processing Units (VPUs) for application task-mapping with synthetic and trace-based traffic generation

• Cycle-accurate SystemC-based TLM Arm Cycle Models, ARC nSim/nCam and xCAM models, Tensilica and MIPS processor families, and HDL co-simulation with user-provided RTL for other processor families

• Accurate performance models of the DesignWare Embedded Vision (EV) subsystem, including nSim/nCAM model of the ARC Vector processor and the Fast Performance Model (FPM) of the Deep Neural Network (DNN) accelerator

Interconnect Models

• Generic, fast, approximately-timed SystemC TLM models for AMBA-based coherent and non-coherent interconnect and network-on-chip

• Integration of architecture models for the Arteris FlexNoC™ Network on Chip (NoC) interconnect

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• Cycle-accurate SystemC TLM bus libraries for Arm CoreLink™ Network Interconnect and Synopsys DesignWare IP AXI interconnect

• Integration of Arm Cycle Models for implementation accurate interconnect models of Arm coherent and non-coherent interconnects

• Flow for integration of 3rd-party interconnect models for full configurability in Platform Architect

• Generic configurable models of chip-to-chip protocols for PCIe and Ethernet

Memory Controller Models

• Accurate SystemC TLM performance models of Synopsys DesignWare DDR memory controllers, including the DDR5/4 controller, the DDR5/4/4X controller and the enhanced Universal DDR Memory Controller (uMCTL2)

• Generic approximately-timed SystemC TLM multi-port memory subsystem models for Arm AXI and CHI protocols

• Cycle-accurate memory subsystem models through HDL co-simulation with user-provided, third-party, and Synopsys RTL memory controller IP

Processor Models

• Cycle-accurate SystemC TLM processor support packages (PSPs) for Tensilica and MIPS processor families, and through HDL co-simulation with user-provided RTL for Arm processor families

CoStart Enablement Services Synopsys CoStart is a packaged service that shortens the ramp-up cycle for architecture design methodologies so that users become productive in the shortest time.

The Synopsys CoStart program contains an intense knowledge transfer, while assisting in architecture study project planning, use case traffic capture, architecture model creation, simulation, and analysis of results:

• Tool, IP model, and methodology training that ensures end-user value at each step, accelerating results

• Modeling services for the development and integration of custom interconnect and memory subsystem models, minimizing the modeling effort to get started and achieve initial value

• Expert consulting and support to maximize ROI through exploration (not just checking)

About Synopsys Virtual Prototyping SolutionsPlatform Architect is part of Synopsys’ comprehensive Virtual Prototyping solution offering that:

• Provides the broadest portfolio of system-level IP models from a single supplier

• Accelerates the creation and optimization of common SoC blocks

• Facilitates SoC architecture exploration and optimization

• Provides the most complete prototyping solutions to accelerate embedded software development and system validation

• Includes comprehensive training materials and examples

• Enables value throughout the semiconductor supply chain

For more information on Platform Architect visit: synopsys.com/platformarchitect