Processor Organization

8/2/2019 Processor Organization

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CPU With Systems Bus


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CPU Internal Structure


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Registers

CPU must have some working space (temporarystorage) Called registers

Number and function vary between processordesigns

One of the major design decisions Top level of memory hierarchy


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User Visible Registers

General Purpose

Data

Address

Condition Codes


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General Purpose Registers

Can be assigned to variety of functions

Can contain the operand for any opcode, However there are

restriction.

ex: There may be dedicated registers for floating - -

point and stack operations

Can be used for addressing functions such as register indirect ,Displacement


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Data Registers

Can hold data and cannot used for calculation purpose.

Address Registers

may be devoted to a particular addressing modeSegment registers holds the address of the basesegment. There may be multiple registers

ex: one for the operating system and one for the

process

Index Registers used for indexed addressing

Stack pointer : That point to the top of the stack


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Condition codes - Flags

Conditions codes are bits set by the processor hardware

as the result of operation.ex : Arithmetic operation may produce negative,

Zero or overflow results


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Control & Status Registers

Program Counter Contains the address of aninstruction to be executed.

Instruction Register : Contain the instruction

most recently fetched

Memory Address Register : Contain the address

of a location in main memory

Memory Buffer Register : Contains a word ofdata to be written or the most recently used


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Program Status Word

Many processors designs include a register or set of

registers, often known as the PSW

The PSW typically contains condition codes plus otherstatus information

Common field or flags contain the following Sign : sign bit of the last arithmetic operation

Zero : Set when the result is 0

Carry : Set if an operation resulted in a carry

Equal : Set if a logical compare result is equality Overflow :Used to indicate arithmetic overflow

Interrupt enable/disable : Used to enable or disable interrupts

Supervisor : Indicates whether the processor is executing in

supervisor or user mode


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Other Registers

May have registers pointing to:

Process control blocks (see O/S)

Interrupt Vectors (see O/S)

N.B. CPU design and operating system designare closely linked


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Example Register Organizations


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Instruction Cycle

Revision

Stallings Chapter 3


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Indirect Cycle

May require memory access to fetch operands

Indirect addressing requires more memoryaccesses

Can be thought of as additional instruction

subcycle


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Instruction Cycle with Indirect


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Instruction Cycle State Diagram


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Data Flow (Instruction Fetch)

Depends on CPU design

In general:

Fetch

PC contains address of next instruction

Address moved to MAR

Address placed on address bus

Control unit requests memory read

Result placed on data bus, copied to MBR, then to IR

Meanwhile PC incremented by 1


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Data Flow (Fetch Diagram)


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Data Flow (Indirect Diagram)


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Data Flow (Execute)

May take many forms

Depends on instruction being executed

May include

Memory read/write

Input/OutputRegister transfers

ALU operations


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Data Flow (Interrupt)

Simple

Predictable

Current PC saved to allow resumption afterinterrupt

Contents of PC copied to MBR Special memory location (e.g. stack pointer)

loaded to MAR

MBR written to memory

PC loaded with address of interrupt handlingroutine

Next instruction (first of interrupt handler) canbe fetched


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Data Flow (Interrupt Diagram)


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Prefetch

Fetch accessing main memory

Execution usually does not access main memory

Can fetch next instruction during execution ofcurrent instruction

Called instruction prefetch


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Improved Performance

But not doubled:

Fetch usually shorter than execution

Prefetch more than one instruction?

Any jump or branch means that prefetchedinstructions are not the required instructions

Add more stages to improve performance


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Pipelining

Fetch instruction

Decode instruction

Calculate operands (i.e. EAs)

Fetch operands

Execute instructions

Write result

Overlap these operations


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Two Stage Instruction Pipeline

Ti i Di f


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Timing Diagram for

Instruction Pipeline Operation

Th Eff t f C diti l B h


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The Effect of a Conditional Branch on

Instruction Pipeline Operation

Six Stage


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Six Stage

Instruction Pipeline


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Alternative Pipeline Depiction

S d F t


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Speedup Factors

with Instruction

Pipelining


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Dealing with Branches

Multiple Streams

Prefetch Branch Target

Loop buffer

Branch prediction

Delayed branching


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Multiple Streams

Have two pipelines

Prefetch each branch into a separate pipeline

Use appropriate pipeline

Leads to bus & register contention

Multiple branches lead to further pipelines beingneeded


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Prefetch Branch Target

Target of branch is prefetched in addition to

instructions following branch

Keep target until branch is executed

Used by IBM 360/91


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Loop Buffer

Very fast memory

Maintained by fetch stage of pipeline

Check buffer before fetching from memory

Very good for small loops or jumps

c.f. cache

Used by CRAY-1


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Loop Buffer Diagram


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Branch Prediction (1)

Predict never taken

Assume that jump will not happen

Always fetch next instruction

68020 & VAX 11/780

VAX will not prefetch after branch if a page faultwould result (O/S v CPU design)

Predict always taken

Assume that jump will happen

Always fetch target instruction


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Predict by Opcode

Some instructions are more likely to result in a jumpthan thers

Can get up to 75% success

Taken/Not taken switchBased on previous history

Good for loops


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Delayed Branch

Do not take jump until you have to

Rearrange instructions


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Branch Prediction Flowchart


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Branch Prediction State Diagram

Dealing With


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Dealing With

Branches


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Intel 80486 Pipelining

Fetch From cache or external memory

Put in one of two 16-byte prefetch buffers

Fill buffer with new data as soon as old data consumed

Average 5 instructions fetched per load

Independent of other stages to keep buffers full

Decode stage 1 Opcode & address-mode info

At most first 3 bytes of instruction

Can direct D2 stage to get rest of instruction

Decode stage 2 Expand opcode into control signals

Computation of complex address modes

ExecuteALU operations, cache access, register update

Writeback Update registers & flags

Results sent to cache & bus interface write buffers


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80486 Instruction Pipeline Examples


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Pentium 4 Registers


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EFLAGS Register


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Control Registers


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MMX Register Mapping

MMX uses several 64 bit data types

Use 3 bit register address fields

8 registers

No MMX specific registers

Aliasing to lower 64 bits of existing floating pointregisters

Mapping of MMX Registers to


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Mapping of MMX Registers to

Floating-Point Registers


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Pentium Interrupt Processing

Interrupts

Maskable

Nonmaskable

Exceptions

Processor detectedProgrammed

Interrupt vector table

Each interrupt type assigned a number

Index to vector table

256 * 32 bit interrupt vectors

5 priority classes


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PowerPC User Visible Registers


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PowerPC Register Formats


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Foreground Reading

Processor examples

Stallings Chapter 12

Manufacturer web sites & specs

Documents

Processor Organization