PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · Avnet Electronics Marketing introduces the EXP speciﬁcation – a versatile expansion interface for FPGA development boards that allows

R

Issue 63First Quarter 2008

Xcell journalXcell journalS O L U T I O N S F O R A P R O G R A M M A B L E W O R L DS O L U T I O N S F O R A P R O G R A M M A B L E W O R L D

INSIDE

At the Heart of Consumer and Automotive Innovation

Marriage Made in Heaven?

Scalable and Flexible In-Vehicle Networking

Designing Portable HandsetsUsing CoolRunner-II CPLDs

A High-Speed Broadcast Video Connectivity Solution

INSIDE

At the Heart of Consumer and Automotive Innovation

Marriage Made in Heaven?

Scalable and Flexible In-Vehicle Networking

Designing Portable HandsetsUsing CoolRunner-II CPLDs

A High-Speed Broadcast Video Connectivity Solution

www.xilinx.com/xcell/

At the Heart of InnovationAt the Heart

of InnovationAt the Heart

of Innovation

P R O G R A M M A B L E S Y S T E M S E D I T I O N

Support Across The Board.™

Add Functionality to Your Prototype Platform

Available EXP Modules

• EXP to P160 Adapter

• EXP Prototype

• Analog Devices EXP Adapter Module

• Video EXP Module

• High-Speed ADC EXP Module

• High-Speed DAC EXP Module

• Interface EXP Module

EXP Baseboards

• Xilinx Spartan-3A DSP Starter Kit

• Xilinx Spartan-3 PCI Express Starter Kit

• Xilinx Virtex-4 FX60 PCI Express Board

• Xilinx Virtex-5 LX Development Kit

• Xilinx Virtex-5 LXT PCI Express Board

• Xilinx Virtex-5 SXT PCI Express Board

Avnet Electronics Marketing introduces the EXP specification –

a versatile expansion interface for FPGA development boards

that allows designers to add application specific daughter

cards and easily connect to FPGA I/Os.

Key EXP Features

• Royalty free, public domain specification

• Full and half card options

• 168 (full module) and 84 (half module) user I/O

• Single-ended and differential pair signaling

• High-performance: > 100 MHz single-ended and

> 300 MHz differential

Learn more about EXP at www.em.avnet.com/exp

Enabling success from the center of technology™

800-332-8638www.em.avnet.com

© Avnet, Inc. 2007. Al l r ights reserved. AVNET is a registered trademark of Avnet, Inc.Al l other brand or product names are trademarks of their respect ive owners.

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©2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

www.xilinx.com/processor

At the Heart of Innovation

Get the Complete Embedded Solution

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O

L E T T E R F R O M T H E P U B L I S H E R

Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3400Phone: 408-559-7778FAX: 408-879-4780www.xilinx.com/xcell/

© 2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands includedherein are trademarks of Xilinx, Inc. All other trade-marks are the property of their respective owners.

The articles, information, and other materials includedin this issue are provided solely for the convenience ofour readers. Xilinx makes no warranties, express,implied, statutory, or otherwise, and accepts no liabilitywith respect to any such articles, information, or othermaterials or their use, and any use thereof is solely atthe risk of the user. Any person or entity using suchinformation in any way releases and waives any claim itmight have against Xilinx for any loss, damage, orexpense caused thereby.

Forrest CouchPublisher

PUBLISHER Forrest [email protected]

EDITOR Charmaine Cooper Hussain

ART DIRECTOR Scott Blair

DESIGN/PRODUCTION Teie, Gelwicks & Associates1-800-493-5551

ADVERTISING SALES Dan [email protected]

TECHNICAL COORDINATORS Kevin KitagawaKevin TanakaTamara SnowdenSilvia Gianelli

INTERNATIONAL Piera Or, Asia [email protected]

Christelle Moraga, Europe/Middle East/[email protected]

Yumi Homura, [email protected]

SUBSCRIPTIONS All Inquirieswww.xcellpublications.com

REPRINT ORDERS 1-800-493-5551

Xcell journal


Behind the WheelOne of the benefits of growing older is that you gain perspective. You have a longer time span fromwhich to observe change and gauge its relative positive and negative consequences.

For example, I can remember that myparents’ new car came luxuriouslyequipped with an AM radio that hadchrome metal push-button tuning,electric windows, a driver’s-side powerseat that went forward and back, and areally cool telescoping radio antennathat magically raised and lowered intothe fender like some kind of futuristicspace vehicle.

Cars back then were basically heavy electro-mechanical devices with a lot of chrome.

Now fast-forward through a myriad of technologies ranging from personal computers, wirelessnetworks, flat-panel displays, mobile phones, global positioning systems, and the Internet, andwe arrive at today’s automobile – a highly sophisticated, computerized transportation system.

What a trip!

The Xilinx® Automotive (XA) product family is ideal for many advanced automotive electronicsmodules and systems, ranging from the latest driver assistance and infotainment systems toreconfigurable instrument clusters and electronic control unit gateways. Essentially, we helpmake the automobile environment more entertaining, informative, and productive.

Xilinx is also responding to rapidly changing consumer product requirements in the low-cost,high-volume markets with domain-optimized PLDs, custom IP, and development boards, creatingsolutions for two key consumer product segments: displays and handsets.

Today we are witnessing a convergence of high technologies that are changing forever the waywe communicate and do business with each other. Limited only by our imagination, there seemsno end in sight.

O N T H E C O V E R

2525

A U T O M O T I V E

4040

P O R T A B L E H A N D S E T S

1515

A U T O M O T I V E

Marriage Made in Heaven?Creating standard automotive platforms with maximum differentiation.

5353A U D I O / V I D E O

A High-Speed Broadcast Video Connectivity SolutionXilinx Spartan-3E and Spartan-3A FPGAs, National Semiconductor PHY,and the Xilinx protocol stack provide a cost-effective and flexibleapproach to the challenges of multi-rate broadcast.

Scalable and Flexible In-Vehicle NetworkingFPGAs and full IP solutions give automotive engineers options in optimizing their electrical architectures.

Designing Portable HandsetsUsing CoolRunner-II CPLDs CPLDs can improve processor-based handsets.

At the Heart of Consumer and Automotive Innovation Xilinx offers silicon, development tools, IP, middleware, and design services for the automotive electronics market while meeting the industry’s temperature, quality, and reliability requirements.

1212 Cover

F I R S T Q U A R T E R 2 0 0 8 , I S S U E 6 3 Xcell journalXcell journal

VIEWPOINTSLetter from the Publisher: Behind the Wheel ........................................................................5

Wim Roelandts: Looking Ahead in 2008.............................................................................8

Kevin Morris: Short Stack with Syrup................................................................................10

Ivo Bolsens: Enabling Efficient Packet Processing................................................................66

FEATURES

CoverAt the Heart of Consumer and Automotive Innovation .........................................................12

AutomotiveMarriage Made in Heaven?.............................................................................................15

Block Matching for Automotive Applications on Spartan-3A DSP Devices ................................16

A Compact Multimedia Display Development Platform for Automotive and Industrial Markets .........20

Scalable and Flexible In-Vehicle Networking.......................................................................25

Portable HandsetsDesigning GPS Systems Using CoolRunner-II CPLDs .............................................................29

Decrease Processor Power Consumption Using a CPLD.........................................................32

Supporting Multiple SD Devices with CPLDs .......................................................................37

Designing Portable Handsets Using CoolRunner-II CPLDs ......................................................40

Easing Design Challenges with CoolRunner-II CPLDs ............................................................43

Audio / VideoDesigning Digital Displays with Spartan-3 Generation FPGAs ................................................46

Taking Device DNA Technology to the Next Level ................................................................49

A High-Speed Broadcast Video Connectivity Solution ...........................................................53

RESOURCESTechnical Papers and Literature ........................................................................................58

Automotive ECU Development Kit .....................................................................................59

Spartan-3AN FPGA Starter Kit ..........................................................................................60

CoolRunner-II CPLD Starter Kit..........................................................................................61

Protect Your Brand with Spartan-3 Generation FPGAs ..........................................................62

Titanium Dedicated Engineering .......................................................................................63

WEB XCLUSIVESThese articles are available at: www.xilinx.com/publications/xcellonline/xcell_63/

Implementing Industrial Ethernet....................................................................................Web

Designing Efficient, Synchronized, and Reliable Motion Networks .......................................Web

Speeding Up Control Automation with EtherCAT................................................................Web

by Wim RoelandtsCEO and Chairman of the BoardXilinx, Inc.

Last year was yet another successful year forXilinx, with record sales of our 90-nm and65-nm devices in consumer and communi-cations applications. Nowhere was thisgrowth more evident than Asia, where rev-enues increased nearly 500 percent.* Ourcustomer base continues to expandthroughout Asia as more and more design-ers adopt Xilinx solutions to meet technicaland time-to-market demands.

The year 2007 also brought the largestsingle order in our history: 8 millionunits for a single socket. As the million-unit orders continue, we envision a timewhere anyone who does logic design willconsider Xilinx. We are perhaps halfwaythere. Industry analysts project furthergrowth for PLDs as new requirementsthroughout the electronics industry forcethe need for flexible architectures that cancope with not only current applicationsbut future and possibly unknown fea-tures. As systems continue to increase incomplexity, designers will naturally makethe transition to a programmable fabric.

8 Xcell Journal First Quarter 2008

Looking Ahead in 2008Looking Ahead in 2008Xilinx is poised for growth in high-volume consumer applications.Xilinx is poised for growth in high-volume consumer applications.

Viewfrom the top

Looking AheadIf economic conditions remain favorable,we anticipate yet another year of growth in2008, particularly in consumer, surveil-lance, automotive, and communicationsapplications. The flat-panel display marketis one of the fastest growing segments inthe electronics industry, thanks to declin-ing prices and government mandates pro-moting digital programming. FPGAs areplaying a key role in enabling many of thekey technologies behind the latest displays.

In fact, our Spartan™ Generationdevices can be found in many of the lat-est flat-panel displays. This is a highgrowth market for Xilinx as panel makersexpand production capacities to meetconsumer demand. According to iSuppli,worldwide shipments of LCD and PDPTVs are expected to reach nearly 80 mil-lion units in 2009.

With the ongoing threats to globalsecurity, demand for high-performancesurveillance video products continues togrow. Today’s surveillance video systemsmust not only record – they must analyzedata in real time. This requires higherquality video and DSP processing capabil-ities, something our devices are very goodat. This is a big opportunity for Xilinx anda major reason we’ve focused on constant-ly pushing the DSP performance capabili-ties of our FPGAs.

In the automotive space, we’re seeingtremendous growth in driver assistanceapplications. Previously only available inhigh-end luxury cars, electronic driverassistance systems are making their wayinto the average vehicle. Market analystsexpect driver assistance system demand togrow by 5x between 2007 and 2012.

Mobile devices also offer an excellentopportunity for PLDs as portable elec-tronic manufacturers continue to rushnew products to market. Today’s designersare now looking beyond the fixed archi-tecture of ASICs and ASSPs to discoverthe innate design flexibility and time-to-

ality, and other functions suited to specificapplication requirements.

Xilinx will continue to expand its effortsin delivering optimized solutions for abroad set of markets and applications. Inaddition to providing just the right amountof features in our silicon, we’re workinghard to provide just the right amount of IP,design tools, and peripherals required todeliver an “out-of-the-box” solution.

*Source: Xilinx Financials, September quarter FY08 versus September quarter FY06.

market benefits of programmable logic.Rather than demanding higher perform-ance, consumers now demand ease of use –the iPhone is an excellent example. PLDsallow designers to differentiate their prod-ucts with ease-of-use features while provid-ing faster time to market.

Finally, in the communications sector, webelieve that growth will accelerate as wirelessservice providers continue their quest toupgrade the infrastructure and triple play con-tinues to be deployed. Next-generation basestation deployments must conquer the chal-lenge of continually reducing cost (as meas-ured by cost per channel) while at the sametime adding increased functionality to sup-port new services, protocols, and changingsubscriber usage patterns. Programmablelogic is the ideal solution for wireless base sta-tions, providing not only a flexible designplatform but allowing service providers tomake future upgrades from a remote location.This can literally save millions in the long run.

ConclusionXilinx pioneered the industry’s transfor-mation toward a focus on vertical marketsand engaging with customers at a systemarchitecture level. Today, this transforma-tion lets us address our customer’s com-plex design challenges by providing themwith innovative, flexible, and compellingsolutions that help them achieve theirobjectives of cost management, time tomarket, and leadership.

And while the beauty of programmablelogic is its flexibility – PLDs can be used invirtually any electronic system so there is noimmediate need to develop new products tomeet the demand of any specific “hot”application – providing just the right mix offeatures for a given application is a great wayto reduce system cost. By optimizing ourdevices for a given domain, we offer thebroadest range of solutions in the industry,providing a unique mix of core capabilities,such as logic, memory, parallel and serialI/Os, embedded processors, DSP function-

First Quarter 2008 Xcell Journal 9

On November 14, 2007, the board of direc-tors of the Semiconductor IndustryAssociation (SIA) elected Willem ("Wim") P.Roelandts, chairman, president and CEO ofXilinx, as its 2008 board chairman.Roelandts succeeds Richard Templeton, pres-ident and chief executive officer of TexasInstruments. Hector de J. Ruiz, chairman andCEO of AMD, was elected vice chairman.

"Wim Roelandts and Hector Ruiz bringmany years of leadership in the micro-electronics industry to the positions ofchairman and vice chairman of the SIAboard," said SIA President George Scalise."That experience will be invaluable as thesemiconductor industry continues itsefforts to secure additional funding foruniversity research, immigration, andeducation reform to ensure access to ahighly skilled workforce, and tax reformto level the global playing field.

"Leadership in innovation is the key toleadership in technology," said Roelandts."The SIA public policy agenda is focused onensuring that the U.S. has a business cli-mate that encourages and supports innova-tion. I welcome the opportunity to be aspokesman for our innovation agenda."

Xilinx Chief Willem Roelandts

Elected SIA Chairman

The beauty of programmable logic is its flexibility to meet the demand of any specific “hot” application.

V I E W F R O M T H E T O P

by Kevin MorrisEditor – FPGA and Structured ASIC Journal [email protected]

Non-volatile FPGAis one of today’s odd-est market segments.

Bound by the ill-defined characteristic of“non-volatility,” the field of availabledevices is diverse from the ground up,with strikingly different architectures,approaches, and benefits.

Actel, long the leader in non-volatileFPGAs, began with antifuse technology(which is one-time programmable) and fol-lowed later with flash-based FPGAs.QuickLogic fielded an antifuse-typeapproach from the beginning, and LatticeSemiconductor joined the fray over a yearago with their LatticeXP hybrid devices,embedding a flash boot PROM on theFPGA for rapid, on-chip configuration.

With the new, non-volatileSpartan™-3AN family, it is clear thatXilinx approached the non-volatile prob-lem differently. Often, on your board,you’d pair a low-cost SRAM FPGA like aSpartan-3 device with a commodity flashmemory for storing the bitstream and pos-sibly other user data. Xilinx just took thedie for that flash memory and the die forthat FPGA, stacked them using packagingtechniques now common in cell phonesand other space-constrained devices, anddropped them into a single package. Voila!A non-volatile FPGA.

Hey, wait, that’s totally cheating, isn’t it?Does stacking the two die vertically insteadof horizontally on your board somehowchange a regular-old volatile SRAM FPGAinto a newfangled non-volatile one? Aren’t

there rules about these things? Somebodybring in a referee. What’s the catch?

In reality, there is no “catch.” Like anyengineering solution to a problem, there aretrade-offs. To understand the ones involvedin Spartan-3AN FPGAs, we need to exam-ine our possible reasons for wanting a non-volatile FPGA in the first place, and thensee how the various options stack up.

As long as we don’t pop open the pack-age and start asking too many questions(we’ll discuss opening the package later, sokeep those Dremel tools powered down forthe moment, lil’ hacker dudes), we canassume that a non-volatile FPGA is one thatdoesn’t require an external boot PROM.You apply power to the pins and (after sometime passes) the FPGA is ready to go, inde-pendent of any other devices on the board.

Why do we care? Well, wemight want the smaller footprintof a single chip. We might wantsimpler board design. We mighthope for lower power consump-tion. We might want additionaldesign security. We might be try-ing to reduce total BOM cost.We might want instant (or near-instant) power on. Comparedwith Spartan-3A devices, howdoes the new Spartan-3AN fam-ily do on these issues? Yes, yes,no, sorta, and probably not.

Xilinx Spartan-3AN FPGAsare available in a subset of thepackage options of theSpartan-3A family. Probablybecause the stacked-die pack-aging process is more expen-sive, Xilinx isn’t rolling out theentire fleet of packages forSpartan-3AN devices. The

company says they will probably be addingadditional packaging options based oncustomer demand, so if the package youwant is not on the list – vote early andoften. The good news is that the packageyou choose will be the only FPGA-relatedthing you have to buy, inventory, place,and connect to your board. You won’t needa separate boot PROM as you would withan SRAM-based FPGA. Board real estateand complexity is definitely reduced.

The FPGA portion of a Spartan-3ANdevice has the same power consumption as acorresponding 90-nm Spartan-3A devicebecause – hey, it’s the same die. As a review– Spartan-3A devices have some nicepower-saving features for an SRAMFPGA. Its 90-nm technology gives it prettygood dynamic power consumption. In addi-


Short Stack with SyrupLooking between the layers of the non-volatile Spartan-3AN family.

First appeared in FPGA and Structured ASIC Journal (www.fpgajournal.com). Copyright Techfocus Media, Inc. Reprinted with permission.

tion, Spartan-3A devices (and thus alsoSpartan-3AN devices) have two additionalpower modes called “Suspend” and“Hibernate” that allow you to drop static(standby) power by 40% with a fast wake-up time (suspend mode) or by 99% with a“normal” wake-up time (hibernate mode).This means that the device is still morepower-hungry than other super-low-powernon-volatile FPGAs like QuickLogic’sPolarPro or Actel’s Igloo, but it maintainsother advantages. (Remember what we saidabout trade-offs?)

The flash portion of the Spartan-3ANFPGA will, of course, have the samepower profile as the commodity flashmemory device that it is. If you droppedone of those on your board next to aSpartan-3A device, your total power char-acteristics should be almost identical. Onecould argue that having the flash separategives you more options on the flash sidethan defaulting to the built-in flash inSpartan-3AN FPGAs. If one argued that,one would be correct.

Security RisksDesign security is one of the issues mostoften cited for wanting a non-volatileFPGA over a conventional SRAM design.The important thing to remember here isthat security is relative. Every option avail-able on the market provides differingamounts and types of security. Almostnothing can protect against the best-fund-ed security risks such as those funded bygovernments. As you move down the scaleon attackers’ budgets and time constraints,however, security measures start to shakeout at different levels.

The biggest design security risk withSRAM-based FPGAs is the availability ofthe configuration bitstream going betweenthe boot PROM and the FPGA duringstartup. Since FPGAs are standard parts, ifthe contents of the boot PROM can becloned, the design is stolen. The normal wayto deal with this is to encrypt the bitstreamin the boot PROM, and to have an encryp-tion key stored in the FPGA that will allowthe bitstream to be decrypted upon load.The problem with SRAM (and non-volatiledevices in general) is that any encryption key

It’s also important to look at Spartan-3AN devices in comparison with othernon-volatile options. After all, from a mar-keting perspective, the Spartan-3ANFPGA is probably most important becauseit gets Xilinx into the non-volatile FPGArace. Before, a list of non-volatile FPGAvendors would have included Actel (fortheir antifuse and flash-based devices),QuickLogic (for their antifuse devices),Lattice (for their LatticeXP hybrid devices)and arguably even Altera for their Max II(which is really an FPGA marketed as aCPLD). Now, that list includes Xilinx withthe Spartan-3AN family.

With a 90-nm SRAM-based FPGA atits core, Spartan-3AN devices will be fasterand have higher density than the otherentrants. Because it uses commodity flashbonded to the FPGA, it will offer morenon-volatile storage than the otherentrants. On the down-side, it will takelonger to configure (in the range of 100milliseconds because of streaming the con-figuration over a serial flash versusmicroseconds or even near-zero for trulynon-volatile devices like antifuse andActel’s flash). It will likely be less securethan the other options, and although itspower consumption will be very good, itwill consume more power in both activeand standby modes than the other non-SRAM alternatives.

The Spartan-3AN family offers devicesranging from 50K to 1.4M “system gates”(corresponding with Spartan-3A devicesXC3S50A to XC3S1400A) with flash mem-ory ranging from 1M to 16M. Three of thedevices, the XC3S200AN, XC3S700AN,and XC3S1400AN are available now, withthe remaining devices (XC3S50AN andXC3S400AN) slated for second quarter.

Xilinx Spartan-3AN FPGAs are likelyto be popular in space-, cost-, and power-constrained high-volume applicationsthat need some of the features of non-volatile FPGAs with the performance anddensity of leading-edge SRAM devices. Inaddition to bringing Xilinx officially intothe non-volatile game, the unique charac-teristics of the Spartan-3AN family givesus another valuable trade-off point in ourFPGA selection.

stored in SRAM is lost when the device ispowered down. This leaves us with a prob-lem in moving encrypted bitstreams thathas been addressed two ways: 1) by attach-ing an external battery to the device tomaintain the encryption key and 2) byadding permanent fuses to each device forstoring the encryption key.

The Spartan-3AN device does neitherof these. Not exactly, anyway. There is apermanent serial number stored in eachdevice, and that serial number can beused to implement various securityschemes as you see fit. It is not, however,used to decrypt the incoming bitstream.Bitstream protection is done by obscur-ing the connection between the FPGAand the boot PROM (now stacked ontop of the FPGA inside a single package).While more secure than a separate bootPROM, the scheme is still far fromimpermeable as far as configurationstream protection goes. (OK, you can fireup those Dremel tools now.)

Because the Spartan-3AN FPGA hasroom for two complete configurations inthe flash, it’s obvious that Xilinx thinksyou’ll be updating the bitstream at somepoint in the product life cycle. TheSpartan-3AN device even has a nice fea-ture that’ll let it boot on the original “gold-en” bitstream if a bad download or othercorruption causes the new, updated one tomalfunction. The problem is, any mecha-nism you have for delivering an updatedbitstream to the device will be snoopableby prying eyes (or prying logic analyzers,really). The bitstream obscuring methoddoesn’t hold up as well when the bitstreamhas to travel from your home base to thedevice in the field. Be sure to design yoursecurity scheme accordingly.

As far as the lower cost question goes,you’ll probably pay a bit of a premium forSpartan-3AN devices compared with thesame Spartan-3A device with the sameflash memory. When you factor in theother costs of an additional device such asboard area and inventory and such, it maybe a wash. On the positive side, you cer-tainly won’t be taking a big BOM hit forusing the new family. Xilinx projects pricesin the $5 range in volume.


by Kevin M. KitagawaDirector, Worldwide Marketing, High-Volume ProductsXilinx, [email protected]

As we move toward an increasingly digitalworld, consumers want to experience con-tent such as audio, video, and data anytimeand anywhere. Better and inexpensive wiredand wireless infrastructure is available todeliver content for a better consumer experi-ence, and product manufacturers are consis-tently challenged to come up with newinnovations to improve that experience.

As an example, digital music players,HDTV digital displays, automotive elec-tronics, cell phones, and broadband Internetaccess have all changed consumer expecta-tions and behavior on how to access andexperience content at home, in the car, or onthe move. Predicting which innovations willbe successful often requires potentially riskyproduct decisions, and manufacturers aretrying to incorporate feedback directly fromconsumers into product development cyclesearly to ensure success of their products.This often translates to the need for quickproduct development cycles to get innova-tive products to market quickly.

The initial costs of developing ASICshave been exponentially rising with eachprocess geometry shrink, making this pathless attractive for most applications. Also,

ASSPs typically cannot meet theneeds of every customer, and siliconmanufacturers must make compro-mises to implement the featurescustomers request the most.

Xilinx® FPGAs and CPLDs are atthe heart of innovation. These productsprovide flexible yet low-cost solutions tomeet the application-specific requirementsof high-volume products such as digital dis-plays, set-top boxes, automotive rear-seatentertainment systems, smartphones, andvideo equipment.

Xilinx in Consumer ElectronicsConsumer electronics manufacturers needto differentiate their products from theircompetitors. They are often driven to deliv-er the latest technologies and innovationsas quickly as possible to the consumer tostay ahead in a highly competitive market-

place. Later in theproduct life cycle, manu-facturers focus on driving productcosts down to deliver more and morevalue at lower prices to the consumer.

As an example, HDTV digital displaymanufacturers are challenged with the evo-lution of new flat-panel technologies andinterface standards while trying to improveimage quality to address any shortcomings


At the Heart of Consumerand Automotive InnovationXilinx offers silicon, developmenttools, IP, middleware, and designservices for the automotive electronics market while meeting the industry’s temperature, quality,and reliability requirements.

C O V E R S T O R Y

Xilinx in Automotive ElectronicsNew and future vehicles are increasinglyreliant on electronics in order to allowOEM automakers to differentiate theirproducts. These electronics systems rangefrom driver information and rear-seat enter-tainment systems to newer driver-assistancetechnologies such as night-view and lane-departure warning systems.

The Xilinx Automotive (XA) family ofproducts brings the scalability and flexibilityof FPGAs and CPLDs to the automotiveelectronics market, allowing automotivetier-ones to bring out innovative featureswhile also giving them platform develop-ment capabilities (even in a fragmentedapplication sector), thus lowering costs.

With the increasing use of LCD/TFTdisplays, multiple networking protocols,video, and graphics, Xilinx XA solutionsallow for quick development cycles and flex-ibility of customization through to produc-tion. By using Xilinx XA programmablelogic, automotive tier-ones can quickly addnew features, improve existing features, orchange interfaces simply by making changeswithin the FPGA fabric without needing towait years until the next time the electronicsare redesigned. FPGAs also allow designersto look again at their overall applicationarchitecture and build systems based on theirneeds instead of what is available in semi-conductor hardware today.

ConclusionWith Xilinx high-volume Spartan,CoolRunner™-II CPLD, and XA productfamilies, manufacturers can afford to delivermore innovative products quickly to market,knowing that they have the flexibility of pro-grammable logic minimizing their risk.

Decreasing costs from our suppliers,along with leading-edge technology, haveallowed us to extend lower prices to our cus-tomers, accelerating our success in high-vol-ume design wins moving into production.With cost points starting in the low singledigits, Xilinx FPGAs and CPLDs can elimi-nate the need to move to ASICs or ASSPs inproduction in high-volume applicationssuch as consumer or automotive electronics,while still allowing endless customization tomeet your customer requirements.

in the quest to deliver the perfect TV pic-ture. Variations in panels used in differentmodels often have different specifications oreven different suppliers.

FPGA programmability enables manufac-turers to easily accommodate these variationsusing image-enhancement algorithms imple-mented in a Spartan™ FPGA and allowingthe same hardware design to be utilized in awhole family of products. Native support formost differential I/O interfaces in SpartanFPGAs makes it easy to directly interface withthe new panel interfaces. These advantagesmake Spartan FPGAs a compelling option inmany consumer electronics products.


C O V E R S T O R Y

Xilinx is Driving Automotive Solutions

Xilinx is Driving Automotive Solutions

As the automotive electronics market grows inthe areas of infotainment, driver assistance, anddriver information systems, Xilinx® devices areat the heart of each new innovation.

■ Image Processing and Recognition –Offering faster development and product dif-ferentiation for driver assistance applications.

■ Video and Graphics – Allowing for highly scalable and cost-efficient implementations of infotainment and driver information systems.

■ Application Development Platforms –Providing developers a quick start andserving as a comprehensive hardwarebase to satisfy their expectations.

■ Xilinx Technology Leadership –Leading the way in programmable logicdevices, one of the fastest growing segments of the semiconductor industry.

■ Vehicle Networking – Designingand supporting key automotive-specificnetwork interfaces.

As the automotive electronics market grows inthe areas of infotainment, driver assistance, anddriver information systems, Xilinx® devices areat the heart of each new innovation.

■ Image Processing and Recognition –Offering faster development and product dif-ferentiation for driver assistance applications.

■ Video and Graphics – Allowing for highly scalable and cost-efficient implementations of infotainment and driver information systems.

■ Application Development Platforms –Providing developers a quick start andserving as a comprehensive hardwarebase to satisfy their expectations.

■ Xilinx Technology Leadership –Leading the way in programmable logicdevices, one of the fastest growing segments of the semiconductor industry.

■ Vehicle Networking – Designingand supporting key automotive-specificnetwork interfaces.

For more information on Xilinx automotive products, visit

www.xilinx.com/automotiveFor more information on Xilinx automotive products, visit

www.xilinx.com/automotive

by Nick DiFioreGeneral Manager, Automotive DivisionXilinx, [email protected]

Within the Automotive Business Divisionof Xilinx, we are very excited by the changeswe see coming. Programmable logic isdeveloping rapidly, as are the requirementsof the automotive market. These changesare providing some great opportunities tocreate solutions to complex problems cur-rently plaguing automotive design.

The advantages of programmable logichave always been flexibility, scalability, andfast time to market. Today, these are advan-tages of key value in the automotive elec-tronics market, as consumer products withhighly complex and varying networkingand interface standards are introduced intovehicles at a rate never seen before.

Vehicle differentiation and high value-add is often provided by the OEMsthrough the electronics, but at the sametime, engineering resource and time con-straints mean that tier ones need to supplycommon platforms and reusable designs.PLDs in automotive electronics make for agreat partnership, but like all partnerships,there are also many challenges.

As a new technology in this market, thefirst challenge is in providing not just cut-ting-edge silicon, but full solutions todemonstrate and prove the technology outto our customers. To achieve this goal, wehave made a large investment at Xilinx torecruit both highly experienced automotivesystem architecture engineers and veteranautomotive semiconductor personnel towork directly with customers and deter-mine what silicon and solutions would be atrue value-add in this market. We have alsoinvested in engineers to develop IP both

internally and externally through ourLogiCORE™ IP and automotiveAllianceCORE programs.

To continue our own learning and alsodrive the market forward, Xilinx has joineda number of consortiums, such asAUTOSAR, JASPAR, the FlexRayConsortium, and the MOST Cooperation.By doing this, we have been able to puttogether an arsenal of fully scalable in-vehi-cle networking and video/graphics solutions.

These critical investments have resultedin complete solutions for applications,such as video displays (“A CompactMultimedia Display DevelopmentPlatform for Automotive and Industrial

Markets,” also in this issue of Xcell Journal),driver assistance systems (“Block Matchingfor Automotive Applications on Spartan-3A DSP Devices” in this issue), and a flex-ible Xilinx MOST solution (see ourdemonstration at CES).

The second challenge is in meeting thevery high-quality and reliability standardsthat the automotive market requires of

semiconductor suppliers. The advan-tages of working with automotive cus-

tomers were recognized at the veryhighest levels of management

within Xilinx. By achievingISO-TS16949 certification,implementing the AEC-Q100 qualification stan-dard, and creating a

separate XA line of productsin order to control bill-of-mate-

rials (BOM) and production sites,we can improve the quality and logistic

processes for all of our customers andensure that we are on the path of continu-ous improvement, which is a key part ofour corporate philosophy.

The last four years of the automotiveXA program at Xilinx have been both chal-lenging and exciting, but our success inbecoming the number-one programmablelogic supplier (based on Semicast data) inthe automotive electronics market showsthat we are on the right track.

Our next challenge is to ensure thateven with all of the possible opportunitiesthere are for programmable logic, we con-tinue to work closely with our automotivecustomers to ensure that we focus on theright solutions to meet their future needs inarchitecture and design.


Marriage Made in Heaven?Creating standard automotive platforms with maximum differentiation.

A U T O M O T I V E

by Daniele Bagni DSP SpecialistXilinx, Inc. [email protected]

Paul ZorattiAutomotive Senior System ArchitectXilinx, [email protected]

Automotive engineers are adaptingnumerous intelligent technologies toassist humans in operating vehicles safely.Prominent technologies in vehicle systemsinclude radar-, ultrasonic-, and camera/vision-based sensing. Collectively referred toas driver assistance (DA) systems, these tech-nologies are designed to facilitate safe driv-ing during adverse conditions andpotentially dangerous roadway situations.

The first generation of camera-basedDA systems is now available on a varietyof production vehicle models. The major-ity of such systems provide drivers with avideo image of the environment aroundthe vehicle. The most prevalent systemsare parking/backup aids that use a rear-facing camera to capture the scene behindthe host vehicle and display the image ona radio/navigation system screen, or on asmall display in the instrument cluster.

A second generation of camera-basedsystems is in development and testing,with some limited deployment. Ratherthan merely providing an image to driv-ers, these second-generation systemsapply image processing and analytics toextract information from the videostream and characterize and evaluate thevehicle environment. If warranted, thedriver receives an appropriate warning.

As engineers gain real-world experi-ence in characterizing the vehicle envi-ronment, future DA techniques willincrease in complexity, offer greater utili-ty to consumers, and enhance the per-formance of other vehicle subsystems.Figure 1 summarizes the variety of cur-rent and future DA features.

Advanced Processing RequirementsProcessing requirements for DA systemscan exceed the capabilities of currentautomotive-grade serial DSP processors.In addition, a growing need exists to bun-dle multiple DA features together, basedon a single suite of vision sensors to driveconsumer value.

For example, a forward-looking visionmodule may need to simultaneously sup-port lane departure warning, intelligentheadlamp control, and sign recognitionfunctionality – all of which require differ-ent processing algorithms. Therefore, theDA market offers a real opportunity forFPGAs to provide system value throughraw processing performance, configurationflexibility, and device scalability.

Image processing and analytics function-ality for vision-based DA schemes caninclude spatial/temporal filtering, lens-dis-tortion correction, image sharpening, con-trast enhancement, edge detection, patternmatching, object recognition, object track-ing, and, in some cases, graphical overlay. Ofparticular interest is a form of pattern-matching functionality that supports motionestimation or stereo disparity calculations.

To illustrate the performance value ofFPGA processing, consider the followingvision-based system: a wide-VGA resolu-tion imaging device (752 x 480 pixels) gen-erating video at a 30-Hz frame rate (fps),and the need to estimate the motion (orflow) of objects from one frame to another.One algorithmic approach – also suitablefor stereo ranging disparity calculations –is to partition the image into blocks (say,4 x 4 pixels in size) and evaluate a matchcriteria for each block in the first frame toa location in the second frame over a spec-ified search area (say, 20 x 20 pixels).

A common match criteria is to findthe minimum absolute error (MAE) ofthe pixel intensities between the 4 x 4


Block Matching for AutomotiveApplications on Spartan-3A DSP DevicesThe Spartan-3A DSP FPGA outshines VLIW DSP-CPUs in automotive driver assistance applications.

A U T O M O T I V E

block in the first image and the pixelswithin the search area on the secondimage by using an operator called SAD(sum of absolute differences).

Our 4 x 4 block matching examplerequires more than 250 MMAE/s (millionsof MAE calculations per second), since(752 pixels) x (480 lines) x (20 x 20 pixelsearch area) x (30 fps) / (4 x 4 pixel blocksize) = 270,720,000 MAE/s. MAE indi-cates the final matching error of a 4 x 4pixel block, whereas SAD refers to the sumof absolute differences calculation on fourindividual pairs of elements. Therefore,every MAE requires four SAD operations.

Processing OptionsProcessing options at the automotive designengineer’s disposal include very longinstruction word (VLIW) DSP-CPUs andFPGAs. FPGAs offer dramatically higher

CPU, thus efficiently executingthe equivalent of 11 elemen-tary instructions in only onecycle, as shown in Figure 2.

For example, the NexperiaPNX1500 media processorequipped with the TriMedia32-bit VLIW-CPU can imple-ment two quadruple SADinstructions on a single clockcycle for 8-bit pixels with twocycles of latency. Associatedwith every long instructionword are as many as five ele-mentary RISC/SIMD instruc-

tions per clock cycle, of which only twocan be SAD (named “8meii” in theTriMedia databook).

Therefore, the MAE on a 4 x 4 block sizewould require five clock cycles, as shown inTable 1: two cycles for pipelining twoquadruple SADs (cycle 1 for sad1/sad2,cycle 2 for sad3/sad4) and three cycles foraccumulating the partial results (cycles 3, 4,and 5). Hence, a 300-MHz NexperiaPNX1500 processor could compute a peakof 60 MMAE/s if processing a single block.

By processing more than one 4 x 4 blockat a time, the peak performance canimprove a little. For example, the MAE oftwo 4 x 4 blocks in parallel could be com-puted in seven cycles, thus achieving 85.71MMAE/s, and three blocks could beprocessed in nine cycles, or 100 MMAE/s.

The maximum amount of blocks thatcan be processed in parallel is limited firstby the number of SIMD SAD operationsallowable in any long instruction word;second by the number of general-purposeregisters of the VLIW-CPU; and third bythe scheduling algorithms of the optimiz-ing compiler. Overall performance goesinto saturation when adding more blocks,which is why we do not consider more thanthree MAEs processed in parallel.

The Texas Instruments (TI)TMSD320DM6437 digital media proces-sor has a long instruction of eight elemen-tary RISC operations per cycle throughtwo separated data paths: each one of fourslots per cycle. Its VLIW-CPU can executeas many as two SAD instructions per cycle(named “subabs4” in the TI DM6437

processing capability than any existingVLIW DSP-CPU. This is because of thearchitecture of the FPGA: the large amountof functional units in parallel (includingprogrammable MACs) allows the FPGA toachieve 10-30 times better performancethan that offered by any DSP, depending onthe application implemented, even if theclock frequency of the FPGA is much lowerthan the clock frequency of the DSP-CPU.Using the block-matching operationexample, we will demonstrate that Xilinx®

FPGAs have superior performance to anyVLIW DSP-CPU processor.

SAD and MAE Calculations in VLIW DSP-CPU ProcessorsA SAD operation on four elements of 8-bitpixel video data could be implemented in asingle-instruction-on-multiple-data(SIMD) within a 32-bit architecture DSP-


Awareness Warning Temporary Control

Panic Brake AssistLane Departure Warning

Front Collision Warning

Back-Up Warning Aid

Pedestrian Detection

Drowsy Driver

Blindspot Detection

Sign Recognition

Park/Back-Up Assist

Lane Change Assist

Night Vision

Pre-Crash Sensing

Side Impact Detection

Pedestrian Protection

Automatic Braking

Lane Keeping

Adaptive Cruise Control

Automated Parking

Convenience Oriented

Safety Oriented

Performance Enhancement

Driver Assistance Features

unsigned unsigned unsigned

unsigned

unsigned unsigned unsigned unsigned unsigned

src1 (32-bit unsigned)

dst (32-bit unsigned)

SAD performs 11 RISC operations

src2 (32-bit unsigned)

--

--

||||

+

++

||||

Figure 2 – An example of SIMD: SAD operation on a quadruple of 8-bit samples

Figure 1 – Driver assistance features

A U T O M O T I V E

databook), each with a latency of onecycle. However, to accumulate the partialresults, a three-cycle latency SIMD MACoperation must be performed (named“dotpsu4”), with a constant 0x01010101.

Therefore, a 600-MHz TI DM6437DSP-CPU could compute an MAE inseven cycles (as shown in Table 2), thusachieving a peak performance of 85.71MMAE/s for 4 x 4 pixel blocks. If twoblocks are processed in parallel, we getnine cycles and 133.33 MMAE/s, whereasfor three blocks we get 11 cycles and163.64 MMAE/s – again lower than our250 MSAD/s requirement.

De-Rating VLIW DSP-CPU PerformanceThus far, we have assumed 8 bits per pixel,which is very suitable for 32-bit architec-ture DSP-CPU processors. However, newCMOS image sensors have a higher resolu-tion range: 12 to 14 bits per pixel. For thesedata types, the classic quadruple 8-bit sub-words SIMD of 32-bit architectures are lesseffective and must be replaced by dual 16-bit half-words SIMD, in which the sub-

word parallelism is only two. Therefore,peak performance degrades significantly,because more clock cycles are necessary tocompute an MAE.

Table 3 shows what could be the pseu-do assembly code of the SAD computa-tion on the TI VLIW DSP-CPU whenusing 16-bit sub-word instructions, con-sidering the correct latency and the func-tional issue slot able to deliver suchinstructions. As a result, eight cycles arenecessary for one 4 x 4 block while 10and 12 cycles are required, respectively,for two and three blocks processed in par-allel. Corresponding peak performance isthen 75 MMAE/s, 120 MMAE/s, and150 MMAE/s. All of these numbers aresmaller than the ones achieved with 8-bitsub-word instructions.

Spartan-3A DSP FPGA SAD and MAE Performance To fill the processing performance gapbetween Spartan™-3 and Virtex™-4devices, Xilinx introduced the Spartan 3A-DSP 1800A and 3400A FPGAs. These

devices incorporate a modified version ofthe DSP48 slices found in Virtex-4 devices.In addition, 3A-DSP parts include a largernumber of on-chip memory (block RAMs).Both of these enhancements, along with aprice point suited to high-volume applica-tions, make 3A-DSP devices a good fit forautomotive vision-based DA systems.

Figure 3 shows the scheme of SAD com-putation for a quadruple of 12-bit pixels onthe Spartan-3A DSP 1800 (XC3SD1800A-4FG676) device. This implementation wasdone with the System Generator for DSPdesign flow (a bit-true, cycle-accurate, syn-thesizable library provided by Xilinx in theSimulink tool). The amount of resourcesrequired is 121 slices (236 LUTs and 140flip-flops). By replicating this structure fourtimes and adding the partial results, we getthe scheme for a whole 4 x 4 block, whichrequires 508 slices (990 flip-flops and 606LUTs) with a throughput of one (whichmeans that at any clock cycle we can startthe computation of a new MAE) and alatency of seven cycles.

Utilizing a 150-MHz clock frequency(of the maximum 250 MHz the devicecould achieve), we would need only twoparallel structures occupying approxi-mately 6% of the device area to achieve300 MMAE/s and meet the 250 MMAE/srequirement of our example application.This leaves ample resources available toimplement other image processing func-


Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Slot 3

sad2=8meii(A2,B2)

sad4=8meii(A4,B4)

nop

nop

nop

Slot 2

nop

nop

nop

nop

nop

Slot 4

nop

nop

nop

nop

nop

Slot 5

nop

nop

nop

nop

nop

Slot 1

sad1=8meii(A1,B1)

sad3=8meii(A3,B3)

sad12=sad1+sad2

sad34=sad3+sad4

tot=sad12+sad34

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Slot 1

L1

d1=subabs4(A1,B1)

d3=subabs4(A3,B3)

nop

nop

nop

sad13=sad1+sad3

tot = sad13+sad24

Slot 2

S1

nop

nop

nop

nop

nop

nop

nop

Slot 3

M1

nop

sad1=dotpsu4(d1, 0x01010101)

sad3=dotpsu4(d3, 0x01010101)

nop

nop

nop

nop

Slot 4

D1

nop

nop

nop

nop

nop

nop

nop

Slot 5

L2

d2=subabs4(A2,B2)

d4=subabs4(A4,B4)

nop

nop

nop

sad24=sad2+sad4

nop

Slot 6

S2

nop

nop

nop

nop

nop

nop

nop

Slot 7

M2

nop

sad2=dotpsu4(d2, 0x01010101)

sad4=dotpsu4(d4, 0x01010101)

nop

nop

nop

nop

Slot 8

D2

nop

nop

nop

nop

nop

nop

nop

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Cycle 8

Slot 1

L1

d1=sub2(A1,B1)

ad1=abs2(d1)

ad3=abs2(d3)

z13=add2(ad1, ad3)

nop

nop

nop

tot = s13 + s24

Slot 2

S1

d3=sub2(A3,B3)

nop

nop

nop

nop

nop

nop

nop

Slot 3

M1

nop

nop

nop

nop

s13=dotp2(z13, 0x00010001)

nop

nop

nop

Slot 4

D1

nop

nop

nop

nop

nop

nop

nop

nop

Slot 5

L2

d2=sub2(A2,B2)

ad2=abs2(d2)

ad4=abs2(d4)

z24=add2(ad2, ad4)

nop

nop

nop

nop

Slot 6

S2

d4=sub2(A4,B4)

nop

nop

nop

nop

nop

nop

nop

Slot 7

M2

nop

nop

nop

nop

s24=dotp2(z24, 0x00010001)

nop

nop

nop

Slot 8

D2

nop

nop

nop

nop

nop

nop

nop

nop

Table 3 – Pseudo assembly code for the MAE computation on the TI VLIW DSP CPU, with dual 16-bit sub-word parallelism

Table 2 – Pseudo assembly code for the MAE computation on the TI VLIW DSP-CPU, with quadruple 8-bit sub-word parallelism

Table 1 – Pseudo assembly code for the MAE computation on the Nexperia/TriMedia VLIW DSP-CPU, with quadruple 8-bit sub-word parallelism

A U T O M O T I V E


tions, data routing pipes, memory interfacecontrollers, and a 32-bit MicroBlaze™embedded processor for serial processingand external communications.

For reference, by utilizing only 70% ofthe whole FPGA device again at 150 MHz,the Spartan 3A-DSP 1800A device couldprocess up to 23 blocks in parallel (70% x16,640 slices/508 slices/block = 23 blocks).This corresponds to a peak performance of3,529 MMAE/s, which is at least 25 timesgreater than the 600-MHz TI DSP-CPU’speak performance.

ConclusionUsing an automotive vision-based applica-tion example, we’ve shown how to leveragethe programmable parallelism of a medi-um-sized, low-cost Xilinx FPGA to providerequired processing performance overVLIW DSP-CPUs. Table 4 summarizes theresults of our analysis.

Note that for MAE calculations on 4 x 4blocks of 12-bit pixel data, the Spartan-3ADSP outperforms the TI TMS320DM6437by 2 times at only one-fourth the clockspeed. Furthermore, resource utilization onthe FPGA is only 6%, thus allowing for theimplementation of other image processingfunctions (in parallel if necessary) on thesame device.

On the other hand, the VLIW DSP-CPU is totally busy during the SAD calcu-lations, leaving little opportunity toconduct other simultaneous functions byconsuming the available slots of the serialprocessor long instructions.

We were quite conservative about theFPGA estimated clock frequency (150 vs.250 MHz), as well as the motion estimationsearch area (the larger the search area,greater the number of MAEs to be comput-ed). A 30 x 30 search area, for example,would require 609 MMAE/s, far beyondthe VLIW DSP-CPU capability but usingonly 12% of the slices on the 1800A device.

Finally, in the MAE implementation wedid not use at all of the DSP48 MAC units:we estimate that a 4 x 4 block of 12-bitinput data MAE could take 400 slices (782flip-flops and 400 LUTs) and four DSP48sby replacing the 100-slice adder tree withfour DSP48 units.

Thus, the Spartan-3A DSP 1800A deviceis well suited for vision-based applicationsrequiring significant processing horsepower,

flexibility, and scalability such as those foundon future generations of automotive driverassistance applications.

Device Configuration Clock Freq. Performance

Example Application Requirement 752 x 480 image N/A > 250 MMAE/s4 x 4 pixel block20 x 20 pixel search area

Philips Nexperia PNX 1500 8-bit pixel depth 300 MHz 100 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

TI TMSD320DM6437 8-bit pixel depth 600 MHz 163.64 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

TI TMSD320DM6437 12-bit pixel depth 600 MHz 150 MMAE/sVLIW DSP-CPU Parallelism: Three 4 x 4 blocks

Xilinx Spartan-3A DSP 1800A FPGA 12-bit pixel depth 150 MHz 300 MMAE/sParallelism: Two 4 x 4 blocks(approximately 6% of deviceresources)

Xilinx Spartan-3A DSP 1800A FPGA 12-bit pixel depth 150 MHz 3,450 MMAE/sParallelism: 23 4 x 4 blocks(approximately 70% of deviceresources)

Figure 3 – System Generator for DSP scheme of the SAD computation for a quadruple of four 12-bit samples in the Spartan-3A DSP 1800 device

• Evaluate the System Generator for DSP design tool.

• Learn more about and purchase the Spartan-3A DSP 1800A device.

• Buy the XtremeDSP Development Platform – Spartan-3A DSP 3400A Edition.

TAKE THE NEXT STEP (Digital Edition: www.xcellpublications.com/subscribe/)

Table 4 – Summary of results

A U T O M O T I V E

by Davor KovacecCEOXylon [email protected]

Market leadership in the fast-moving elec-tronics market continuously demandsinnovative and cost-effective products.With an ever-shrinking time-to-marketwindow, design tools and pre-designed IPblocks are important elements of success.

The right development platform canmake all the difference between success andfailure. It is a balancing act between the con-tradictory requirements of having a standardbut still highly configurable solution.

Combining Xilinx® FPGAs with theXylon logicBRICKS IP cores library,Xylon’s feature-rich logiCRAFT 3 com-pact multimedia display developmentplatform is an ideal solution, addressingthe time-to-market and flexibility needs ofthe high-volume customer base. You canquickly turn system designs running onthis generic FPGA development platforminto specialized products. Such a designapproach enables a large portion of designreuse through different hardware (IPcores) and software modules. You canreuse these same modules in many systemdesigns for different applications.

The logiCRAFT PlatformThe logiCRAFT 3 compact multimediadisplay development platform (Figure 1)is an FPGA-based board using hardwaremodules in the form of IP cores to devel-op FPGA functionality. The platform isdesigned to support a wide variety ofaudio and video sources and handle a


A Compact Multimedia DisplayDevelopment Platform for Automotive and Industrial Markets Xilinx FPGAs and Xylon IP cores shorten design cycles and lower production costs for multimedia applications.

A U T O M O T I V E

variety of display types. With several stan-dard communication interfaces, you caneasily integrate the logiCRAFT 3 platforminto a larger system. Figure 2 showslogiCRAFT 3’s functional blocks.

A wide variety of system interfaces such asaudio/video (A/V) I/Os, line drivers, gener-

through two embedded IR headphone audiooutputs for the RSE is also an opportunity toreduce system cost. The FM modulation isimplemented using the logiAIR IP core,enabling the use of a low-cost field effecttransistor (FET) for IR LED driving. Thereis also the flexibility to enable Bluetooth withthe addition of a Bluetooth module.

Audio and video streams, as well as con-trol data, are transferred to the RSE head-rest unit by using an embedded high-speedGbps digital link. The low data-rate con-tent, such as push-button status, remotecontroller data, touch-screen data, and oth-ers are transferred using the same link.

The link itself requires only two twistedpair lines. One line may also be used forpowering the platform, resulting in a sig-nificant reduction in infotainment wiringcosts. You can have the A/V devices con-nected to the logiCRAFT 3 through thecomposite video blanking and sync

al-purpose I/Os, and COG power suppliesmakes this platform extremely versatile.

The logiCRAFT 3 platform is primarilyaimed at the automotive market, includingapplications such as navigation, infotain-ment, rear-seat entertainment (RSE), anddriver assistance. Other multimedia appli-cations are equally applicable, such as con-sumer, medical, and measurementinstrumentation or factory automationapplications.

Figure 3 shows block schematics of anautomotive RSE system. In this particularexample, the logiCRAFT 3 is used in the carheadrests and serves to deliver A/V content.

The platform’s flexibility can helpreduce overall solution costs as well as timeto market. For example, the platform’scapability to fully support a number of dif-ferent displays enables you to make selec-tions when required for cost or availability.Implementing high-quality wireless audio


FPGALCD

TV

logiCRAFT3

PAL/NTSC/

SECAM

CAMERA

Four CVBS or

Two S-VIDEO

Inputs

Four LVDS Pairs

One (two) Twisted

Pair Lines

IR

Remote

Sensor

Eight 3V3 TTL

Lines

CAN

CAN

iPod Serial

Control

Bluetooth Port

Four Stereo Audio

Line Inputs

Microphone

Input

Audio Codec

TVL320AIC23

Single Wire CAN

Interface

Gbps Pixel Link

Receiver

INAP125R24

IR Remote

Sensor

Interface

8-bit General-

Purpose I/O

PAL/NTSC/SECAM

Decoder 1

SAA7113A

PAL/NTSC/SECAM

Encoder

SAA7120H

FLASH

FLASH

Headphones

Output

Four LVDS Pairs

Display Data Out

CVBS/S-VIDEO Out

Stereo Audio Out

Channel 1

Stereo Audio Out

Channel 2

Line Out

SDRAM

COG Display

Power Supply

GAMMA Correction

CCFL/LED Backlight

Power and Control

Touch Screen

Controller

PAL/NTSC/SECAM

Decoder 2

SAA7113A

CAN Interface

User

Config.

IR LED

Drivers

2 x SI9955DY

RS232 InterfaceRS232

XBOX

PLAYSTATION

DVD

User-

Selectable

Assembly

Select

User-

Selectable

Figure 1 – LogiCRAFT 3 compact multimediadisplay development platform

Figure 2 – LogiCRAFT 3 platform’s functional blocks

A U T O M O T I V E

(CVBS) or S-video inputs (video) andstereo line inputs (audio). An iPod can alsobe connected as required.

The logiCRAFT 3 platform can also beused in stand-alone human machine inter-face (HMI) applications such as:

• Instrument cluster applications (Figure 4)

• Car radio and navigation

• Industrial and medical instrumentation(Figure 5)

In these applications, you can use eitherthe CAN network connection for all datatransfer or the standard RS232 channel forcommunication and debugging. For appli-cations requiring HMI control, an embed-ded IR remote control sensor, touch-screeninterfaces, and GPIO for buttons andLEDs are provided.

You can also add features by usingXilinx LogiCORE™ IP, other third-partyIP cores, or by designing a custom circuit.

The list of key IP cores that can be utilizedon the logiCRAFT 3 includes:

• logiCVC-ML – compact multilayervideo controller

• logi2D – 2-D graphics accelerator

• logiCAN – CAN 2.0B-compatible net-work controller

• logiUART – universal asynchronousreceiver/transmitter

• logiWIN – versatile video input

• logiMEM – flexibleSDRAM/DDRAM/flash memory controller

• logiI2S – I2S transceiver

• logiRC – IR remote controller receiver

• logiAIR – digital FM modulator for IRheadphones

Spartan™-3E FPGA hardwareresources, dedicated multipliers, digitalclock managers (DCMs), and block RAMsensure that IP cores operate at higherspeeds and consume less area on the FPGA.In addition, FPGA configuration from anexternal byte-width memory provides fastboard startup time, which is of a greatimportance in automotive applications. AllXylon IP cores are carefully designed for


IR Audio

Gbps High-Speed Digital Link

+

Power Supply

FLASH

FLASH

Gbps Receiver

INAP125R24

Audio/Video

Separation

I2C Controller

MicroBlaze

Processor

logiRC

logiAIR

Audio

Video

FPGA

logiCRAFT 3

Touch-Screen

Controller

IR Remote

Sensor

Interface

DISPLAY

Touch Screen

IR

Remote

Sensor

IR RemoteControl Sensor

BluetoothRF Module

BluetoothRF Module

Gbps High-Speed LinkAV Content, Control Data,

Low Data Rate Back-Channel+

Power Supply

Gbps High-Speed LinkAV Content, Control Data,

Low Data Rate Back-Channel+

Power Supply

Compact Multimedia FPGAPlatform

Compact Multimedia FPGAPlatform

DISPLAY and TOUCHSCREEN

IR Audio

DISPLAY and TOUCHSCREEN

IR Audio

IR RemoteControl Sensor

INFOTAINMENTMASTER BOARD

logiCRAFT 2

Figure 3 – Rear-seat entertainment system

Figure 4 – Platform/FPGA structure for rear-seat entertainment application

A U T O M O T I V E


the lowest FPGA resource utilization,making them particularly suitable for high-volume applications.

Platform Features

• Small form factor 155 mm x 115 mm(4” x 3”)

• Supports Spartan-3E3S250E/500E/1200E 256-pin FPGAs

• 8 MB of NOR flash

• 16 MB/32-bit-wide SDRAM runningup to 133 MHz

• Up to two simultaneous video inputsselectable from:

• Four CVBS or two S-videoPAL/NTSC/SECAM inputs

• One LVDS channel (clock + threedata pairs) directly connected tothe FPGA

• High-speed LVDS Gbps digital transceiver

• 8-bit general-purpose I/O

• Touch-screen controller

• CAN interface and single-wire CANinterface

• RS232 interface

• Interface to external Bluetooth module

• iPod control interface

• One stereo audio input selectable fromfour stereo line inputs

• Microphone input

• Audio line output

• Headphone output

• Two stereo IR headphone audio outputs

• Video output configurable as:

• CVBS/S-video PAL/NTSC/SECAM output

• One LVDS channel (clock + threedata pairs) directly from FPGA

• Digital RGB interface

• Power supply for COG displays,including GAMMA correction andVCOM circuits

• Power and control output for CCFLbacklight inverters and LCD backlights

RSE ExampleFigure 4 shows the platform/FPGA struc-ture for an RSE application where theFPGA design is based on Xylon’s IP cores.In such applications, A/V and control datais usually transferred between an infotain-ment master board and the electronics,which are embedded into car headreststhrough a number of cables.

The LogiCRAFT 3 platform, with itssupport for a high-speed Gbps digital link,

dramatically reduces the complexity andcost of the wiring required. You can trans-fer all digital video, audio, and bi-direc-tional control data using only two twistedpair lines. You can also discard the powercable, because the platform can be poweredthrough one of the two twisted pair lines.

Besides the reduction in wiring com-plexity, the logiCRAFT 3 platform alsointegrates many functions otherwise sup-ported by dedicated integrated circuits intojust one low-cost Spartan-3 XC3S250EFPGA. You will not need additional elec-tronics for IR audio FM modulation, IRremote protocol decoding, or I2C bus con-trol, among others. The logiCRAFT 3 rep-resents an ideal solution for saving yourbudget without having to sacrifice anythingfrom the set of common RSE features.

Instrument Cluster ExampleFigure 5 shows the platform/FPGA structurefor an instrument cluster, where the powerfulyet compact logiCVC multilayer displaycontroller will help you create a state-of-the-art instrument panel. With a 60-fps refreshrate, you will be able to animate on-screengauges and give them the motion smooth-ness of their analog counterparts.

In addition, the logi2D graphic acceler-ator, with its bitmap image rotating capa-bility, offers additional flexibility forinstrument animation. You can easily

Touch PanelTouch-Screen

Controller

FLASH

logiMEM

logiMEM

logiWIN

logiCAN

GPIO Bus

PAL/NTSC/SECAM

Decoder

SAA7113A

IR Remote

Sensor

Interface

IR

Remote

Sensor

Parking

Assist

Camera

Measured

Values

Control

Buttons

8

RS232

CAN

RS232 Interface

CAN Interface

FPGA

logiCRAFT 3

logiRC

logiUART logiBITBLT

MicroBlaze

Processor

I2C Controller

logiCVC

SDRAM

DISPLAY

Figure 5 – Platform/FPGA structure for instrument cluster application

A U T O M O T I V E

design an instrument panel with GUIbuilder or graphic libraries to efficiently useXylon’s graphics acceleration IP cores.

Communication between the vehicleengine control unit data and the platformis easy by using the onboard CAN interfacewith our logiCAN IP core. You can alsoconnect a suitable camera using the Gbpsdigital link, thus adding a parking assistcapability to the list of features. You can usea standard PAL/NTSC/SECAM as well.

With the help of our logiWIN IP core,you can de-interlace scale and positionincoming video to optimize it for your par-ticular display. All FPGA functionalityrequired to support the instrument clusterconfiguration will fit into one Spartan-3XC3S1200E FPGA. This way, you canachieve an outstanding cost-to-perform-ance ratio and provide a very competitivesolution for today’s demanding and fast-changing markets.

Industrial Application ExampleFigure 6 shows the platform/FPGA struc-ture where a LogiCRAFT 3 compact multi-media display development platform servesas a central unit for monitoring and con-trolling industrial processes, with the FPGAdesign based on Xylon IP cores. As in theprevious example, the logiCVC/logi2D

combination, supported with dedicatedgraphic software libraries, gives you every-thing you need for making and combiningscreen elements required for successfulprocess monitoring and control. You canalso use an embedded touch-screen con-troller to make human-machine interactionintuitive and logical.

For handling classical buttons and indi-cators, an I2C-controlled GPIO interface isat your disposal. If your application calls forreal-time environment surveillance or real-time video process monitoring, the plat-form’s PAL/NTSC/SECAM video decodersprovide an excellent solution.

By introducing the logiWIN IP coreinto your FPGA configuration, you caneasily handle decoded video signals interms of de-interlacing, scaling, and posi-tioning. The platform also provides themeans to create audio alarms in an emer-gency situation. To implement this, youcan use an embedded audio codec in com-bination with the logiI2S IP core. The plat-form-process communication can beestablished by using the on-board CANinterface and logiCAN IP core.

If you wish to connect the platform to aPC, you can do that through the platform’sRS 232 interface. To host all of this function-ality, logiCRAFT 3 utilizes a Spartan-3

XC3S1200E FPGA, which gives you enoughroom to develop the optimal configuration.

However, your actual final productionconfiguration may require less FPGAresources, so a smaller and less-expensiveFPGA would suffice. The logiCRAFT 3addresses this issue by providing pin-com-patible scalability between Spartan-3XC3S500E and XC3S250E FPGAs, thusdelivering an additional feature for tailoringyour final product.

ConclusionThe value of the LogiCRAFT 3 compactmultimedia display development platformfrom Xylon lies in the high number ofsupported display types; the innovativesystem architecture, small form factor, andbroad feature set; and the ability to beconfigured for performance, price, lowdevelopment, and production cost withvirtually no obsolescence.

Based on the Xilinx Spartan-3E family,with its low cost-per-gate and feature-richarchitecture, the logiCRAFT 3 provides anexcellent base on which to build.

For more information about theLogiCRAFT 3 compact multimedia displaydevelopment platform and logicBRICKSXylon IP library, please e-mail [email protected] or visit www.logicbricks.com.


SDRAM

FLASH

8

CAN

RS232

FPGA

Control

ButtonsGPIO Bus

logiCAN

I2C Controller

MicroBlaze

Processor

logi2D

logiWIN

logiMEM

logiCVC-ML

Touch Screen

ControllerTouch Panel

DISPLAY

logiUART

CAN Interface

RS232 Interface

PAL/NTSC/SECAM

Decoder

SAA7113A

Measured

Values

Surveillance/

Process

Monitoring

Camera

logiCRAFT 3

Audio Codec

TLV320AIC23

logil2S

Figure 6 – Platform/FPGA structure for industrial application

A U T O M O T I V E

by Kevin TanakaWorldwide Automotive Marketing and Product Planning ManagerXilinx, [email protected]

Over the past 10 years, in-vehicle network-ing architectures have become much morecomplex. Although the number of in-vehi-cle networking protocols has been reduced,the number of networks actually beingdeployed has increased dramatically. Thisleads to network architecture scalabilityissues and semiconductor device optimiza-tion to match each application and net-work’s actual needs.

FPGAs, once thought of as a solutionfor development purposes only, havecome down in price to the point wheremany issues can be resolved and put intoproduction at a lower overall system costthan the traditional ASIC or ASSP solu-tion. All of the major FPGA suppliers tothe automotive market are now ISO-TS16949 certified, making programma-ble logic devices a mainstream technologyin the automotive market.

In-Vehicle Network Electrical ArchitectureDuring the last ten years, many propri-etary OEM automaker networking proto-cols have made way for more standardizedglobal protocols like CAN, MOST, andFlexRay. This lets semiconductor vendorsconcentrate on building devices with thosespecific protocols built in, bringing morecompetition and lower prices to tier-onesand more module interoperability at theOEM level. However, in today’s vehicleelectrical architectures, both OEMs andtier-ones still struggle with many issues.

Engineers can partition and build net-working strategies in several different ways.High-end vehicles can have anywhere upto seven different network buses runningsimultaneously. For instance, a single vehi-cle could have a LIN loop for mirrors, alow-speed CAN loop at 500 Kbps for low-end functions like seat or door control, a

high-speed CAN loop at 1 Mbps for bodycontrol, another high-speed CAN loop fordriver information systems, a FlexRay loopat 10 Mbps for real-time driver assistancedata, and a MOST loop at 25 Mbps forcontrol and media streaming within oracross various infotainment systems likenavigation or rear-seat entertainment.

On the other hand, low-end vehiclesmay have no more than a single LIN orCAN loop, with all of the other modulesworking on their own with almost no inter-action. Each OEM automaker deals withinter-module communication and vehiclenetwork topology differently, and eachvehicle platform is different, making it dif-ficult for tier-ones to develop reusablemodule architectures with the correct inter-faces. Uncertainty of the final architectureinto which a module will go is an areawhere FPGAs excel.


Scalable and Flexible In-Vehicle NetworkingFPGAs and full IP solutions give automotive engineersoptions in optimizing their electrical architectures.

First appeared in Chip Design magazine, June 26, 2007. Copyright Extension Media. Reprinted with permission. A U T O M O T I V E


Because of their fixed hardware archi-tecture, ASICs, ASSPs, and microcon-trollers are usually either under- orover-resourced with no flexibility. The pro-grammability (and re-programmability) ofthe FPGA allows for the simple additionor subtraction of on-chip channels (forexample, channels of CAN), along withthe re-use of IP. With this flexibility, anoptimized solution for the number andtype of networking interfaces can be builtinto a module quickly.

Semiconductor Implementation of Network ProtocolsThe scalability of the FPGA for the num-ber and types of interfaces is not its onlymerit. In the case of ASSPs, ASICs, andmicrocontrollers, the peripheral macrosare implemented in hardware, makingthem inherently inflexible. In an FPGAenvironment, the networking interfaceIP itself can be optimized depending onthe IP being used.

For example, with Xilinx® LogiCORE™CAN or FlexRay networking IPs, userscan flexibly program the number of trans-mit and receive buffers along with thenumber of filters. In traditional hardwaresolutions, an engineer working with aCAN controller would typically only havethree configuration choices: 16, 32, or 64message buffers. The Xilinx scalableMOST network interfacing solutionincludes network controller IP that can beconfigured for either master or slave oper-ation and a host of IP, such as asynchro-nous sample rate converters (ASRC), datarouters, or encryption engines for copyprotection, depending on the level of sys-tem functionality and available processingoutside of the FPGA.

The IP allows for optimization and theability to push into lower density devicesfor low-end solutions and higher density

devices for high-end solutions, oftenusing the same package footprint on themodule target board. Also, for each mainprotocol, middleware stacks and drivershave been developed to round out thesolution. This type of scalability as well asthe versatility of an FPGA-based solutionis just not possible in a traditional auto-motive hardware solution.

All of the major FPGA vendors havesoft microprocessors that can be efficientlyimplemented in the fabric for control func-tions and can run at speeds that rival someof those embedded in hardware. Anothermajor advantage of the FPGA architectureis the ability to offload processing functionsfrom the microprocessor and partition byusing the parallel DSP processing capabili-ties found in either multipliers or hardMACs on-chip, increasing overall perform-ance and throughput.

We’ve Come a Long WayProgrammable logic devices have come along way in becoming a mainstream tech-nology in the automotive market. The fieldhas evened on the reliability side, andFPGA technologies are allowing scalableand flexible integration that has neverbefore been possible in traditional ASIC,ASSP, or microcontroller architectures.Overall production system costs arereduced because of shortened developmentcycles, advanced process technologies usedby programmable logic device vendors, andthe economies of scale that a programma-ble device inherently brings with it.

With the key IP and solutions for in-vehicle networking coming to fruition andthe added performance capabilities ofFPGA architectures, programmable logicdevices will become a major player in help-ing alleviate some of the engineering diffi-culties inherent in developing in-vehicleelectrical architectures.

• Download more information about the Xilinx Automotive NetworkingLogiCORE solution.

• Buy a Xilinx Automotive ECU Development Kit.


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Spartan™-3 GenerationDisplay SolutionsSpartan™-3 GenerationDisplay Solutions

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High Speed I/O Connector x4 Option Board: DVI Tx and Rx

FeaturesXilinx Device: XC3S1600E-FG484C, XCF08P-FS48Memory: DDR SDRAM 512Mb x 16bit x 4 (32bit x 2ch)Flash Memory: 16Mbit SPIInterfaces: RS-232C x1

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by Arthur YangTechnical Marketing Manager, Micro Scale DivisionXilinx, [email protected]

Asking for directions is becoming a foreignconcept. It’s fast dying out, much like theart of folding a map or a newspaper. Itsimpending extinction can be attributed tothe increasing popularity of the GlobalPositioning System (GPS).

GPS is present in a growing number ofproducts: automobiles, cell phones, person-al data assistants, even wristwatches. Witheach GPS vendor showcasing a product lineof several dozen GPS products, consumersare overwhelmed with the selection.

Therefore, success lies in product differ-entiation and specialization. Xilinx®

CoolRunner™-II CPLDs are the idealchips to add features or interface withanother device to make your GPS productstand out from the rest – without breakingthe power budget.

The Power AdvantageBoth portable and in-dash GPS devices mustadhere to a strict power budget.CoolRunner-II CPLDs have the advantageof minimal power consumption without theneed for sleep mode states. The smallestCoolRunner-II device has a quiescent powerof 13 µA. In some portable applications, asleep mode is sufficient and a wake-up timein the hundreds of milliseconds is acceptable.

In some cases, however, the currentdesign states are lost. When using sleepmode, your entire device shuts down. Youmust rely on a secondary device to poll forinterrupts and initiate a wake-up sequence.CoolRunner-II devices offer a unique sleepmode without the associated designheadaches through its DataGATE feature,a self-contained and user-configurable cir-cuit that allows you to disable as much ofthe device as you desire.

By enabling DataGATE, you can turnoff whichever inputs you choose in sever-al nanoseconds, thereby shifting thepower consumed by the CPLD closer to aquiescent state. This could be done peri-odically, such as when polling for an inter-rupt, or it could be dependant on a


Designing GPS Systems Using CoolRunner-II CPLDs

Designing GPS Systems Using CoolRunner-II CPLDsExpanding functionality using low-power CoolRunner-II CPLDs.Expanding functionality using low-power CoolRunner-II CPLDs.


particular state of operation. Thus, por-tions of the CoolRunner-II device canremain active while others are in standby.

Let’s look at an example to explain fur-ther. The CPLD sits on an address and databus between a microprocessor, mobileSDRAM, and SD flash card. Data movesbetween each of the devices. The CPLDmonitors the data activity and blocks traf-fic based on the particular function. If thecurrent task is to move data from themicroprocessor to the SD card, then theCPLD blocks any data to and from theSDRAM using DataGATE.

Within the CPLD, you can write codeto simply decode the function being per-formed (either from watching the addresslines or by parsing frame data) and thenenable/disable whichever data path isrequired. This is a trivial example that ispossible to a much lesser degree with otherprogrammable logic devices (PLDs) byusing output 3-states.

The advantage of DataGATE is that iteffectively 3-states at the input of theCPLD. Power savings increase because theCPLD I/O as well as core circuitry areplaced in a quiescent state, whereas alter-nate solutions require the entire PLD tostay in active mode.

The Security AdvantageGPS system pricing makes it an attractivetarget for product cloning. To help preventthis, you can utilize CoolRunner-II CPLD’sread/write protect security to implement asecurity system that prevents cloning byoverbuilding. Overbuilding occurs when acontract manufacturer orders extra compo-nents for a given production run and thenbuilds extra products that are identical tothe authentic versions.

The concept is that the system requiresinteraction with the CPLD to perform anydesired function. You can implement thissecurity in any number of ways. The moststraightforward solution would be to have aCPLD act as a data-traffic cop, directing databetween the individual devices on the board.

A more complex solution involves usingthe CPLD to implement a block cipher.This would have the microprocessor sub-mit a random stream of data to be encrypt-

blank CPLDs is not useful without accessto the programming file.

Achieving Product Differentiation in GPS UnitsOriginal consumer GPS units werestraightforward. They simply gave locationinformation in the form of latitude andlongitude. Today’s GPS units not only offerreal-time maps and directions, they offerMP3 playback or integration with cellphones via Bluetooth. There are also mar-ket-specific GPS systems with features suchas traffic updates for in-car navigation,

ultra-small units for runners or cyclists tomeasure their pace, units with sonar forfishermen – even GPS-enabled collars forkeeping tabs on the family pet.

Each product requires an interface tosomething different – and that’s where theCoolRunner-II CPLD is a perfect fit. Thefollowing topics demonstrate some uses forCoolRunner-II CPLDs. I’ve also listedassociated Xilinx application notes at theend of this article. Figure 1 demonstratesfunctions where Xilinx CPLDs can benefita GPS application.

ed by the CoolRunner-II device andreturned. This data would then be decrypt-ed and verified against the original data.

The CoolRunner-II CPLD’s security isimplemented through multiple program-ming bits, so someone attempting todetermine which bits are relevant forsecurity must find and disable several bitsout of tens of thousands in the non-volatile array. The security inCoolRunner-II CPLD read/write securityprevents readback and programming ontop of the existing pattern. So the device

will not permit extraction of the pro-grammed JEDEC file, nor will it allowsomeone to overlay a modified version ofthe code on top of an existing pattern. Toreprogram the device, the entire devicemust first be erased, in which case thedesign information is lost.

A critical factor in any of these flows isthat pre-programmed CPLDs must be pro-vided to the contract manufacturer from atrusted source (Xilinx or an authorizedXilinx distributor). This prevents over-building – because simply ordering more

Antenna

ADC

VCO OSC

Clock

Driver

SAW

Filter

SAW

Filter

Frequency

Synthesizer

LNA

DSP/

Microprocessor

CoolRunner-II

CPLD

Keypad Interface Flash Card

SD/CF

Memory

Controller

Interfaces

GPIO Port

Expansion

SM Bus, UART

SPI, I2C

Touch Screen

Thermometer

SPI Flash

Mobile

SDRAM

Figure 1 – GPS block diagram




SD Card InterfaceSD memory (in its various physical formatssuch as mini-SD and micro-SD) has sepa-rated from the pack of memory interfacesthat competed a few years back. Althoughother interfaces such as MMC andCompact Flash are still around, they repre-sent only a small percentage of the market.Flash cards are essential for any productwith picture or MP3 playback; both fea-tures are becoming more prevalent in GPShandheld units.

Mobile SDRAM InterfaceYou can simplify microprocessor code byallowing the CPLD to act as the memoryinterface. If your high-end model requiresmultiple memory modules but your low-end product does not, let the CPLD codechange, not your microprocessor.

Level TranslationAs GPS moves into newer consumer areas,they connect to components that are notyet optimized for low-voltage operation.CoolRunner-II CPLDs have a minimumof two I/O banks (increasing to four I/Obanks in the largest device), allowingmulti-voltage interfaces to be addressedeasily. Supported voltage standards include1.5 V, 1.8 V, 2.5 V, 3.3 V, SSTL 2-1, SSTL3-1, and HSTL-1. 5-V interfaces are sup-ported with some external circuitry.

Keypad ScannerMany of the lower end GPS models cannotuse a touch-screen interface because of costconstraints or size limitations. Even in theexpensive models, a few buttons are desig-nated for certain features such as power orvolume control. Some form of keypad orbutton interface is used in most models.This is an ideal use for CoolRunner-IICPLDs because when there is inactionfrom users, the CPLD remains in a quies-

cent state and can immediately respond toa user key press without having to wake upfrom sleep mode. Furthermore, it can bedesigned to verify user data before wakingup the rest of the system.

For example, many cell phones requirethat you press two keys in sequence beforewaking up to ensure that the buttonsweren’t accidentally pressed.

Microprocessor InterfaceA common role for CoolRunner-II CPLDsis port expansion. Many microprocessorssimply lack sufficient I/O for the multitudeof devices with which they must communi-cate. CoolRunner-II CPLDs allow a productplatform design to add and change moduleswithout changing the core processor.

Serial Peripheral Interface (SPI)SPI is a common interface used by manyperipherals, including flash storage chips,LCDs, touch screens, and temperature sen-sors. Its popularity can be attributed to asimple four-wire interface and improvedthroughput over I2C or SMBus.

ConclusionXilinx CoolRunner-II CPLDs demonstratetheir usefulness in lowering power, increasingsecurity, and providing connectivity solutionsfor today’s GPS systems. With our portfolioof small form-factor packages, these devicescan fit into the smallest portable packagessuch as cell phones, dog collars, and wrist-watches. Personally, I can’t wait until theyembed a GPS into car keys.

• Start evaluating CoolRunner-II CPLDs for your GPS application and purchase the CoolRunner-II Design Kit.

• Learn more from these Xilinx application notes:

• XAPP347, “Decreasing Processor Power Consumption using a CoolRunner-II CPLD”

• XAPP395, “Using DataGATE in CoolRunner-II CPLDs”

• XAPP906, “Interfacing with Multiple SD Devices with CoolRunner-II CPLDs”

• XAPP398, “CompactFlash Card Interface for CoolRunner-II CPLDs”

• XAPP394, “Interfacing to Mobile SDRAM with CoolRunner-II CPLDs”

• XAPP785, “Level Translation Using Xilinx CPLDs”

• XAPP512, “Implementing Keypad Scanners with CoolRunner-II”

• XAPP799, “An SMBus/I2C Compatible Port Expander”

• XAPP341, “UARTs in Xilinx CPLDs”

• XAPP386, “CoolRunner-II Serial Peripheral Master”


Xilinx CoolRunner-II CPLDs demonstrate their usefulness in lowering power,increasing security, and providing connectivity solutions for today’s GPS systems.

With our portfolio of small form-factor packages, these devices can fit into thesmallest portable packages such as cell phones, dog collars, and wristwatches.


by Mark NgApplications EngineerXilinx, [email protected]

One of the most critical factors in design-ing handheld, portable electronics today isreducing overall system power consump-tion. With increased consumer expecta-tions, portable devices require longerbattery life and higher performance. Evenpower reductions on the order of 10 mWare crucial to portable system designers andmanufacturers.

Several design techniques are used bydesigners today to significantly reduce over-all system power consumption, such as:

• Reducing operating voltage

• Optimizing system and CPU clock frequency

• Eliminating spikes of large current consumption during the power up sequence

• Efficiently managing system battery operation

• Efficiently managing operating mode of system devices

• Minimizing bus activity

• Reducing bus capacitance

• Reducing switching noise


Decrease Processor Power Consumption Using a CPLDDecrease Processor Power Consumption Using a CPLDUtilizing a CPLD to offload operations from the system microprocessor keeps the processorin a power saving mode longer and contributes to significant power savings.Utilizing a CPLD to offload operations from the system microprocessor keeps the processorin a power saving mode longer and contributes to significant power savings.

First appeared in Electronic Component News (http://www.ecnmag.com). Copyright Advantage Business Media. Reprinted with permission.


These are just a few examples of designtechniques for reducing the power con-sumption in any end application.

One of the most important power sav-ing techniques mentioned in this list is theability to manage the operating mode ofdevices in the system. Many manufacturerstoday offer devices with power savingmodes that temporarily suspend the devicefrom its normal operation. These deviceshave the option to power down or transi-tion to a non-functioning state if the deviceis not active for a specific amount of time.This feature is available on many of today’smicroprocessors and microcontrollers. Bytaking advantage and managing the operat-ing mode of large power consumers on aPCB, such as the processor, the overallpower consumption of the system can bereduced significantly.

Reducing power consumption not onlyinvolves correct management of the operat-ing mode of a device, but designing a sys-tem to take advantage of the modes adevice can operate within. Offloadingoperations of the microprocessor allows itto stay in its low-power state for a longeramount of time. One way to reduce systempower is to allow a low-power programma-ble logic device, such as a CPLD, to man-age these offloaded operations. This articlewill describe this possibility, along withtypes of operations that allow a processor toremain in a low power state longer, therebyreducing system power consumption.

Microprocessor Operating ModesIn some portable applications, the CPUcan consume 30% of the overall systempower. Figure 1 illustrates the typical powerconsumption of system components in aWeb Pad application.

Microprocessor power consumptioncan range from 720 uW to 1 W duringnormal operation. Microprocessor operat-ing modes vary by part and manufacturerand include modes such as Normal, Run,Sleep, Suspend, Standby, Stop, and Idleoperation. Operating modes can vary inpower consumption as much as 230 mWbetween states. Normal operation ofsome low power microprocessors can beas little as 250 mW.

Sleep. In Normal operation, the CPU isfull-on, with the device fully powered andreceiving active clocks. In Idle mode,even though power is applied to the CPUand other components, all clocks to theCPU are stopped, with only clocks toperipheral devices active. In Sleep mode,power to the CPU and other peripheralcomponents is disabled. Sleep mode dis-ables all functions except the real-timeclock, interrupt controller, power manag-er, and general purpose I/O.

Operating Mode ControlMicroprocessors with power saving modeshave an on-board power management con-troller. Operating modes allow the operat-ing system or software application totemporarily suspend the CPU. The micro-processor executes a series of instructions tobe placed into a power saving state. Oncein a power down mode, several compo-nents of the microprocessor can stillrespond to system interrupts.

For example, the Idle mode of theStrongARM SA-1110 processor saves sig-nificant power, but certain modules remainpowered, such as the LCD, memory, andI/O controllers. Even though the clock tothe CPU is stopped, peripheral modulesare still active. The Idle mode can still con-sume a significant amount of power, on theorder of 100 mW. By placing the processorinto the Sleep mode, only active modulesare powered to respond to interrupts andwake up signal requests. Sleep mode con-sumes even less power than Idle mode; cur-rent consumption can be less than 100 mA.

ExampleNote: The microprocessor reference pro-vided is an example to illustrate the powerconsumption in different operating modes.Since no standard method exists to deter-mine power consumption, the data provid-ed in this document is based on dataprovided by the manufacturer and is to beused for reference only. Please see“References” for more information.

To illustrate the difference in powerconsumption of operating modes in amicroprocessor, an example is provided.Figure 2 illustrates the power consumptionof the Intel StrongARM SA-1110 micro-processor operating modes. The power dis-sipation numbers shown in Figure 2 aredetermined by operating at 206 MHz witha nominal external voltage supply of 3.3 Vand internal voltage supply of 1.8 V.

Operating modes of the StrongARMprocessor include Normal, Idle, and


30%

20%

Sleep

<50 uA

Idle

<100 mW

Normal

<400 mW

Figure 1 – Web Pad power consumption

Figure 2 – Intel StrongARM SA-1110 power consumption


For a microprocessor to return to nor-mal operation from a power down mode,an event must occur. The followingevents can wake up the processor, butvary based on manufacturer, part, andcurrent operating mode:

• Hardware reset

• System interrupt

• General-purpose I/O interrupt

• Real-time clock interrupt

• OS timer interrupt

• Peripheral interrupt

• External wake-up signal

Upon recognition of an enabled wake-up event, the microprocessor will begin aseries of steps to wake up from a powerdown state. Figure 3 illustrates the generalflow for a processor waking up from apower down mode.

CPLD DesignOperating modes are utilized when themicroprocessor is idle for a specificamount of time. When a microprocessorreceives an enabled interrupt, the proces-sor will respond to the interrupt request.When the processor is responding to theinterrupt, it will operate in its run or nor-mal mode. Reducing the number of inter-rupts to the processor will increase thetime the processor is in a power savingstate. Ideally, if the microprocessor doesnot have any instructions to execute, it willremain in a power saving mode forever.Inserting an external device to respond andhandle system interrupts can reduce theoperations required of the processor. Byallowing the microprocessor to stay in itspower down mode as long as possible, sig-nificant power savings can be realized.

Utilizing a low power programmablelogic device to supplement the micro-processor will save system power andincrease system battery life. The industry’slatest CPLD offerings simultaneouslydeliver high performance and low power

consumption. Standby current of a typicallow power CPLD is less than 100 uA.Figure 4 illustrates using a reprogrammableCPLD to interface to incoming systeminterrupts. Utilizing an external data acqui-sition device to offload interrupt requestsrequired of the microprocessor will reduceoverall system power.

System InterruptsDepending on the end application for theprocessor, a variety of external devices mayinterrupt the processor. These interruptsinclude both data acquisition and data pro-cessing requests. By separating data pro-cessing interrupts to the microprocessor,data acquisition interrupts can now be serv-iced by the external CPLD. Utilizing aCPLD to handle data acquisition interruptswill offload interrupt requests to the micro-processor and save power.

Categorization of the type of data acqui-sition interrupts to the CPLD will dependon the end application. Peripheral devicesor incoming data demanding a response toincoming data can be classified as data


Sleep

Mode

Wake up event

Wait

(WDT Count)

Clock

Applied

Status Bits

Updated

Normal

Operation

CPLDExternal Interrupts

(Data Acquisition)

Remote Data

Processor

(Data Processing)

System

Components

Inserting an external device to respond and handle system interrupts can reduce the operations required of the processor.

By allowing the microprocessor to stay in its power down mode as long as possible, significant power savings can be realized.

Figure 3 – Wake-up sequence Figure 4 – System block diagram



acquisition interrupt requests. Data acqui-sition interrupts include:

• Memory access interrupts

• Communication interfaces such as I2C,UART, SPI, or ISA

• General-purpose I/O interrupts

• LCD interface interrupts

This is not a complete list of interruptsthat can be processed by the CPLD, but pro-vides a starting point for the system design.

Operational FlowFigure 5 illustrates the main operationalflow for the design of a CPLD. Once avalid external interrupt is recognized by theCPLD, it will determine if it contains thefunctionality to process the interrupt.Once the CPLD has processed the inter-rupt, it can assert an interrupt to theprocessor for any data processing requestsneeded. If the CPLD is unable to processthe interrupt, the interrupt is passed to theprocessor. The CPLD also monitors theoperating state of the processor.

FunctionalityThe low-power CPLD design consists of aninterrupt interface and controller to handleinterrupt requests, the functionality toprocess the interrupt, and a processor inter-face. The main functions of the CPLD aredescribed in more detail next and separatedas follows:

• Interrupt interface for system devices

• Interrupt controller

• Interface with peripheral devices forinterrupt processing

• Microprocessor interrupt interface

• Microprocessor operating mode interface

Interrupt InterfaceThe interrupt interface of the CPLDreceives all external device interruptrequests previously recognized by themicroprocessor. The interrupt interfacedetermines if the CPLD is capable of pro-cessing the interrupt request. The CPLDhandles data acquisition interrupts that

request data receiving and storage capa-bilities. If the CPLD is unable to processthe interrupt, the interrupt is passed tothe microprocessor.

The CPLD interrupt interface providesthe masking capability for all interruptsources and the ability to determine theinterrupt source. Programmable logic pro-vides flexibility to change the trigger mode,which includes a high or low level andfalling or rising edge sensitivity. The CPLDinterrupt control registers are similar to theregisters in the microprocessor.

Interrupt ControllerThe CPLD interrupt controller emulatesthe functionality that exists in the systemmicroprocessor. The interrupt controllerinterprets from which device the dataacquisition interrupt was received and ini-tiates the processing of the interrupt. TheCPLD processes the data acquisition inter-rupt request that would have otherwiseinterrupted the microprocessor.

The interrupt controller initiates theaction to process the request. An example ofthis is an application where the CPLD isreceiving data from a remote device. Thedevice is requesting to write the data beingsent into memory. The CPLD interruptcontroller recognizes a valid interrupt andinitiates the memory interface to interpretthe data.

Peripheral Device InterfacesThe CPLD provides the interface to systemdevices that are needed in processing inter-rupt requests. Device interfaces that are need-ed are dependent on the end application.When an external device interrupts theCPLD to read or write data into a memorycomponent, that particular memory interfaceis needed in the CPLD design. The types ofinterfaces needed can range from memoriesto LCD interfaces to communication inter-faces such as PCI, UART, SPI, and ISA.

Microprocessor Interrupt InterfaceThe CPLD, like any external device request-ing services of the processor, has the capabil-ity to interrupt the microprocessor. TheCPLD must be able to interrupt the micro-processor once a data acquisition operation iscomplete. The designer has the option to setthe priority level of interrupt requests fromthe CPLD and whether or not interruptsreceived from the CPLD will wake theprocessor from a power down state.

Microprocessor Operating Mode InterfaceDepending on the system microprocessor,the CPLD will be able to recognize theoperation state of the processor. Somemicroprocessors provide external pins thatrepresent the current operating mode.Depending on the CPLD and microproces-sor design, the CPLD could recognize thecurrent operating state of the processor anddetermine whether to assert an interrupt tothe processor to execute a waiting interrupt.For example, if a low priority interrupt isreceived by the CPLD and the processordoes not need to transition from its lowpower state, the CPLD can create a registerindicating pending interrupts. Then whenthe processor wakes, the interrupt pendingregister can be read by the microprocessor.

External

Interrupt

?

CPLD

Handle

Interrupt

?

No

No

N

Yes

Wake

Processor

?

Process

Interrupt

Interrupt

Microprocessor

Microprocessor

Data Processing

Yes

Yes

Figure 5 – CPLD flow diagram


BenefitsFigures 6 and 7 illustrate the power savingsthat may be realized in a typical battery-operated device using a leading-edge, low-power CPLD (Figure 7) versus a standalone microprocessor design (Figure 6). Thepower requirements of the CPLD are mini-mal compared to the power savings realizedby keeping the microprocessor in its lowpower modes for a longer amount of time.Standby current of a typical low powerCPLD is on the order of 100 uA. The oper-ating power consumption depends on theapplication and clock frequency. For a 64-macrocell CPLD fully populated with 16-

bit counters and a 50-MHz clock, ICC isaround 10 mA. Note that the actual powersavings realized will depend on the systemdesign, including the type of microproces-sor and the CPLD design.

Along with power savings attained usinga CPLD, interrupt response time is reduced.The peripheral device no longer has to waitthe delay time for the microprocessor towake from a power saving state. Additionaldesign savings can be realized and include:

• Reducing the number of interruptionsto the processor

• Reducing the number of processorwake-up cycles over a length of time

• Reduction of clock frequency withoutimpact on throughput

• Running the processor at a lower fre-quency for data processing operations

• Running the CPLD at a higher fre-quency for data acquisition operations

ConclusionDesigning a power-sensitive applicationinvolves not only using software for powermanagement, but utilization of hardwaredesign techniques. Designing a low-powerCPLD to keep a microprocessor in a lowpower operating state longer can signifi-cantly reduce system power consumption.The latest CPLDs on the market todayoffer a flexible combination of low powerand high speed for any end application.


Normal

Idle

100%

Operating Time

Sleep

Pow

er

Consum

ption

Normal

Idle

100%

Operating Time

Sleep

Pow

er

Consum

ption

CoolRunner CPLD

Figure 6 – Stand-alone processor power consumption

Figure 7 – Power consumption of processor and CoolRunner-II CPLD

References

Intel StrongARM SA-1110 MicroprocessorDeveloper’s Manual. June 2000.

DragonBall Power Management. Motorola Semiconductor Application Note. Motorola, Inc. 1998.

Geode GX1 Processor Series Low PowerIntegrated x86 Solution. NationalSemiconductor. October 2000.

Turley, Jim. Microprocessors for ConsumerElectronics, PDAs, and Communications.

Microprocessor Report. September 1999.

EDN Access. 27th AnnualMicroprocessor/Controller Report. September 2000.

Xilinx Global Trade Show

CalendarXilinx participates in numerous

trade shows and events through-out the year. This is a perfectopportunity to meet our silicon

and software experts, ask questions, see demonstrations

of new products, and hear other customer success stories.

For more information and themost current schedule, visit

www.xilinx.com/events/.

.

North America

January 7-10, 2008Consumer Electronics Show

Las Vegas, Nevada

April 14-17, 2008National Association

of BroadcastersLas Vegas, Nevada

April 15-17, 2008Embedded Systems Conference

San Jose, California

Europe

February 11-14, 20083GSM

Barcelona, Spain

February 26-28, 2008Embedded WorldMunich, Germany

Xilinx Global Trade Show

CalendarXilinx participates in numerous

trade shows and events through-out the year. This is a perfectopportunity to meet our silicon

and software experts, ask questions, see demonstrations

of new products, and hear other customer success stories.

For more information and themost current schedule, visit

www.xilinx.com/events/.

.

North America

January 7-10, 2008Consumer Electronics Show

Las Vegas, Nevada

April 14-17, 2008National Association

of BroadcastersLas Vegas, Nevada

April 15-17, 2008Embedded Systems Conference

San Jose, California

Europe

February 11-14, 20083GSM

Barcelona, Spain

February 26-28, 2008Embedded WorldMunich, Germany

R


by Mark NgStaff Applications Engineer, CPLD Applications EngineeringXilinx, [email protected]

There has been an increasing demand toadd multiple Secure Digital (SD) devicesin a single system. The problem, however,is that most host devices/processors – forexample Intel PXA270, TI OMAP, orQualcomm MSM processors – only pro-vide a single SD interface. Fortunately,Complex Programmable Logic Devices,otherwise known as CPLDs, can be usedto allow host devices to support any num-ber of SD devices. This article details ascalable, auto-sensing bi-directional mul-tiplexer-based design.

Figure 1 shows a generalized CPLDusage model to incorporate any number ofSD ports for a given host device that only

has a single native SD interface. The CPLDis placed between the host controller andthe SD devices. As such, the CPLD partperforms a bi-directional multiplexingfunction, allowing the host to communicatewith any selected SD device. More impor-tantly, this design has no directional controlpins, which means that the CPLD auto-matically detects the direction of data flow.

This implementation is extremely flexi-ble and scalable, meaning that the numberof SD ports can be increased or decreasedas desired. The design also supports any ofthe defined SD card modes – SPI, 1-bit, or4-bit data modes.

While the primary purpose of using aCPLD device in this type of application is toprovide additional SD ports to the host con-troller, secondary benefits include leveltranslation and logic isolation between thehost and the SD card. Figure 1 shows thecase where the host is 1.8 V but the SDDevices are 3.3 V. The industry’s latestCPLDs provide negligible standby currentand ultra-low dynamic power consumption.Hence, incorporating a complex program-mable logic device in your system will notsignificantly impact your power budget.

Compliance with the SDA SpecificationThe SDA (Secure Digital Association)specification states that one SD bus canonly support one SD device. The clock pincan be shared, but the DAT[3:0] andCMD lines must be unique for every SDdevice. See Figure 2 for additional details.

This reference design is fully compliantwith the SDA Specification. The followingsection will show you how to satisfy theabove requirements while supporting anynumber of SD devices using a controllerwith a single bus.

CPLD DesignA block diagram showing typical use ofthis design for two SD devices sharing thesame SD host interface can be seen inFigure 3. Conceptually, the design can beviewed and used as a bi-directional multi-plexer. The host device controls the


Supporting Multiple SD Devices with CPLDsCreating an SD multiplexer using CPLDs.

First appeared in PLD DesignLine (http://www.pldesignline.com). Copyright CMP Media LLC. Reprinted with permission.

SD

Device

CoolRunner-II

CPLDHost Controller

(ASIC or uP)SD

Device

3.3V

Select Lines

1.8V

Figure 1 – Using CoolRunner-II CPLDs to provide additional SD ports


CPLD via the ‘Select’ signals, thereby dic-tating which SD device to communicatewith. Once an SD device has been select-ed, the logic in the CPLD device auto-matically detects the direction of data flowand allows data to stream accordingly(either from the host to the SD card orfrom the SD card to the host). A direc-tional control pin is not required, therebymaking this design easy to use.

The host can access each SD deviceindividually without affecting the state ofthe other when the multiplexer is switchedaccordingly. If neither the host nor the SDis driving data, the CPLD allows the sys-tem to be in the default high impedancewith weak pull-up state. The primary pur-pose of this circuit is to provide additionalSD capability to the host, but this circuitcan also be used to provide level translationand/or logic isolation.

Implementation DetailsFigure 4 shows the actual logic circuit for a1:2 bi-directional multiplexer design, whichcan be described using VHDL. In the initialcondition or idle state, the Host and SDcards should be high impedance with a weakpull-up. Hence, the circuit in Figure 4 isdesigned to 3-state the CPLD’s outputbuffers, thereby allowing the external pull-upresistors to take effect. Register A (A_REG)and Register B (B_REG) are both designedto be initialized to logic ‘0’ upon power-up.

The SD cards are selected via the ‘Select’inputs to the CPLD. When ‘Select’ is logic‘0,’ SD1 is chosen and when ‘Select’ is logic‘1,’ the SD1 device is chosen. For simplici-

the clock input of A_REG. After clocking,A_REG’s Q output becomes logic ‘1’ andtherefore prevents B_REG from receiving aclocking event. In parallel with the A_REGclocking and triggering, gate B1 outputs alogic ‘1’ when A goes Low. This enables the‘B’ Output Buffer and, ultimately, B willfollow A and drive Low.

Conversely, when it is driven from Lowto High, gate B1 outputs a Low and 3-states the B output buffer. This forces B togo High via the external pull-up resistor.Once the A and B sides are both High,A_REG and B_REG are reset to 0. Thisprocess is repeated indefinitely. The reverse

ty while describing this circuit, let’s assumein the following discussion that the Host isonly choosing to communicate with SD1.

The auto-directional control aspect ofthis design is implemented in the followingmanner – a transaction is initiated wheneither the host or SD1 drives Low. Forexample, if the host wants to send data tothe SD1 device, the host would begin bydriving the A side Low. Upon driving Low,the logic in the circuit detects the Lowgoing edge and responds by enabling the ‘B’output buffer, but continues to keep the ‘A’output buffer disabled. Specifically, when Ais driven Low, a rising edge is delivered to

SD Memory

Card (A)

Host

CLKCLK

VDDVDD

VSSVSS

D0-3, CMD

CLK

VDD

VSS

D0-3, CMD

D0-3(A)

CMD(A)

D0-3(B)

CMD(B)

SD Memory

Card (B)

SD Bus

SD 1

SD 2

CoolRunner-II

CLKCLK

SD

Hos

t Con

trol

ler

Bid

irect

iona

l MU

X

CMDDAT0DAT1DAT2DAT3

CMDDAT0DAT1DAT2DAT3

CMDDAT0DAT1DAT2DAT3

CLK

SD Bus 1

SD Bus 2

SD Select 2

SD Select 1

A

B

Q D

A_REG

SEL

R

QD

B_REG

SEL

SD1

SD2

R

SEL

QD

R

SEL

Figure 2 – SD system bus topology Figure 3 – Block level diagram: A bidirectional multiplexer

Figure 4 – SD multiplexer circuit for two SD devices



happens when SD1 attempts to drive datatoward the host. Additionally, if the hostwishes to communicate with the SD2device, the ‘Select’ inputs to the circuit areset to a logic ‘1’ and the sequence of eventsare similar to the above.

Design VerificationSimulation ResultsFunctional and timing simulations havebeen extensively performed on this circuitusing ModelSim, and test stimuli have beenincluded with the reference design. Figure 5shows some simulation results.

In the first part of Figure 5, the Selectinput is held Low. A dotted white linedenotes a “Weak 1” condition, or in otherwords, represents a pulled-up state. In thefirst transaction, the host attempts to drivedata toward SD1, and SD1 follows accord-ingly. Immediately after, the SD1 deviceattempts to drive data toward the host, andthe host follows. Similar events happenwhen the Select input is driven Low. Thehost drives data toward the SD2 device, thenthe SD2 device drives data toward the host.

Hardware ResultsXilinx created an SD Multiplexer demoboard, and has used this board to verify thisbi-directional multiplexing design. Figure 6shows the demo board, which features aCoolRunner™-II XC2C32A CPLD locatedin the center. Two SD card sockets are locat-ed along the top edge of the board. The bot-tom-most portion of the board is designed tomimic the physical dimensions of an SDcard. Figure 7 shows the demo board pluggedinto a USB SD card reader. As expected, theXC2C32A allows a PC to communicate witheither the first or second SD card flawlessly.

Device UtilizationTable 1 shows device utilization statisticsfor various implementations. As stated inthe SDA specification, there are three sig-naling modes defined for SD cards: SPIMode, 1-bit SD Data Transfer Mode, and4-bit SD Data Transfer Mode. This designcan be easily adapted for any chosen mode.The design can also accommodate anynumber of SD expansion ports, withdefault VHDL code set to two ports.

Voltage and Current ConsiderationsThe SDA specification contains strin-gent voltage and current requirementsfor SD cards. Programmable logicdevices are ideal for this applicationbecause they are extremely low powerand have features such as I/O Banking.The I/Os can be configured as 1.5 V, 1.8 V,2.5 V, or 3.3 V, allowing them to inter-face to any SD device. CPLDs also con-tain I/O Banks, which allow for voltagetranslation capabilities between theprocessor and SD card.

The extremely low power nature ofmodern complex programmable logicdevices allow for standby operation as lowas 15 µA. The addition of a low powerCPLD in a system will minimally impactthe current budget.

VHDL DownloadThe VHDL files to compile and simulatethese designs are located at:www.xilinx.com/products/silicon_solutions/cplds/resources/coolvhdlq.htm.

ConclusionAs SD devices gain in popularity, the needwill increase for ways to support morethan one SD device with host controllers.This article provides a verified solution tothe problem at hand. This solution willgive designers the flexibility to implementtwo or more SD devices into a system.

Number of Device Macrocell Utilization Macrocell UtilizationSD Expansion Ports (SPI or 1-Bit Data Mode) (4-Bit Data Transfer Mode)

1 XC2C32A 13 Macrocells 19 Macrocells



Figure 5 – Simulation results

Figure 6 – Xilinx SD multiplexer demo board

Figure 7 – Xilinx demo board plugged into a USB SD card reader

Table 1 – Device utilization statistics for various implementations



by Mark NgStaff Applications EngineerXilinx, [email protected]

Portable consumer electronic designs suchas cell phone handsets, PDAs, and MP3players are typically very high-volumeproducts. Because of this, product design-ers look first to ASIC or ASSP methodolo-gies to pack the greatest functionality intotiny, portable packages.

This solution “hits the mark” for densefunctionality and usually has acceptablepower consumption. But the consumerworld is rapidly changing – features envi-sioned at one point in time can becomeobsolete within a matter of months, ascompetitors react to ever-changing tech-nologies and market dynamics to deliverdifferentiated solutions.

The term “cutthroat” is frequently usedto describe this level of competition.Mistakes are not tolerated, and mistakes areexpensive. Choosing the correct ASSP ordesigning an ASIC correctly every time isnearly impossible. Mitigating these circum-stances is crucial to sustaining market share.

Today’s designers are now lookingbeyond the fixed architecture of ASICs andASSPs to discover the innate design flexibil-ity and time-to-market benefits of program-mable logic. Xilinx® CPLDs offer portabledevice designers a viable alternative to stan-

dard cell technology, providing one of thelowest cost, lowest power CPLDs in theindustry with CoolRunner™-II devices.

Since 2001, the Xilinx CoolRunner-IICPLD family has provided designers withpricing low enough to beat that of discretelogic devices, allowing designers to easilyimplement a wide variety of logic func-tions in a single package. In this article, I’lldemonstrate ways to expand beyond thelimitations of today’s ASIC/ASSP portablehandset solutions, with simple, cost-effec-tive, low-power programmable logic usingCoolRunner-II CPLDs. As most handsetsare OMAP-, XScale-, or i.MX-baseddesigns, I’ll describe solutions to severalspecific problems, with links to applicationnotes that provide in-depth details.

Level TranslationInterfacing two chips of different voltagestandards is a common problem. Everytype of memory is not made at every volt-

age standard, and microprocessors areoffered at many voltages. Matching stan-dards can be as simple as introducing leveltranslators, but they are expensive andtake more area than might be desired.Using a CPLD is a better solution andoffers substantially greater flexibility. AllCoolRunner-II CPLDs are capable oftranslating between two voltages, andsome can handle as many as four.

CoolRunner-II CPLD I/O banks easilytranslate between voltages ranging from1.5 V to 3.6 V in a single chip, as shown inFigure 1. But this totally disregards the pro-grammability of the devices. You get thetranslation as part of the whole package,which means you get a bundle of logic,flip-flops, power reduction resources, andI/O buffers frequently priced below leveltranslator chips. XAPP785 explains thedetails on taking advantage of this powerfulfeature to expand the capabilities of yourOMAP, XScale, or i.MX designs.


Designing Portable Handsets Using CoolRunner-II CPLDsCPLDs can improve processor-based handsets.


Pin ExpansionHigh pin-count ASICs are more expensivethan low pin-count ASICs, in general. Ifyour logic needs dictate a low capacity butyour I/O requirements dictate a highcapacity, you may be paying for logic youwill never use to gain the pins. One solu-tion to this is adding a CoolRunner-IICPLD to operate as a “pin expander,” asshown in Figure 2.

The basic idea is to identify GPIO pinsthat typically operate at a slow speed. Then,rather than assign ASIC pins to them,attach CoolRunner-II CPLD pins tothe slow-moving GPIO signals, seri-alize the signals, and import them tothe ASIC on fewer net pins.Serializing/deserializing is donethrough simple, efficient shifting,and can drop the pin counts dramat-ically on expensive ASICs. Xilinxapplication note XAPP799 showshow to do this through an I2C port,but you can use other methods.

As an alternate viewpoint,OMAP, XScale, and i.MX processorsprovide specific pin mixes to supportthe applications their vendors deemappropriate. This doesn’t mean thatyou must agree. CoolRunner-IICPLD pin expansion permits you tocreate your own GPIO pins ofassorted voltages and additionalcapabilities (pulsing, PWM, individ-ually 3-stated).

Pin SwizzlingCPLDs offer the ability to rearrangeyour pinouts when PCB layouterrors occur. This valuable quality iskey to keeping you on schedule andwithin financial and power budgets.Correcting misconnections on aboard without having to re-spin thePCB can shave weeks to months offof product schedules.

CoolRunner-II CPLDs are builtfrom powerful logic blocks usingprogrammable logic arrays that canreassign pin logic at will. You will beamazed at how well these devicesretain pinouts through multipleedits yet permit re-assigning a design

be sequenced by CoolRunner-II CPLDs, aswell as other controlling signals that needto be well defined early in board operation.Xilinx application note XAPP436 describessome of these capabilities.

Power ReductionXScale-, OMAP-, and i.MX-based chipsetsall include some version of the ARMmicroprocessor. This is not a surprise.Advanced RISC machines started earlywith developing low-power methods tooperate microprocessors. Subsequently, the

licensing vendors have all addedtheir own methods to further reduceprocessor power. Typical powerreduction operations include clockgating, voltage throttling, and on-board memory management toreduce transfers within the device.These are sometimes referred to asrun, wait, doze, sleep, and hibernate.

Also, operating systems likeSymbian have added “power aware-ness” to the mix, so that unusedresources can be parked in the lowestpower mode possible for the currenttasks being executed. This all workswell and lowers processor power.However, lowering power in the restof the system exceeds the scope ofthese methods.

Enter CoolRunner-II CPLDs.CoolRunner-II CPLDs are designedto be inherently low-power parts.That is important, but alone is notenough. CoolRunner-II special fea-tures also can be used to lower thepower in other devices. Using clockdividers and Xilinx DataGATEtechnology can reduce power inmany (if not all) of the chips onyour design, as shown in Figure 3.Blocking power to other chips canalso reduce electromagnetic fieldsbeing propagated on your boardand emanating from your system.This powerful signal blocking tech-nique can pay off in many ways.

Logic ConsolidationHaving three two-input AND gates,two three-input OR gates, and a

onto different pins as needed. TheCoolRunner-II family data sheet explainsthe architecture and points you to applica-tion notes that give all the detail you willneed to understand the value of PLAs.

Power Control Quick power up is one of the strengths ofCPLDs. Containing their own configura-tion cells permits CoolRunner-II CPLDsto power up and direct the activities ofother chips as they subsequently arise. Thisincludes some power regulators, which may


TI

OMAPFabric

Ban

k1

Ban

k2

CoolRunner-II CPLD

Intel

PXA 850

XScale

CoolRunner-II CPLD

DRAM

SRAM

I/O

EPROM

DataGATE Blocking

CoolRunner-II

CPLD

i.MX

Processor

Figure 1 – CoolRunner-II CPLD-level translation of TI OMAP signals

Figure 2 – CoolRunner-II CPLD pin expansion of XScale processor

Figure 3 – DataGATE blocking extraneous switching to various devices


Schmitt buffer package on your board canburden your bill of materials (BOM), eataway at your power and cost budgets, andlower your reliability. Collecting that straylogic into a consolidated, low-powerCoolRunner-II not only solves these prob-lems but stores additional unused logic rightthere on your board – ready to use withfuture improvements/edits. WP214 showswhat you can expect from collecting logicgates/flip-flops into CoolRunner-II CPLDs.Table 1 summarizes the “burn rate” for logic.

ConclusionCoolRunner-II CPLDs are quicklybecoming the standard for low-power,low-cost, high-volume, portable con-sumer products. This article has focusedon how these powerful products canmake life easier when building systemswith OMAP, XScale, and i.MX proces-sors, but CoolRunner-II CPLDs workjust as well with many other processors toadd functionality, save power, and getproducts to market fast.


• Read the application note, “Level Translation Using Xilinx CoolRunner-II CPLDs.”

• Read the application note, “An SMBus/I2C-Compatible Port Expander.”

• Read the application note, “Managing Power with CoolRunner-II CPLDs.”

• Read the application note, “Using CoolRunner-II Advanced Features” to learnhow to do signal blocking.

• Read the white paper, “The Real Value of DataGATE” to learn how muchpower you can save with DataGATE.


Function Macrocells P-Terms Flip-Flops

Shift Register (Simple) 1 per bit 1 per bit 1 per bitCounter (Simple) 1 per bit 1 per bit 1 per bit2:1 Mux 1 2 04:1 Mux 1 4 08:1 Mux 1 8 08-bit Loadable Shifter 8 16 88-bit Loadable/SL/SR Shifter 8 24 88-bit Loadable Counter 8 16 88-bit Load/Up/Dn Counter 8 24 8Full Adder / Bit 2 7 0/1 (optional)2:4 Decoder 4 4 03:8 Decoder 8 8 04:16 Decoder 16 16 08-bit Equality Comparator 1 16 0And/Nand Gate (1-40 Inputs) 1 1 0Or/Nor Gate (1-40 Inputs) 1 11 0Ex-Or/Ex-Nor (2-3 Inputs) 1 2-3 0Level Translator (Per Bit) 1 1 0

Table 1 – Macrocell “burn rate” for common TTL functions


by Arthur YangTechnical Marketing Manager, Micro Scale DivisionXilinx, [email protected]

You shake your head in frustration as youstare at the flat line on the oscilloscope. Forthe umpteenth time, you shuffle throughthe data sheets on the table and check theinput waveforms and pin connections. Theclock ticks past six; with a sigh, you reachfor the phone. Another late evening withsoldering irons, neon-colored scope traces,and takeout pizza. What a way to spend aFriday night.

Prototyping with a new device doesn’thave to be such a headache. Imagine a full-featured design kit that is easy to use andinexpensive. It would have a number of dif-ferent visual outputs, LEDs for status val-ues, numeric displays for counters and statemachines, and character displays for textmessages. It would have several I/O portsto test interface standards and peripherals,and user interface buttons and switches. Itwould be easy to get power readings. Itwould interface to a PC so the softwareguys could interact with it. And it would tobe cheap enough to not even cause a blipon the budget.

Working together, Xilinx and DigilentInc. have partnered to create the newCoolRunner™-II Starter Kit, makingwhat you once imagined a reality.


Easing Design Challenges with CoolRunner-II CPLDsEasing Design Challenges with CoolRunner-II CPLDsThe CoolRunner-II CPLD Starter Kitpromotes ease of use.The CoolRunner-II CPLD Starter Kitpromotes ease of use.


CoolRunner-II CPLD Low-Power FeaturesAt the heart of the CoolRunner-II CPLDStarter Kit is a 256-macrocellCoolRunner-II CPLD, an ultra-lowpower programmable logic device. TheCoolRunner-II family has quiescent poweras low as 13 µA and a number of designfeatures that help reduce dynamic power aswell. Let’s briefly discuss two of these fea-tures, the clock divider and DataGATE.

CoolRunner-II devices, starting fromthe 128-macrocell device, have a built-inclock divider circuit. This componentallows you to not only save user logic butalso lower power by reducing the fre-quency of a clock that may not need torun at full speed. The clock divider pro-vides divisions of 2, 4, 6, 8, 10, 12, 14,and 16 and outputs directly onto a globalclock net. If used in conjunction withdual-edge triggered registers, you canobtain odd values of division.

DataGATE is effectively an input 3-state. When signals toggle at an I/O pin,current flows at the I/O transistors as wellas in all of the traces within the CPLD.There are many situations where you canignore specific I/Os, such as in idle statesor don’t-care conditions. In these situa-tions, you can disable unnecessary inputsto save current.

DataGATE is also useful for signals thathave slow rise or fall times. The largestamount of power consumed in the I/Otransistors occurs when the voltage at thepin is roughly one-half of VCCIO. You canuse DataGATE to periodically enable aninput to sample its state and then disable itto save power. Without DataGATE, veryslow switching signals will waste multiplemilliamps of current.

CoolRunner-II CPLD Kit FeaturesThe CoolRunner-II CPLD Starter Kithas eight peripheral module expansionports, each with four I/O pins. Each of

XMeter: Built-In Power MeasurementOne of the greatest features of aCoolRunner-II CPLD is its low poweroperation. One of our more populardemonstrations is the “fruit-powered”demo, where we run the device from theelectrical current generated by a few piecesof grapefruit.

But fruit won’t replace the AAA battery,so you need a way to exactly determine theoperating lifetime for your design. Powerestimators have their place, but measuringthe real thing is critical.

One feature built into the CoolRunner-IICPLD Starter Kit is real-time power meas-urement and reporting. XMeter is a pro-gram that reads power measurements forthe 1.8-V power supply and charts the datain real time. Figure 1 shows the XMeterprogram in operation. The sample designwas consuming 200 µA at full frequency;when DataGATE was enabled, the currentdropped down to ~86 µA.

these ports is capable of accepting anyof 29 peripheral modules (PMods).The board itself has two push buttons,and the kit comes with three PMods toget you started quickly: quad switches,a PS/2 connector, and a dual seven-segment display.

PMods offer total flexibility withoutthe expense of time and money. Thismeans no more time wasted solderingdevices onto a breadboard, no more pay-ing for an on-board Ethernet PHY thatyou’ll never use, and no need to pur-chase an expensive programming cableor design software. Simply buy the mod-ules that you need for your project andplug them into any of the I/O expansionports. Update the pin constraints inyour design file and you’re ready to go.

A number of PMods cover the userinterface. There are simple switches(such as quad switches, buttons, or arotary switch) and more complex PMods(such as the PS/2 adapter that facilitatesconnection to a standard PS/2 key-board). An RS232 adapter even allowsdata transfer using a UART.

For display purposes, there are sever-al LEDs on the board itself, along withthe provided dual seven-segment dis-play. For more detailed display options,there is a 16 x 2-character display PMod.

Here is a short list of availablePMods:

• Analog to digital: two 12-bit 1 MSPS A/D

• Digital to analog: two 12-bit 1 MSPS D/A

• 16-Mb SPI flash

• Infrared light detector

• H-bridge for DC motor drive

• Speaker/headphone amplifier

• Servo-motor connectorFigure 1 – XMeter showing DataGATE power savings

One feature built into the CoolRunner-II CPLD Starter Kit is real-time powermeasurement and reporting. XMeter is a program that reads power

measurements for the 1.8-V power supply and charts the data in real time.




Note that DataGATE power savingsare entirely design-dependant. You canimplement DataGATE in a number ofdifferent ways based on your designrequirements, so expected power savingswill vary from this example.

XMeter makes it easy to load up differ-ent versions of your code and determinewhich one has the optimum power con-sumption profile, taking the guesswork outof power optimization.

PC-to-Kit CommunicationThe programming cable provided withthe kit is a standard USB to mini-USBcable available at any electronics store.Chances are one was included with yourdigital camera or cell phone. JTAG com-munication between the PC and the

board is handled through a Cypress EZ-USB chip, so to program the board youwould use Digilent’s Export program-ming software. (The board supports pro-gramming from iMPACT, but thisrequires a separate Xilinx programmingcable not included in the kit.)

The advantage of this communicationmethod is that an application program-ming interface (API) allows you to createyour own PC-based programs and com-

municate directly withthe CPLD. Figure 2shows a program thatallows you to read fromand write to registerswithin the CoolRunner-IICPLD.

ConclusionThe CoolRunner-IICPLD Starter Kit is opti-mized for low poweroperation and removesmany roadblocks for pro-totyping. Ease of use iscovered by pre-builtmodules that can beplugged into the boardwithout warming up thesolder gun. The suggestedresale price of this kit is

less than $50. Every chip on the board wasselected for low power and power measure-ment is built-in, so easy power benchmark-ing and design evaluation is covered. Thiskit offers low power, low cost, high func-tionality, ease of use, and no compromises.Get your evenings back.

• Order the CoolRunner-II CPLD Starter Kit.

• Read about DataGATE power consumption savings in the white paper, “The Real Value of CoolRunner-II DataGATE.”

• See a complete list of available PMods.

• Download the Digilent Adept SDK API and transport design.


Figure 2 – PC application communicating with CoolRunner-II CPLD


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by Glenn CrowStrategic Marketing Manager, General ProductsDivisionXilinx, [email protected]

The dynamics of the digital displaymarket to constantly strive forimprovement while reducing total sys-tem cost has caused models to changebetween two to four times per year.These changes can be challenging asdisplays evolve; incorporating theright feature set in a very short time tomarket (TTM) becomes the standardbusiness model to lead the pack orsimply to stay competitive. Choosethe wrong features and the productwill be slow to gain market share;more importantly, it will fail to reachits full potential in a market that turnsseveral times a year, affecting revenue.

Extending the life of an existingASIC is imperative to meet cost goals.The TTM of an ASIC cannot keeppace with the dynamics of this rapidlypaced market without revenue losscaused by a missed feature inclusionor design modification. When anASIC requires a re-spin because of adesign error or newly required feature,the market window of opportunitycan be missed.


Designing Digital Displays with Spartan-3 Generation FPGAsProgrammable solutions improve your time to market.

A U D I O / V I D E O

By incorporating a Xilinx® Spartan™-3Generation FPGA alongside an ASIC, thelife of the ASIC can be increased, allowingthe development and engineering costs tobe spread out over a larger number ofdevices. This enables fast TTM and allowsmany new features to be incorporated atany point throughout the design process.

Coupling the ASIC with an FPGAprovides optimum design flexibility,allowing the design to be quickly upgrad-ed and keep pace with the market whilealso getting the maximum benefits fromportions of the design that will be re-usedin future products.

For more than five years, Spartan-3Generation FPGAs have helped designersof digital displays by reducing system costand complexity while integrating new andunique features. These FPGAs provide theindustry’s lowest cost solution by eliminat-ing the need for external components.

In this article, I’ll explain how Xilinxconsumer display solutions incorporatecomplex video image enhancement algo-rithms effortlessly, implement hassle-free

can be easily implemented with embeddedmultipliers, DSP blocks, and block RAM tocreate product differentiation.

Hassle-Free Panel Interfacing Each new generation of displays integrates awide variety of panel sizes and types con-taining distinct interface, timing, and imagecharacteristics. Newer LCD panels incorpo-rate even more complexity, with featuressuch as dynamic backlight and ambientlight control. Spartan-3 Generation FPGAssupport the latest interface I/O standards,as well as flexible timing controllers to adaptto different panel timing variations.

In addition, you can easily implementimage processing to improve the imagequality of each panel and enhance featureslike backlight control for truer colors,deeper blacks, and more detail in darkscenes. This represents some of the func-tionality that can be accomplished inblocks 2 and 3 (Figure 1).

The best way to keep pace with newpanel technology as well as panel interfacestandards is with the only FPGAs that have

commonly used high-speed panel inter-faces, and provide instant access to theindustry’s widest support of I/O interfacesfor changing standards and protocols. Inaddition, they keep your design and IPprotected with design-level security tech-nology and support green requirementswith dual-power management modes.

Video Image EnhancementXilinx Spartan-3 Generation FPGAs pro-vide pre- and post-image processing func-tions to enhance or extend the life ofexisting ASICs/ASSPs. As display technolo-gy and sizes change, adjustments to theimage may be required that the ASIC/ASSPcannot perform. A custom image process-ing algorithm can also be used for productenhancement and differentiation.

As shown in Figure 1, blocks 1 and 2 caneasily implement functions such as motion-adaptive temporal noise reduction, de-interlacing artifact filters, intra-frame noisereduction, color space converters, anddynamic range compression to improveimage quality. These functions and more


Tuner

Flash SDRAMDisplay Panel

SDRAM

Image ProcessorASSP

De-InterlacerScaler

Gamma CorrectionPIP/POP

OSD

SDRAM

5

2

3

1

4

ATSCNTSCPALSECAM

Functionality Supported by Xilinx

R,G,B

Video/Tuner Board Panel Display Board

HDMI/DVI

USB

Composite

YPrPb/RGB

S-Video

Component

VideoDecoder

MicroBlazeProcessor

EthernetController

IDE/SATA

IEEE1394

SD/MMC

Smart CardController

PHY

PC toGPIO

Mux/Switcher

LVDS

Image Enhancement3D Color Management

Edge EnhancementDynamic Gamma

CorrectionColor Temp AdjNoise Reduction

RSDS/PPDS Tx

FPD-Link (LVDS Rx)

TCON

Image

Enhancement

Algorithm

Dynamic Backlight

Control (Optional)

Figure 1 – This diagram shows five different blocks marked with a yellow dotted line on two separate boards that can be implemented in a Spartan-3 generation device. Depending on the design requirements and cost target, one or all of the

Xilinx-supported blocks on the video/tuner or panel display board could be implemented in a single device.


native support (without external compo-nents) for the latest differential standardssuch as Transition Minimized DifferentialSignaling (TMDS) and Point-to-PointDifferential Signaling (PPDS).

Instant Access to Changing Standards and Protocols Today’s displays must support a variety ofstandards and protocols that range fromvideo input such as DVI and HDMI tointernal memory, ASSP/ASIC, and panelinterfaces. Spartan-3 Generation FPGAscan help you stay connected with existinginterfaces like DDR, DDR2, USB, andFirewire (IEEE1394) standards. Blocks 4and 5 in Figure 1 show some of the manyinterfaces/features that may change frommodel to model.

As consumers demand more features ondigital displays, the only way to quicklyreact is through a programmable solution.Spartan-3 Generation FPGAs offer theability to support network, hard drive, andmultiple memory interfaces as well as thelatest digital video interfaces.

The support of different standards ordifferent combinations of standards is aseasy as reconfiguration with MultiBoot.MultiBoot allows you to change the func-tionality by simply reconfiguring theSpartan-3 Generation FPGA, which sup-ports low-cost serial, parallel, and platformflash configuration devices.

Protection with Built-In Design-Level Security Protecting valuable, proprietary imageenhancement algorithms and timing con-trol systems from cloning, overbuilding,and reverse engineering has becomeincreasingly critical. Low-cost, robust secu-rity that can be designed quickly to protect

product improvements without impedingquick TTM is a key feature.

Xilinx offers many levels of security thatrange from hidden bitstreams to advancedata manipulation. Spartan-3 GenerationFPGAs offer the right security solution tohelp protect key IP, data, and the completedesign in high-volume, low-cost products.With the ease and flexibility to change thesecurity, each model or generation of dis-plays could have a different scheme, mak-ing tampering or theft of key circuitry or IPeven more difficult.

Go GreenIncreased global regulations are requiringmore consumer products to reduce standbypower consumption. The Spartan-3Generation offers multiple power-savingmodes to help meet your power budgetgoals. All Spartan-3A, 3AN, and 3A DSPdevice platforms offer suspend and hiber-nate modes. The hibernate mode canreduce static power by as much as 99%,while the suspend mode will reduce staticpower by at least 40%.

ConclusionSpartan-3 Generation FPGAs offer today’sdigital display designers the optimal low-cost programmable solution. No othersolution combines the flexibility of pro-grammable logic with the native support ofcutting-edge I/O and interface support, awide array of IP, flexible design-level secu-rity, and multiple development boards andstarter kits to quickly design and test yourvideo applications.

No extra components needed for thebuilt-in security and access to standards thatkeep you ahead of the game give you theability to re-use your workhorse ASIC orASSP and extend its usefulness.


• Learn more about Xilinx digital display solutions.

• Learn more about Spartan FPGAs.

• Download your free ISE™ WebPACK™ software design tools and begin designing immediately.


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by Maureen Smerdon Strategic Marketing Manager Xilinx, Inc. [email protected]

Graeme DurantCEOHelion Technology [email protected]

In today’s world, device cloning and unau-thorized overbuilding have driven designsecurity to a higher level of importance. Inconsumer electronics applications, designsecurity has become as important as themedia encryption flowing across the device.Example applications include broadbandaccess, wireless networking, routers, high-definition DVD, and DVRs.

In 2007, Xilinx introduced its DeviceDNA technology, offering a range of securityfeatures to safeguard against reverse engineer-ing, cloning, and unauthorized overbuilding.Xilinx offers this revolutionary capability inits latest low-cost Spartan™-3 FPGAs,specifically Spartan-3A, Spartan-3AN, andSpartan-3A DSP devices.

To expand the capabilities of this technol-ogy, Xilinx worked closely with Helion, aXilinx Alliance IP partner specializing in dataencryption and security solutions, to developDevice DNA Checker, an IP block specifi-cally designed to work in conjunction withSpartan-3 devices to provide designers with aneven more solid and robust security solution.

Device DNABefore understanding how the HelionDevice DNA Checker works together withSpartan-3 devices, let’s look at the core ofXilinx Device DNA technology.

Xilinx Device DNA technology is a per-manent, factory-set ID code that is differentin every device. Starting at 57 bits and pro-grammable up to any bit length to meet userrequirements, the Device DNA enablesadvanced 64-bit, 128-bit, or even more com-plex 256-bit algorithms. This unique ID canbe used to tie a design to a specific FPGA.

Every design can hold a unique authenti-cation algorithm to further increase designsecurity and reduce reverse engineering andpotential threats. This allows you to precise-ly select the complexity of the algorithm and

directly control the amount of securityneeded. With this flexibility, you can spendas much or as little on security as necessary,depending on the security needs of yourspecific application.

The authentication algorithm youchoose is implemented in the FPGA andtakes in the ID value and generates a uniqueresult for that ID. The result is then storedwherever you choose, such as in externalmemory or internal flash (for Spartan-3ANFPGA devices only). Each time the FPGAis powered, the generated and stored resultsmust match in order to authorize thatdevice. The algorithm is the secret to thesecurity because it is known only to you,and is almost impossible to determine with-out access to the original design source.

Designers have full flexibility in cus-tomizing algorithms for both authentica-tion as well as responses to authenticationfailures. With its embedded flash, theSpartan-3AN device further enhances secu-rity by hiding any configuration communi-cation from the outside, making itextremely difficult to understand thedesign contained within the FPGA.


Taking Device DNA Technology to the Next Level

Taking Device DNA Technology to the Next LevelXilinx and Helion work together to make low-cost FPGA designs more secure.

Xilinx and Helion work together to make low-cost FPGA designs more secure.


This security or licensing process isdesigned with complete flexibility inmind. You can easily change the securityor licensing process from model to model,thus increasing design security. The read-only Device DNA is accessible througheither the external JTAG port or the inter-nal DNA port for easy connection to thesecurity algorithm.

If a cloner or overbuilder copies the bit-stream and places it into another FPGA,the Device DNA of the new FPGA will bedifferent. After using the algorithm tocheck the Device DNA, the design willreturn an unauthorized or a failed result,allowing the user or designer to determinehow to respond to the security breach.

is non-authorized or illegitimate. Thesimplest way is to disable functionality.This can easily be accomplished by utiliz-ing global control signals such as resets,3-states, or clock gating.

During normal operation, the device ispowered up and the bitstream is loaded forconfiguration of the FPGA. The securityalgorithm reads the Device DNA and gen-erates an active value. It then compares theactive value with the check value storedduring the initial setup. If the check valueis equal to the active value, the device willoperate normally.

You can design your product to respondin one of the following ways when the twovalues do not match:

• No functionality. The design complete-ly ceases to function. This can be easilyimplemented in a Spartan-3 FPGA byusing global control signals like 3-state,gated glocks, or flip-flop clock enable.

• Limited functionality. The design haspartial or basic operation but key func-tionality is disabled or bypassed. Thisresponse allows a third-party test houseor contract manufacturer to build andtest while preventing overbuilding. Italso allows the system to be run inevaluation or demo mode.

• Time bomb. The design operates withfull functionality for a predeterminedamount of time before shutting off.This response allows a third-party testhouse or contract manufacturer tobuild and test. It also allows the sys-tem to operate in demo mode or forIP evaluation.

• Self-destruction (Spartan-3AN devicesonly). Uses flash sector erase and lock-down protection to erase all sectorsand permanently lock flash memory toall zeros. This response prevents repeat-ed unauthorized access attempts.

Authentication Algorithms The techniques necessary to create a solu-tion using Device DNA and protect a prod-uct against overbuilding and cloning aredescribed both in this article and in Xilinxwhite papers such as WP266, “Security

Figure 1 shows a graphical representa-tion of the security flow.

The Device DNA security process is likean ATM transaction. To withdraw moneyfrom an ATM, you insert your ATM cardand enter your PIN on the touch pad. Ifyour card and associated PIN match the IDstored at the bank, your transaction isapproved and your money is available. Ifthe match fails, your transaction is rejectedand you do not get your money. Figure 2shows the how the ATM transaction com-pares to the security flow.

Unauthorized OperationUsers have more flexibility in the deter-mination of what happens when a design

•

•

•

IncreasedSecurityOptions

Device DNA(57 bits) Active

Value

FPGA is configured from Flash

Using the same user-defined algorithm, it generates

Active Value

Active Value is compared against the Stored Check

Value. If design is authorized, it works normally. If

failed, there are several user-defined "failure" options.

Factory Flash ID

Additional Bits

(Spartan-3AN Devices Only)

Normal Operation

Security

Algorithm

Stored

Check

Value

Secured

or

Failed=

What You Have What You Know

Bank

Computer

System

Resources

Compared

with Stored

Value

Active Value

Yes/No

ATM Card ATM PIN

Device DNASecurity

Algorithm

Active Value

Yes/No

Compared

with Stored

Value

Figure 2 – ATM transcactions and Device DNA security flow

Figure 1 – Device DNA design-level security




Solutions Using Spartan-3 GenerationFPGAs” (www.xilinx.com/documentation/white_papers/wp266.pdf). However, actuallyimplementing such a solution quickly andsecurely and ensuring that it does not useexcessive logic resources in your device canbe time-consuming. Thus, there is a strongcase for using a ready-made and tested IPblock specifically designed for the purpose.

Helion, using its well-established crypto-graphic IP and expertise, developed a ready-made solution comprising a pair of IP cores,allowing designers to easily implementDevice DNA technology in their designs.

The Helion approach uses a selection ofstrong cryptographic functions to imple-ment the security algorithm and variousobfuscation techniques to ensure that anyreverse-engineering attacks are made suit-ably difficult. Most importantly, the designis highly parameterized so that each usercan make their implementation unique tothem. Other customers using these IPblocks – even Helion itself – cannot workaround the scheme.

The Helion Device DNA CheckerThe Helion Device DNA Checker com-prises a ready-made IP building block thatis dropped into the user design to sit along-side the main FPGA application. It has rel-atively low resource requirements and isintended to coexist easily with the maindesign. Its interface is simple; it requires aninput from the Device DNA block in theFPGA, and after processing generates a

“pass/fail” flag. This flag can be used todegrade normal operation of the rest of thedesign if the check does not pass. Simple“go” and “done” signals start the checkprocess. Figure 3 shows a block diagram ofthe Helion Device DNA Checker.

Helion’s Device DNA Checker uses boththe Device DNA code plus additional checkbits stored in non-volatile system memory toenhance security. These additional bits are amixed-up combination of randomly gener-ated bits that form part of the check algo-rithm; randomly generated bits that areignored (sometimes called “salt” bits); andthe final stored check code itself. This addi-tional data is simply streamed into theChecker after the Device DNA bits via thecascade input to the Device DNA block.

So that each customer using this solu-tion can be confident that their protectionis unique to them, the exact operation ofthe Checker is highly parameterized andnot fixed by Helion. You set your ownsecret “configuration value” when the

Checker block is synthesized. This is effec-tively a long string of bits that define thelow-level operation of each part of thecheck algorithm used in the block. Becausethis is set at synthesis time, the configura-tion value can result in significantly differ-ent logic for each user.

Neither Helion nor any other user of thistechnology can replicate the algorithmwithout access to the secret configuration,adding another layer of protection into thesystem. In the diagram, the functions of theblocks shown in pink are all affected by thissecret compile-time configuration value.

Internal OperationWithin the Checker, the input stream goesone of three ways. It is either used in thecryptographic hash, used as the stored checkcode (to be compared to the generated activecode after the hash is complete), or discard-ed. The choice of which bits go where isdetermined by the user configuration previ-ously outlined and is different for each user.

Non-VolatileUser Memory

Added Device DNA Bits(128 bits to 16k bits typical)

Device DNA(57 bits)

Note: Function of blocks in pink are controlled by userconfiguration at synthesis time

Helion Device DNA CheckerCheck"GO" Control

Discard

Check"DONE"

Pass/Fail

CryptographicHash

ObfuscationFunction

eq

ObfuscationFunction

C-Code Application

User CONFIG

List of Device DNAValues

Flash Data Blocksfor Each DNA

Figure 4 – Using Device DNA in a software application

Figure 3 – Device DNA Checker block diagram



Any bits destined for hashing or for thecheck code go through “obfuscation” func-tions before being used. These are intendedto further obscure the processing being per-formed. Their exact definition is again driv-en by the user configuration outlinedabove, so each user’s implementation will bedifferent. Even the choice of cryptographichash function used is determined by yoursecret configuration. Once the appropriatebits have been hashed to form an activecode and the stored check code has beenregenerated, the two are compared and thefinal pass/fail result is indicated.

Getting AuthorizedFor each legitimate product that has aunique Device DNA and contains theDNA checker, the product must be activat-ed by generating the additional DeviceDNA bits to be stored in non-volatile mem-ory. This can be achieved in two ways:

1. Software application. In this case, asoftware application supplied byHelion models the algorithms used inthe Checker to calculate the necessaryadditional Device DNA data. It takesin a list of authorized Device DNAvalues and a copy of the customer’ssecret compile-time configuration andgenerates data sets to be placed intothe systems’ non-volatile memories(see Figure 4). This application couldbe used remotely to generate data sets

on demand, perhaps automaticallyover the Internet. Clearly this softwareand the user-configuration informa-tion must only be distributed to high-ly trusted parties; otherwise the wholescheme is compromised. However,remotely enabling manufactured unitsmay be a great way to achieve separa-tion between trusted and non-trustedparties in the manufacturing process.

2. Hardware download. In this case, anoptional second IP block called theHelion Device DNA Generatorimplements the same algorithms asthe Checker to generate the neces-sary additional Device DNA data(Figure 5). You would put together aspecial programming bitstreamincorporating this block using thesame user configuration as theChecker at synthesis time. This doesnot include any of your normaldesign, as it is only required for con-figuring non-volatile user memorywith the appropriate additional

Device DNA data. This FPGAimage could be self-contained, tak-ing the data generated by the Helionblock and burning it into the appro-priate non-volatile memory, therebyenabling that unit.

Again, this special bitstream must onlybe distributed to highly trusted parties. Itwould need to be loaded once into themanufactured hardware to authorize theunit, so it cannot be used remotely. Thismay be more appropriate in some manu-facturing processes than the alternativesoftware approach, however.

ConclusionHelion’s solution for accessing the benefitsof Xilinx Spartan-3 FPGA Device DNAtechnology is both off-the-shelf yet uniqueto each user. It is easy to use and requiresminimal device resources. It can bedeployed in an existing design very quickly,offering the benefits of protection againstoverbuilding and cloning during out-sourced manufacture.

• Learn more about the Spartan-3A device family or the Spartan-3ANdevice family.

• View a security demo on the Spartan-3AN device family.

• Learn more about Helion, www.heliontech.com.


Helion Device DNA GeneratorControl

Discard

Learn"GO"

Learn"DONE"

Control

CryptographicHash

ObfuscationFunctionObfuscation

Bit Source

ObfuscationFunction

Device DNA(57 bits)

AdditionalDevice DNA

Bits forUser Memory

Note: Function of blocks in pink are controlled by userconfiguration at synthesis time

Figure 5 – Using Device DNA as a hardware download


by Bob Feng Spartan Applications EngineerXilinx, Inc. [email protected]

Mark SauerwaldSDI Applications EngineerNational [email protected]

Today’s high-speed video application design-ers have significant challenges in addressingboth the digital IP and analog physical inter-face requirements of their products. Becausedigital and analog components often havevery different requirements, trying to sup-port both in one ASSP chip often compro-mises the quality or cost-effectiveness of thesolution. It can also be difficult to find asolution that has exactly the right IP andphysical interface without waste in eitherarea, or with the flexibility to meet therequirements of multiple standards.

A new chip set featured by Xilinx andNational Semiconductor combines the bestof the digital and analog worlds into one

highly integrated solution. This solution,including the protocol IP stack, is handled bythe Spartan™-3E or Spartan-3A FPGA sili-con. The analog section is handled byNational Semiconductor SDI PHY productsfor the greatest signal quality with the lowestjitter. It allows professional audio/video broad-cast (AVB) system developers to concentratemore on their own specific video content pro-cessing functionality and IP instead of thefront-end interface connectivity.

SDI Video StandardsSerial digital interface, or SDI [SMPTE-259M], is a broadcast industry standardwidely adopted today to transport uncom-pressed standard-definition (SD) video sig-nals over a single coaxial cable. Bydefinition, SDI typically supports data ratesof 270 Mbps to cover screen formats of 480iat 60 Hz (480i60).

High-definition (HD) SDI, or HD-SDI[SMPTE-292M], boosts the bit rate up to1.485 Gbps to support high-definition for-mats like 720p60 and 1080i60.

Three-gigabit SDI, or 3G-SDI [SMPTE-424M], further extends the serial digitalthroughput up to 2.97 Gbps in order tocarry the highest screen resolution: 1080p60.

National Semiconductor PHYsNational Semiconductor offers a completeportfolio supporting the physical layertransmission for SDI applications.National’s new family of SDI serializersand deserializers have speed grade optionssupporting SD SMPTE 259M at 270Mbps, HD SMPTE 292M at 1.485 Gbps,and the new 3-Gbps standard (3G-SDI)SMPTE 424M at 2.97 Gbps (Table 1).


A High-Speed Broadcast Video Connectivity SolutionA High-Speed Broadcast Video Connectivity SolutionXilinx Spartan-3E and Spartan-3A FPGAs, National Semiconductor PHY, and the Xilinx protocolstack provide a cost-effective and flexible approach to the challenges of multi-rate broadcast.Xilinx Spartan-3E and Spartan-3A FPGAs, National Semiconductor PHY, and the Xilinx protocolstack provide a cost-effective and flexible approach to the challenges of multi-rate broadcast.

Soft SERDES Pixel Processing

SD-SDI 27 MHz 27 MHz

HD-SDI 148.5 MHz 74.25 MHz

3G-SDI 297 MHz 148.5 MHz

Table 1 – FPGA design frequency domains


National’s LMH034x family highlightssuperior analog performance:

• Ultra-low output jitter: 50 ps typical atHD and 3-Gbps rates (Figure 1)

• Exceptional input jitter tolerance: 0.6UI minimum (Figure 2)

• Integrated, high-precision PLL for seri-al clock reference and data recovery

• Integrated cable driver in LMH0340transmitter

FPGA from a 20-bit, single-ended inter-face to a five-channel low-voltage differ-ential signaling (LVDS) interface. Thisinnovative narrow differential bus reducesEMI and simplifies board layout byreducing the number of traces on theinterface and using fewer pins on the hostFPGA. Additionally, National’s discretePHYs do not require any external VCOsor jitter-reducing PLLs (Figure 3).

The combined National/Xilinx Spartansolution enables low-cost FPGAs into thehigh-end AVB market supporting SD,HD, and 3-Gbps data rates for profession-al video applications.

Spartan Features for Video ApplicationsThe Spartan-3E and Spartan-3A FPGAfamilies suit many aspects of video applica-tions by offering high performance, highdensity (logic and I/O), great flexibility,and scalability with unique, cost-effectivefeatures such as:

• 50,000 to 1.6 million system gates

• True LVDS differential I/O drivers atmore than 666 Mbps, with internaltermination on receiver for direct chip-to-chip communication

• Double data rate (DDR) I/O registersat more than 300 MHz to increaseeffective bandwidth beyond 600 Mbps

• 18-Kb dual-port block RAMs at morethan 200 MHz for FIFOs and databuffering

• Dedicated 18 x 18 multipliers at morethan 200 MHz for high-speed digitalsignal processing

• Digital clock managers (DCMs)

• Clock deskew

• Frequency synthesis

• High-resolution phase shifting

• Wide frequency range (5 MHz tomore than 300 MHz)

• Full programmability to easily modifythe design during development or inthe field, or to support multiple stan-dards in a single solution

• Integrated serial re-clocked loopthrough and driver

• Low power consumption

• TX: 435 mW

• RX: 590 mW

• No external VCOs or clock required

In addition to leading-edge analogperformance, National’s LMH familyreduces the traditional parallel busbetween the PHY device and the host

Equipment: Tektronix CSA8000 sampling scope with 20-GHz sampling heads.

Input Signal: PRBS 215 -1 Data Rate: 2.97 Gbps

LMH0341 Sinusoidal Jitter Tolerance

0.1

1.0

10.0

1000.0

100.0

1.0E+3

10.0E+3

100.0E+3

1.0E+6

10.0E+6

100.0E+6

Jitter Frequency

Jit

ter A

mp

litu

de

(U

I)

LMH0341, 297G

SMPTE Transit output jitter template

Data Rate: 2.97 Gbps

Equipment: Agilent J-BERT

Figure 1 – LMH0340 3-Gbps output jitter: 30 ps at HD and 3G rates

Figure 2 – LMH0341 minimum input jitter tolerance: 0.6 UI




• Software and IP to quickly implementkey features of video applications

• Design examples and reference boardsto get started quickly

By using FPGAs, you can be compliantto industry standards while differentiatingyourself from your competitors. Such differ-entiation may be too difficult to find usingan ASSP solution and too expensive toaddress with an ASIC. The flexibility of aprogrammable solution provides faster time

to market, while field updates provide longertime in market. Numerous standards (andversions) cause uncertainty, so designs needflexibility in transmission schemes, MPEGprofiles, display formats, and color correction.

Interconnect Soft SERDES and Protocol IP StackWhile the National Semiconductor PHYtakes care of the SDI physical interface, theFPGA plays an essential role in supportingall digital functions in the protocol IPstack, including:

• 20:5/5:20 LVDS soft serialization andde-serialization (SERDES)

• SMPTE scrambling/descrambling

• Video framer/de-framer

• CRC and line number insertion

• Rasterization

• ANC insertion

• Video standard detection and flywheel

The FPGA design is effectively dividedinto two frequency domains: “softSERDES” and “pixel processing,” as illus-trated in Table 2. The clock frequencyused in the soft SERDES is typically onlyhalf of the serialization bit rate, by lever-aging the DDR technique. On the otherhand, the pixel processing clock frequencyis determined by the relevant video trans-mission format: 74.25 MHz for 720p60and 148.5 MHz for 1080p60.

The timing closure challenge is mainlyon the soft SERDES side, as 297-MHzoperation is required to achieve 594Mbps across all of the differential chan-nels. The Xilinx® Spartan applicationsteam has been offering this soft SERDESreference design in a beta version sinceMay 2007. Since then, Xilinx andNational Semiconductor have conductedextensive testing. All three data rates havepassed BERT test suites developed byXilinx. Figure 4 illustrates the basicSERDES construct.

Xilinx has a long history of supportingSDI interfaces in the Virtex™ family ofFPGAs. XAPP514, “Audio/VideoConnectivity Solutions for the BroadcastIndustry,” is a video connectivity IP andreference design book that details allaspects of the protocol stack: SDI, HD-SDI, DVB-ASI, SDTV/HDTV test pat-tern generation, and even embeddedaudio. Xilinx and National Semiconductorare actively working to port these highlyvaluable reference designs into Spartan-3Eand Spartan-3A FPGAs. Figure 5 illus-trates a list of successfully ported referenceblocks used for demonstration purposesbased on an internal evaluation board.Figure 6 illustrates an SMPTE 75% colorbar display generated by the board.

CLK

CLKx2

D0

D+

D-

CLK-

CLK+

D1

D0

D1

CLK_N

CLK_PCLKx2not

CLKx2not

CLKx2

CLK

20-bit

20-bit

BUFG

BUFG

BUFG

BUFG

BUFG

BUFG

DCM

20:5

Ser

ializ

er

5:20

De-

seri

aliz

er

OD

DR

2O

DD

R2

IDD

R2

Transmitter

ReceiverAlignment = C0/C1

DCMCLK-

CLK+

D-

D+

20:5/5:20 LVDS SERDES

FPGAHD-SDI

Serializer

Low-Cost

FPGA

LMH0340

3G-SDI

VCO

Cable

Jitter

THEN

NOW

Narrow parallel bus:

Simplifies layout

Differential Signaling Reduces EMI

Wide parallel bus:

Introduces EMI

Burdens layout

Max Serial data rate:

1.485 Gbps

Max Serial data rate:

2.97 Gbps

Output Jitter: 50 ps

Output Jitter:

~115 ps

SDI OUT

SDI OUT

Single Ended TTI

20-bit

clk

Figure 3 – SDI bill of materials reduction

Figure 4 – Basic soft SERDES construct in Spartan-3E FPGAs



Target ApplicationsXilinx low-cost Spartan-3 generationFPGAs have been used successfully in a widerange of consumer and professional videoapplications. These include a JVC profes-sional broadcast HDV camera/recorderusing the Spartan-3E FPGA. The combina-tion of the Spartan FPGA for the digitallogic and National Semiconductor PHY forthe analog interface opens up new possibili-ties in high-end applications in professionalvideo, broadcasting, and digital cinema.Applicable products include high-definitionvideo cameras, digital video recorders, videoeditors, and display monitors.

ConclusionThe power of Xilinx Spartan-3E andSpartan-3A FPGAs, combined with aproven National SemiconductorSD/HD/3G-SDI transceiver and theXAPP514 protocol IP, delivers a trulycost-effective solution to the ever-increasing data throughput require-ments of broadcast video applications.Although the complete hardware solu-tion is available today, a complete SDIevaluation kit will be offered by Xilinxdistribution partner Avnet in the firstquarter of 2008.

• Learn more and select the best Spartan FPGAs for your applications.

• Download XAPP514, “Audio/Video Connectivity Solutions for theBroadcast Industry.”


Product ID Description Max Data Rates SMPTE Standards Data Rate Supported Supported

LMH0340 Serializer and Driver 3G 2.97G 424M1.485G 292M270M 259M

LMH0341 Reclocking Deserializer 3G 2.97G 424M1.485G 292M270M 259M

LMH0040 Serializer and Driver HD 1.485G 292M270M 259M

LMH0041 Reclocking Deserializer HD 1.485G 292M270M 259M

LMH0050 Serializer HD 1.485G 292M270M 259M

LMH0051 Deserializer HD 1.485G 292M270M 259M

LMH0070 Serializer and Driver SD 270M 259M

LMH0071 Reclocking Deserializer SD 270M 259M

Table 2 – National Semiconductor PHY families

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Interested in adding “published author” to your resume and achieving a greater level of credibilityand recognition in your peer community? Consider submitting an article for global publication inthe highly respected, award-winning Xcell Journal.

The Xcell team regularly guides new and experienced authors from idea development to publishedarticle with an editorial process that includes planning, copy editing, graphics development, andpage layout. Our author guidelines and article template provide ample direction to keep you ontrack and focused on how best to present your chosen topic, be it a new product,research breakthrough, or inventive solution to a common design challenge.

Our design staff can even help you turn artistic concepts into effective graphics or redraw graphics that need a professional polish.

We ensure the highest standards of technical accuracy by communicating withyou throughout the editorial process and allowing you to review your article to make any necessary tweaks.

Submit final draft articles for publication in our Web-based Xcell Online orour digital and print Xcell Journal. We will assign an editor and a graphicsartist to work with you to make your papers clear, professional, and effective.

For more information on this exciting and highly rewarding opportunity, please contact:

Forrest CouchPublisher, Xcell [email protected]

Would you like to write for Xcell Publications? It’s easier than you think.

Get Published

Rwww.xilinx.com/xcell/

“Solutions Without Compromise: How to Match Consumer Timelines with Automotive and Industrial Requirements and ReduceRisks of Obsolescence Using FPGAs andIntellectual Property”

www.logicbricks.com/pdf/Xilinx%20Electronic%20Displays%20Conference%202007.pdf

FPGAs are enabling a new automotiveworld, where compromises in (andbetween) flexibility, scalability, time to mar-ket, and system cost are no longer required.In a number of different automotive appli-cations, these value propositions are key.

Multimedia and infotainment systemsare always adapting to different types ofdisplays. Graphic controllers have shortlifetimes that do not fit automotive andindustrial embedded requirements. Whynot think about a solution in programma-ble logic that can drive any display, instead

of using different graphic controllers andchanging them for different displays?

“Automotive FPGAs Offer Innovative Solutionsto Automotive Displays Challenges”

www.techonline.com/showArticle.jhtml?articleID=193103236&queryText=Automotive+FPGAs+Offer+Innovative+Solutions+to+Automotive+Displays+Challenges

There is a continuing trend in the automo-tive industry to improve the comfort, safe-ty, convenience, productivity, andentertainment experience for the driver.This trend is spurning increased use of amyriad of display technologies includingTFT, LCD, and OLED.

Along with the benefits of these newtechnologies are unique challenges thattraverse a wide spectrum of issues, includ-ing high-performance, low-EMI signaling;

complex timing control; high-performanceimage processing; and integration with a

wide spectrum of automotive buses – allinfluenced by continuously evolving

standards and degrees of adoption acrossthe automotive industry. Although these

challenges are significant, low-cost automo-tive FPGAs are taking a lead by providingcomprehensive solutions and driving the useof a wide range of display technologies.

This white paper explores the various usesof automotive display technologies and asso-ciated challenges, highlighting the benefitsand cost-effectiveness of FPGAs in address-ing these challenges within the context of arear-seat entertainment system.

“Security Solutions Using Spartan-3 Generation FPGAs”

www.xilinx.com/bvdocs/whitepapers/wp266.pdf

Whether boarding a plane, closing the frontdoor, or beginning your next-generation cir-cuit design, security has become a significantissue. In our homes, we try to build in the rightamount of security to protect ourselves againsttheft. Security is rapidly becoming a necessityin the electronics industry as well.

It is important to understand why secu-rity issues have escalated to the forefront inelectronics design. One reason is the alarm-ing amount of counterfeited goods. Thesegoods threaten the U.S. economy and havea significant effect worldwide in the con-sumer market, according to the Anti-Counterfeiting Coalition.

This white paper identifies the top designsecurity threats, explores basic levels of securi-ty, and describes how new, low-costSpartan™-3A, Spartan-3AN, and Spartan-3ADSP FPGAs from Xilinx can help protect yourproducts and profits.


Featured White PapersFrom high-volume consumer to automotive to global security, Xilinx white papers help you stay on top of technology applications.

T E C H N I C A L L I T E R A T U R E

Xilinx has teamed up with Si-Gate GmbH(www.si-gate.com), a leading provider ofautomotive electronics solutions, to developan automotive electronic control unit (ECU)development kit for in-vehicle networkingsystems, infotainment, driver assistance, anddriver information systems.

What’s Included

• XA1600E development board equippedwith a Spartan™-3E XC3S1600EFG484FPGA, with 1.6 million system gates andinterfaces for expandability

• EDK and ISE™ software evaluation tools

• Resource CD with reference designs foreasy evaluation

• Power supply with universal adaptor

• Programming cable

• Custom serial cable

• QuickStart guide

Key Features

• Xilinx device: XC3S1600EFG484 FPGA

• Complete out-of-the box development system

• On-board hardware interfaces such asCAN 2.0C, Ethernet 10/100, USB2.0, SPI, and SCI

• Support for pre-verified Xilinx® andpartner IP for high- and low-speed CAN,FlexRay, and MOST network interfaces(the latter requires a daughtercard)

Targeted Applications

• Automotive subsystems

• In-vehicle networking systems

• Infotainment

• Driver assistance and information systems


Automotive ECU Development KitXilinx offers a complete development platform ideal for designing intelligent automotive subsystems.

Price: $1,495Part Number: HW-XA3S1600E-UNI-G

• Learn more about theAutomotive ECU Development Kit.

• Buy online from Avnet, Nu Horizons, or your local distributor.

• E-mail [email protected] more information.


T H E B O A R D R O O M

The general-purpose non-volatile Spartan™-3Generation FPGA platform evaluation boardincludes DDR2 memory, 10/100 EthernetPHY, A/D circuitry, VGA and RS232 connec-tors, and an expansion mechanism. Robustsubsystems allow you to:

• Multi-boot pre-programmed referencedesigns in a single session

• Prototype countless applications withsupport for 26 single-ended and differential I/O standards

• Connect to DDR2 memory for rapiddata transfer using a proven memoryinterface controller

• Shorten development time with pre-verified design files and schematics

• Safeguard your designs with exclusiveSpartan-3AN FPGA features

What’s Included

• Evaluation board

• Xilinx® ISE™ software, WebPACK™software, and ISE Foundation softwareevaluation

• 100-240 V, 50/60 Hz power supply withuniversal plug adaptors

• Quick-start guide

• Programming cable

• Product collateral

Key Features

• Xilinx Devices: Spartan-3A FPGA(XC3S700A-FG484) and Platform FlashPROM (XCF04S-VOG20C)

• Clocks: 50-MHz crystal oscillator on-board, open slot for optional user-installed clock

• Memory: 4-Mb Platform Flash PROM,32 M x 16 DDR2 SDRAM, 32-Mb par-allel flash, two 16-Mb SPI flash devices

• Analog Interface Devices: Four-channelD/A converter, two-channel A/D con-verter, signal amplifier

• Connectors and Interfaces: Ethernet10/100 PHY, JTAG USB download port,two 9-pin RS-232 serial port, PS/2-stylemouse/keyboard port, 15-pin VGA con-nector capable of 4,096 colors, one FX2100-pin and two 6-pin expansion con-nectors, 20 user I/O available on stan-

dard header pins, stereo mini-jack forPWM audio, rotary/push-button func-tion switch, eight individual LED out-puts, four slider switches, fourpush-button switches

• Display: 16-character, two-line LCD


• Markets: Consumer, telecom/datacom, servers, storage

• Applications: General prototyping


Spartan-3AN FPGA Starter KitWith its out-of-the-box guarantee, you’ll be testing and designing FPGA solutions in minutes with the new Spartan-3AN Starter Kit.

Price: $225Part Number: HW-SPAR3AN-SK-UNI-G-PROMO

• Learn more about the Spartan-3AN FPGA Starter Kit.


• E-mail [email protected] for more information.


B O A R D S A N D K I T S

This design kit is an ideal platform toevaluate and implement your CPLDdesigns quickly. A unique evaluation boardwith eight peripheral connectors allowsyou to select from a variety of peripheralexpansion modules (sold separately) toexpand the capabilities of your design.

What’s Included

• X-Board with XC2C256-TQ144

• Resource CD, including referencemanual, software, application notes,web seminars, and data sheets

• USB cable

• ISE™ software WebPACK™ CD

• PMod-PS2 (PS2 module to connect akeyboard or other PS2 device to the X-Board)

• PMod-SSD (seven-segment displaymodule)

• PMod-SWITCH (switch module forinterfacing to four slide switches)

Key Features

• XC2C256 CoolRunner™-II CPLD in TQ144 package

• USB interface

• Eight 6-pin connectors for standardperipheral modules

• One 26-pin and one 16-pin connectorfor daughterboards

• Built-in temperature and power monitor

• Free reference designs


• Low-power design

• Logic consolidation

• Memory control and interfacing

• Display control

• Microprocessor interface

• State machines

• ADC interfacing

• Stepper motor control

• RFID telemetry

• Bluetooth or Wi-Fi interface

• Power or heat monitor

• MP3 player

• UART

• Smart Card reader


CoolRunner-II CPLD Starter KitThe ideal CPLD low-power design platform.

Price: $49.95

Part Number: HW-CRII-SK-G

• Learn more about theCoolRunner-II CPLD Starter Kit.


• Buy the Peripheral ModuleBundle (HW-CRII-PM-ACC-G).Extend your CPLD functionalityby adding peripheral expan-sion modules to your system,such as ADC, motor control,serial flash, and more for $99.

• View the CoolRunner-II StarterKit Demo.

• E-mail [email protected] more information.


B O A R D S A N D K I T S

In today’s world, security is a huge concernfor our global society. Whether boarding aplane, closing the front door, or beginningyour next-generation circuit design, securi-ty has become a significant issue.

In our homes, we try to build in theright amount of security to protect our-selves against theft. Security is rapidlybecoming a necessity in the electronicsindustry as well. It is important to under-stand why security issues have escalated tothe forefront in the electronics design field.

One reason is the alarming amount ofcounterfeited goods that are the result oftheft. These goods threaten the economyand have a significant effect worldwide inthe consumer markets, according to theAnti-Counterfeiting Coalition. The WorldCustoms Organization estimates thatcounterfeiting accounts for 5% to 7% ofglobal merchandise trade, equivalent to lostsales of as much as $512 billion in 2004.This threat grows by more than 12% peryear, tarnishing the reputation and long-term credibility of genuine brands.

High-volume solutions, served byXilinx® Spartan™-3 Generation FPGAsand CoolRunner™-II CPLDs, includetechnologies such as configuration dataprotection, hidden bitstream, activedefense, and Device DNA design-levelsecurity for low-cost hardware and soft-ware IP protection. Taken together, thesefeatures enable designers to implement alow-cost, highly robust security solutionto deter reverse-engineering, cloning, andoverbuilding.

How Device DNA WorksThe Device DNA security mechanism issimilar to an ATM transaction, in whichthe active value generated from the card-plus-pin combination is compared to anumber stored in a bank computer thatauthorizes or rejects the transaction.

Similarly, the unique 57-bit DeviceDNA number is used with a customer-defined security algorithm to generate an

active value. The active value is comparedto a pre-stored check value to determinewhether design functionality can proceed.

Our Device DNA demo highlights howeasy it is to implement a low-cost securitysolution for high-volume applications withDevice DNA technology. It requireseither the Spartan-3A FPGA Starter Kitor the Spartan-3AN FPGA Starter Kit.Documentation is provided.


Protect Your Brand with Spartan-3 Generation FPGAsBuild a low-cost security solution for high-volume applications.

• Download the Device DNA demo.

• Read the white papers, “Security Solutions Using Spartan-3 Generation FPGAs” and “Advanced Security Schemes for Spartan-3A/3AN/3A DSP FPGAs.”

• Read the brochure, “Design Security for High-Volume Applications.”


ATM Card ATM PIN Bank Computer

(Compare with Stored Value)

(Compare with Stored Value)

Active Value

Active Value

Yes/No

Yes/NoDevice DNA

SecurityAlgorithm

SystemResources

Figure 1 – Similarities between Device DNA security and ATM transactions

D O W N L O A D S

by Jannis McReynoldsSenior Manager, Services MarketingXilinx, [email protected]

In today’s environment, the pressure toproduce more complex products fasterand at a lower cost is only increasing.Making these challenges even more com-plex are such issues as compressing designcycles, implementing new technologies,overcoming design obstacles, and aug-menting your knowledge base.

In the automotive electronics market,technical challenges are ever-present in theareas of in-vehicle infotainment, comfort,and convenience, as well as in gateway anddriver-assistance systems.

The consumer marketplace continues tohave time-to-market pressures, along withthe continued advancement of digital con-sumer applications for home networking andinformation appliances.

Xilinx® Titanium Dedicated Engineeringhelps you meet your specific design chal-lenges by producing the exact results youneed when you need them. Our technicalteam provides faster issue resolution, expertdesign advice, and risk mitigation. Yourresult is faster time to market, lower produc-tion costs, and a competitive edge.

What is Titanium Dedicated Engineering?Titanium Dedicated Engineering sendsyou a dedicated application engineer on acontract basis. The engineer can workremotely or at your site. Whether you arestarting a new project or are nearing yourdeadlines and need that extra expertise tomeet design performance, TitaniumDedicated Engineering is the answer.

Titanium engineers bring expertise andexperience from multiple, focused engage-ments in areas such as embedded support,

general debugging, general tool usage, per-formance optimization, timing closure,triple modular redundancy support, andPlanAhead™ software floorplanning.

Key Features

• Skilled at providing solutions andexperts in Xilinx knowledge

• Trusted advisors proven to performunder time pressures

• Easily integrates into team environments

• Available for quick deployment

• Can work on- or off-site

Benefits

• Quick and direct access to a dedicatedengineer

• Leading-edge Xilinx expert designprocess knowledge

• Leverage in-factory support of product experts

What Our Customers Have to Say

“The Xilinx team responded with extremelyshort notice and solved a major bug for usin an incredibly short time. The engineerwas extremely knowledgeable. He not onlysolved the bug, but also advised our teamhow to get far better performance on thedesign. He paid for himself by allowing atranscontinental team to immediatelybecome productive after days of inactivitytracking this bug.”

– Large multinational customer

ConclusionRegardless of where you are in your designcycle, turn to Titanium DedicatedEngineering. To learn more, visit www.xilinx.com/titanium.

To purchase Titanium DedicatedEngineering in North America, contactyour local Xilinx sales representative, or e-mail [email protected]. In Europe, contactyour local Xilinx sales representative, or e-mail [email protected].


Titanium Dedicated EngineeringThis Xilinx program provides skilled experts when you need them.

D E S I G N S E R V I C E S

Prove yourdesign with highspeed FPGA hard-ware logic emulation,that plugs directly intoyour PC. This 12+ milliongate, 8-lane PCIe board, isready to go: fixed PCIe core,extensive on board memory andeight independent clock networks willget your design running — fast! TheDN9000K10PCIe-8T features six Virtex-5,LX330 chips with 100% of FPGA resourcesuser-available.

There are no unreliable cables or stacks of overheatingboards. The price, with the biggest and baddest FPGAs, isless than $70,000. Why pay more for a “some assemblyrequired” toy? Visit www.dinigroup.com to see our completeselection of real high-speed prototyping solutions.

1010 Pearl Street, Suite 6 • La Jolla, CA 92037 • (858) 454-3419 • e-mail: [email protected]

www.agilent.com/find/fpga© Agilent Technologies, Inc. 2007 Windows is a U.S. registered trademark of Microsoft Corporation

X-ray vision for your designsAgilent 16998A High-performance FPGA AnalyzerX-ray vision for your designsAgilent 16998A High-performance FPGA Analyzer

Agilent's New 16998A FPGA AnalyzerNow you can see inside your FPGA designs in a way that will save weeks of development time.

Agilent's 16998A high-performance FPGA analyzer allows you toaccess different groups of signals inside your FPGA for debug—without requiring design changes. You’ll increase visibility into internal FPGA activity by gaining access up to 128 internal signalswith each debug pin.

Deep memory is essential to capture enough system activity to get to the root cause of complex problems. With the FPGA analyzeryou receive an upgrade to 4 M acquisition memory and the FPGAdynamic probe software for FREE.

Whether your signals are single-ended or differential, you can debugyour FPGAs and surrounding system faster and more effectively withAgilent's 16998A high-performance FPGA analyzer.

• Increased visibility with FPGA dynamic probe • Customized protocol analysis with

Agilent's exclusive packet viewer software• Accurate and reliable probing• Pricing starts at $9,970

Agilent portable and modularlogic analyzers

by Ivo BolsensCTOXilinx, [email protected]

I recently attended anintriguing Clean Slateworkshop at StanfordUniversity. The topic

focused on the idea of reinventing theInternet infrastructure in order to solvesome of its shortcomings and enable newapplications and services (http://cleanslate.stanford.edu/).

Driven by an increase in rich mediaapplications such as video, service conver-gence, and broadband access deployment,global IP traffic is showing explosivegrowth. Furthermore, IP data networktraffic is highly dynamic, with constantlychanging demands and substantially dif-ferent characteristics when compared totelephony voice.

Today, IP backbones are designed tohave core routers directly connectedthrough static circuits. This assumption ofstatic links means that links must be gross-ly over-designed to deal with peak trafficuncertainties and link failures. As IP trafficgrows, such a network design implies big-ger links and bigger routers – neither ofwhich can be scaled cost-effectively.Moreover, the reliability and security of thenetworking infrastructure to support agrowing demand of dependable applica-tions becomes a serious challenge.

Network VirtualizationThe Clean Slate researchers agreed that“network virtualization” would become anessential technology to provide futurevalue-added services and robustness.

Network virtualization is a capabilitythat allows you to create multiple yet verydifferent concurrent networks on top of thesame physical infrastructure of diverseresources, and would imply a functionality

that extends beyond current packet rout-ing and forwarding.

Today, traditional networking featuresnodes with fixed architectures. Flexibility innetworks comes from packet switchingitself – guided by look-up tables – plus therelatively slow evolution of protocol devel-opment and node software updates. To sup-port desirable concepts like virtualizationand technological convergence, it will benecessary to be much more flexible in termsof node architectures and protocol defini-tion. Therefore, data processing (whetherpacketized or something else) may be car-ried out using very different styles, depend-ing on widely differing applications. Theprotocols providing the rules for such pro-cessing will also vary widely and requiremuch more dynamic definition.

From a Xilinx® perspective, FPGAtechnology is experiencing a parallel shiftthat complements the future direction ofnetworking. Many people see FPGAs asASIC substitutes; once programmed, thedevices have the characteristics of fixedhardware. Today, however, FPGAs areproviding a basis for delivering flexible,“soft” processing architectures that can bematched to particular problem instances.

For example, you can essentially buildyour own network processing unit

(NPU) every time rather than forcingproblems onto fixed architectural solu-tions such as an ASSP or NPU (be it aconnection of multi-threaded engines ordeeply pipelined parallel data paths).Moreover, the soft architecture can evolveover time in response to changes indemand and usage.

Today’s FPGA architectures enable thecreation of soft packet processing architec-tures that, depending on application func-tionality, can be configured as highlypipelined parallel data paths or networksof multi-threaded micro-engines.

These soft processing architecturesallow the memory architecture, the con-nection of the different packet processingfunctions, and the packet operationalunits to be tailored to the application athand. This results in the implementationof packet processing functions in FPGAsthat are outperforming NPUs and ASSPsin throughput, power consumption, andcost by at least one order of magnitude.

An important component is the availabili-ty of programming tools that harness thehighly concurrent capabilities of the FPGAand move away from traditional hardwaredesign paradigms toward new, flexible proto-col implementation paradigms.


Enabling Efficient Packet ProcessingA clean-slate approach to reinventing the Internet.

101010101001001 X P E C TAT I O N S

Enabling the next generation of digital consumer applications

Xilinx programmable logic devices (PLDs) are the technology

of choice for today’s consumer products. Already pervasive in

flat-panel displays, smart handsets, automotive infotainment,

home networking and much more, Xilinx PLDs are also enabling

tomorrow’s consumer technology innovations.

Low-Power, Low-Cost, High-Security Solutions

Known for their design flexibility, low-cost, enhanced security

and time-to-market advantages, Xilinx solutions are optimized

for a variety of end markets and applications. Combine this

with custom IP, starter kits and award-winning design tools, and

you can see why Xilinx is the world’s leading PLD provider.

Visit our website to learn more about Xilinx solutions—at

the heart of innovation in the consumer marketplace.

©2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All

other trademarks are the property of their respective owners.

www.xilinx.com

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Documents

PROGRAMMABLE SYSTEMS EDITION Xcell - Xilinx · Avnet Electronics Marketing introduces the EXP speciﬁcation – a versatile expansion interface for FPGA development boards that allows