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Quantum Transport in InAs Nanowires with Etched Constrictions and Local Side-gating
by
Yao Ma
A thesis submitted in conformity with the requirements for the degree of Master of Applied Science
Graduate Department of Electrical and Computer Engineering University of Toronto
© Copyright by Yao Ma 2012
ii
Abstract
Quantum Transport in InAs Nanowires with Etched Constrictions and
Local Side-gating
Yao Ma
Master of Applied Science
Graduate Department of Electrical and Computer Engineering University of Toronto
2012
To study transport properties in single InAs nanowires (NW) with etched constrictions, a bunch
of back-gated single InAs NW devices were made. The standard device contained a NW section
with an etched constriction, placed between two pre-patterned side-gates. For comparison,
devices either without etched constriction or without side-gates were also fabricated.
Transport measurement results of three devices were presented and discussed. The device
without side-gates exhibited Coulomb blockade due to electron tunneling through double
quantum dots (QDs). The device without the etched constriction displayed conductance
quantization. The standard device showed both Coulomb blockade (due to electron tunneling
through either multiple QDs or single QD) and Fabry-Perot conductance oscillation at different
gate bias regime.
A 3-D electrostatic and 2-D eigenvalue coupled simulation was conducted to explain the
observed conductance quantization. This model suggests that the nonuniform potential
distribution in a thick NW dramatically modifies the confinement energies in the NW.
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Acknowledgments
I begin by sincerely thanking my thesis supervisor Prof. Harry Ruda, Director of the Center for
Advanced Nanotechnology (CAN), first of all for his support and encouragement throughout
completion of the research activities. Prof. Ruda’s exceptional scientific creativity and
knowledge shine through in the feedback he gives his graduate students. He guided me through
all kinds of difficulties and always made sure I was on the right track. I cannot express more of
my gratitude to him.
I reserve special and most emphatic thanks to Dr. Joe Salfi, a former PhD student of CAN, for
teaching me all the necessary experimental skills I needed and inspiring my research curiosity in
every way he could.
I thank Dr. Selva Nair, a senior scientist of CAN, for fruitful discussions on the theoretical
modeling which is presented in Chapter 4. He is always kind, patient and ready to help me. I
learned so much from him.
I am very grateful to Dr. Fangmin Zhang, one of my best friends, for her help in some of the data
processing as well as her encouragement and company during the past three years.
I also want to thank Michael Chen, a master student of CAN. He helped me finish fabricating
and measuring the sample discussed in Chapter 4 during my absence.
To my committee consisting of Prof. Ruda, Prof. Kherani, Prof. Helmy and Prof. Ng, I reserve
special thanks for them to spend time reading my thesis and examine the thesis defence.
Finally, to my parents and my wife, I express my sincere thanks for their support and
encouragement.
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Contents
Chapter 1 Introduction ............................................................................................................. 1
1.1 Semiconductor Nanowires as Building Blocks for Future Electronic Devices .................... 1
1.2 Background Theory .............................................................................................................. 3
1.2.1 Single Electron Tunneling in Semiconductor Quantum Dots........................................ 3
1.2.2 Ballistic Transport in Quantum Wires ......................................................................... 10
1.2.3 Fabry-Perot Electron Interference in Electron Waveguides ........................................ 19
1.2.4 Surfaces and Interfaces in Semiconductor Nanowire Devices .................................... 20
1.3 Motivations, Objectives and Thesis Outline ....................................................................... 22
Chapter 2 Methods .................................................................................................................. 24
2.1 Single InAs Nanowire Device Fabrication ......................................................................... 24
2.2 Experimental Setup for Transport Measurements .............................................................. 29
Chapter 3 Quantum Transport Phenomena in Single InAs Nanowires with Etched
Constrictions ................................................................................................................................ 33
3.1 Introduction ......................................................................................................................... 33
3.2 Side-gating Effect: Hysteresis ............................................................................................. 34
3.3 Coulomb Blockade in an Etched InAs Nanowire without Side-gating .............................. 36
3.4 Transport Phenomena in an InAs Nanowire with Single Etched Constriction and Side-
gating ......................................................................................................................................... 40
3.4.1 Interaction between Side-gate and Back-gate .............................................................. 41
3.4.2 Transport Phenomena in the Short-etched Section — Low Back-gate Bias ............... 43
3.4.3 Transport Phenomena in the Short-etched Section — High Back-gate Bias ............... 48
3.4.4 Transport Phenomena in the Long-etched Section ...................................................... 51
v
3.5 Conclusions ......................................................................................................................... 52
Chapter 4 Conductance Quantization in a Thick InAs Nanowire with Side-gating ......... 53
4.1 Introduction ......................................................................................................................... 53
4.2 Data Processing ................................................................................................................... 55
4.3 Evidence of Subband Quantization ..................................................................................... 58
4.3.1 Linear and Nonlinear Transport at Low Temperature ................................................. 58
4.3.2 Linear Transport in a Magnetic Field .......................................................................... 60
4.3.3 Linear Transport at Higher Temperatures .................................................................... 62
4.4 Three-dimensional Electrostatic and Two-dimensional Eigenvalue Coupled Modeling of
the Nanowire System ................................................................................................................ 64
4.4.1 Model Description ....................................................................................................... 65
4.4.2 Results of the Model .................................................................................................... 68
4.5 Validation of the Model ...................................................................................................... 75
4.6 Conclusions ......................................................................................................................... 79
Chapter 5 Conclusions and Future Outlook ......................................................................... 81
Bibliography ................................................................................................................................ 83
vi
List of Tables
Table 3.1: Measured gate leakage current at different gate biases. 1st and 2nd number in
each cell represent Ibg and Isg, respectively, in unit of nA. ............................................... 42
Table 3.2: Key parameters of the QD extracted from the labeled Coulomb diamonds in
Figure 3.6b. .......................................................................................................................... 45
Table 3.3: Extracted lever arms for the three Coulomb peaks marked with arrows in Figure
3.6a, using Eq. (1.5) and assuming the electron temperature to be around 15 K. ............... 46
Table 4.1: Comparison between the calculated and observed subband spacing. The 1st and
2nd column list calculated subband spacing between two successive subbands located
above and below the Fermi level at the onset and end of each plateau, respectively,
based on our coupled simulation. The 3rd column is the extracted average subband
spacing for each plateau from the transconductance diamonds in the stability diagram.
The 4th column is the calculated subband spacing of the “particle in a cylinder”
model. .................................................................................................................................. 73
vii
List of Figures
Figure 1.1: Schematic diagram of the QD system based on CI model. The QD is coupled to
source and drain through two tunnel barriers and its energy structure is tuned by a
nearby gate. Note that tunnel barriers are characterized by a tunnel resistor and a
capacitor connected in parallel, as indicated in the inset. ...................................................... 4
Figure 1.2: QD in the linear transport regime. (a) If no level in the dot lines up with the
chemical potential in the leads, the electron number is fixed at N-1 due to Coulomb
blockade. (b) The level is in resonance with the chemical potential in the leads, so
the number of electrons can alternate between N-1 and N, resulting in a single
electron current. (c) Calculated Coulomb peak lineshape in the liner response regime
with experimental parameters. ............................................................................................... 6
Figure 1.3: QD in the nonlinear transport regime. (a) Stability diagram of a few-electron
QD with fixed number of electrons on the dot and physics (Coulomb blockade (CB),
single electron tunneling (SET) and double electron tunneling (DET)) labeled in the
corresponding regions. The red line represents the linear transport regime ( 0).
The dashed lines indicate where the current changes due to the onset of transitions
involving excited states. (b) – (e): Energy level alignment diagrams for four points
labeled as gray square, black circle, black square and gray circle, respectively. Top
and bottom black lines represent chemical potentials for the 2nd GS(2) and 3rd
GS(3)electron, thick and thin blue lines represent exited states for the 1st ES(1)and
2nd ES(2) electron. ................................................................................................................. 8
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Figure 1.4: Schematic diagram of two QDs connected in series coupled to each other
through a tunnel barrier. A common gate bias is used to tune the energy levels of the
two dots at the same time. ..................................................................................................... 9
Figure 1.5: 1-D subbands and electron transmission. (a) Dispersion relation in the 1-D
channel. States with negative propagate from right to left and are fed from the
right reservoir with chemical potential and vice versa. The energy interval is
given by the bias V applied between the two reservoirs. Here V < 0, so a net current
flows from left to right. (b) Schematic diagram of the adiabatic limit and the abrupt
limit for the interfaces between the reservoirs and the 1-D channel with the
dimension of the channel and the illustrative energy spectrum of the system labeled.
(c) The single-mode transmission probabilities and total transmission probabilities as
a function of 0 for = 3 based on the saddle-point model, showing T
as a step-like function of the energies in the channel. ......................................................... 13
Figure 1.6: (a) Classical motion of a particle in a 1-D conductor with a magnetic field
perpendicular to the transport direction for different energies and center coordinates,
showing the formation of pure cyclotron orbit (red circle) and skipping orbit (solid
blue curve). While the impurity may momentarily disrupt the forward propagation of
the electron, it is ultimately restored as a consequence of the strong Lorentz force.
Thus the skipping orbit in a conductor at high magnetic fields can suppress
backscattering. (b) Schematic Zeeman splitting of spin-degenerate magneto-subbands
in a magnetic field. .............................................................................................................. 16
Figure 1.7: (a) Stability diagram of 1-D system. Diamond patterns represent conductance
plateaus with labeled conductance values in unit of 2e2/h. Blue arrow denotes a type
of intersection whose corresponding bias levels equal the subband spacing. Inset: The
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spatial distribution of the chemical potential along the 1-D system at finite source and
drain bias. (b) - (d) Energy landscapes for points labeled as black, gray and empty
square, respectively, illustrating the meaning of left/right-tilted stripes and the
evolution of the integer-half-integer plateau behavior expected as the bias is
increased. The half plateau appear when the number of conducting subbands for the
two directions of transport differs by 1 and the integer plateau is retrieved when the
number differs by 2. ............................................................................................................ 17
Figure 2.1: Main steps of device fabrication. (a) 1st exposure and metallization transferred
patterns of the source (S)/drain (D) contacts, side-gate (SG) electrodes and local
markers onto the substrate with respect to the NW. (b) 2nd exposure opened an
etching window for the etchant, which was aligned to previous metal patterns via
local markers. Using resist as the etching mask, the NW section exposed to the
etchant was etched to a desired depth. (c) 3rd exposure and 2nd metallization
transferred patterns of bonding pads and traces (yellow) connecting previous metal
patterns (orange) onto the substrate. Previous metal patterns are barely seen at this
scale. (a) and (b) are actually enlarge views of the dark blue square region. ...................... 28
Figure 2.2: Experimental setup. (a) Custom built sample holder. A top cooper plate presses
down the LCC towards the spring loaded probes mounted inside the G10 fixture,
providing both thermal anchor and electrical contacts for the sample. (b) Cryostat and
electromagnetic system. The sample holder is located in the extender of the cryostat
which can be inserted into the gap of the two magnets and rotated by 90 °. The
magnetic field is controlled by a programmed power supply (Agilent E3631A). (c)
Circuit layout for differential conductance measurement. AC and DC source/drain
biases are coupled by a transformer, attenuated by a divider and then applied onto the
x
drain contact of the device. Current from the source contact is amplified by a current
preamp and measured by a lock-in. Back/side-gate biases are applied through
protecting resistors to the rear of the sample and side-gate electrodes, respectively. ......... 31
Figure 3.1: (a) Transfer characteristics of a side-gated InAs NWFET, showing distinct
hysteresis at room temperature (black curve) and reduced hysteresis at lower
temperatures (red and blue curves). Green arrows indicate the sweep directions of
side-gate voltage. (b) Transfer characteristics of the same device gated by the back-
gate at room temperature showing little hysteresis. (c) Schematic of the proposed
oxide trap charging mechanism for side-gating. Here the NW is grounded through
source and drain contacts and a positive bias is applied to the side-gate. When the
bias reaches a certain value, the electric field between the gate electrode and the NW
may be high enough to induce electron tunneling from the oxide traps to gate
electrode. Corresponding energy diagram is also shown to illustrate the tunneling
situation. .............................................................................................................................. 35
Figure 3.2: (a) Linear conductance in the pinch-off region of the transfer characteristics of
the device. Three peaks are visible. The second peak is superimposed with RTS. The
third peak denotes the onset of the channel. Inset (I): SEM image of the device with
the source and drain contacts labeled. Inset (II): Transfer characteristics of the device.
The pinch-off region is highlighted with red rectangle. (b) Stability diagram
corresponding to the same back-gate voltage range in (a). Large diamonds reflect the
charge state of the smaller dot while the fast oscillations superimposed on the
boundaries of large diamonds are due to the charging of the larger dot. ............................ 38
Figure 3.3: (a) SEM image of the device studied in this section. Two etched constrictions
were fabricated on the same NW to examine the effect of etching length on transport
xi
properties. (b) Linear conductance as a function of side-gate and back-gate biases for
the short-etched constriction. The slope of stripes in region I and III is different from
the one in region II. Detailed bias spectroscopy was performed along marked arrows
except for the light green one. ............................................................................................. 41
Figure 3.4: (a) Schematic of the proposed model to explain observed change of relative
coupling between back/side-gate and the channel. Leakage paths from source and/or
drain contacts and side-gate electrodes to the back-gate were probably created during
the wire bonding which can be characterized by variable resistors. (b) Measured gate
leakage current at different gate voltages with side-gate connected to back-gate. ............. 43
Figure 3.5: (a) Linear conductance response along the orange arrow in Figure 3.3b. The
pattern looks very “noisy”, with random switching superimposed onto the
conductance trace. (b) Corresponding bias spectroscopy, showing irregular diamond
patterns that are not closed in the pinch-off region. ............................................................ 44
Figure 3.6: (a) Linear conductance response along the yellow arrow in Figure 3.3b. (b)
Corresponding bias spectroscopy. Three Coulomb diamonds labeled with numbers
can be clearly identified with well defined boundaries. ...................................................... 46
Figure 3.7: Enlarged view of the three Coulomb peaks marked with arrows in Figure 3.6a
(gray curves) and the best fit to theses peaks (black curves). ............................................. 47
Figure 3.8: Linear conductance response of the device at Vbg =2.7 V, corresponding to the
light green arrow in Figure 3.3b. Inset: Linear conductance response of the device at
Vbg =3 V, corresponding to the purple arrow in Figure 3.3b. ............................................. 49
Figure 3.9: Linear conductance in the pinch-off region (a) and the following overshooting
region (b) at Vbg = 3 V (along the purple arrow in Figure 3.3b). (c) Linear
conductance on the first plateau at Vbg = 2.7 V (along the red arrow in Figure 3.3b).
xii
(d) - (f) Bias spectroscopy corresponding to the linear conductance in (a) - (c). The
grayscale bars are in the unit of 2e2/h. ................................................................................. 50
Figure 3.10: A representative measurement result taken at Vbg = 2V for the long-etched
section. (a) Linear conductance in the pinch-off region. (b) Linear conductance in the
following sub-threshold region. (c) and (d) Bias spectroscopy corresponding to linear
conductance in (a) and (b). Scale bars are in the unit of 2e2/h. ........................................... 51
Figure 4.1: (a) SEM image of the device. This chapter focuses on the measurements on the
section without etching. (b) Gray scale profile along the yellow dashed line providing
a more accurate measure for the geometry dimensions (c) Linear conductance as a
function of side-gate and back-gate biases. Stripes with almost constant slopes
indicate independent coupling to the channel from the two gates. Experiment results
along the two arrows are presented in this chapter. ............................................................. 54
Figure 4.2: Raw data of the finite bias spectroscopy and associated data processing. (a)
Raw data of G-VDS traces (only the positive scan of VDS, i.e., from -30 mV to 30 mV
is plotted) for different Vg. Vg was increased from -8 V to 8 V stepped by 0.05 V
between successive VDS sweeps. (b) G-VDS traces after the subtraction of “self-gating”
effect and compensation for the dip near zero source and drain bias based on the raw
data in (a). (c) G-VDS traces of testing resistors, demonstrating the irrelevance
between the dip feature and the sample conductance. (d) Correction for the dip
feature. By multiplying the conductance in the dip region with the calculated average
peak-to valley ratio, the dip is compensated to an average conductance level outside
the dip. ................................................................................................................................. 57
Figure 4.3: (a) Linear conductance as a function of gate voltage. 11 conductance plateaus
can be identified with the middle 5 ones marked by arrows. Inset: A zoom-in of the
xiii
2nd plateau, showing the small oscillations superimposed on the plateau. (b) Gray
scale plot of the normalized absolute value of transconductance as a function of gate
voltage and source/drain bias. Diamond patterns around zero bias corresponding to
linear conductance plateaus in (a) are visible. (c) Gate voltage sweeps of G for fixed
values of VDS from 0 to 30 mV, stepped by 3 mV. Black circles highlight half
plateaus. ............................................................................................................................... 59
Figure 4.4: Magnetotransport characters of the device. Differential conductance was
measured as function of side-gate bias without magnetic field (black curve) and with
a magnetic field of 0.6 T which is perpendicular to the sample plane (red curve). Four
plateaus labeled with numbers can be identified. Compared to the case where B = 0 T,
at B = 0.6 T, conductance on each plateau increases and there is a half plateau
appearing between the 3rd and the 4th plateaus possibly due to the Zeeman splitting of
a spin-degenerate level, as indicated by the blue ellipse. The distance in terms of Vsg
between the split plateaus and the original plateau is marked by the green dashed
lines. ..................................................................................................................................... 61
Figure 4.5: Liner transport at higher temperatures. G-Vg curves corresponding to T = 20 K
and 30 K are shifted for clarity. Most conductance plateaus are washed out at T = 30
K, providing a rough estimation for the subband spacing. Inset: G-Vg curve at room
temperature, from which the field-effect mobility can be extracted. .................................. 63
Figure 4.6: Screenshot of the 3-D electrostatic simulation result, showing the simulated
geometry and the potential distribution with source and drain grounded and Vbg = Vsg
= -7 V. .................................................................................................................................. 67
Figure 4.7: Simulated number of occupied subbands as a function of gate bias. Red curve:
result from the coupled simulation carried out by the author. Labeled numbers
xiv
represent the resembled conductance plateaus. Black curve: result from the approach
adopted by Fort et al [Fort 2012]. ....................................................................................... 70
Figure 4.8: Calculated probability density profiles at Vg = -6 V for the five lowest lateral
modes with corresponding energy levels with respect to conduction band edge
labeled. No degeneracy is observed and the wave functions are pushed up and
sideways by back and side-gate bias, indicating the effect of the nonuniform potential
distribution inside a thick NW at large negative gate bias. ................................................. 71
Figure 4.9: (a) Calculated gate capacitance per unit length as a function of gate bias
from the 3-D electrostatic simulation. Also shown is the back-gate capacitance
calculated using Eq. (4.2) for the same device. (b) Calculated quantum capacitance
per unit length as a function of gate bias using a combination of Eq. (4.8) and results
from the 2-D eigenvalue simulation. ................................................................................... 74
Figure 4.10: Calculated potential distribution profiles inside the NW at the middle slice (x
= 0 nm) and the slice 100 nm left to it (x = -100 nm), at two gate biases (Vg = -2 and -
6 V). ..................................................................................................................................... 76
Figure 4.11: (a) Average electrostatic energy distribution along the NW. From top to
bottom: distributions at Vg = -8 ~ 8 V stepped by 2 V. (b) Lowest subband level
distribution along the NW with fitted Fermi level labeled. From top to bottom:
distributions at Vg = -8 ~ 0 V stepped by 2 V. .................................................................... 77
Figure 4.12: Calculated 1-D carrier concentrations as a function of gate bias based on the
3-D Thomas-Fermi scenario (squares) and the 2-D Schrodinger equation at T = 10 K
(circles) and T = 0 K (triangles). ......................................................................................... 79
1
Chapter 1
Introduction
1.1 Semiconductor Nanowires as Building Blocks for Future
Electronic Devices
Electronic devices form the basic constituents of modern integrated circuits. They come in many
varieties and are used to process analog signals, perform logic operations and store information
in digital memories. Apart from these purely electronic functions, other devices interact with
light, or sense changes in the environment. Semiconductor nanowires (NWs) offer many
opportunities for the assembly of nanoscale devices by the “bottom-up” paradigm [1] and have
been proposed and intensively studied as a realistic add-on to mainstream Si technology [2]. One
key factor motivating the boom of NW research is that, compared with device structure
fabricated by the “top-down” approach, “bottom-up” synthesized NW materials offer well-
controlled size in at least on critical device dimension, channel width, that is at or beyond the
limits of top-down lithography [1]. In addition, the crystalline structure, smooth surfaces and the
ability to produce radial and axial heterostructures can reduce scattering and result in higher
carrier mobility, meanwhile, offer exciting new possibilities for device architecture [3].
Thus far, all the above mentioned functions of electronic devices have been demonstrated using
semiconductor NWs [1, 4, 5, 6]. To keep the scope of this introduction manageable, in the
following part of this section, we only focus on NW devices and applications that are relevant to
this thesis and restrict ourselves within the content of electronics.
Semiconductor NWs are quasi-one-dimensional (quasi-1-D) systems by nature. In
semiconducting 1-D structures (also referred to as quantum wires), carriers are confined in two
2
dimensions. One of the representative 1-D systems is quantum point contact (QPC), a narrow
constriction between two wide electrically conducting regions, of a width comparable to the
electronic wavelength [7]. The hallmark of QPC is its quantized conductance in unit of e2/h per
electronic subband. Since the conductance of QPC strongly depends on the confinement
potential of the constriction, any potential fluctuation in the vicinity will influence the current
through the QPC. Therefore, QPCs can be used as extremely sensitive charge detectors. In view
of quantum computation in solid-state systems, QPCs may be used as readout devices for the
state of a quantum bit (qubit) [8]. In Section 1.2.2 we will see that conductance quantization is a
universal characteristic of 1-D systems, provided that the transport is ballistic (scattering-free) or
quasi-ballistic. Thus we expect semiconductor NWs to have similar behavior [9, 10] and
applications.
An emerging frontier in condensed matter research is the coherent, optics-like manipulation of
electrons for information processing and storage. In high quality 1-D or quasi-1-D systems, such
phase coherent transport over hundreds of nanometers has been observed [11, 12]. Interferometer,
a staple of coherent optics, has also been realized in these systems. For instance, Fabry-Perot (F-
P) electron/hole interference has been observed in carbon nanotubes [13, 14, 15, 16] and more
recently, in semiconductor NWs [17, 18], which underscores the potential of NWs for on-chip
realization of electron optics [19].
Quantum dots (QDs) are zero-dimensional (0-D) systems in which the motion of carriers is
confined to very small “box-like” volumes. QDs are considered as promising systems for
implementation of spin “qubits” in proposed schemes for quantum computation [20]. The
cylindrical morphology makes NWs natural platform for fabricating QDs: the cylindrical
geometry has already provided lateral confinement for carriers, thus one only needs to create two
longitudinal barriers to form a QD. What makes NWs more attractive to host QDs is that linear
arrays of coupled QDs can be easily made along the axis of a NW if multiple longitudinal
barriers are created. At the ends of the arrays, the QDs can be coupled to 1-D, quasi 1-D or bulk-
like reservoirs, depending on the lateral dimensions of the hosting NWs [21].
3
1.2 Background Theory
1.2.1 Single Electron Tunneling in Semiconductor Quantum Dots
Among the different QD systems that have been studied, the type that is relevant to this research
involves a semiconducting island coupled to source and drain contacts by two tunnelling barriers.
When the electron tunneling to and from the dot is sufficiently weak, the number of electrons on
the dot will be a well defined integer N. To increase this number by 1, electrons in the reservoirs
must have sufficient energy to overcome the mutual electrostatic Coulomb repulsion among
electrons in the QD plus the quantization energy due to the confinement potential within the QD.
If this condition is satisfied, current flow will occur through sequential tunnelling events of
single electrons through the dot, causing N to fluctuate by one; otherwise the QD is said to
operate in Coulomb blockade regime and no current can flow through the QD. To gain better
control over the QD system, a gate electrode is normally added to electrostatically tune the
energy in the QD. In the following section, a widely used model based on the above device setup
will be introduced and its implications for the lineshape of the Coulomb peaks and the stability
diagram will be discussed. Finally the model will be extended to the case of DQD.
Constant Interaction Model
The constant interaction (CI) model [22] provides an approximate description of the electronic
structure of the QD system. It is based on two assumptions. First, the Coulomb interactions
among electrons in the dot, and between electrons in the dot and those in the environment, are
parameterized by a single, constant capacitance C, which is the sum of the capacitances between
the dot and the source , the drain and the gate . Second, the single-particle energy levels
are independent of the electron-electron interactions. A circuit representation of the QD
system based on above descriptions is depicted in Figure 1.1.
4
Figure 1.1: Schematic diagram of the QD system based on CI model. The QD is coupled to source and drain through
two tunnel barriers and its energy structure is tuned by a nearby gate. Note that tunnel barriers are characterized by a
tunnel resistor and a capacitor connected in parallel, as indicated in the inset.
Under these assumptions, the total energy of a dot with N electrons in ground state, with
voltages , and applied to the source, drain and gate, respectively, is given by
| | 2⁄ ∑ (1.1)
where | | represents both the unintentional background polarization charge due to
workfunction differences and random charges trapped near the junctions.
The chemical potential of the dot is defined as
N 1 | | (1.2)
where ⁄ is the charging energy. When N is fixed, a change in gate voltage ∆ induces
a change in the chemical potential by | |
∆ | | ⁄ ∆ . The ratio ⁄ is
called lever arm.
The energy required to realize the transition between successive ground states is the so called
addition energy:
1 ∆ (1.3)
QD
RD,CS
Vbg
Drain Source
RD,CD
CG
VDS
R
C
5
where ∆ is the adjacent single-particle level spacing. To resolve well defined
Coulomb blockade effects, the Coulomb gap, , must greatly exceed the thermal energy:
. A further constrain is that the quantum fluctuations in the electron number, N,
are so small that the electron is well localized on the dot. A hand-waving argument is to consider
the energy uncertainty relationship ∆ ∆ /2, where ∆ ~ and the time to transfer
electron into and out of the island given by ∆ where is the smaller of the two tunnel
resistances [23]. Combining these two expressions together gives . Neglecting
∆ for relatively large QDs, we have , so that = 25.8 kΩ, i.e., the tunnel
resistance should be greater than the quantum resistance of 25.8 kΩ in order to see clear
Coulomb charging effects.
Linear Transport Regime
When the source and drain bias is small ( , ∆ , ), the QD system is operated
in the linear transport regime, where current can only flow when the chemical potential of the dot
lines up within a few of the chemical potential in the leads by tuning the gate bias. This
gives rise to a series of conductance oscillations as a function of gate bias, as illustrated in Figure
1.2a-b. Equating the induced chemical potential change in the dot by gate bias with Eq. (1.3), we
obtain the gate period corresponding to two successive conductance peaks:
∆ (1.4)
As long as , the width of these peaks will essentially be limited by thermal
broadening and therefore smear out at temperatures greater than the energy width of the
Coulomb blockade regime. The conductance linewidth has been calculated in the classical limit
of ∆ by Beenakker as [24]
. (1.5)
6
where G is the height of the Nth peak. Results using Eq. (1.5) for = 1meV, = 0.25 and
= 3.2aF, which are similar to the extracted device parameters from experiment, are shown in
Figure 1.2c, illustrating the expected lineshape.
Figure 1.2: QD in the linear transport regime. (a) If no level in the dot lines up with the chemical potential in the
leads, the electron number is fixed at N-1 due to Coulomb blockade. (b) The level is in resonance with the
chemical potential in the leads, so the number of electrons can alternate between N-1 and N, resulting in a single
electron current. (c) Calculated Coulomb peak lineshape in the liner response regime with experimental parameters.
Nonlinear Transport Regime
By increasing , multiple dot levels can participate in electron tunneling, which is the situation
of nonlinear transport. Typically the chemical potential of only one reservoir is changed in
experiments and the other one is kept fixed [8]. Here we set the source to be grounded, i.e., = 0.
As changes, the levels of the dot also changes due to the capacitive coupling between the dot
and the drain. A powerful tool, called the stability diagram, which is a plot of differential
0 50 100 150 200 250 3000.0
0.2
0.4
0.6
0.8
1.0
1.2
G/G
max
VG(mV)
N N+1N-1
(a)
(c)
(b)
7
conductance ⁄ as a function of and , is widely used to investigate the nonlinear
transport characteristics of the QD system. A schematic example of such a diagram for a few-
electron QD is shown in Figure 1.3a. The red line denotes the linear response discussed earlier,
where cross points represent the Coulomb peaks. For each transition point, at either sign of ,
a V-shaped region is outlined. For instance, the point labeled by empty square represents the
alignment of 2 with and . Starting from this point, when 0, two lines labeled
with L and R form edges of the V shape, which denote the alignment of 2 with drain and
source, respectively, as depicted in Figure 1.3b and d. To obtain the slopes of these lines,
consider the change of chemical potential of the dot induced by the change of and based
on Eq. (1.2). On the line labeled with R, ∆ 2 induced by ∆ equals to ∆ 2 induced by ∆ ,
thus we have | | ∆ | | ∆ ; On L, ∆ equals to the summation of ∆ 2 induced by
∆ and ∆ , which gives | |∆ | | ∆ | | ∆ . Solving for these two equations, and
note that ∆ ∆ since = 0, we obtain
∆∆
, ∆∆
(1.6)
Within the V shapes, chemical potentials and associated excited states of the QD fall into the bias
window and single electron tunneling happens. The overlapping area constituted by the outside
of all V shapes forms diamond-like Coulomb blockade regions where the number of electrons on
the QD is fixed at the labelled value. When is further increased such that the bias window is
equal or greater than the addition energy (see Figure 1.3e), the electron number can alternate
between N-1, N and N+1, leading to double electron tunneling. We can imagine that increasing
even more would eventually result in triple electron tunneling, quadruple electron tunneling,
etc.
We can also use the stability diagram to find the energies of the excited states. Where a line of a
transition involving one excited state touches the Coulomb blockade region, the bias window
exactly equals the energy level spacing. Figure 1.3b-d shows the level diagrams for 1
2 , 1 2 and 2 2 , where and represent the ground
state and the excited state for N electrons in the QD.
8
Figure 1.3: QD in the nonlinear transport regime. (a) Stability diagram of a few-electron QD with fixed number of
electrons on the dot and physics (Coulomb blockade (CB), single electron tunneling (SET) and double electron
tunneling (DET)) labeled in the corresponding regions. The red line represents the linear transport regime ( 0).
The dashed lines indicate where the current changes due to the onset of transitions involving excited states. (b) – (e):
Energy level alignment diagrams for four points labeled as gray square, black circle, black square and gray circle,
respectively. Top and bottom black lines represent chemical potentials for the 2nd GS(2) and 3rd GS(3)electron, thick
and thin blue lines represent exited states for the 1st ES(1)and 2nd ES(2) electron.
Classical Theory of Electrostatically Coupled Double Quantum Dots
Here we consider two QDs connected in series, coupled to each other by a tunnel barrier
represented by a tunnel resistor and a capacitor in parallel. Each dot is capacitively
coupled to a gate bias through a capacitor , and to the source or drain through a tunnel
barrier represented by a tunnel resistor and a capacitor in parallel. The source and
drain bias is applied to the drain, with the source grounded. The cross coupling between
(b) (c) (d) (e)
(a)
V DS
VG
01 2
3 4 5CB CBCB CB CB
SET SETSETSETSET
DET DET DET
DET DET
TET TET
V DS <
0
LR
9
source and dot 2 ( ) and between drain and dot 1 ( ) are also included. A schematic diagram
of the described DQD system is shown in Figure 1.4.
Figure 1.4: Schematic diagram of two QDs connected in series coupled to each other through a tunnel barrier. A
common gate bias is used to tune the energy levels of the two dots at the same time.
We ignore the influence of discrete quantum states. If stray capacitances are negligible, the
double dot electrostatic energy in the linear transport regime reads [25]
, + (1.7a)
| |
(1.7b)
where is the number of electrons on dot 1(2), is the charging energy of the
individual dot 1(2), is the electrostatic coupling energy, which is the change in the energy of
one dot when an electron is added to the other dot. These energies are expressed in terms of the
capacitances as follows:
EC CC C
C C CM, EC C
C CC C CM
, ECM CM
C CC C CM
(1.8)
where is the total capacitance of dot 1(2):
Similar as the single QD case described in CI model, the chemical potential , of dot
1(2) is defined as
QD1 QD2
RM, CM
VG
source drain
RS, CS1 RD, CD2
CG1 CG2
VDS
CS2 CD1
10
, , 1,
| |
(1.9a)
, , , 1
| |
(1.9b)
In the case of nonlinear transport, assume the bias voltage is applied to the drain and the source
is grounded, then the bias voltage is coupled to the DQD through the capacitance of the drain and
hence also affects the electrostatic energy of the system. The bias dependence can be accounted
for by replacing CG1(2)VG with CG1(2)VG +CD1(2)VDS in Eq. (1.7) and Eq. (1.9).
1.2.2 Ballistic Transport in Quantum Wires
In this section we consider a simple case where a 1-D conductor is connected to the left and right
electron reservoirs with chemical potentials and . The current carried by N occupied 1-D
modes is the sum of right and left-moving current due to the electron flows from the left and
right reservoirs, and is given by [23]
| | ∑ ∑ , , (1.10)
where is the transmission probability of an incoming wave in mode i on one side, to be
transmitted into mode j on the other side. , is the quasi-equilibrium distribution
function of the left (right) contact. When , a net current can flow through the system
because the distribution functions for left and right-moving electrons will differ, as is depicted in
Figure 1.5a.
In the linear transport regime where , , ,
⁄ , combined with Eq. (1.10) we obtain the linear conductance:
∑ ∑ (1.11)
11
We now decouple the effect of temperature and transmission probabilities to exam these two
effects separately.
Linear Transport in an Ideal 1-D Conductor
When T 0 K, the distribution function can be approximated as a step function, so Eq. (1.10)
becomes | | ∑ ∑ , which gives ∑ , where
∑ .
We first assume the 1-D conductor is a perfect channel, i.e., there is no backscattering due to
impurities in the channel and surface states/roughness. This assumption allows us to focus on the
effect of the shape of the conductor (see Figure 1.5b) on . We classify the 1-D system into
two types, long and short, based on the aspect ratio, L/W, where L and W are the channel length
and width, respectively. By examining how smooth the transition is from the 1-D channel to the
reservoirs, we can also distinguish the 1-D system with sharp transitions and smooth transitions.
To be more precise, a 1-D system with smooth transition is described by the “adiabatic model”
[26], which assumes the spatial variation of the potential in the transport direction is much
slower than in the transverse direction. The case of sharp transition limit was studied by Szafer
and Stone [27]. Both limits give similar . To appreciate how depends on , we adopt
the saddle point model [28] which assumes the electrostatic potential near the bottleneck of the
constriction has the form of , with the corresponding
subband levels , where i = 1, 2, 3, …, is the potential at the saddle,
and represent the curvatures of the potential. Thus
1 1 exp 1 1 exp 2 . Based on this
expression, transmission probabilities as a function of for = 3 are reproduced in Figure
1.5c, from which we can see that the transmission rises quickly from 0 as the subband level
moves toward the Fermi level of the channel, and approaches unity when the subband level is
below the Fermi level. The total transmission probability T, and also the conductance, is
therefore a step-like function of the energies of the channel. Experimentally, the energy levels of
12
the channel can be tuned by a gate bias, thus we expect to observe conductance quantization with
the unit of as the gate bias is swept for a 1-D ballistic conductor. Note that even though the
electron transport in the channel is truly ballistic without experiencing any scattering, there still
exists a minimum resistance , which was interpreted by Imry [29] as a contact resistance
arising from the rearrangement of the current from being carried by a large number of modes in
the reservoirs to being carried by very few modes in the channel, as illustrated in Figure 1.5b.
Another important point here is that the conductance is controlled by the mode spacing at the
narrowest point of the channel. Thus either a QPC or a longer wire may exhibit conductance
quantization, provided that the electron transport remains ballistic.
13
Figure 1.5: 1-D subbands and electron transmission. (a) Dispersion relation in the 1-D channel. States with negative
propagate from right to left and are fed from the right reservoir with chemical potential and vice versa. The
energy interval is given by the bias V applied between the two reservoirs. Here V < 0, so a net current flows from
left to right. (b) Schematic diagram of the adiabatic limit and the abrupt limit for the interfaces between the
reservoirs and the 1-D channel with the dimension of the channel and the illustrative energy spectrum of the system
labeled. (c) The single-mode transmission probabilities and total transmission probabilities as a function of for
= 3 based on the saddle-point model, showing T as a step-like function of the energies in the channel.
One difference between the two limits is that under the adiabatic approximation the off-diagonal
elements of the transmission matrix can be neglected, i.e., = 0 for , whereas an
abrupt transition may give rise to intersubband scattering by itself and disrupt the conductance
N+1
N
N‐1
EF
Lμ
Lμ
Rμ
Rμ
E1
E2
E3 LμRμ
eV
E
kZ
(a) (b)
(c)
zL
W
0 1 2 3 4 5 6 7 8 9 100
1
2
3
h
T3(E)T2(E)
T(E)
(E-V0)/ ωz
T1(E)
h hh
E3/ ωzE2/ ωzE1/ ωz
14
quantization. Another difference lies in the response to the length of the channel. When the
channel is short the conductance steps are rounded due to tunneling through the channel for a
Fermi energy just below the next unoccupied level. This behavior has been observed in both
limits. However, as the channel becomes longer, sharp steps are found for a 1-D system in
adiabatic limit whereas resonances as a result of alternatively constructive and destructive
internal reflection within the channel appear as soon as the channel is long enough to damp out
the evanescent modes.
Effects of Disorder and Finite Temperature
Now we relax the previous assumption about a perfect channel and briefly discuss the influence
of disorder on the transmission properties of 1-D system. Backscattering by the potential
fluctuation due to impurities in the channel, surface roughness and surface states is normally
inevitable in real devices, which degrades the conductance below . It is important to realize
that in small nanostructures such as quantum wires the total scattering matrix through the
structure depends on the exact location of the impurities and boundary fluctuations. If such
inhomogeneous effects are important, the conductance in a sample with a slightly different
impurity configuration will be completely different. This behavior contracts from that of
diffusive transport over very long length scales, in which the contribution of many impurities
averages to a constant contribution to the conductance that depends only on their density but not
their exact location.
After we examine the role of transmission probabilities in determining the conductance at
ultralow temperatures, we now consider the influence of temperature on the conductance by
assuming the transmission coefficient of the ith mode is unity for energies greater than the
subband minimum and zero below. Then Eq. (1.11) becomes ∑
∑ ∑ ⁄ . This expression shares the identical feature
with the temperature dependence of Fermi-Dirac distribution function: the increase of
15
temperature causes the increased rounding of the plateaus until they eventually disappear when
the separation between mode energies is comparable to, or smaller than a few .
Edge States and Zeeman Splitting in 1-D Magnetotransport
A magnetic field perpendicular to the transport plane may also have its effects on the quantized
conductance. Van Wees et al. [30] showed that the plateaus are flattened with increasing
accuracy to about as a function of increasing magnetic field. Additional plateaus are seen to
arise at high fields, but at half steps of .
The flattening of the plateaus with increasing field is taken as a sign of reduced backscattering
and increased transmission due to an increasing amount of current being carried by edge states
[23]. Edge states in a quantum wire with the presence of a magnetic field can be understood in
the following qualitative picture: Assume electrons can only propagate along z directions in a
quantum wire with a hard wall confinement. The magnetic field is applied along –y direction, as
depicted in Figure 1.6. From the quantum mechanical solution of the electron motion in the plane
perpendicular to the magnetic field, the quantized cyclotron radius is given by
2 , corresponding to the associated Landau levels
, n = 0, 1, 2,…where ⁄ is the magnetic length and ⁄ is the cyclotron
frequency. The solution also defines a parameter called center coordinate: / , which
represents the average position of the wavefunction and the center position of the circular
cyclotron orbit of radius . From the viewpoint of the classical motion of the particle in the
waveguide, if is less than the distance from the center coordinate to one wall or the other so
that no scattering of the particle off the wall occurs, pure cyclotron-type motion is possible, as
shown by the red circular orbits in Figure 1.6; if is greater than distance between the center
coordinate to either wall, boundary scattering occurs, giving rise to skipping orbits, as shown by
solid blue orbits in Figure 1.6. If boundary scattering is assumed to be specular, the reflected
momentum is reflected momentum is such that the electron has a net momentum in the plus or
minus z direction, depending whether (and thus ) is positive or negative. The states
16
associated with these skipping orbits are referred to as edge states. As point out by Buttiker [28],
electrons propagating in edge states cannot be easily scattered over distances larger than the
magnetic length , because even if the electron is backscattered by an impurity, the resulting
Lorenz force exerted on the electron tends to push it back towards the boundary and so maintain
its skipping motion (Figure 1.6).
Figure 1.6: (a) Classical motion of a particle in a 1-D conductor with a magnetic field perpendicular to the transport
direction for different energies and center coordinates, showing the formation of pure cyclotron orbit (red circle) and
skipping orbit (solid blue curve). While the impurity may momentarily disrupt the forward propagation of the
electron, it is ultimately restored as a consequence of the strong Lorentz force. Thus the skipping orbit in a
conductor at high magnetic fields can suppress backscattering. (b) Schematic Zeeman splitting of spin-degenerate
magneto-subbands in a magnetic field.
The appearance of half integer plateaus at high fields can be straightforwardly explained by the
split of the two-fold spin-degenerate magneto-subbands by an amount of in a magnetic
field, forming distinct spin-up and spin-down states as depicted in Figure 1.6b. However, they
contribute only to the conductance, since the density of states is now reduced by a factor of
two.
Finite Bias Spectroscopy
Similar to the nonlinear transport in QD introduced in Section 1.2.1, employing a DC source and
drain bias as an energy reference gives access to the subband spacing, thus providing a powerful
tool (termed as finite bias spectroscopy) to further characterizes the 1-D system.
z
xB
impurity
(a) (b)EN
EN-1
17
Picciotto et al. explained how the chemical potential in the channel shifts with the applied finite
bias as a result of satisfying charge neutrality condition [31, 32]. An important point here is that
the charge density in the wire is nearly independent of the bias. This arises because with a small
wire capacitance, a large potential energy penalty is associated with charge imbalance. Charge
neutrality is thus facilitated by a uniform shift of the potential in the wire, such that
/2 (see the inset of Figure 1.7a). This potential shift reflects the screening of the applied bias
by the free charges and is accomplished by the two potential steps at the inlet and outlet of the
wire, respectively.
Figure 1.7: (a) Stability diagram of 1-D system. Diamond patterns represent conductance plateaus with labeled
conductance values in unit of 2e2/h. Blue arrow denotes a type of intersection whose corresponding bias levels equal
the subband spacing. Inset: The spatial distribution of the chemical potential along the 1-D system at finite source
and drain bias. (b) - (d) Energy landscapes for points labeled as black, gray and empty square, respectively,
illustrating the meaning of left/right-tilted stripes and the evolution of the integer-half-integer plateau behavior
expected as the bias is increased. The half plateau appear when the number of conducting subbands for the two
directions of transport differs by 1 and the integer plateau is retrieved when the number differs by 2.
EN
EN+1EN+2(b)
(a)
EN
EN+1EN+2(c)
EN
EN+1EN+2
(d)
VD
S
VG
VD
S>0
N N+1N-1N-2
N
N
N+1/2
N+1/2
N-1/2
N-1/2
N+3/2N-3/2
N-3/2
N-1 N+1
N-1
18
Glazman and Khaetskii [33] predicted that when | | , additional plateaus will appear in
the differential conductance. If the number of occupied subbands N is large, the additional
plateaus (half plateaus) are predicted to be midway between the plateaus given by . For
small N some deviations of the conductance from half-integer values could be expected. Patel et
al. [34] presented the first evidence for the appearance of the half plateaus. The concept of half
plateaus can be illustrated by sketches of energy landscapes shown in Figure 1.7b-d. When is
small such that same number of subbands (N) lies below and , the total number of
conducting subbands is 2N, and the associated conductance is . When is increased
to a level such that one subband bottom lies in between and , the total number of
conducting subbands becomes 2N+1, generating a conductance of / . When is
further increased such that two subband bottoms reside in between and , the total number
of conducting subbands returns to 2N so the integer plateau with is retrieved.
If we plot G as a function of gate voltage and source and drain bias, just as in Section 1.2.1, we
will obtain similar stability diagram for nonlinear transport in 1-D system. A schematic drawing
is shown in Figure 1.7a. For simplicity we assume all subbands are equally spaced and the
spacing does change with Vg and VDS. To be consistent with the experimental conditions (to be
introduced in Chapter 2), the chemical potential of the source contact is always set to ground.
Similar to Coulomb diamonds for 0-D system, here we see a series of diamond patterns as well,
but with different physical meaning: they represent conductance plateaus with labeled
conductance values in unit of 2e2/h. Similar to the 0-D case, left/right-tilted lines denote the
alignment of subband bottoms with chemical potentials of drain/source, as depicted in Figure
1.7c-d. The intersections (such as the one pointed by the blue arrow in Figure 1.7a) therefore
represent the situation where two successive subband edges both line up with contact potentials,
and the corresponding bias levels provide a direct measure of the subband spacing.
19
1.2.3 Fabry-Perot Electron Interference in Electron Waveguides
In analogy with the interference due to multiple reflections of light between two reflecting
surfaces of an optical F-P cavity, which gives rise to the constructive and destructive interference
patterns, the wave-nature of electrons allows quantum interference between propagating electron
waves in coherent electron waveguides. Such systems can also be regarded as open quantum dots
with the resonances corresponding to the broad energy levels of the quantum dot [35].
Now we focus the F-P interference in InAs NW system. Assume the propagating electron wave
in the cavity is a plane wave. Constructive interference is observed for 2 2 where N is
an integer and L is the length of the cavity. For a parabolic electron dispersion relation, the
chemical potential in the channel can be expressed as 2⁄ , where is
the Fermi level, is the bottom of the corresponding 1 D subband and is the effective mass.
Meanwhile, the chemical potential is proportional to the gate voltage: . Thus, the system
can be tuned in and out of the constructive interference which modulates carrier transmission
through the channel, leading to periodic conductance oscillations as a function of gate voltage.
The period in Vg is directly related to L. The change of the Fermi wave vector over one period of
the Fabry-Perot oscillations is / and the corresponding change in the carrier density is
2 ⁄ ∆ /| |, where is the gate capacitance per unit length, ∆ is the
oscillation period and D is the orbital degeneracy of the subband. Therefore, the effective length
of the cavity is [17]
2 | |/ ∆ (1.12)
As mentioned in Section 1.2.2, when the source and drain bias satisfies | | , the
total charge in the channel will be unaffected by . In this case, we can view the effect of
as raising the chemical potential of one contact by | | /2 while lowering the other by
| | /2. Now we follow the approach proposed by Liang et al [13] to briefly examine the
nonlinear response upon the application of bias voltage. If the electron transport through the
channel is ballistic, the total energy of the electrons involved in transport is conserved. The total
energy of electrons at the Fermi surface can be expressed as a sum of their kinetic energy and the
local self-consistent potential energy: , where z is the spatial position along the
20
channel. Using the parabolic electron dispersion relation, the wave number of electrons is given
by 2 2 ⁄ . The resulting phase shifts are given by
2 (1.13)
According to Eq. (1.13), changing the total energy of electrons at the Fermi surface by a source
and drain bias will shift the phase of electron waves. When the bias voltage increases to a critical
value VC such that 2 | | 2 , the condition of constructive interference
is satisfied and conductance resonance will occur. So we can imagine that in a stability diagram
where the differential conductance is plotted as a function of gate and source/drain bias,
conductance peaks/dips corresponding to constructive/destructive interferences will be periodic
in Vg and VDS, and F-P electron interference will manifest itself as chessboard-like patterns which
have been observed by all the above mentioned literatures.
1.2.4 Surfaces and Interfaces in Semiconductor Nanowire Devices
Surface states exist on both clean and adsorbate-covered semiconductor surfaces, originating
from dangling bonds and bonds between adsorbate and semiconductor surface atoms. At abrupt
metal-semiconductor interfaces, the wavefunctions of metal electrons decay exponentially into
the semiconductor. These tails represent metal-induced interface states. This concept also applies
to semiconductor-dielectric interfaces.
The net charge per unit surface area in surface states is given by
| | (1.14)
where and are the donor and acceptor surface state densities, and
are the donor and acceptor distribution functions, respectively [36]. The surface
state distributions can be characterized by a charge neutrality level , above which there are
predominantly acceptors and below which there are mainly donors. Eq. (1.14), together with the
concept of the charge neutrality level, will be adopted in Section 4.4.1 to model the potential
distribution in one of our NW devices.
21
Surface/interface states have pronounced effects on the nature and efficacy of carrier transport in
field-effect transistors (FETs). Due to the large surface area to volume ratio of NWs, these
effects play more significant roles in NW FETs. The high density of surface states can lead to
Fermi-level pinning, thereby depleting the carriers from near the surface [37] and acting as
scattering centers which reduce carrier mobility. We will return to this point in Chapter 4 where
we will evaluate this surface scattering effect in terms of diameter-dependency of NWs. Another
important consequence of surface states is the degradation of gate control efficacy, which leads
to surface recombination of carriers and also causes hysteresis due to charge-discharge transients
from the surface states [38].
InAs is known to have donor-type surface states which lead to the formation of an accumulation
layer at the surface. This mechanism was explained by Noguchi et al. [39]. Electrons usually
occupy the surface states below the charge neutrality level where the states derive their weight
equally from valence and conduction bands. The conduction band edge Ec at the Γ point in InAs
is much lower than the Χ minima so that is located above Ec. Therefore the surface states
between Ec and can emit electrons into the conduction band, forming the surface
accumulation layers. This important property facilitates the formation of Ohmic contacts
between InAs and most metals [40]. In Section 4.4 we will see that according to the fitting
between a proposed model and the experimental data, the donor-like surface states in one of our
InAs NW devices provide a significant fraction of free carriers in the NW channel and
locates approximately 100 meV above the “effective” .
For the Si/SiO2 interface of MOSFET devices, one can distinguish between charges located deep
inside the oxide (oxide-trapped charges and mobile ionic charges) and charges located at the
interface (fixed oxide charges and interface trap charges) [41]. Some forms of interface trap
charges may also be present at the bare surface of SiO2 in our samples. For example, non-
bridging oxygen (oxygen dangling bond) may be formed when Si-O bond is broken, which may
act either as acceptors or donors. Together with charges in the bulk of the oxide, they can
exchange charges with NWs or gate electrodes and affect the transfer characteristic of NW
devices. This issue will be further discussed in Section 3.2.
22
It is know from work done on MOSFETs that the presence of large number of capture and
emission processes with a broad distribution of timescales produces a 1/f-type noise spectra,
while in submicrometer devices the individual traps assume importance and produce discrete
switching events and random telegraph signals (RTS) [42]. This phenomenon has been carefully
studied in NW systems such as ZnO [43] and InAs [44, 45] NWFETs. Similar switching events
were observed in our etched NWs and manifest themselves in stability diagrams as abrupt
dislocations of conductance patterns in a similar fashion reported by Klein et al. [46], which
blurs the regular patterns and prevents us from accurately extracting some physical parameters of
the devices. This will be covered with more details in Chapter 3.
1.3 Motivations, Objectives and Thesis Outline
One common method to create tunneling barrier is to narrow the carrier transport channel by dry
or wet etching. QDs defined by such etched constrictions have been realized using top-down [46,
47, 48] and bottom-up [49] approach. Meanwhile, these constrictions can also be regarded as
QPCs [47]. Very recently, transport through single etched constriction fabricated by top-down
approach has been reported [50]. Yet there has not been a systematic study on such a constriction
in single semiconductor NW. This forms the initial motivation of this thesis.
Among the III-V semiconductor NWs, InAs is distinguished by its native electron accumulation
layer, relatively low effective mass, and correspondingly large electronic mean free path and
subband quantization. Combined with its large g-factor and strong spin-orbit coupling, InAs
NWs are extremely suitable for nano-electronic and nano-spintronic devices [51].
Tunneling barrier may be formed between the metallic contact electrode and the NW [52, 53, 54].
For back-gated InAs NWs, the formation of these barriers is attributed to the nonuniform
electrical potential produced by the back-gate and the grounded contacts [17, 54]. Therefore, if
part of the NW section between the two contacts is narrowed, depending on the relative height
between the etched barrier and the contact barriers, we may expect electron transport through
single QD, DQD or a QPC. This expectation is based on the assumption that there is no
23
additional potential barrier presented in the channel, which is hardly true for real devices due to
the existence of disorder. Hence the actual phenomena observed from the measurements can
provide useful information about disorder. We can then use this information to improve the
design of the device.
For back-gated devices, changing the back-gate voltage will affect the height of all the barriers at
the same time. To gain separate control for the etched barrier, side-gate electrode can be placed
in the vicinity of the constriction. Single etched constriction between a pair of side-gate
electrodes constitutes the standard device architecture studied in this thesis. For comparison,
devices either without etched constriction or without side-gates should also be fabricated.
The above motivations naturally set objectives of the thesis project: successfully fabricate the
three types of devices, perform transport measurements on these devices and understand the
underlying physics from the observed phenomena.
The thesis is organized into five chapters. Chapter 2 describes the pertinent nanowire device
fabrication and experimental methodology. Chapter 3 discusses measurement results of a
standard device and a device without side-gates. Various quantum transport phenomena observed
in the former device are discussed according different gate bias regime. For the latter device, we
only consider the physics in the pinch-off region. Other than quantum transport phenomena, we
also characterize the hysteresis effect of side-gating and the interaction between side-gates and
the back-gate. Chapter 4 focus on the measurement results of a device without etched
constriction. The necessity of performing some preliminary processing on the raw data is first
described. This is followed by presenting the observed phenomena under different measurement
conditions. In the remaining part of this chapter, we show the logic and results of a simulation
conducted to account for the observed phenomena in this device. The validity of this simulation
is also discussed. Finally, we summarize main conclusions of this thesis and propose some future
works of this project.
24
Chapter 2
Methods
2.1 Single InAs Nanowire Device Fabrication
Transfer Nanowires onto the Substrate
Device fabrication starts with cut pieces (approximately 12 mm 12 mm in size) of heavily-
doped p+ Silicon wafer (resistivity 0.002-0.005 Ω - cm) with a 100 nm thick SiO2 layer
grown by thermal oxidization. These substrates were first patterned with global metallic markers
to position the NWs. After that, they were dipped in N-Methyl-Pyrrolidinone organic stripper at
60 for 15 minutes to remove the residual resist from metallization of markers. This was
followed by a standard solvent cleaning step consisting of immersion in heated (120 ) acetone
and isopropanol (IPA) for 2 minutes and de-ionized (DI) water rinse. These procedures ensure a
clean substrate surface, which is crucial for facilitating good NW adhesion according to our
experience. InAs NWs studied in this thesis were grown by the metal-catalyzed vapour-liquid-
solid (VLS) method [55] in a modified commercial molecular beam epitaxy (MBE) system
(ATC-EP3). They were mechanically transferred to the receiving substrates by putting the
growth substrate upside down on the SiO2 surface of the receiving substrates and gently touching
the rear of the growth substrate with a tweezers. A successful NW transfer yields a desired
density of NWs on the receiving substrates with few broken pieces and undamaged SiO2 surface.
The receiving substrates were then heated at 120 for 15 minutes to get a good adhesion
between NWs and the SiO2 surface so that NWs would not move during the subsequent spin-
coating steps.
25
Locate Nanowires and Form Ohmic Contacts/Side-gates
To find proper NWs and locate them, samples were loaded into a commercial electron beam
lithography (EBL) system (RAITH Elphy Plus) and the coordinates of the selected NWs were
recorded with respect to the predefined markers. After taking samples out of the EBL system,
they were spin-coated by a Poly-Methyl-Methacrylate (PMMA)-based resist and reloaded into
the EBL chamber for exposure. Note that any spin-coating step is associated with a preheating
(at 120 for a few minutes) before the coating to dehydrate the surface of the substrate and a
soft-baking (at 170 for 90 seconds) after the coating to reduce the remaining solvent content in
the resist. The patterns to be transferred onto the samples include the source/drain electrodes on
top of the NWs, the side-gate electrodes by the side of the NWs, and local markers to align
patterns of different exposures. After the exposure, samples were developed in methyl-isobutyl-
ketone (MIBK) and IPA (1:3) for 40 seconds and were rinsed in IPA to terminate the
development. The residual resist on the exposed regions must be removed to lower the contact
resistance and improve the liftoff. This was done by loading samples into a homemade oxygen
plasma system with the plasma ignited for 8-10 seconds at 100mbar of oxygen and 70 Watts of
total power (the plasma was generated by a commercial McCarroll cavity (Opthos Instruments)
operating at 2.45 GHz.
Prior to metal evaporation, samples were dipped in a solution of 0.3% by weight ammonium
polusulfide in DI water for 8 minutes to get rid of the native oxide at the exposed regions of the
NWs and terminate their surface with Sulfur atoms. This step was found to be essential for
formation of low contact resistance to InAs NWs [56]. After the treatment, samples were quickly
rinsed in DI water, blown dry and immediately loaded into a custom-built evaporation system.
This system is equipped with thermal sources (MDC Vacuum model Re-vap 900) for Au
evaporation and electron-beam sources (Oxford Applied Instruments model EGN4) for Ti
evaporation. The pressure inside the chamber could be brought down to 3 10 mbar within 40
minutes before the metallization, which minimized the re-oxidize of the exposed NW surfaces.
Normally, a Ti (around 10 nm) / Au (around 100 nm) bilayer is evaporated with Ti providing
good adhesion to the SiO2 surface. Liftoff was performed by immersing samples in acetone
26
overnight followed by the standard solvent cleaning step. A schematic view of samples at this
fabrication stage is shown in Figure 2.1a.
Etch the Nanowires
After the liftoff, samples were loaded in a scanning electron microscope (SEM) system (Hitachi
S-4500) housed in the Department of Material Science and Engineering, University of Toronto to
pick up NWs that have good alignment with side-gate electrodes. Afterwards, samples were
spin-coated with a thinner PMMA resist for finer etching patterns and loaded into the EBL
system. Local metallic markers near centers of NWs patterned during the first exposure were
used to align the etching patterns with respect to side-gates. After the exposure, samples were
developed and treated with oxygen plasma ashing to obtain clean etching windows.
An etchant consisting of citric acid (C6H8O7) and hydrogen peroxide (H2O2) was chosen to etch
the NWs because it gives a high etching selectivity of InAs over GaAs (about 13:1 at room
temperature) at a volume ratio 1:5 [57] for potential usage in engineering our InAs-GaAs core-
shell NW system [58]. The etching mechanism is attributed to an oxidation-reduction reaction at
the III-V semiconductor surface by the hydrogen peroxide, with the dissolution of the oxide
material by the acid [59]. The PMMA resist serves naturally as the etching mask because
C6H8O7/ H2O2 mixture with volume ratios between 0.1 and 100 does not erode photoresist [60].
To optimize parameters for the etching of InAs NW, a bunch of testing samples were made.
These samples contained selected InAs NWs patterned with metal markers. Etching results under
different conditions were compared by taking SEM images of these testing samples. Optimized
etching procedures are given below. First, anhydrous citric acid crystals were dissolved in DI
water at the ratio of 1g C6H8O7: 1ml DI water at least one day prior to the etching to ensure
complete dissolution and room temperature stability. Approximately 15 minutes before
conducting the etching, the liquid citric acid/water mixture was mixed with fresh 30% hydrogen
peroxide and diluted with DI water. A volume ratio C6H8O7: H2O2: DI water of 1:5:25 was
identified to give the most proper etching rate (estimated to be 2 nm/second at 22 ). The 15
minutes delay was used to allow the etchant to return to room temperature, if any temperature
change occurs due to mixing. The etching rate turned out to be very sensitive to the temperature
27
and the concentration of the solution. To minimize the variation of the two factors, fresh etchant
was always made each time before conducting the etching in our clean room where a relatively
constant room temperature and humidity is maintained. The 30% hydrogen peroxide was
frequently replaced to avoid using the degraded solution. Taking these precautions, a robust
etching rate could be expected. Diameters of the NWs were measured from the SEM images so
the desired etching depth was known. Therefore, the corresponding etching time could be
calculated, and samples were dipped in the etchant for that amount of time. The etching was
ceased by rinsing samples in DI water. The resist was then removed by dipping samples in
acetone for a few minutes followed by the standard cleaning step. A schematic view of samples
after the resist was removed is shown in Figure 2.1b.
Wire-bond the Samples
After the etching step, samples were loaded into the SEM again and only NWs with desired
etching profiles were chosen for the subsequent processing. To connect the electrodes of selected
NWs with the measurement system via wire-bonding, bonding pads with traces connected to the
electrodes need to be made. A copolymer/PMMA bilayer resist, which provides a retrograde
resist profile, was used at this stage to enhance yield for liftoff of thicker metal deposition (Ti (10
nm) / Au (180 nm)). A schematic view of samples after the liftoff is shown in Figure 2.1c.
28
Figure 2.1: Main steps of device fabrication. (a) 1st exposure and metallization transferred patterns of the source
(S)/drain (D) contacts, side-gate (SG) electrodes and local markers onto the substrate with respect to the NW. (b) 2nd
exposure opened an etching window for the etchant, which was aligned to previous metal patterns via local markers.
Using resist as the etching mask, the NW section exposed to the etchant was etched to a desired depth. (c) 3rd
exposure and 2nd metallization transferred patterns of bonding pads and traces (yellow) connecting previous metal
patterns (orange) onto the substrate. Previous metal patterns are barely seen at this scale. (a) and (b) are actually
enlarge views of the dark blue square region.
To make the surface of NWs as clean as possible before the measurement (thus reduce the
number of surface states), samples were immersed in the stripper again followed by the standard
cleaning step. They were then cut again into a smaller piece (smaller than 6 mm 6 mm) to fit
into the ceramic 28-pin leadless-chip-carriers (LCCs). The anchor of samples onto LCCs was
achieved by melting a small indium piece in between the rear of samples and surface of LCCs’
cavity which serves as the conductive glue. A commercial wedge-bonder (Kulicke and Soffa
model 4526) was employed for the wire-bonding.
S D
S D
SG
SG
SG
SG
SG
SG
S D
SiO2
p++ Si
local marker
(b)(a)
(c) SG
bonding pad
trace
29
Once the electrodes on top of NWs are bonded to the pins of LCCs, the single NW devices
become subject to the threat of electro-static discharge (ESD) which according to our experience
can vaporize or melt the NWs. Thus, all necessary precautions have to be taken to avoid the
ESD damage to the devices. A custom LCC chip holder was assembled onto the stage of the
bonder providing a resistance of 50 kΩ to ground for each pin. Our measurement system also
contains a homemade electrical breakout box that can ground LCC pins when they are not being
connected to instrument terminals, which will be further introduced in the next section.
Therefore, the devices are safe when samples are either in the wire-bonder chip carrier or inside
the measurement system. Samples were temporarily kept in a LCC chip holder inserted in a
conductive mat after the wire-bonding and were ready to be loaded into the measurement system.
When they have to be carried by hand, one must properly ground him/herself to minimize the
ESD damage.
2.2 Experimental Setup for Transport Measurements
Electrical measurement was performed in a closed cycle He cryostat (Advanced Research
Systems model ARS DE 202) with a temperature range of 7-350 K. The temperature could be
adjusted and monitored by a heater and a sensor attached to the copper coldfinger of the cryostat,
under the control of a temperature controller (LakeShore model 330). The LCC was placed
inside a custom built copper hip holder screwed onto the coldfinger. A top copper plate was used
to press the pins at the back of LCC against the bottom spring loaded probes. These probes were
mounted inside a plastic (G10) fixture attached to the copper frame. This design ensures both
electrical contact and thermal anchoring for the LCC. The back ends of 24 probes were soldered
to 12 low frequency twisted pairs with bandwidth practically limited to approximately 50 kHz by
wiring capacitance. An image of the sample holder is shown in Figure 2.2a with the above
components marked in the image. The twisted pairs were connected to the measurement circuit
by a vacuum electrical feedthrough (24 pin Fisher). The circuit was placed inside a homemade
RF-shielded electrical breakout box (see Figure 2.2b) with toggle switches which provide choice
between translating the feedthrough to coaxial connectors demanded by electrical instruments
and grounding the electrodes of devices through 1 MΩ resistors. The latter protects the devices
30
against ESD damage when the electrodes are not connected to the terminals of electrical
instruments.
The DC voltage biases (i.e., the gate biases Vbg and Vsg and source/drain DC bias VDS) were
provided by the source-measurement unit (SMU) of a semiconductor characterization system
(Keithley model 4200), with the current being measured at the same time. A pair of side-gates
was always connected together. Since gate bias is normally in the range of several volts, a
protecting resistor (1 MΩ) was always placed between the SMU and the pin that provided the
bias in case of a serious gate leakage to protect the SMU. The source/drain AC bias
2 came from the AC output of a low-frequency (100 kHz) lock-in (Stanford Research
Instruments SR830). The amplitude of A was chosen such that the root mean square (RMS)
of | |√
~ to avoid electron heating by . VDS and Vds were inductively coupled to each
other using a magnetically shielded signal transformer (Triad Magnetics), attenuated by 1/100
via a resistor-divider network, and fed to the drain electrode of the NW. Current from the source
electrode Ids was first amplified by a low-noise current preamplifier (Ithaco Instruments model
DL1211) and then obtained using the lock-in. The differential conductance is therefore obtained
as ⁄ , which we will refer to as “conductance” for convenience throughout this thesis.
The circuit layout of the differential conductance measurement is shown in Figure 2.2c. The
input resistance of the current preamp depends on the chosen sensitivity and is either 20 Ω or 200
Ω in all the measurements done for the thesis. In either case, it is trivial compared to the NW
resistance (at least a few KΩ), so the chemical potential of the source electrode can be viewed as
pinned to the ground potential all the time.
The applied magnetic field was generated by an adjustable gap electromagnet (Alpha model
4600) controlled by a power supply (Alpha model 3002), which was in turn controlled by a
programmable power supply (Agilent model E3631A) to set the step and invert the direction of
the magnetic field. The magnetic field intensity could be varied from -0.6 T to 0.6 T. The metal
frame that carries the extender of the cryostat was modified so that the extender could rotate 90 °
within the gap between the two magnets, providing a range for the direction of the magnetic field
from being parallel to being perpendicular to the sample plane. Figure 2.2b shows an image of
the electromagnetic system. The intensity of the magnetic field could be verified by inserting a
probe of a gaussmeter (LakeShore model 450) to the gap region between the two magnets.
31
Figure 2.2: Experimental setup. (a) Custom built sample holder. A top cooper plate presses down the LCC towards
the spring loaded probes mounted inside the G10 fixture, providing both thermal anchor and electrical contacts for
the sample. (b) Cryostat and electromagnetic system. The sample holder is located in the extender of the cryostat
which can be inserted into the gap of the two magnets and rotated by 90 °. The magnetic field is controlled by a
programmed power supply (Agilent E3631A). (c) Circuit layout for differential conductance measurement. AC and
DC source/drain biases are coupled by a transformer, attenuated by a divider and then applied onto the drain contact
of the device. Current from the source contact is amplified by a current preamp and measured by a lock-in.
Back/side-gate biases are applied through protecting resistors to the rear of the sample and side-gate electrodes,
respectively.
top copper plate
G10 fixture
copper frame
LCC with sample inside
(a) (b)
cold finger
temperature sensors
twisted pairs
AgilentE3631A
electromagnets
vacuumfeedthrough
power supply(Alpha 3002)
electrical breakout box
metal frame
extender of the cryostat
cryostat
Vbg
Vsg
A/V Lock-in
VDS Vds
(c)
transformer
voltage divider current preamp
32
Ground loops occur when the grounds of apparatus and circuits are actually at different
potentials. They could couple stray AC signals (especially the 60 Hz noise and its harmonics)
from other equipments into the measurement circuit which degrade the signal-to noise ratio.
Thus, efforts were put to eliminate them by troubleshooting while monitoring the change of the
noise spectrum using a digital sampling oscilloscope (Agilent model Infiniium 54845a).
After the sample was loaded into the cryostat, it was always pumped overnight to a pressure less
than 10-5 mbar before any measurement was performed. This was proved to be necessary to
stabilize the transistor characteristics and obtain minimal hysteresis of the devices, which might
be a result of the detachment of species on the surface of NWs due to the pumping, thus reduced
the number of surface/interface states.
33
Chapter 3
Quantum Transport Phenomena in Single
InAs Nanowires with Etched Constrictions
3.1 Introduction
As mentioned in Section 1.3, if we selectively etch part of an ideal NW, we expect to see a
transition of transport from 1-D to 0-D on the same device: conductance quantization when the
channel is turned on by the gate bias, and Coulomb blockade due to electron tunneling through
either DQD or a single dot when the channel is turned off. In reality, disorder exists in NWs and
the etching might induce further surface roughness or surface states. This may lead to the
formation of multiple tunneling junctions (MTJ) in the pinch-off region and smear the
conductance plateaus when the 1-D transport takes place. Adding a pair of side-gate at the two
sides of the etched constriction allows locally tuning the potential in the constriction. Side-gating
may exhibit hysteresis [61]. Although this effect can be explored for memory applications [62], it
is detrimental for transport properties of NWFETs [63].
In this chapter we present typical transport measurement results in etched single InAs NWs. Two
types of device were studied: Section of NW with an etched constriction controlled by the back-
gate, and section of NW with an etched constriction controlled by both the back-gate and the
side-gates. We first discuss the hysteresis of side-gating in the following section since it does not
belong to the category of quantum transport phenomena. This is followed by discussion of
results on the first type of device shown in Section 3.3. Then we focus on different transport
phenomena observed in the second type of device in Section 3.4. This section also includes a
proposed electrostatic model to account for the observed interaction between the back-gate and
side-gates.
34
3.2 Side-gating Effect: Hysteresis
In this section we describe a universal side-gating effect observed in our side-gated devices.
Figure 3.1 shows the typical transfer characteristic of one such device in terms of side-gating.
For the G-Vsg curve at each temperature, side-gate voltage was swept toward more positive
values and then swept back toward more negative values, with the back-gate grounded. At room
temperature, large hysteresis was clearly observed. The conductance increased after the positive
sweep of Vsg and decreased after the negative sweep, as indicated by the green arrows. The
hysteresis was reduced at lower temperature (red curve), and eventually disappeared at 200 K
(blue curve). Figure 3.1b displays the transfer characteristic of the same device in terms of back
gating (with side-gate grounded) from which we could barely see the hysteresis. The
measurement was taken at room temperature and at lower temperatures hysteresis was even
harder to resolve. All the measurements shown in Figure 3.1 were performed at the same gate-
voltage sweep rate.
The transfer characteristics of top-gated InAs NWFETs have been studied by Dayeh et al. [63,
64] where the observed hysteresis was attributed to the capacitive effects of donor-like interface
trap states. They found that slower gate-voltage sweep lead to a charge neutral interface with
reduced capacitance and smaller hysteresis. It is this reason that caused the hysteresis in our
devices, we should also observe distinct hysteresis from the back-gate voltage sweeps because
donor-type interface states exist all over the surface of InAs NWs, as introduced in Section 1.2.4.
The absence of significant hysteresis in back-gate voltage sweeps therefore indicates that this
scenario alone is not enough to account for the different magnitude of hysteresis between side-
gating and back gating.
35
Figure 3.1: (a) Transfer characteristics of a side-gated InAs NWFET, showing distinct hysteresis at room
temperature (black curve) and reduced hysteresis at lower temperatures (red and blue curves). Green arrows indicate
the sweep directions of side-gate voltage. (b) Transfer characteristics of the same device gated by the back-gate at
room temperature showing little hysteresis. (c) Schematic of the proposed oxide trap charging mechanism for side-
gating. Here the NW is grounded through source and drain contacts and a positive bias is applied to the side-gate.
When the bias reaches a certain value, the electric field between the gate electrode and the NW may be high enough
to induce electron tunneling from the oxide traps to gate electrode. Corresponding energy diagram is also shown to
illustrate the tunneling situation.
The side-gating effects on Si NWs fabricated by top-down approach were studied by Matsukawa
et al. [65]. They observed the same sign hysteresis in the n-type NWs and attributed it to the
effect of positively charged oxide traps due to both impact ionization and injection of holes from
side-gates as the gate voltage was swept to large positive values. This viewpoint provides a clue
-6 -4 -2 0 2 4 6
0.02
0.04
0.06
0.08
0.10G
(2e2 /h
)
300K 250K 200K
Vsg(V)
-3 -2 -1 0 1 2
0.00
0.04
0.08
0.12
0.16
0.20
G(2
e2/h
)
Vbg(V)
Ti/Au
SiO2
NW
(a)
(b) (c)
E field
EC
36
to explain our data. As mentioned in Section 1.2.4, SiO2 has interface and bulk traps whose
charge state changes with gate voltage. Interface traps are populated continuously as the gate
voltage is tuned, regardless of gate type, thus they cannot be used to account for the different
hysteresis behaviors between the back-gate and side-gates. Oxide traps, on the other hand, are
charged only with carrier injection at gate fields above 3×105 V/cm [66] and may response
differently to back-gate and side-gate biases. Experimentally, if a sweep to large positive values
of gate voltage creates a negative shift in the threshold voltage, this means holes are injected into
oxide trap states (or electrons leave the trap states), enhancing the accumulation of electrons at
the surface of InAs NW. As can be seen from SEM images of devices with side-gates (Figure
3.3a and Figure 4.1a), the end edge of all side-gates are sharp tips. These sharp terminals of side-
gates were not intentionally made (all side-gate patterns were drawn as rectangles), but results of
the proximity effect during the exposure [67]. Similar to the “point discharge” principle, the
electric field near the sharp tips may be strong enough (such strong field may be absent in back
gating) to induce the tunneling of trapped electrons from the trap states to side-gate electrodes
when side-gate voltage is increased above a certain positive value. This scenario is depicted in
Figure 3.1c. The trap states will remain positively charged until the side-gate voltage is
decreased below a certain negative value which favors the reverse tunneling from gate electrodes
to oxide traps. This tunneling mechanism should be suppressed in lower temperature [66], which
is consistent with our observation that hysteresis at side-gating decreased as temperature was
lowered.
3.3 Coulomb Blockade in an Etched InAs Nanowire without
Side-gating
We begin the study of etched InAs NWs by fist investigating the simplest case: an etched InAs
NW section tuned by a global back-gate. Inset I of Figure 3.2a is the SEM image of the device.
The diameter of the NW and the etched constriction are 50 ± 2 nm and 25 ± 2 nm, respectively.
The etched constriction has a length of 110 ± 2 nm and the distance between the two contacts is
610 ± 2 nm. The measurement was performed at T= 10 K. The AC source and drain bias was set
to a RMS of 1 mV with a frequency of 1450 Hz.
37
The transfer characteristics of the device are shown in inset II of Figure 3.2a. The channel is
turned on at Vbg > 0.95 V. The remarkable conductance dip at Vbg > 1.5 V is most likely due to
the universal conductance fluctuations (UCF) with a magnitude of e2/h, originating from
electrons being multiply scattered by randomly distributed disorder in the channel [23]. UCF has
been observed in InAs NWs and appear to be random in Vg [54] with no regular pattern in the
Vg-VDS plane [68].
Figure 3.2a is the enlarged view of the pinch off region marked by the red rectangle in the inset
II, from which three linear conductance peaks around Vbg = 0.71 V, 0.8 V and 0.93 V can be
identified. The third peak is the mark of the end of pinch off region and onset of the channel.
Most part of the second peak is superimposed with high conductance state of RTS so the
conductance value is higher than its normal value. The stability diagram of the same back-gate
voltage range in Figure 3.2a is shown in Figure 3.2b. Two large irregular Coulomb diamonds can
be identified, whose boundaries are superimposed with small “kinks”. The two diamonds
correspond to the two Coulomb blockade regions separated by three conductance peaks in Figure
3.2a. Such behavior is characteristic for an unequal double quantum dot structure controlled by a
common gate, which has been realized based on some 1-D systems [69, 70, 71]. The large
diamonds reflect the charge state of the smaller dot while the “kinks” are due to charging of the
larger dot. Coulomb blockade is lifted whenever an energy level of the smaller dot is aligned
with an energy level of the larger dot, or they fall into the bias window, so that an electron can
tunnel sequentially through the two dots.
38
Figure 3.2: (a) Linear conductance in the pinch-off region of the transfer characteristics of the device. Three peaks
are visible. The second peak is superimposed with RTS. The third peak denotes the onset of the channel. Inset (I):
SEM image of the device with the source and drain contacts labeled. Inset (II): Transfer characteristics of the device.
The pinch-off region is highlighted with red rectangle. (b) Stability diagram corresponding to the same back-gate
voltage range in (a). Large diamonds reflect the charge state of the smaller dot while the fast oscillations
superimposed on the boundaries of large diamonds are due to the charging of the larger dot.
We can adopt the model of DQD introduced in Section 1.2.1 to do some preliminary analysis.
Applying a voltage to the back-gate tunes both dots simultaneously. In a qualitative picture, the
smaller dot is expected to contain fewer electrons than the larger dot and the capacitive coupling
of the gate to dot 1 is expected to be smaller than that of dot 2 (recall Figure 1.4). Tuning the
back-gate voltage will therefore fill dot 1 more slowly than dot 2. Following this logic, it is
straightforward to understand that “kinks” superimposed on the boundaries of large diamonds are
the result of electrons leaving/entering the larger dot and consequently lowering/raising the
chemical potential of the smaller dot due to interdot coupling.
(a)
(b)
(I) (II)
0.000
0.003
0.006
0.009
0.012
0.015G
(2e2 /h
)
0.650 0.675 0.700 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925-30
-20
-10
0
10
20
30
Vbg(V)
V DS(m
V)
-0.0060
0.0011
0.0048
0.025
0.130.23
0.8 1.0 1.2 1.4 1.6 1.80.0
0.1
0.2
0.3
0.4
0.5
0.6
G(2
e2 /h)
Vbg(V)
G(2e2/h)
S
D
39
We focus on one edge of the large diamond to see how we can extract information from the
“kinks”. Depending on how the double dots are connected to the contacts, there are two possible
scenarios. (A): The smaller dot is directly coupled to the source. In this case, edges represented
by the blue line denote the alignment of the energy level of the smaller dot µ to the chemical
potential of the source µS and edges represented by the orange line denote the alignment of the
energy level of the larger dot µ to the chemical potential of the drain . (B): The smaller dot is
directly coupled to the drain. In this case edges represented by the blue line denote the alignment
of µ to µS and edges represented by the orange line denote the alignment of to the . Take
the alignment of µ to µS as an example. According to Eq. 1.9, this condition means the following
relation has to be satisfied: ∆ ∆| |
∆| | .
Similarly, we can build up such relations for other alignment conditions. This leads to the
following expressions for the slopes of the blue and orange border lines in two scenarios:
Scenario A:
Blue line ( = ): ∆ ∆⁄ ⁄
Orange line ( = ): ∆ ∆⁄ ⁄
Scenario B:
Blue line ( = ): ∆ ∆⁄ ⁄
Orange line ( = ): ∆ ∆⁄ ⁄
Since the origin of the DQD is not clear, it is hard to determine which scenario it would be for
the configuration of the DQD system. The source and drain contacts used during the experiment
are labeled in the inset (I) of Figure 3.2a. Intuitively, if one believes it is the contact barriers plus
the etched barrier that defines the DQD, scenario B is probably the case because the length of the
unetched section close to the source (270 nm) is a bit longer than that of the unetched section
close to the drain (240 nm). However, more reliable speculation on the origin of the DQD should
be based on the estimated dot length, which in turn requires the knowledge of gate-to-dot
capacitances Cbg1 and Cbg2.
40
The shift of right-tilted borderlines, e.g., the blue arrow, is indicative of the interdot coupling
strength . The separation of the left-tilted borderlines, e.g., the orange arrow, is indicative of
the addition energies of the larger dot ∆ where ∆ is the level spacing of the
larger dot. The separation of Coulomb peaks in linear transport regime measures the addition
energies of the smaller dot ∆ . Nonetheless, as can be seen from Figure 3.2b,
severe RTS shift differential conductance patterns at certain back-gate voltage ranges, which
prevents accurate extraction of capacitances from above relations.
3.4 Transport Phenomena in an InAs Nanowire with Single
Etched Constriction and Side-gating
In the previous section we presented the measurement result of an etched InAs NW controlled by
a global back-gate. As mentioned in Section 1.3, one drawback of back-gated NW devices is that
tuning the back-gate voltage not only changes the energy in the channel but also modifies the
coupling between the channel and contacts. To gain separate control over the channel, we added
a pair of side-gates to the two sides of each etched constriction. In this section we focus on
transport properties for such a device. Figure 3.3a is the SEM image of this device. The diameter
of the NW and etched constrictions are 56 ± 2 nm and 36 ± 2 nm, respectively. Two etched NW
sections with lengths 780 nm and 740 nm, are separated by a common source electrode. The
purpose of having two etched sections on the same NW is to compare transport properties at
different length of etched constrictions. The length of the top left constriction is 170 ± 2 nm, to
which we will refer as “short-etched constriction”. The length of the bottom right constrain is
260 ± 2 nm and we will refer to it as “long-etched constriction”. All the measurements shown in
this section were performed at T= 10 K. The AC source and drain bias was set to a RMS of 1 mV
with a frequency of 210 Hz.
41
Figure 3.3: (a) SEM image of the device studied in this section. Two etched constrictions were fabricated on the
same NW to examine the effect of etching length on transport properties. (b) Linear conductance as a function of
side-gate and back-gate biases for the short-etched constriction. The slope of stripes in region I and III is different
from the one in region II. Detailed bias spectroscopy was performed along marked arrows except for the light green
one.
3.4.1 Interaction between Side-gate and Back-gate
Figure 3.3b shows the linear conductance as a function of side-gate and back-gate biases for the
short-etched constriction. A series of dark stripes running from top left to bottom right with
conductance less than 0.15 conductance quantum can be identified but the slopes of these stripes
vary from place to place. In general, slopes in region I and III are similar and they are steeper
than slopes in region II. These stripes are linear conductance peaks and there slopes represent the
relative coupling strength between the side-gates to the channel and the back-gate to the channel.
The variation of the slopes therefore indicates the change of relative coupling strength at
different gate biases.
To understand the origin of this phenomenon, we notice that the leakage current of both side-gate
and back-gate are significant in this device and they keep changing as gate bias varies. The
measured gate leakage current is summarized in Table 3.1 with the first/second number in each
cell represent Ibg and Isg, respectively, in unit of nA. From this table we can conclude that Ibg is
large as Vbg increases, regardless of the value of Vsg. The absolute value of Isg, on the other hand,
(a) (b)
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.01.0
1.5
2.0
2.5
3.0
3.5
Vsg(V)V
bg(V
)
-1.00E-03
0.0930
0.187
0.281
0.375
G(2e2/h)
Ι
ΙΙ
ΙΙΙ
42
becomes large only when the voltage difference between Vsg and Vbg is large. This is a strong
indication that the back-gate has a leakage to the source or the drain, while side-gate does not but
has a leakage to the back-gate.
Vbg\Vsg (V) 0 1 2 3
1 270/-70 220/0 205/25 18/310
2 880/-470 600/-2 600/1 545/90
3 1600/-1000 1100/-180 1000/0 1000/12 Table 3.1: Measured gate leakage current at different gate biases. 1st and 2nd number in each cell represent Ibg and
Isg, respectively, in unit of nA.
Based on the analysis of gate leakage current, we propose a simple model to account for the
observed gate coupling variation. During the wire bonding, the oxide underneath the bonding
pads may be destroyed by the wedge of the wire bonder, creating leakage paths to the back-gate.
These leakage paths can be characterized by variable resistors, as depicted in Figure 3.4a. In the
case of linear transport measurement, the NW is grounded through source and drain contacts, so
a leakage from source and/or drain to the back-gate would form a gate leakage current loop.
Similarly, a leakage from the side-gate electrode to the back-gate allows current to flow
whenever there is a voltage difference between the two gates. The coupling between the two
gates is weak when the voltage difference between the two gates is small, and becomes stronger
when the voltage difference is larger. Therefore, we see in Figure 3.3b that in region II where the
voltage difference between the two gates is small, the two gates are relatively independent from
each other, rendering constant slope of the stripes. When the voltage difference of the two gates
is large (region I and III), the mutual coupling between the two gates becomes stronger, leading
to the steeper bend of stripes, which means the coupling between the back-gate and the channel
becomes relatively weaker compared to the coupling between the side-gates and the channel.
43
Figure 3.4: (a) Schematic of the proposed model to explain observed change of relative coupling between back/side-
gate and the channel. Leakage paths from source and/or drain contacts and side-gate electrodes to the back-gate
were probably created during the wire bonding which can be characterized by variable resistors. (b) Measured gate
leakage current at different gate voltages with side-gate connected to back-gate.
If we connect the side-gate and the back-gate together, there will be no voltage difference
between the two gates and thus no current flow in between. The gate leakage current in case
should reflect the leakage from the back-gate to the contacts. This result is plotted in Figure 3.4b,
from which we can conclude that the back-gate coupling to the channel keeps decreasing and
become constant at Vg > 1.5 V. The decrease of back-gate coupling to the channel as back-gate
voltage increases is responsible for the steeper slope in region I than the one in region III.
3.4.2 Transport Phenomena in the Short-etched Section — Low
Back-gate Bias
At low back-gate bias, the contacts are expected to be more opaque, and the Fermi level in the
channel may be below some potential fluctuations, leading to tunneling through MTJ. This
scenario was confirmed in this device by performing bias spectroscopy near the pinch off regime
of back gating. Figure 3.5 shows such a measurement along the orange arrow in Figure 3.3b,
where the back-gate voltage was kept at Vg = 1 V and side-gate bias was swept. At Vsg < 2.75 V,
S/D
SiO2
Vds
Vsg
Vbg
Ids
Ibg
Isg
0.0 0.5 1.0 1.5 2.0 2.5 3.00
200
400
600
800
1000
I g(n
A)
Vg(V)
side gate
(a) (b)
44
the linear transport is completely pinched off (see the linear response in Figure 3.5a), but from
the bias spectroscopy in Figure 3.5b, several irregular diamond-shaped regimes of different
height can be seen. The diamonds do not close, and the slopes are not constant, which is a strong
sign of charge transport through multiple QDs defined by a number of defects along the 1-D
channel [11, 71]. At 3.06 V< Vsg < 3.175 V and Vsg > 3.175 V, the first and second conductance
plateaus show up with average conductance values of 0.06 and 0.12 conductance quantum,
respectively. There are several quasi-periodical oscillations superimposed on the conductance
plateaus. This feature will be discussed in the next section. However, the conductance trace is not
smooth. Rather, it is corroded by random conductance switching, which is a strong indication of
the presence of RTS.
Figure 3.5: (a) Linear conductance response along the orange arrow in Figure 3.3b. The pattern looks very “noisy”,
with random switching superimposed onto the conductance trace. (b) Corresponding bias spectroscopy, showing
irregular diamond patterns that are not closed in the pinch-off region.
Changing the gate voltage shifts the Fermi level relative to the barriers in the structure. As the
Fermi level is raised above some of the barriers in the MTJ, the dots merge to form larger dots
with increased capacitances. At certain gate bias ranges, we find sign of formation of single QD.
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
G(2
e2 /h)
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4-30
-20
-10
0
10
20
30
Vsg(V)
V DS
(mV)
-1.00E-03
0.0402
0.101
0.190
0.267
G(2e2/h)
(b)
(a)
45
Figure 3.6b is the bias spectroscopy along the dark green arrow in Figure 3.3b, where the side-
gate was connected to the back-gate. In the gate voltage range of 1.15 V < Vg < 1.3 V, three
Coulomb diamonds (labeled with numbers) with well defined boundaries are clearly seen.
Applying the CI model introduced in Section 1.2.1, we obtain the key parameters of the QD as
gate bias varies, which are summarized in Table 3.2 as follows:
Diamond EC (meV) C (aF) Cg (aF) α=Cg/C CS (aF) CD (aF)
1 11 14.6 3.7 0.25 10.4 0.5
2 10 16 3.7 0.23 11.4 0.9
3 7.5 21.3 4 0.19 16 1.3 Table 3.2: Key parameters of the QD extracted from the labeled Coulomb diamonds in Figure 3.6b.
From Table 3.2 we see that the total capacitance increases as gate voltage increases, a
phenomenon in electronic QD system that has been reported as a result of increased QD size at
higher gate bias [22, 72]. It is also obvious from Table 3.2 that the coupling between the QD and
source is much stronger than the coupling between the QD and the drain, which explains the
asymmetry of slopes for left-tilted and right tilted diamond edges in Figure 3.6b. Although due to
the gate leakage, we may not directly use the extracted gate capacitance to estimate the length of
the QD, the change of C and Cg of QD is a strong indication that the single QD is formed
between the contact barriers.
46
Figure 3.6: (a) Linear conductance response along the yellow arrow in Figure 3.3b. (b) Corresponding bias
spectroscopy. Three Coulomb diamonds labeled with numbers can be clearly identified with well defined boundaries.
In the classical regime, the line shape of an individual Coulomb peak can be described by Eq.
(1.5). From the best fit (using least square method for the nonlinear curve fitting) to the three
peaks marked with arrows in Figure 3.6a, we obtain the estimated lever arms for each peak,
assuming the electron temperature is around 15 K. These lever arms are summarized in Table 3.3.
These values represent lever arms at the three intersections of Coulomb diamonds 1 and 2 in
Figure 3.6b, and they are very close to the lever arms of Coulomb diamonds 1 and 2 estimated in
Table 3.2 using the CI model. This confirms that our approaches to estimate parameters of QD
are reliable.
α1 α2 α3
0.24 0.22 0.2 Table 3.3: Extracted lever arms for the three Coulomb peaks marked with arrows in Figure 3.6a, using Eq. (1.5) and
assuming the electron temperature to be around 15 K.
0.000
0.008
0.016
0.024
0.032
0.040
G(2
e2 /h)
G(2e2/h)
1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70-30
-20
-10
0
10
20
30(b)
Vg(V)
VD
S(m
V)
-1.0E-030.0120.0390.0690.0980.130.160.21
1 2 3
(a)
47
Figure 3.7: Enlarged view of the three Coulomb peaks marked with arrows in Figure 3.6a (gray curves) and the best
fit to theses peaks (black curves).
Around the labeled Coulomb diamonds in Figure 3.6b, we do not observe conductance stripes
running in parallel with edges of diamonds, which means excited states of QD is blurred by the
thermal energy , i.e., ΔE < . This situation is further confirmed by the quasi-periodicity
of Coulomb oscillations for the marked Coulomb peaks and diamonds in Figure 3.6. Eq. (1.4)
can be simplified to ∆ ⁄ under the condition that ΔE EC. From Figure 3.6b we can see
that for the labeled diamonds EC is around 10 meV, so the above condition is satisfied. Using a
general expression for the quantum confinement energy [73]: ∆ ~ ⁄ , and assuming the
electron temperature to be 15 K (which gives a satisfactory consistency of lever arms estimated
by Eq. (1.5) compared with values obtained by CI model, as described above), we have
⁄ < 1.3 meV, which gives L > 320 nm. Since the smallest energy quantization of a QD
is determined by its longest dimension, the above result means the length of the QD is at least
320 nm, which is most likely formed between the two contact barriers.
0
0.002
0.004
0.006
0.008
0.01
1.15 1.17 1.19 1.21 1.23 1.25 1.27
G (2
e2/h)
Vg (V)
Original peaks
Fitted peaks
48
3.4.3 Transport Phenomena in the Short-etched Section — High
Back-gate Bias
At high back-gate bias, the contacts become more transparent and the Fermi energy overcomes
most of the potential barriers in the channel, so the carrier transport is more likely to take place
in a clean 1-D system. This intuition is supported by the linear conductance response taken at
=2.7 V, which is shown in Figure 3.8. Quasi-periodic oscillations can be seen superimposed
on the first conductance plateau and the pinch-off regime. Such superimposition of oscillations
on the conductance plateaus has been attributed to F-P electron interference [15, 16] as
introduced in Section 1.2.3, and suggests that the transport in our NW is likely to be ballistic. If
not, the carrier’s path length would have been randomized by scattering leading to the
randomization of the phase and smearing of F-P oscillations [17]. Compared with the “noisy”
pattern in low back-gate bias region (Figure 3.5a), random conductance switching is absent here.
Similar switching events observed in InAs NWs have been modeled by the scattering of
electrons from a gate-voltage-dependent potential barrier produced when a defect captures an
electron [44]. As the back-gate bias is increased, the Fermi level in the channel may be well
above the trap level and therefore may overcome the scattering potential generated by the
electron trapping events. This viewpoint explains the suppressed random conductance switching
in the high back-gate bias regime. One interesting feature is the overshooting at the onset of each
plateau, which manifests itself as two thick stripes in Figure 3.3b. This phenomenon has been
attributed to the tunneling via discrete impurities [74], back scattering from defects [75] and
enhanced many-body interactions [76]. Another striking feature is the occurrence of F-P
oscillations in the pinch-off region, which, to our knowledge, has never been reported before.
This feature differs significantly from those in the low back-gate bias case where Coulomb
blockade due to electrons tunnel through either MTJ or a single dot is observed. Electron
interference requires that electron waves are phase coherent. In the pinch-off region electrons in
the contacts face a potential barrier in the channel. If the observed conductance is due to the
thermionic emission of electrons over the barrier, the phase information of electron waves cannot
be maintained. Electron transport by tunneling through the barrier is phase coherent, but a more
quantitative investigation needs to be done to better understand this mechanism in our device.
49
Figure 3.8: Linear conductance response of the device at Vbg =2.7 V, corresponding to the light green arrow in
Figure 3.3b. Inset: Linear conductance response of the device at Vbg =3 V, corresponding to the purple arrow in
Figure 3.3b.
To further demonstrate the existence of electron interference, bias spectroscopy was performed
in the pinch-off and overshooting region at Vbg = 3 V (the linear conductance response at Vbg = 3
V is shown in the inset of Figure 3.8) and the first conductance plateau at Vbg = 2.7 V (indicated
by the rectangle in Figure 3.8). The result is shown in Figure 3.9d-f, with corresponding linear
conductance shown in Figure 3.9a-c. Clear chess-board pattern in the grayscale nonlinear
conductance plot, which is a signature of F-P interference as introduced in Section 1.2.3, can be
seen in Figure 3.9d-e. The interference pattern diminishes as |VDS| is increased, suggesting the
occurrence of heating or dephasing when the electron energy distribution deviates from
equilibrium [13]. For the nonlinear transport on the first conductance plateau (Figure 3.9f), the
conductance peaks around zero source and drain bias due to constructive interference are barely
seen. This may indicate a strong role of the above mentioned mechanism.
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.20.00
0.05
0.10
0.15
0.20
0.25
G(2
e2 /h)
Vsg(V)
-0.2 0.0 0.2 0.4 0.60.00
0.02
0.04
0.06
0.08
0.10
0.12
G(2
e2/h
)Vsg(V)
50
Figure 3.9: Linear conductance in the pinch-off region (a) and the following overshooting region (b) at Vbg = 3 V
(along the purple arrow in Figure 3.3b). (c) Linear conductance on the first plateau at Vbg = 2.7 V (along the red
arrow in Figure 3.3b). (d) - (f) Bias spectroscopy corresponding to the linear conductance in (a) - (c). The grayscale
bars are in the unit of 2e2/h.
In Figure 3.9d, a decrease of the critical value VC mentioned in Section 1.2.3 with increased side-
gate voltage can be clearly identified. The condition which determines VC described in Section
1.2.3 implies that the length of the cavity should be inversely proportional to VC. Therefore, the
decrease of VC reflects the increase of the cavity length as side-gate bias is increased. In principle,
we can also use Eq. (1.12) to estimate the cavity length. However, in this device side-gates are
coupled to the back-gate and this coupling changes with the voltage differences between the two
gates. The resulting gate capacitance per unit length required for Eq. (1.12) may not be constant.
A more reliable way to estimate the cavity length is to use the condition that determines VC. In
the numerical integral of Eq. (1.13), can be obtained by performing a 3-D electrostatic
simulation using the same device geometry. Another remarkable feature of Figure 3.9d-e is the
different slopes of right and left sloping differential conductance lines, which may arise from
different electron reflection probabilities at the two interfaces [13].
0.000
0.003
0.006
0.009
0.012
0.00
0.03
0.06
0.09
0.12
0.04
0.05
0.06
0.07(a)
(b)
(c)
Vsg(V)
-0.3 -0.2 -0.1 0.0 0.1 0.2-30
-20
-10
0
10
20
30
(d)2.0E-04
0.0010
0.0055
0.029
0.15
0.30 0.36 0.42 0.48 0.54 0.60
(e)0.0040
0.063
0.12
0.18
0.22
0.80 0.88 0.96 1.04 1.12 1.20
(f)0.040
0.065
0.11
0.17
0.28VD
S(m
V)G
(2e2 /h
)
51
3.4.4 Transport Phenomena in the Long-etched Section
A series of measurement was also performed for the long-etched section, in a similar way as
what has been done for the short-etched section. The main difference here is that Coulomb
blockade dominates the physics in the pinch-off region even at high back-gate biases, unlike the
case for the short-etched section where F-P oscillations extend all the way to the complete pinch-
off at high back-gate biases. Figure 3.10 is a representative measurement result taken at Vbg = 2
V. The result is separated into two parts to magnify the feature near the complete pinch-off
region (Figure 3.10a and c). Similar to Figure 3.9, here Figure 3.10a and b are the linear
conductance response and Figure 3.10c and d are the corresponding bias spectroscopy. Familiar
F-P oscillations and interference pattern can be identified in Figure 3.10b and d, but in Figure
3.10a and c we see Coulomb peaks and irregular diamonds, which suggests electron tunneling
through MTJ. Since the only difference between the two sections is the length of the etched
constrictions, the comparison indicates that transport through longer constriction may experience
stronger potential fluctuation, in consistent with the result of dry-etched constrictions [48].
Figure 3.10: A representative measurement result taken at Vbg = 2V for the long-etched section. (a) Linear
conductance in the pinch-off region. (b) Linear conductance in the following sub-threshold region. (c) and (d) Bias
spectroscopy corresponding to linear conductance in (a) and (b). Scale bars are in the unit of 2e2/h.
0.0000
0.0005
0.0010
0.0015
0.0020
0.0025
(d)(c)
G(2
e2 /h)
(a) (b)
-0.60 -0.55 -0.50 -0.45 -0.40 -0.35-30
-20
-10
0
10
20
30
(a)
Vsg(V)
VD
S(m
V)
-8.0E-04
0.0017
0.0057
0.00970.026
-0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00
0.0
0.023
0.045
0.068
0.090
0.000
0.005
0.010
0.015
0.020
0.025
52
3.5 Conclusions
Transport measurement was performed on InAs NWs with etched constrictions. Some etched
NW devices have pairs of side-gate in the vicinity of etched constrictions. A universal side-
gating effect observed in all side-gated devices was first presented and the observed hysteresis
was attributed to carrier injection at high gate fields due to the sharp tip of side-gates. For the
measured device without side-gates, we did not observe conductance quantization. When the
channel was turned on, the conductance trace fluctuated with a magnitude of e2/h as a function of
back-gate voltage, a possible indication of UCF in a weakly disordered 1-D channel. When the
channel was turned off, i.e., in the pinch-off region, Coulomb blockade arise from electron
tunneling through DQD was observed. For the measured device with side-gates, non-constant
coupling from side-gates and back-gate to the channel was discovered from the linear
conductance map as a function of side-gate and back-gate bias. A simple electrostatic model was
proposed to account for this phenomenon. Conductance plateaus were observed in this device. F-
P oscillations were found in the sub-threshold regime and on the first conductance plateau. At
low back-gate bias regime, close to the pinch-off region, signs of electron tunneling through
either multiple QD or single QD were observed at different biases. RTS was found being
superimposed onto the conductance trace for the whole side-gate voltage range. At high back-
gate bias regime, RTS disappeared as a result of Fermi level overcoming the trap level. Near the
pinch-off region, transport in the long-etched section still exhibited the sign of tunneling through
MTJ, whereas in the short-etched section, F-P oscillations extended all the way to complete
pinch-off. The latter phenomenon has never been reported before in the literature and requires
further investigation.
53
Chapter 4
Conductance Quantization in a Thick InAs
Nanowire with Side-gating
4.1 Introduction
In Section 1.2.2, we discussed the conductance quantization in a 1-D conductor as a result of the
formation of 1-D subbands. At low temperature where subband spacing significantly excesses
the thermal energy , as long as the transport is ballistic or quasi-ballistic, the conductance
quantization should be resolved. As a 1-D/quasi-1-D system, NW provides a natural platform to
explore the 1-D transport phenomenon. Nonetheless, very few related result have been reported
in NW system [9, 10], presumably due to the blur of conductance quantization by
impurity/surface scattering. From this perspective, our MBE-grown InAs NWs possess the
advantage of producing relatively cleaner channels compared with those grown by other growth
techniques due to the unique principle MBE technology [77].
In designing the experiment to study conductance quantization in single NW devices, the
consideration involves a trade-off between the two prerequisites for observing this phenomenon.
Apparently, thinner NWs have larger subband spacing owing to stronger lateral confinement, so
it is easier to satisfy the requirement of ∆ . Meanwhile, thinner NWs also suffer stronger
surface scattering which dramatically reduce the transmission probabilities of conductance
plateaus [78, 79].
In this chapter we focus on an InAs NW section without etching. A thick NW was picked mainly
for the sake of obtaining a deep etching profile on one section of the NW. Figure 4.1a is the SEM
image of the fabricated device. The diameter of the NW is 95 2 nm. The distance between the
54
source and drain contact is about 800 nm. The distances between side-gates and the NW are 60
nm and 140 nm, respectively. Figure 4.1b is the gray scale profile along the yellow dashed line in
Figure 4.1a from which we obtain more accurate measure of dimensions.
Figure 4.1: (a) SEM image of the device. This chapter focuses on the measurements on the section without etching.
(b) Gray scale profile along the yellow dashed line providing a more accurate measure for the geometry dimensions
(c) Linear conductance as a function of side-gate and back-gate biases. Stripes with almost constant slopes indicate
independent coupling to the channel from the two gates. Experiment results along the two arrows are presented in
this chapter.
Other than the measurement discussed in Section 4.3.3, all other measurements were performed
at T= 10 K. The AC source and drain bias was set to a RMS of 0.3 mV with a frequency of 210
Hz. The linear conductance as a function of side-gate and back-gate biases (see Figure 4.1c) was
first measured to get guidance for the subsequent experiments. A series of stripes with almost
constant slope can be identified from this plot, which differs significantly from the case
described in Section 3.4.1. Gate leakage currents Isg and Ibg were very small within the bias
ranges, which means the coupling between side-gate and back-gate can be neglected. This
confirms the model proposed in Section 3.4.1, where relative changes of gate-channel coupling
strength in that device are caused by changes of the coupling between the two gates. From the
slope of the stripes we obtain the ratio of gate capacitance ⁄ 5.5. This result is in
0 100 200 300 400 500 600 700 8000
40
80
120
160
200
Gra
y sc
ale
D istance (nm )
95 60140
-8 -6 -4 -2 0 2 4 6 8-8
-6
-4
-2
0
2
4
6
8
Vsg(V)
Vbg
(V)
0.00
0.984
1.90
2.82
3.70
4.50
G(2e2/h)
(a) (c)
(b)
55
agreement with our expectation since side-gates only have a local effect on the channel. Besides,
as mentioned in Section 3.2, owing to the proximity effect during the exposure, the end of side-
gate forms a sharp tip, which would further reduce the side-gate coupling to the channel.
Therefore, as long as the back-gate bias is small, the back-gate always has a much stronger
coupling to the channel than the side-gate does.
Most results presented in this chapter are based on measurements along the yellow arrow in
Figure 4.1c, where side-gates and back-gate were connected together. The only exception is the
magnetotransport measurement described in Section 4.3.2, where the back-gate was grounded
and the side-gate bias was scanned, i.e., along the cyan arrow in Figure 4.1c. To explain the main
experimental observations, a 3-D electrostatic and 2-D eigenvalue coupled simulation was
performed and the results are presented in Section 4.4 and 4.5.
4.2 Data Processing
This section describes the necessity of performing some processing to the raw data. Figure 4.3a
shows the traces of differential conductance G versus DC source and drain bias VDS (only the
positive scan of VDS, i.e., from -30 mV to 30 mV is plotted) for different gate voltages Vg. The
gate voltage was increased from -8 V to 8 V stepped by 0.05 V between successive VDS sweeps.
One noticeable feature of this plot is the dip of the traces around zero DC bias. To investigate the
origin of this dip, we connected two successive pins of a LCC with a 10 KΩ surface mount
resistor and loaded this test chip into the measurement system. The only difference between the
test measurement and the sample measurement is the replacement of the sample with the test
resistor, all other features were kept the same. The same G-VDS measurement was performed and
the result is shown in Figure 4.2c (red curve, both positive and negative scan of VDS is plotted).
The same dip appears, indicating that it is a feature of the measurement system rather than a
feature of the sample itself. So effort needs to be made to correct this system error, so that real
sample character can be resolved.
The sample resistance in this plot ranges from a few KΩ to a few MΩ. To check how the dip
feature evolves with the change of resistance, we replaced the 10 KΩ resistor with a 1 MΩ one
56
and the G-VDS relation is shown as the black curve in Figure 4.2c. G is magnified 100 times for
comparison with the 10 KΩ case. The dip is still visible for the 1 MΩ resistor. To compare the
peak-to valley ratio for the two cases, G is first averaged from the positive and negative scan via
/2 where and represent the G value at a given
VDS from positive and negative scan, respectively. After this symmetric treatment, the peak can
be defined as the average outside the dip region and the valley is defined as the average inside
the dip. The calculated peak-to valley ratio for both cases is 1.03, meaning the dip is independent
of resistance. Thus, we can correct the dip for the whole range of the measured conductance. By
multiplying each conductance in the valley with the peak-to-valley ratio, the dip is compensated
to an average conductance level outside the dip, as shown in Figure 4.2d.
57
Figure 4.2: Raw data of the finite bias spectroscopy and associated data processing. (a) Raw data of G-VDS traces
(only the positive scan of VDS, i.e., from -30 mV to 30 mV is plotted) for different Vg. Vg was increased from -8 V to
8 V stepped by 0.05 V between successive VDS sweeps. (b) G-VDS traces after the subtraction of “self-gating” effect
and compensation for the dip near zero source and drain bias based on the raw data in (a). (c) G-VDS traces of testing
resistors, demonstrating the irrelevance between the dip feature and the sample conductance. (d) Correction for the
dip feature. By multiplying the conductance in the dip region with the calculated average peak-to valley ratio, the
dip is compensated to an average conductance level outside the dip.
Another feature of Figure 4.2a is the asymmetry of the traces with respect to VDS. Kristensen et al.
have attributed this asymmetry to the effect of VDS influencing the confinement potential and
termed as “self-gating” [80], i.e., the confinement potential is not only defined by the sample
parameters, the geometry and the gate bias, but also, to some extent, by the DC source and drain
(b)(a)
-30 -20 -10 0 10 20 300.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-30 -20 -10 0 10 20 30
G(2
e2 /h)
VDS(mV)
-30-25-20-15-10 -5 0 5 10 15 20 25 30
0.95
1.00
1.05
1.10
1.15
G(2
e2 /h)
VDS(mV)
10K 1M
-30-25-20-15-10 -5 0 5 10 15 20 25 30VDS(mV)
before correction after correction
G(2e
2/h)
1.11
1.12
1.13
1.14
1.15
1.16
1.17
(c) (d)
58
bias. Following the same correction method reported in literatures [80, 81], this trivial
electrostatic effect is subtracted from the data by using | | /2,
making the G-VDS traces perfectly symmetric with respect to VDS. Figure 4.2b shows the G-VDS
traces after the subtraction of the “self-gating” effect and the compensation for the dip.
4.3 Evidence of Subband Quantization
4.3.1 Linear and Nonlinear Transport at Low Temperature
The G-VDS traces in Figure 4.2b exhibits a series of “bundles” with high density of traces. Since
all traces are separated in Vg equally, bundles therefore represent situations where G does not
change with Vg, which are exactly the conductance plateaus described in Section 1.2.2. Bundles
around zero bias are linear conductance plateaus whereas those at high bias can be classified into
half plateaus because their conductance values locate roughly in the middle of two successive
linear conductance plateaus’ values.
The linear conductance as a function of Vg is plotted in Figure 4.3a. Eleven plateaus can be
identified superimposed with small oscillations. Similar oscillations on conductance plateaus
were attributed by Biercuk et al. as Fabry-Perot interference [82]. The inset of Figure 4.3a shows
an enlarged view of the 2nd plateau from which we can see that these oscillations are quasi-
periodical in Vg with an average period of ∆ 0.12V. Plugging in the calculated gate-to-wire
capacitance per unit length Cg 30 aF (to be discussed in Section 4.4.2) into Eq. 1.12, we obtain
the effective length of the F-P cavity L 90 nm. This could be explained by the presence of a
scatterer such as a point defect located 90 nm away from a contact. The first nine plateaus
have an average plateau height of about 0.25 times conductance quantum G0 (2e2/h), which
implies that some electron scattering processes prevent full transmission of electrons from the
source to the drain. The heights of the 10th and the 11th plateaus, however, are about 0.5G0.
Another interesting feature is the change of Vg span on each plateau—decreases from about 1.0
V for the first four plateaus to about 0.5 V for the middle five plateaus, and then increase to
59
about 1.0 V for the last two plateaus. Explaining these two phenomena is the main motivation for
performing a simulation and will be covered in full detail in Section 4.4.
Figure 4.3: (a) Linear conductance as a function of gate voltage. 11 conductance plateaus can be identified with the
middle 5 ones marked by arrows. Inset: A zoom-in of the 2nd plateau, showing the small oscillations superimposed
on the plateau. (b) Gray scale plot of the normalized absolute value of transconductance as a function of gate voltage
and source/drain bias. Diamond patterns around zero bias corresponding to linear conductance plateaus in (a) are
visible. (c) Gate voltage sweeps of G for fixed values of VDS from 0 to 30 mV, stepped by 3 mV. Black circles
highlight half plateaus.
(a)
(b)0.00.51.01.52.02.53.03.54.04.5
111098
765
432
G(2
e2 /h)
1 Vg(V)
G(2
e2 /h)
-6.0 -5.8 -5.6 -5.4 -5.2 -5.00.3
0.4
0.5
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8-30-20-10
0102030
Vg(V)
V DS(
mV)
0
1|dG/dVg| (a.u.)
(c)
-8 -6 -4 -2 0 2 4 6 8 10 12 14 16 180.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
G(2
e2 /h)
Vg(V)
60
Half plateaus can be better resolved by plotting gate voltage sweeps of G for fixed values of VDS
as shown in Figure 4.3c. The left-hand trace was measured at VDS = 0 and the successive traces,
offset to the right for clarity, were incremented in steps of 3 mV up to 30 mV. For finite bias, the
integer plateaus becomes less pronounced as VDS is incremented up to 21 mV while additional
structure develops at conductance values approximately midway between the original integer
values, as indicated by black circles. At higher VDS all the structure becomes smeared out.
Rossler et al. pointed out that half plateaus can only be observed in clean samples, presumably
because scattering events in the NW become more likely when more unoccupied subband states
are energetically available at larger VDS [83]. At even higher bias, the conductance is usually
obscured by noise [50] or increases/decreases due to various self-gating effects [80]. Although
we do not observe the retrieval of integer plateaus, the presence of half plateaus can be
interpreted as the result of the cleanliness of the channel, which reduces the probability for
backscattering.
In Section 1.2.2 we mention that subband spacing can be extracted directly from the stability
diagram of a 1-D system. We can also plot the stability diagram in terms of transconductance
(dG/dVg, which is calculated by numerical differentiation from the measured differential
conductance G = dIds/dVds) rather than the differential conductance. The transconductance is zero
(or small) on conductance plateaus and show peaks in the transition regions between plateaus.
Such a stability diagram therefore emphasizes the boundaries of diamond patterns and makes the
identification of the intersections much easier. Figure 4.3c is the gray scale plot of the
normalized absolute value of transconductance calculated from the data in Figure 4.2b. A series
of diamonds around zero bias corresponding to linear conductance plateaus in Figure 4.3a are
visible. We will leave further discussion of these diamonds for Section 4.4.2 where a comparison
between extracted subband spacing from this diagram and calculated subband spacing from a
theoretical model will be provided.
4.3.2 Linear Transport in a Magnetic Field
To study the magnetotransport properties of the device, a magnetic field perpendicular to the
sample plane was applied and the liner conductance was measured as a function of side-gate bias
61
(Vbg was fixed at 0 V) at different field intensities. Figure 4.4 shows the linear conductance
response at B = 0 T (black curve) and 0.6 T (red curve). Four plateaus as labeled can be
identified in the scanned side-gate bias range, corresponding to the 5th -8th plateaus in the G-Vg
curve. Two distanced features arise at B = 0.6 T: The conductance on each plateau increases and
there is an additional half plateau appearing between the 3rd and the 4th plateaus (indicated by the
blue dashed ellipse in Figure 4.4).
Figure 4.4: Magnetotransport characters of the device. Differential conductance was measured as function of side-
gate bias without magnetic field (black curve) and with a magnetic field of 0.6 T which is perpendicular to the
sample plane (red curve). Four plateaus labeled with numbers can be identified. Compared to the case where B = 0 T,
at B = 0.6 T, conductance on each plateau increases and there is a half plateau appearing between the 3rd and the 4th
plateaus possibly due to the Zeeman splitting of a spin-degenerate level, as indicated by the blue ellipse. The
distance in terms of Vsg between the split plateaus and the original plateau is marked by the green dashed lines.
The first phenomenon is a possible indication of the reduced backscattering. As introduced in
Section 1.2.2, the presence of a static magnetic field perpendicular to the wire axis can result in
the formation of hybrid magneto-electric subbands which are a mixture of the quantization due to
the lateral confining potential of the wire and the quantizing effect of the magnetic flux in terms
of Landau level formation. As the magnetic field increases, more and more current is carried by
the edge states that can greatly suppress the backscattering. A simple estimation can provide
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
G(2
e2 /h)
Vsg(V)
B=0T B=0.6T
1
2
3
4
62
some insights about the emergence of edge states. At B = 0.6 T, the cyclotron radius of the 1st
Landau level is 0 33 nm. From the perspective of classical motion, up to 66
nm away from the boundary, the injected electrons can still scattered by the boundary and form
skipping orbit. So there should be significant contribution to the conductance from the edge
states.
The emergence of the half integer plateau between the 3rd and 4th plateaus is possibly due to the
Zeeman splitting of a spin-degenerate energy level as introduced in Section 1.2.2. Assume the g
factor of the InAs NW to be 15, which equals its bulk value, then at B = 0.6 T, 0.5 meV.
As will be discussed in Section 4.4.2, the predicted spacing between the 7th and the 8th subbands
by a theoretical model is about 2.5 meV. At B = 0 T, the two plateaus are spaced about 4.5 V
apart in terms of side-gate bias. Accordingly, the two split plateaus should be located equidistant
from the two sides of the original plateau with a side-gate bias range of 0.45 V, assuming the
capability of the side-gate to tune the energy levels in the channel does not change with the
applied magnetic field. From Figure 4.4, the side-gate spacing between the two split plateaus and
the original plateau is marked by the green dashed lines and is about 0.75 V. This discrepancy
could arise from a faulty previous assumption about gate control, and/or a change of subband
spacing due to the effect of Landau quantization.
4.3.3 Linear Transport at Higher Temperatures
The linear conductance as a function of gate bias was also measured at temperatures higher than
10 K and the result is shown in Figure 4.5. The conductance responses at T = 20 K and 30 K are
shifted for clarity. Most plateaus disappear as temperature increases from 10 K to 30 K. As is
introduced in Section 1.2.2, the conductance plateaus eventually disappear when the separation
between mode energies is comparable to, or smaller than a few (use 3 here). The fact
that plateaus can be observed at 10 K and are smeared out at 30 K gives a rough lower and upper
boundary for the subband spacing: ∆ ~ (2.6 meV, 7.8 meV), which is consistent with the
observed subband spacing from the transconductance map.
63
Figure 4.5: Liner transport at higher temperatures. G-Vg curves corresponding to T = 20 K and 30 K are shifted for
clarity. Most conductance plateaus are washed out at T = 30 K, providing a rough estimation for the subband
spacing. Inset: G-Vg curve at room temperature, from which the field-effect mobility can be extracted.
The inset of Figure 4.5 is the G-Vg relation at room temperature. Curves corresponding to
positive and negative Vg scan are presented, showing little hysteresis. The difference between the
traditional transistor character at room temperature and the conductance quantization at low
temperature is distinct. From this figure we can extract the gate voltage dependent field-effect
mobility using
(4.1)
where L is the channel length and is the summation of back-gate capacitance and side-
gate capacitance and the quantity can be obtained by numerical differentiation of the
measured G-Vg characteristic. We can apply an analytical expression for the back-gate
capacitance of a cylinder separated from a conducting plane by a dielectric slab:
/ (4.2)
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 80.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
G(2
e2 /h)
Vg(V)
30K 20K 10K
-5 -4 -3 -2 -1 0 1 2 3 4 50
1
2
3
4
G(2
e2 /h)
Vg(V)
room temperature
64
where R is the NW radius, t is the thickness of the dielectric layer and = 2.2 is an effective
gate dielectric constant taking the inhomogeneous dielectric surroundings of the NW into
account [84]. Using in the parameters of our device (L = 800 nm, t = 100 nm and R = 50 nm)
gives 55 aF. Using the fact that ⁄ 5.5, we obtain 10 aF and in turn
= 65 aF. Substituting into Eq. (4.1) gives the peak field-effect mobility
7900 cm2/(V-s). However, Eq. (4.2) assumes a metallic channel with infinite length. It has been
reported that relaxing these assumptions leads to a reduction of about 30% of close to the
depletion regime of a thin Si NW [85]. In addition, the presence of side-gates in our device
would screen the electric fields of the back-gate and further decreases . Therefore,
calculated by applying Eq. (4.2) for will be overestimated and 7900 cm2/(V-s) is actually the
lower boundary of the peak field-effect mobility .
As will be shown in Section 4.4.2, the calculated using a 3-D electrostatic simulation which
accounts for all the above factors gives 24 aF. Using this result, 21000 cm2/(V-s).
Recently Ford et al. studied the diameter-dependent mobility of InAs NWs [79] and found the
mobility increases with increasing diameter, which the authors attributed to the reduction of
surface roughness scattering. Another study [58] using the InAs NWs grown by similar
conditions as the NWs used for this thesis showed similar trend, and the mobility should be
around 5000 cm2/(V-s) for an InAs NW whose diameter is 100 nm, assuming a liner relationship
between the mobility and the diameter. The estimated here, whether based on Eq. (4.2) or
the simulation, is much higher than 5000 cm2/(V-s), which indicates a dramatic reduction of the
impurity scattering for the NW studied in this Chapter, which in turn supports the observed
quasi-ballistic nature of the transport in this device.
4.4 Three-dimensional Electrostatic and Two-dimensional
Eigenvalue Coupled Modeling of the Nanowire System
Although the presence of linear conductance plateaus and finite bias half plateaus provide strong
evidence of subband quantization, and from the temperature-variate measurement we deduct a
65
rough range of 2.6 ~ 7.8 meV for the subband spacing, detailed band structure remains to be
unclear. If subband spacing is almost constant and does not vary gate bias (such as the subband
quantization due to a saddle point potential introduced in Section 1.2.1), both the gate span and
the height of each conductance plateau should be roughly the same, assuming the capability of
tuning the energy in the channel by the gate bias does not change and the transmission
probabilities for each mode are identical. As mentioned in Section 4.3.1, the linear conductance
response in Figure 4.3a exhibits variable gate span of each plateau and doubled height for the last
two plateaus. We understand these phenomena as signs of deviation from constant equally-
spaced subband structure. Very recently, Ford et al. have used the subband spacing calculated
from the simple “particle in a cylinder” model combined with a derived relation between the gate
bias and the energy in the channel to explain the observed conductance plateaus in InAs NWs
[10]. However, this procedure is only valid for a thin NW (the thickest NW they measured has a
diameter of 35nm) so that the lateral potential difference inside the NW can be neglected. The
diameter of our NW is 95nm, the potential distribution from the bottom to the top of the NW
may play an important role in modifying the solution of 2-D Schrodinger equation and in turn
dramatically deviate the subband spacing from the “particle in a cylinder” case. Our instinct was
further supported by the failure of trying to use the subband spacing of the “particle in a cylinder”
case to explain our data, as will be shown in Section 4.4.2. The above considerations form the
motivation of performing a detailed simulation to gain better insight into the experimental results.
4.4.1 Model Description
The strategy of the modeling is getting the potential distribution in the NW from a 3-D
electrostatic simulation and coupling it to the 2-D Schrodinger to obtain the subband spacing.
The geometry of the 3-D simulation (see Figure 4.6) is exactly the same as the real device with
all dimensions obtained by fabrication parameters and SEM images. The potential distribution
V(x, y, z) is governed by the 3-D Poisson equation
· , , , , (4.3)
where , with each dielectric material volume assigned their respective values of (15.5
for InAs, 3.9 for SiO2 and 1 for the vacuum). The space charge density is set to be
66
| | in the NW and zero otherwise. Here, is the uniform
background density of ionized donors, and are 3-D electron and hole concentrations
and are given by
2 / | | (4.4a)
2 / | | (4.4b)
where is the effective mass of electrons in InAs, * * 3/2 * 3/2 2/3( )dh lh hhm m m= + is the effective mass
of holes in InAs with contributions from light holes ( ) and heavy holes ( ), and are
conduction band edge and Valance band edge, respectively, is the Fermi level of the system,
1 exp is the complete Fermi-Dirac integral of order j
with Γ being the gamma function.
Charging of the surface states is included using a simple model employing a spatially continuous
surface state density with a uniform energy distribution. The surface charge density is
| | | |
| | (4.5)
where is the surface states, | | , | | , is the surface
potential and is the surface charge neutrality level described in Section 1.2.4.
67
Figure 4.6: Screenshot of the 3-D electrostatic simulation result, showing the simulated geometry and the potential
distribution with source and drain grounded and Vbg = Vsg = -7 V.
The 3-D simulation was carried out using the electrostatic solver of a commercial finite-element
analysis (FEA) software COMSOL Multiphysics. Dirichlet boundary conditions were used for
the back and side-gates (Vbg = Vsg = Vg) and source/drain electrodes (VS = VD = 0), since the main
goal of the model is to explain linear transport phenomena observed with back-gate and side-
gates connected. Neumann boundary condition, i.e., the electric field perpendicular to the
boundary planes is zero, was applied to the top and side boundaries of the entire simulation
domain. The size of the domain was chosen to be large enough so that a change in simulation
results with further increase in domain size would be negligibly small. The potential distribution
in the simulation domain is shown in Figure 4.6 with Vbg = Vsg = -7 V.
The x axis is assumed to be the transport dimension and is centered at x = 0 nm. The calculated
potential distributions V(x, y, z) at different cross sections, x = xc, of the NW serve as input to the
2-D Schrodinger equation
, , , , (4.6)
68
This equation was solved at different Vg within the NW domain using Dirichlet boundary
condition ( 0), and the eigenvalue solver of COMSOL Multiphysics. Subband quantization
as a function of gate bias and the position along the NW can therefore obtained once E is
computed. A key assumption of the coupled model is that the linear conductance of the system is
determined by the subband quantization at the middle slice (x = 0) of the NW (which will be
justified in Section 4.5), so Eq. (4.6) was only solved with 0, , for different Vg.
From the expression of space charge density we see that this model assumes two sources for the
free carriers inside the NW: background impurities inside the NW and surface charges due to
surface states. Their relative contributions to the space charge density provide one more
parameter to play with. The charge neutrality condition is satisfied at Vg = 0, where potential is
zero everywhere and charges due to the free carriers in the NW are compensated for by
background impurities in the NW and surface states at fixed positions. This condition is
equivalent to treating the NW as “floating” in the vacuum. Thus, a simple 2-D electrostatic
simulation that mimics the floating situation could be adopted, from which could be
estimated once the portion of free electrons coming from surface states was determined. To
reduce the number of fitting parameters in this coupled model, was set to be 150 meV above
. Following this choice, and the portion of free electrons coming from surface states at Vg =
0 were adjusted until both the 3-D electrostatic simulation and the 2-D eigenvalue simulation
gave an identical depletion (threshold) voltage of Vg -7.7 V, which is consistent with the
experimental result.
4.4.2 Results of the Model
The best fit gives = 82 meV above and almost 100% of the portion of free electrons
coming from surface states at Vg = 0. The latter reinforces the reason to observe the conductance
quantization in a thick NW at low temperature: there is little backscattering in the channel and
the effect of surface scattering is also reduced for a thick NW. The calculated energy
quantization at the center of the NW as a function of Vg is obtained. Subbands with energy levels
below are occupied, and the number of occupied subbands versus Vg is plotted in Figure 4.7
(red curve). A series of steps (labeled with corresponding number) resemble the observed
69
conductance plateaus and the two main features of experimental data are basically met here: the
gate span of each step decreases from about 1 V for the first few steps to about 0.5 V for the
following steps, and then increase to above 1 V for the 10th and 11th steps. Starting from the 9th
step, subbands become two-fold degenerate, tuning the gate bias would therefore dragging two
subbands across the Fermi level at the same time, giving rise to a conductance plateau that is
doubled in height. For comparison, the energy levels calculated from the “particle in a cylinder”
model are shifted by the average electrostatic energy of the middle slice of the NW (
| | 0, , ) at different Vg, obtained from the 3-D electrostatic simulation, to
get the occupied number of subbands below . This N-Vg relation is also plotted in Figure 4.7
(black curve). This approach was adopted by Ford et al. [10] and three features can be concluded
from the result: first, the onset of the first step happens at Vg -4.7 V, which is not consistent
with the calculated threshold voltage of the 3-D electrostatic simulation; second, the gate span of
each step does not follow the observed trend; third, most steps are double-heighted due to the
onset of two-fold degenerate subbands. The comparison between the two modelling approaches
is straightforward: if we only carry out the 3-D electrostatic simulation and use the calculated
average potential to directly shift the energy levels corresponding to the well known “particle in
a cylinder” problem, the result is far from being self-consistent and deviates severely from the
observed features. They therefore cannot be used to explain our data. On the other hand, our
coupled model, while showing deviation, captures the main features of the experimental data,
and therefore stands out from its counterpart.
70
Figure 4.7: Simulated number of occupied subbands as a function of gate bias. Red curve: result from the coupled
simulation carried out by the author. Labeled numbers represent the resembled conductance plateaus. Black curve:
result from the approach adopted by Fort et al [10].
The deviation of subband spacing from the case of “particle in a cylinder” can be understood by
considering the screening effect from free carriers in the NW. When the channel is enhanced at
positive gate bias, the free electron density is high. The channel behaves more like a metallic one
in this case, strongly screening the electric field due to the potential difference between the gate
and the contacts. The potential variation inside the NW is thus negligible. When the channel is
depleted at large negative gate bias, however, the free electron density is low. The screening
effect is strongly suppressed in this case, generating large potential differences across the NW
(can be up to several hundred mV, see Figure 4.10). It is this nonuniform potential distribution
inside the NW that strongly modifies the electronic confinement potential and the subband
spacing. If the NW is thin, the absolute value of threshold voltage is usually small. This means
the nonuniformity of potential distribution inside the NW at depletion is not severe, so we only
need to consider the geometrical confinement, i.e., the “particle in a cylinder” model alone is
enough to describe the subband spacing. This model predicts that certain subbands show two-
fold degeneracy arising from the structural symmetry of cylindrical NW. As mentioned above,
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 50
4
8
12
16
20
24
28
32
36
40
44
48
num
ber o
f occ
upie
d su
bban
ds
Vg(V)
3D electrostatic simulation + "particle in a cylinder" model 3D electrostatic simulation + 2D eigenvalue simulation
3 4 5 6 7 89
1011
1 2
71
when the gate bias is close to 0, starting from the 9th step, the step height doubled owing to the
two-fold degeneracy of subbands. This is a strong indication of the recovery of symmetrical
confinement with the absence of the nonuniform potential distribution. Figure 4.8 shows the
calculated probability density profiles, | , | , for the five lowest lateral modes (subbands) at
Vg = -6 V. No degeneracy is observed here and the wave functions are pushed up and sideways
by back and side-gate bias, which differ significantly from the “particle in a cylinder” case.
These profiles therefore confirm our point that the nonuniform potential distribution inside the
NW at large negative bias breaks the symmetry and strongly modifies the electron confinement,
and in turn, the subband spacing.
Figure 4.8: Calculated probability density profiles at Vg = -6 V for the five lowest lateral modes with corresponding
energy levels with respect to conduction band edge labeled. No degeneracy is observed and the wave functions are
pushed up and sideways by back and side-gate bias, indicating the effect of the nonuniform potential distribution
inside a thick NW at large negative gate bias.
We have learned that the potential distribution across a thick NW plays an important role in
determining the electronic confinement. Since a change in Vg modifies the potential distribution,
we expect the electronic confinement, and in turn, subband spacing, to change with Vg as well,
which has been verified by our model. As mentioned earlier, in the stability diagram of 1-D
transport in terms of transconductance, the intersections of left/right tilted stripes of linear
conductance diamonds give a direct measure of the subband spacing between two successive
subbands, located above and below the Fermi level, respectively. In developing this concept, we
72
have assumed that the subband spacing is independent of gate bias. In our case, subband spacing
keeps changing with gate bias, and we can imagine that the transconductance diamonds will be
distorted with unequal slopes for left/right tilted boundaries, depending on whether the spacing is
increasing or decreasing. This unique feature, combined with the superimposed Fabry-Perot
oscillations, dramatically complicates the transconductance patterns. Nevertheless, we can still
trace the left/right tilted white stripes (transconductance peaks) in Figure 4.3b and locate the
intersections. From the corresponding source and drain bias, the subband spacing is obtained and
listed in the 4th column of Table 4.1. A prediction of the change of subband spacing based on our
coupled simulation is shown in the first two columns of Table 4.1. The 1st column is the subband
spacing between two successive subbands located above and below the Fermi level at the onset
of each plateau; the 2nd column is the subband spacing between the same two subbands, but at
the end of each plateau. The two spacing, ΔEstart and ΔEend, thus track the evolution of spacing
corresponding to each plateau. The measured spacing ΔEexperiment from transconductance
diamonds should therefore be located between the corresponding ΔEstart and ΔEend, and can be
viewed as an average effect of the change of subband spacing. From the table, we can see that
the predicted spacing for the 9th and 10th plateaus shows some deviation from the observed
values. All other predicted spacing matches the observed spacing with the right trend. For
comparison, subband spacing of the symmetric cylindrical confinement is listed in the last
column of Table 4.1, and it clearly shows that the subband spacing of the “particle in a cylinder”
cannot be used to explain the observed spacing.
73
Plateau ΔEstart ΔEend ΔEexperiment ΔEsymmetric
(meV) (meV) ( ± 0.5 meV) (meV)
1 9.2 7.8 9 5.9
2 7.5 6.2 7.5 7.8
3 6.7 5.8 6 2.8
4 3.6 3.6 4 6.8
5 2.8 3.1 3 5.6
6 3.7 2.6 4 5.5
7 2.8 2.4 2.5 8.8
8 6.7 7.6 7 2.7
9 2.4 4.5 7.5 1.4
10 6.3 3.6 9 12.1
11 8.1 9.8 9 2.3 Table 4.1: Comparison between the calculated and observed subband spacing. The 1st and 2nd column list calculated
subband spacing between two successive subbands located above and below the Fermi level at the onset and end of
each plateau, respectively, based on our coupled simulation. The 3rd column is the extracted average subband
spacing for each plateau from the transconductance diamonds in the stability diagram. The 4th column is the
calculated subband spacing of the “particle in a cylinder” model.
A byproduct of the model is the capability to perform capacitance calculations. The 3-D
electrostatic simulation includes the screening effect of nonuniform carrier distribution by
treating the channel as a semiconductor, as well as the edge effect due to the distortion of the
electric field near metal contacts [85]. It can therefore provide a more accurate estimate of the
gate capacitance. We define the total gate-to-wire capacitance as the total space charge
induced by the voltage difference between the gate (Vg) and the electrodes (grounded):
| | (4.7)
The volume integration was performed within the entire NW domain and the result is shown as
red dots in Figure 4.9a. Given that ⁄ 5.5, should be a factor of 0.85 of . was
also calculated using Eq. (4.2) with our device geometry and the result is shown as black dots in
Figure 4.9 as a comparison. As mentioned in Section 4.3.3, Khannal et al. [85] assumed a
semiconducting channel with finite length and their 3-D electrostatic simulation gave a 30%
reduction of close to the depletion regime of a thin Si NW compared with the value
74
calculated from Eq. (4.2). of our device only accounts for about 30% of the value calculated
from Eq. (4.2), indicating a further reduction of due to the screening effect from the side-
gates.
Figure 4.9: (a) Calculated gate capacitance per unit length as a function of gate bias from the 3-D electrostatic
simulation. Also shown is the back-gate capacitance calculated using Eq. (4.2) for the same device. (b)
Calculated quantum capacitance per unit length as a function of gate bias using a combination of Eq. (4.8) and
results from the 2-D eigenvalue simulation.
Quantum capacitance (QC), first introduced by Luryi [86], is an important concept in NW
devices, which accounts for the fact that the gate field penetrates through the wire since it is not
completely screened on the wire surface as is the case in an ideal macroscopic conductor.
Physically, the QC is the energy broadened density of states evaluated at the Fermi Level:
⁄ ∑ ⁄, ∑ 2 ⁄ |, (4.8)
where , are eigenvalues of Eq. (4.6) solved at the middle slice of the NW, i.e.,
energy levels of lateral modes due to the strongest confinement along the NW. Calculated QC as
a function of gate bias is shown in Figure 4.9b. The effect of discrete well-spaced modes on the
QC is clearly seen.
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 815
20
25
30
35
40
45
50
55
60
65
70
75
-8.0 -7.6 -7.2 -6.8 -6.4 -6.0 -5.6 -5.2 -4.8 -4.4 -4.0
(b)
Cap
acita
nce
(pF/
m)
Vg(V)
Cbg Cg
(a)
Vg(V)
Capacitance (pF/m
)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
75
QC affects how the band edge under the gate responds to the gate bias. To see this, we consider
an electrostatic model for a ballistic transistor [87]. The potential at the top of the barrier in the
channel is ⁄ , where is the mobile charge in the
channel, . Assume the source is grounded. In terms of energy, we obtain the
conduction band edge under the gate: / , where /
and / . Taking the derivative of with respect to , and using the fact that
⁄ , we have
| | 1⁄ (4.9)
In fact, the gate-to-channel capacitance is a series combination of the geometric ( ) and
quantum ( ) capacitance [88]. Comparing the capacitance values in Figure 4.9, we can see that,
except for the depletion case where is exponentially reduced, , which indicates that
. Therefore we expect that the value of | |⁄ is small and will keep decreasing
as Vg increases, reflecting the increasing screening effect due to the enlarged charge density in
the channel. This leads to an inefficient gate tuning of the energy levels in the channel. From
Figure 4.3a and b we see that for the left three plateaus about 1 V change in Vg can move two
successive subbands with a spacing of around 7 meV across the Fermi level, giving a
| |⁄ value of about 0.007, which is indeed very small compared with reported value
for InAs single NWFET [45].
4.5 Validation of the Model
As mentioned in Section 4.4.1, a key assumption of the model is that the linear conductance of
the NW is determined by the middle slice of the NW. This assumption originates from the logic
that at negative gate biases, since source and drain are grounded, the middle of the NW should
possess the most negative average potential, and therefore highest conduction band edge. The
presence of side-gates pointing to the middle of the NW further enhances this effect. At positive
gate biases with high carrier concentration, the gate has weaker capability in dragging the
76
conduction band edge of the middle region below the grounding level. Applying this assumption
will not generate a result that is far from the real case.
To support this assumption qualitatively, we show in Figure 4.10 the calculated potential
distribution profiles inside the NW at two slices: the middle slice (x = 0 nm) and the slice 100 nm
left to the middle one (x = -100 nm), at two gate biases (Vg = -2 and -6 V). The potential
distributions are very similar for the two slices at both gate biases, implying that the middle
region (at least from -100 nm to 100 nm) of the NW has a relatively uniform potential
distribution which can be represented by the distribution in the middle slice. Note that the
potential differences for the two biases are about 90 meV and 300 meV across the NW,
respectively, which supports our statement in Section 4.4.2 that nonuniform potential
distributions up to hundreds of meV exist with lateral cross section of the NW at negative gate
bias and are responsible for the modification of electronic confinement.
Figure 4.10: Calculated potential distribution profiles inside the NW at the middle slice (x = 0 nm) and the slice 100
nm left to it (x = -100 nm), at two gate biases (Vg = -2 and -6 V).
To further support the assumption, we calculated the average electrostatic energies at different
positions along the transport dimension x of the NW using
77
| | , , (4.10)
The position dependent energies at different gate biases are plotted in Figure 4.11a. From the top
to bottom, curves represent axial potential energy distributions at Vg = -8 ~ 8 V stepped by 2 V.
The middle section of the NW has the highest electrostatic energies at negative gate biases and
the lowest electrostatic energies at positive gate biases but with flatter potential profiles. The plot
also shows that the axial potential varies slowly except near the contact regions. This is an
essential condition to apply Thomas-Fermi picture that carrier concentration is determined by
local potential energy (Eq. (4.4)), which validates our approach of the 3-D electrostatic
simulation.
Figure 4.11: (a) Average electrostatic energy distribution along the NW. From top to bottom: distributions at Vg = -8
~ 8 V stepped by 2 V. (b) Lowest subband level distribution along the NW with fitted Fermi level labeled. From top
to bottom: distributions at Vg = -8 ~ 0 V stepped by 2 V.
The potential energy shifts the quantized energy levels in the channel. To see how this is
achieved, we use the lowest subband energy of the middle slice of the NW 0 shifted by
the potential energy differences along the x axis to represent the lowest subband distribution
020406080
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-400 -360 -320 -280 -240 -200 -160 -120 -80 -40 05055606570758085
Elec
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atic
ene
rgy(
meV
)
(b)
E 1(m
eV)
x(nm)
EF
(a)
78
along the transport dimension of the NW: 0 0 , and plot the
results at different gate biases in Figure 4.11. From the top to bottom, curves represent axial E1
distributions at Vg = -8 ~ 0 V stepped by 2 V. The fitted Fermi level is also shown in this plot.
This plot clearly shows that along the transport dimension of the NW, the lowest subband energy
at the middle of the NW is the highest. This approach can be extended to obtain the axial
distribution of multiple subbands and those at the middle slice of the NW all possess highest
energies. That is to say, the Fermi level needs to be above the subband levels at the middle of the
NW first for them to conduct. So we only need to perform the 2-D eigenvalue simulation at the
middle slice of the NW and use the corresponding eigenvalues to predict conductance
quantization characteristics.
Ideally, one should conduct the 3-D Poisson and Schrodinger self-consistent simulation coupled
through the carrier concentration to get a more accurate modeling of the device. However, this
type of simulation is computationally intense. Although our 3-D and 2-D coupled simulations are
not self-consistent, a comparison of the calculated carrier concentrations based on the two
simulations gives an estimate of how much the two simulations deviate from each other.
From the Thomas-Fermi scenario, the 1-D carrier concentration can be calculated by performing
the integration of the 3-D carrier concentration obtained from Eq. (4.4) over the middle cross
section of the NW:
0, , (4.11)
From the 2-D Schrodinger equation, the 1-D carrier concentrations at finite temperature and zero
temperature are given in the following forms:
∑ | , | 2 2 ⁄, (4.12a)
∑ | , | 4 2 ⁄, (4.12b)
where , and are eigenfunctions and eigenvalues of the Schrodinger equation and
the integrations are performed over the middle slice of the NW.
79
The calculated 1-D carrier concentrations using Eq. (4.11) and Eq. (4.12) at different gate biases
are shown in Figure 4.12. calculated from Schrodinger at T = 0 K and T = 10 K are very
close to each other. At Vg < -3 V, the two simulations give almost identical 1-D carrier
concentrations. At Vg > -3 V, the two simulations begin to deviate from each other. This
comparison shows that the coupled simulations possess good quality at negative gate biases.
Figure 4.12: Calculated 1-D carrier concentrations as a function of gate bias based on the 3-D Thomas-Fermi
scenario (squares) and the 2-D Schrodinger equation at T = 10 K (circles) and T = 0 K (triangles).
4.6 Conclusions
The transport properties of a thick InAs NW device controlled by a pair of side-gates and back-
gate were studied. The trivial electrostatic “self-gating” effect was first subtracted by making the
conductance versus source and drain bias traces symmetric with respect to the bias. Conductance
compensation was added around the zero bias regions of the traces to cure the system error. The
existence of linear conductance plateaus and half plateaus provides strong evidence of subband
quantization in the NW. The observation of conductance quantization at low temperature is very
likely to be a result of reduced backscattering in the channel. Magnetotransport measurements
indicate the emergence of magneto-electric-hybrid subbands characterized by edge states and
Zeeman splitting of these spin-degenerate states. Most of the linear plateaus disappeared as the
-8 -7 -6 -5 -4 -3 -2 -1 0
123456789
10111213
n 1D(m
-1)
Vg(V)
Thomas-Fermi Schrodinger (10K) Schrodinger (0K)
108
80
temperature was increased to 30 K, suggesting a rough range of 2.6 ~ 7.8 meV for the subband
spacing. The calculated room temperature electron mobility is higher than reported values of
InAs NWs with similar growth conditions, implying a cleaner channel for this NW, which
supports the quasi-ballistic nature of transport in the NW.
A 3-D electrostatic and 2-D eigenvalue coupled simulation was conducted to explain the
observed linear conductance features. The best fit to the data was achieved for the condition that
the background impurity concentration in the channel is very low and almost 100% of the free
carriers come from the surface sates. This condition reinforces the reason to observe the
conductance quantization in a thick NW at low temperature: there is little backscattering in the
channel and the effect of surface scattering is also reduced for a thick NW. The calculated
subband spacing from the model was compared with the values extracted from the
transconductance stability diagram and shows satisfactory agreement. The spacing differs
significantly from the “particle in a cylinder” case, where a uniform potential distribution inside
the NW is assumed, strongly indicating a modification to the electronic confinement of the NW
from the nonuniform potential distribution inside the NW, as confirmed by the model. The
underlying assumption of the model is that it is the subband quantization in the middle region of
the NW that determines the linear transport so that one only needs to solve the 2-D eigenvalue
problem within the middle slice of the NW to get the representative subband spacing. This
assumption was supported qualitatively by the potential distribution profiles along the NW from
the model and quantitatively by the calculated average potential energy and lowest subband level
distribution along the NW. Finally, a comparison of calculated 1-D carrier concentration based
on the 3-D Thomas-Fermi scenario and the 2-D Schrodinger equation shows the good quality of
the coupled model at negative gate biases.
81
Chapter 5
Conclusions and Future Outlook
This thesis studied electron transport properties in three types of single InAs NW devices.
Devices with local side-gating exhibited a universal hysteresis in the transfer characteristics,
which was attributed to carrier injection at high gate fields due to the sharp tip of side-gates. Not
all the devices with single etched constriction showed sign of conductance quantization. We
understand this as the influence of disorder which is sample-specific. For the device without
side-gates, Coulomb blockade due to electrons tunneling through DQD was presented in the
pinch-off region. For a side-gated device with an etched constriction, F-P conductance oscillation
was found superimposed onto the first conductance plateau, which is a strong indication of the
quasi-ballistic nature of the transport. In the pinch-off region, as the back-gate voltage increased,
Coulomb blockade due to electrons tunneling through MTJ, single QD and F-P oscillation was
successively observed. F-P oscillation extending all the way to the pinch-off region has never
been reported to our knowledge. Remarkable conductance quantization was observed in a thick
InAs NW without etched constriction, which is very likely to be the result of reduced surface
scattering for a thick NW. The calculated room temperature electron mobility is higher than
reported values of InAs NWs with similar growth conditions, implying a cleaner channel for this
NW, which supports the quasi-ballistic nature of transport in the NW. According to the
conducted simulation, the background impurity concentration in the channel is very low and
almost 100% of the free carriers come from the surface sates. This result reinforces the reason to
observe the conductance quantization in a thick NW at low temperatures. The calculated subband
spacing from the simulation was compared with the values extracted from the transconductance
stability diagram and shows satisfactory agreement. The spacing differs significantly from the
“particle in a cylinder” case, where a uniform potential distribution inside the NW is assumed.
This deviation strongly indicates a modification to the electronic confinement of the NW from
the nonuniform potential distribution inside the NW. Finally, the underlying assumption of the
82
simulation was validated. Overall the simulation successfully captured the main features of the
measurement results.
The complicated device fabrication turned out to be extremely difficult. Due to the long
processing period and low yield, only a few devices were measured. Meanwhile, the low
resolution of our EBL also limited the length of etched constrictions. To reach more convincing
conclusions on transport through single etched constriction in NW, a group of devices with
different etching length and aspect ratios need to be fabricated and studied. Nevertheless, this
thesis provides preliminary insight for a novel design of single InAs NW devices. Compared
with existing results reported from literature, at least two striking achievements have been
accomplished: first, Fabry-Preot oscillations in the sub-threshold region of a quasi-1D system
have been observed; second, conductance quantization has been observed in a thick NW, and the
simulation advances the understanding to the role of high gate biases on the confinement energy
of thick NWs. This platform exhibits potential of integrating QD, QPC and interferometer onto a
single NW, which is very promising for quantum computing applications.
83
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