Reconfigurable Computing -VHDL

John MorrisComputer Science/

Electrical and Computer Engineering

The University of Auckland

Iolanthe racing off Fremantle,Western Australia

Resources

These notes Will be available on the Web You can download them fromhttp://cs.auckland.ac.nz/~jmor159/reconfig

Other resources Links will be available on the same web site

VHDL text Any text on VHDL will be adequate! Recommended

P J Ashenden, Designer’s Guide to VHDL(A fellow Australian!)

Ashenden’s other text andseveral other suitable texts in the library

Background

US Department of Defense ‘High Order Language’ projectAim: One language for all defense needsResult: Ada

AdaGeneral purpose programming languageBased on PascalOriginal Ada was not Object-OrientedAda’95 has OO capabilitiesNamed after Ada, Countess of Lovelace

Never write it as ADA – it’s not an acronym!but VHDL is one!

VHDL

VHSIC Hardware Design Language VHSIC = Very High Speed Integrated Circuit

Standardized; mature IEEE 1076-2002 IEEE 1076-1987 (VHDL’87) IEEE 1076-1993 (VHDL’93) Several associated standards

IEEE.std_logic IEEE.numeric_std

Based on Ada Extensions added to support Hardware Design VHDL compiler should accept simple Ada programs Ada compiler should accept VHDL functions

About half of all high-level electronic design uses VHDL Remainder is Verilog (C based) Verilog did not become a standard until 1995 and was revised in 2001

(IEEE1364-2001)

VHDL - Basics

Case insensitiveConvention

Keywords in upper case• BEGIN, END, ENTITY, ARCHITECTURE, LOOP, ….

Variables in lower case• i, j, k, clock, …

Types in lower case• integer, std_logic, std_logic_vector

This is just a convention – you can choose your own!

For these slides, I will use this font and colour ENTITY adder IS …

for anything that you could type into a VHDL model

Assignment operator is :=

Type follows variable list

Statement terminated by ;

VHDL - Basics

Statements similar to PascalVariable declaration

x, y : integer;

Assigment x := 5.0*y + 2;

Program blocks delimited by BEGIN … END;

ExamplePROCEDURE SQR( x: integer ) RETURNS integer IS VARIABLE z : integer; BEGIN z := x * x; RETURN z; END;

VHDL is quite verbose (long winded!)

VHDL – Entities and Architectures

VHDL supports abstraction throughEntities

Defines interface for a module

Architectures Implementation of a module There may be several architectures corresponding to one

entity• Generally, there are several ways (circuits) that will

produce the same result

VHDL – Entities

Example: n-bit adder

ENTITY adder IS PORT (

a, b : IN std_logic_vector; sum : OUT std_logic_vector; carry_out : OUT std_logic;

);END adder;

adder

8

8a

b

sum8

carry_out

There are several ways ofImplementing an n-bit adder

… but all have the same interfaceor ENTITY in VHDL

Architectures

An architecture contains the implementation detailsAt a high level, a designer is only interested in the

interface – information contained in the VHDL ENTITY

Each ARCHITECTURE is associated with an ENTITY

ENTITY adder IS PORT ( … );END adder;

ARCHITECTURE ripple OF adder IS …END ripple;

ARCHITECTURE c_select OF adder IS …END c_select;

One entity

One or more architectures

Architecture – Style

Styles of architectureYou can design a circuit in several waysIn VHDL, you can build a model for a circuit in

several ways too!Behavioural

a Dataflow

b Algorithmic

Structural

Architectures – Style example

ExampleConsider a full adder:

Logic equations are:

adder

1

1

a

c_in

sum1

carry_out

1b 1

sum := a xor b xor c;carry_out := (a and b) or (b and c) or (a and c);

ENTITY full_adder IS PORT ( a, b : IN std_logic; sum : OUT std_logic; carry_out : OUT std_logic; );END adder;

Architectures – Dataflow style

ExampleConsider a full adder:

Logic equations are:

Dataflow architecture is

adder

1

1

a

c_in

sum1

carry_out

1b 1

sum := a xor b xor c;carry_out := (a and b) or (b and c) or (a and c);

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

Architectures – Behavioural (Dataflow ) styleExample

Consider a full adder:

Logic equations are:

Dataflow architecture is

adder

1

1

a

c_in

sum1

carry_out

1b 1

sum := a xor b xor c;carry_out := (a and b) or (b and c) or (a and c);

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

Note that these are signal assignments.Although they are similar to ordinary assignments (using :=),

there are some important differences which we will consider soon!

ARCHITECTURE df OF full_adder IS BEGIN sum <= a xor b xor c; carry_out <= (a and b) or (b and c) or (a and c); END df;

Architectures – Structural style

ExampleConsider a full adder:

Logic equations are:

A Structural model builds a model from other models

adder

1

1

a

c_in

sum1

carry_out

1b 1

sum := a xor b xor c;carry_out := (a and b) or (b and c) or (a and c);

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

Architectures – Structural style

Build basic models for internal elements: xor or and

Build the full adder from these elements

ENTITY xor IS a, b : IN std_logic; c : OUT std_logic;END xor;

ENTITY or IS a, b : IN std_logic; c : OUT std_logic;END xor;

ENTITY and IS a, b : IN std_logic; c : OUT std_logic;END xor;

Architectures – Structural style

Build basic models for internal elements:xororand

For these, the architecturesare trivial

ENTITY xor IS a, b : IN std_logic; c : OUT std_logic;END xor;

ARCHITECTURE A OF xor IS c <= a xor b; END xor;

Instantiate a second xor circuit, label it x2

x2

Instantiate an xor circuit, label it x1

x1

Architectures – Structural style

Now you ‘wire up’the basic elementsto make the full adder circuit

Considering the sum part only

a

bc

sum

ab

Map the signals in xor’s ENTITYto actual wires in this circuit

ARCHITECTURE structural OF full_adder IS SIGNAL ab: std_logic; BEGIN x1: xor PORT MAP( a => a, b => b, c => ab ); x2: xor PORT MAP( a => ab, b => c, c => sum ); … -- or / and circuits to compute carry outEND structural;

Architectures – Algorithmic style & mixturesAlgorithmic models can include any type of

construct that you find in a high level language – if … then … else, case, loop, procedure calls, etc.We will look at some examples of this style after

we’ve reviewed VHDL statements

Note that styles can be mixed in one modelA structural style model may include some

dataflow statements and some algorithmic blocks, etc.