Reducing the EMI Susceptibility of a Kuijk Bandgap

876 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 50, NO. 4, NOVEMBER 2008

Reducing the EMI Susceptibility of a Kuijk BandgapEnrico Orietti, Member, IEEE, Nicola Montemezzo, Member, IEEE, Simone Buso, Member, IEEE,

Gaudenzio Meneghesso, Senior Member, IEEE, Andrea Neviani, Member, IEEE, and Giorgio Spiazzi, Member, IEEE

Abstract—In this paper, the susceptibility of a Kuijk bandgapvoltage reference to electromagnetic interferences (EMIs) superim-posed to the power supply is investigated. A model of the bandgapcircuit is derived from experimental tests consisting of scatteringparameters and susceptibility measurements on a test chip. Themodel is able to correctly predict the susceptibility of the circuit bymeans of SPICE transient simulations. The simulations identify thefundamental stray components responsible for EMI coupling thatare usually not taken into account in postlayout analyses. Fromthe EMI point of view, the rectification phenomenon of bipolartransistors, used in the bandgap cell, and the operational amplifier(op-amp) input distortion are shown to cause the voltage refer-ence performance degradation. In particular, for the first time,the importance of the bandgap cell is pointed out, suggesting thatthe measures to reduce the susceptibility of the op-amp may notbe sufficient to guarantee the bandgap immunity. Moreover, theanalyses of main parasitic paths (from the power supply net to themore sensitive nodes) demonstrate the relevance of paths that arenot commonly considered during the design phase and that maylead to an immunity degradation. Possible solutions to reduce thebandgap susceptibility are also explored, suggesting design crite-ria, filtering techniques, and layout variations. A second test chipis designed and manufactured to validate the suggested improve-ments and verify the critical role of the bandgap cell. Finally, asimplified theoretical analysis, which allows a fast bandgap sus-ceptibility evaluation, is presented. This tool is used to point outthe importance of the rectification phenomenon compared to theop-amp differential pair distortion.

Index Terms—Differential pair distortion, Kuijk bandgap, RFinterference, rectification, stray components.

I. INTRODUCTION

E LECTROMAGNETIC susceptibility (EMS) is becominga relevant issue at chip level; while modern ICs operate

at lower supply and bias voltages, the amplitude and varietyof environmental RF interferences are steadily growing. As aconsequence, the assessment of an IC immunity to EMI is nowa-days compulsory not only for its qualification for the military,avionic, and automotive markets, but also for less demandingapplications, as those related to household appliances, lighting,and telecommunications. Because of that, a lot of susceptibilitytests have been standardized and performed on various families

Manuscript received March 27, 2007; revised December 21, 2007 andApril 4, 2008. First published October 28, 2008; current version publishedNovember 20, 2008.

E. Orietti, G. Meneghesso, A. Neviani, and G. Spiazzi are with the Depart-ment of Information Engineering (DEI), University of Padova, Padova 35131,Italy (e-mail: [email protected]; [email protected]; [email protected];[email protected]).

N. Montemezzo is with Canova Tech Srl., Padova 35129, Italy (e-mail:[email protected]).

S. Buso is with the Department of Technology and Management of In-dustrial Systems (DTG), University of Padova, Vicenza 36100, Italy (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.org.

Digital Object Identifier 10.1109/TEMC.2008.2004581

of integrated devices. As an example, several studies arereported in the literature where custom analog chips used inautomotive applications have been tested [1], [2]. Following amore general and systematic approach, simulations and anal-yses (manual calculations based on simplified formulas) werepresented for different operational amplifiers (op-amps) [3], [4],which can be considered key devices for a whole lot of analogICs. As an immediate extension, other tests and simulationsfocused on the bandgap voltage reference [5]–[8], whoseprecision influences the accuracy of the front-end devices, prac-tically all analog ICs. The majority of these studies, however,was focused on the role of the op-amp (inherently embeddedin most bandgaps). The inspiring idea was that designing ahighly immune op-amp would be sufficient to increase oreven to guarantee the overall bandgap immunity. In particular,the op-amp was designed so as to achieve high-power-supplynoise attenuation (PSNA) and low distortion, because it wasconsidered the only or, at least, the main responsible of theoverall voltage reference immunity degradation.

In this paper, instead, the susceptibility of the bandgap cell isinvestigated, demonstrating its critical role and suggesting thatall efforts to design a highly immune op-amp can be useless ifthis issue is not taken into proper consideration. The relevanceof rectification phenomena on the overall bandgap susceptibilitywill be pointed out and additional EMI parasitic paths will be ex-plored, suggesting nonobvious reasons why the op-amp PSNAis not always the key factor for high immunity achievement.

The starting point of this discussion will be the validation ofa SPICE model used to investigate the bandgap immunity. Val-idation is obtained from comparisons between simulations andexperimental measurements on a test chip that we designed andmanufactured for this purpose. In Section II, the most importantdesign and modeling aspects will be described, highlighting thekey stray components that we identified for optimal suscepti-bility simulations and that are not usually taken into account inpostlayout analyses.

Section III examines the mechanisms that cause the bandgapmalfunction in the presence of RF noise. The change of thevoltage reference value, when disturbances are superimposedon the power supply, will be explained as a consequence of therectification phenomenon of bipolar transistors in the bandgapcell and the op-amp input distortion. A simple procedure willbe suggested to evaluate the susceptibility of a bandgap voltagereference without performing transient simulations (very time-consuming). This approach, based on small-signal simulationsand the mathematical description of the dc shift presented inSection III, will be validated for the tested Kuijk bandgap. Themain parasitic paths followed by the interfering signals to cou-ple with the IC will also be explored in this section. It will bedemonstrated that the op-amp rejection of the noise coupled to

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ORIETTI et al.: REDUCING THE EMI SUSCEPTIBILITY OF A KUIJK BANDGAP 877

Fig. 1. Schematic of the Kuijk bandgap with Miller OTA using a wide-swing cascode current source.

Fig. 2. Microscopic photograph of the designed Kuijk bandgap voltage refer-ence. Total occupied area is 450 µm × 100 µm (excluding bonding pads).

the supply network (expressed by its PSNA) is not as importantas usually assumed, as other paths, such as the parasitic capaci-tive coupling of poly silicon resistors or the path from the supplynet to input nodes of the operational transconductance amplifier(OTA), play a very significant role.

Finally, in Section V, some possible solutions to increase thebandgap immunity will be presented. Design criteria, filteringapproaches, and layout variations are first investigated throughsimulations and then validated by measurements on a new testchip. Results show that the overall voltage reference suscepti-bility can be drastically reduced operating on both the bandgapcell and the op-amp.

II. DESIGN OF THE KUIJK BANDGAP

The measurements, simulations, and analyses presented inthis paper refer to a Kuijk bandgap voltage reference (see Fig. 1for a detailed scheme of this implementation) [9]. The circuit hasbeen manufactured, on our design, using a 0.7-µm Bi-CMOStechnology intended for smart power applications (30-V lateraldouble-diffused MOS (DMOS) are indeed available). Fig. 2 de-picts a microscopic photograph of the device. Table I reportsthe main specifications met by the designed bandgap. For the

TABLE IKUIJK BANDGAP AND MILLER OP-AMP CHARACTERISTICS

bandgap section, the rated values were fully validated by exper-imental measurements on prototype chips.

In the scheme of Fig. 1, the two main blocks constituting thebandgap voltage reference are shown.

1) The bandgap cell, responsible for dc reference value andtemperature drift compensation, made up of two p-n-pbipolar junction transistors (BJT) (Q1 area is 5.76 µm2

while Q2 is eight times Q1 to create a common cen-troid structure) and three resistors (R1 = R2 = 140 kΩ,R3 = 17.5 kΩ) integrated in the chip using a multifingercommon centroid topology. A 6-µA bias current is usedfor this cell, i.e., 3 µA for each transistor.

2) The op-amp is mainly used to regulate and mirror the twocurrents inside the Kuijk cell.

The three-stage op-amp was designed using a very standardtopology: a Miller OTA followed by a common drain stage, toobtain the low output impedance necessary to drive the bandgapload. The input pair is biased by a 10-µA current, while thesecond stage (a common source amplifier with RC Miller com-pensation) is biased by a 40-µA current. In order to achievethe bandgap specifications and increase the op-amp power sup-ply rejection ratio (PSRR), a wide-swing cascode topology isused for the OTA bias net. The input differential pair is made


Fig. 3. Blocks diagram of CTW analyses for susceptibility tests using the“direct voltage injection.”

up of two PMOS transistors (W = 300µm and L = 1.6µm)operating in a subthreshold region, so as to increase the OTAdifferential gain, to minimize the input transistor mismatch, andconsequently, to meet the voltage reference accuracy specifi-cation. SPICE simulations confirmed that the weak inversionPMOS biasing, as compared to the strong inversion’s one, al-lowed to increase the op-amp PSRR, at least at low frequencies.

III. SUSCEPTIBILITY TESTS ON THE BANDGAP

Immunity tests at the IC level have only recently been stan-dardized by IEC committees with the IEC-62132 norm for EMItests on ICs from 150 kHz to 1 GHz.

Immunity measurements can be performed using the follow-ing methods (described in detail in [10] and [11]):

1) workbench Faraday Cage;2) TEM cell;3) direct RF power injection;4) bulk current injection (BCI).To enable a better understanding of immunity issues at the

chip level and easily replicate EMI in test bench simulations,the direct RF injection is preferred. The main idea is to superim-pose a deterministic noise (for instance, a continuous-time wave(CTW) sinusoid of known amplitude and frequency) to one ofthe input (or even output) pins of the device under test (DUT).The presence of RF noise may alter the behavior of the DUT,and the noise effect can be monitored using oscilloscopes, mul-timeters, network analyzers, etc. Differently from the proceduredescribed in [10], in our tests, we measured and saved the inputnoise voltage instead of the input noise power. This allowedthe experimental conditions to be more easily replicated in thesimulations.

In Fig. 3, the setup for susceptibility measurements onthe bandgap is presented. The RF noise (generated usingthe HP8647A signal generator and amplified with the AR-10W1000C RF amplifier), in the frequency range from 1 MHzto 1 GHz, is superimposed to the supply voltage VDD = 3V(two AA batteries have been used in order to avoid additionalnoise injection) through a bias tee, while the output voltage ref-erence is checked by means of the HP3458A multimeter. Themeasurements on the prototypes are performed on the silicondie (packaging is not applied to avoid the influence of bonding

Fig. 4. EMI test on the Kuijk bandgap with a 200 mVrm s interfering CTWnoise superimposed to supply voltage. Comparison between measurements andsimulations (schematic with ideal components and optimized schematic includ-ing stray components).

and encapsulation parasitics) by means of RF probes. To avoidenvironmental electromagnetic pollution, all measurements areperformed inside an RF-shielded probe station.

As can be seen from Fig. 4, the effect of RF noise superim-posed to the supply voltage is to induce a reduction of the outputvoltage reference. In particular, the percentage output voltagevariation (with respect to the nominal dc value) induced by EMIis plotted as a function of the interfering noise frequency.

The susceptibility shape can be compared to a “bell shape” [3]because the most critical frequency range is placed at mediumfrequencies (for this particular device from 30 to 200 MHz)while at low and high frequencies, the bandgap presents a higherimmunity. The physical explanation will be given later, after adiscussion of the main RF noise coupling and conductive pathsand the malfunction mechanisms.

A great effort has been made to correctly model the device, inorder to obtain a good match between measurements and simu-lations, both with small-signal analyses (scattering parameters)and transient simulations of the voltage reference susceptibility(taking into account all nonlinear effects).

To correctly simulate the bandgap behavior in the presence ofRF noise and with small-signals perturbations, particular atten-tion was paid to some parasitic elements that are not automati-cally extracted in our postlayout simulations tool. The followingparastic elements have thus been manually calculated and addedto the SPICE netlist:

1) capacitive coupling between polyresistors used in thebandgap cell and N-well underneath;

2) N-well parasitic resistances;3) parasitic capacitances between N-well and the substrate;4) metal–metal, metal–well, and metal–substrate

capacitances.As an example, Fig. 5 shows the equivalent SPICE schematic

that, taking into account the first three stray components justdescribed, has been used to model the most critical of the high-resistivity (HR) polyresistor employed in the circuit. The figurealso shows how each element of the equivalent circuit is relatedto the physical structure (on the die) of the component.

Scattering parameters measurements and simulations wereperformed considering the bandgap voltage reference as a two-port device, where PORT 1 is the supply net while PORT 2


Fig. 5. Layout of HR polyresistors including the schematic of parasitic devicesused to model N-well resistance and polysilicon-well-substrate capacitances.

is represented by the output reference node. The comparisonbetween measurements and simulations is depicted in Fig. 6.

In Fig. 4, three different curves are plotted: an experimentaltest with an interfering noise of 200 mVRMS and two simula-tions with the same disturbing noise superimposed on a simpli-fied ideal schematic and a SPICE netlist including all the straycomponents just described.

The satisfactory results shown in Figs. 4 and 6 suggest the im-portance of accurate modeling to correctly predict the bandgapbehavior in the presence of RF disturbances. The EMI simula-tions were performed replicating the same test bench presentedin Fig. 3, by means of transient analyses (very time-consuming)in order to include all nonlinear effects, whose importance willbe shown in the following.

The accurate SPICE model, obtained for the voltage refer-ence, allowed us to simulate the possible paths used by interfer-ences to couple with the IC. Three main paths were analyzed,as depicted in Fig. 7.

1) PATH 1 was through the parasitic capacitances of polysil-icon resistors toward the N-well (connected to the supplynet). Fig. 7 highlights the three main resistors (R1 , R2 ,and R3) used in the Kuijk bandgap voltage reference thatcouple the RF noise coming from the power supply net.

2) PATH 2 was from the op-amp supply net (in particularthrough the OTA bias net) to the amplifier inputs, as de-scribed in Fig. 8. In particular, CS represents the parasiticcapacitance between VDD and common-source node “X,”while Cg1 and Cg2 represent the gate-to-source and gate-to-bulk capacitances of the differential pair.

3) PATH 3 was from the op-amp supply net to its outputand back through the bandgap cell to the OTA inputs (seeFig. 7).

PATH 1 and PATH 2 can be considered more relevant forinterference propagation in this bandgap. To validate the state-ment, some ac simulations were performed on the voltage ref-erence device. Fig. 9 shows the simulated transfer functionsfrom the bandgap supply net to three fundamental nodes of thedevice under test (nodes A, B, and C, as labeled in Fig. 7). Eachfigure includes the contributions of the three paths compared tothe overall transfer function. It can be noticed that PATH 3 is neg-ligible at medium frequencies, where the bandgap susceptibility

is greater, demonstrating that measures to obtain a high PSNAwould not, by themselves, significantly improve the bandgapimmunity.

IV. SIMPLIFIED ANALYTICAL APPROACH

The main effect of RF noise applied to the inputs of an op-ampis the output offset caused by slew-rate asymmetries [3], as wellas distortion phenomena in the differential input pair [4], [12].

Up to now, these aspects, related to the op-amp only, wereconsidered uniquely or, at least, fundamentally responsible forvoltage reference malfunctions [5], [7]. Our analyses show thatthe op-amp is, in fact, not the only amplifier responsible for theoutput voltage degradation, and also that the bandgap cell playsa fundamental role on the circuit dc shift.

The following sections describe in detail the effects on thebandgap voltage dc shift of the rectification phenomenon in-volving the two p-n-p BJTs. The op-amp input distortion effectis also analyzed (as presented in [12]) for a subthreshold biasedinput pair, in order to compare the effects of the two phenomena.

A. Rectification Phenomenon on the Kuijk Bandgap

Equation (1) expresses the Kuijk bandgap voltage output asa function of the dc base–emitter voltage of p-n-p transistorsQ1 and Q2 and resistors ratio R2/R3 (as is described in detailin [9])

VREF = VEB1 +R2

R3(VEB1 − VEB2) . (1)

The current in the two transistors, with forward-biased diodeconfiguration, can be evaluated as

IC = IS expVEB

VT(2)

where IS represents the junction reverse saturation current andVT the thermal voltage. If a sinusoidal noise (with amplitudevEB |RF ) is superimposed on the emitter–base voltage, the col-lector current is affected by a dc shift that can be evaluatedas

IC |dc IS expVEB |dc

VT

[1 +

(vEB |RF

2VT

)2]

(3)

where a second-order approximation has been applied. If theop-amp has no voltage offset at its inputs, the p-n-p bipolarscurrents can be assumed to be equal, leading to

IQ1 = IQ2

IQ1 = IS1 exp VE B 1 |d c

VT

[1 +

(vE B 1 |R F

2VT

)2]

IQ2 = IS2 exp VE B 2 |d c

VT

[1 +

(vE B 2 |R F

2VT

)2]

.

(4)

Moreover, the Kuijk topology implies that

VEB1|dc − VEB2|dc

R3

= IS1 expVEB1|dc

VT

[1 +

(vEB1|RF

2VT

)2]

. (5)


Fig. 6. Scattering parameters for the designed Kuijk bandgap. PORT1 is the IC supply net while PORT2 is represented by the output net. Measurements on theprototype are compared to the simulations on a simplified schematic (only ideal components) and an optimized netlist including all major parasitic devices.

Fig. 7. Main paths for RF noise propagation in the Kuijk bandgap.

The equation system given by (4) and (5) can be solved, theunknown variables being VEB1|dc and VEB2|dc , resulting in

VEB1|dc = VT log

1

R3IS1/VT

[1 +

(vEB1|RF/2VT

)2]

× log

IS2

IS1

1 +(

vEB2|RF

2VT

)2

1 +(

vEB1|RF

2VT

)2

(6)

Fig. 8. Input differential pair parasitic capacitances responsible for RF noisescoupling from supply net. This is one of the two most important paths followedby power supply EMI to disturb the op-amp inputs, causing input distortion andbipolar transistor rectification.

VEB2|dc = VEB1|dc − VT log

IS2

IS1

1 +(

vEB2|RF

2VT

)2

1 +(

vEB1|RF

2VT

)2

. (7)

Substituting (6) and (7) to (1), the final value of the Kuijkbandgap voltage reference can be evaluated when an RF noiseis superimposed to the base–emitter voltage of BJTs. The valuesvEB1|RF and vEB2|RF represent the power-supply residual noise


Fig. 9. Simulated transfer functions from the bandgap supply net to (a) op-amp positive input, (b) op-amp negative input, and (c) Q2 emitter. Each figure includesthree separate contributions of paths 1, 2, and 3 compared to the overall transfer function when all paths are enabled.

applied to the base–emitter terminals of the p-n-p transistors.These values cannot be obtained from measurements on theprototype because the setup would influence the bandgap be-havior; consequently, they must be calculated from SPICE sim-ulations, exploiting the SPICE model we developed and tuned.To this purpose, it is interesting to note that, instead of usingslow transient simulations, the residual RF noise on the BJTemitter terminals can be found, leading to the same results, byfast ac simulations simply by computing the following transferfunctions between the supply and the emitter nodes:

HEB1,2|RF =vEmitter(1,2)

vbandgap−power−supply. (8)

If the bandgap dc shift has to be evaluated when the RF noiseis applied to another IC net, only the transfer functions (8) mustbe substituted with the proper ones (i.e., the transfer functionsbetween the noise injection pin and the BJT emitters).

In Fig. 10, the effect of the rectification phenomenon on thebandgap behavior is depicted. The dc shift induced by the rec-tification effect is compared to the susceptibility measurementperformed on the test chip.

It can be noticed that the approximated analytical approachpredicts the so-called bell shape. This is mainly due to the trans-fer functions (8) that present a reverse susceptibility shape. In-deed, the residual RF noise on the BJT emitter terminals isfiltered both at low and high frequencies [see Fig. 9(a) and (c)],and consequently, no rectification can take place. In the low-frequency range, the noise does not reach the bipolar emittersbecause the parasitic N-well to HR-poly capacitances, whichact as high-pass filters, do not allow the noise to propagate, andmoreover, PATH 2 is also blocked by the high PSRR of thebias-net current mirrors. Conversely, at high frequencies, thestray capacitance connected to the supply net acts as a bypassfilter capacitor, preventing the noise from coupling with the op-amp. In particular, the 50-Ω output impedance of the RF signalgenerator (or possibly the RF amplifier) creates a low-pass fil-ter with the N-well to the substrate capacitor of the op-amp

Fig. 10. DC output voltage variation induced by a 564 mVPP interfering noisesuperimposed on bandgap power supply. The overall estimated dc shift is plot-ted and compared to the two separate contributions given by rectification effectand op-amp distortion.The estimated global effect (sum of distortion and recti-fication effects) is also plotted.

bias net (a large N-well is used to physically create the PMOSnecessary to bias the Miller OTA) and the polysilicon resistors.

B. Differential Pair Offset Induced by RF Noises

In this section, the effect of RF noise applied to the input netsof an op-amp will be investigated. In particular, the differentialnoise voltage superimposed to a common-mode noise at thesame frequency will be demonstrated to generate a dc shift ofthe op-amp output voltage. The differential pair dc shift, whichcan be considered as an op-amp input offset, will ultimatelycause a deviation of the bandgap voltage regulator output fromthe nominal value.

The following analysis was previously presented in [12] foran NMOS or an n-p-n input differential pair. A different math-ematical approach was presented in [4] for NMOS and n-p-ntransistors, leading to the same results. Here, these analyses areapplied to a PMOS subthreshold input pair, also including the


Fig. 11. PMOS differential pair including parasitic capacitances and inputvoltages for offset calculation in the presence of an RF signal with differential-and common-mode components.

effect of an RF noise on the power-supply net of the same OTA.It will be demonstrated that this interference acts as a common-mode noise, and therefore, can induce a dc shift in the outputcurrent, when it is superimposed to a differential voltage (forinstance, on the OTA input pins).

The subthreshold expression for a PMOS transistor drain cur-rent is known to be:

iD = ISW

Lexp

(vSG − VTp

nVT

).

Considering the differential current

∆iD = iD1 − iD2

the following expression can be obtained:

∆iD = IS1W1

L1exp (VX − VCM − VTp/nVT )

× exp(vx − vcm − (vd/2)/nVT )

− IS2W2

L2exp(VX − VCM − VTp/nVT )

× exp (vx − vcm + (vd/2)/nVT ) (9)

where vX represents the voltage at the common-source node ofthe differential pair.

Assuming the input pair uses identical devices, i.e., W1 =W2 , L1 = L2 , and IS1 = IS2 , and considering a second-orderpower series reduction, (9) can be written as

∆iD −IBIAS|dc

2vd

nVT

(1 − vcm − vx

nVT

). (10)

Taking into account Fig. 11, it is possible to write

vX =s(CGS1 + CGS2) + gm1 + gm2

s(CGS1 + CGS2 + CN + CS ) + gm1 + gm2vCM

+sCS

s(CGS1 + CGS2 + CN + CS ) + gm1 + gm2vRF (11)

that can be simplified into

VX (s) =2gm + s(2CGS)

2gm + s(2CGS + CT )VCM(s)

+sCS

2gm + s(CGS + CT )VRF(s) (12)

assuming CGS1 = CGS2 = CGS , CT = CS + CN , and gm1 =gm2 = gm . Substituting (12) to (10) and noting that

gm =IBIAS

2nVT

Y (s) =2gm sCT

2gm + s(CT + 2CGS)

it is possible to write

∆iD (s)=−IBIAS

2nVTvd(s)

1− vcm(s)Y (s)

IBIAS+Y (s)

CS

CT

vrf

IBIAS

.

(13)Considering the differential- and common-mode signals

vd = vd,pk cos(ωt)

vcm = vcm ,pk cos(ωt + φd−cm)

vrf = vrf ,pk cos(ωt + φd−rf )

where φd−cm represents the phase difference between thedifferential- and common-mode voltages while φd−rf representsthe phase difference between the differential noise on OTA in-puts and RF interference on OTA supply net; it is possible toderive from (13) the dc offset caused by the multiplication ofthe two components (vd and vcm ) at the same frequency ω

∆iD |dc = − 12nVT

vd,pkvcm ,pk |Y (jω)|2

× cos[φd−cm + phase(Y (jω))]

+1

2nVT

CS

CT

vd,pkvrf ,pk |Y (jω)|2

× cos [φd−rf + phase(Y (jω))] . (14)

The differential pair output current dc offset just evaluatedcan be used to calculate the voltage offset at op-amp inputsusing the transconductance amplification of the differential pairstage. The following expression can be used:

∆VIN |Diff .PairDistortion@DC = −∆iD |dc

gm. (15)

Expression (15) can now be used as the op-amp input offsetvoltage to evaluate the deviation from the nominal value in aKuijk bandgap, due to op-amp distortion, when an RF noise withdifferential- and common-mode components is superimposed tothe inputs. This yields

∆VREF = −∆VIN |Diff .PairDistortion@DC

(1 +

R2

R3

)(16)

considering an ideal op-amp (infinite gain and no intrinsic dcoffset).

The residual RF noise amplitude and phase for both op-amp input nodes (vMINUS and vPLUS ) can be evaluated using aSPICE analysis of the whole bandgap schematic, including alllayout parasitic devices. As previously described, a small sig-nal (ac) simulation can be performed to calculate all necessaryvalues in the frequency range of interest (i.e., 1 MHz–1 GHz),or alternatively, some transient simulations (requiring a greaterCPU effort) can be used, leading to the same results. A dc sim-ulation (or possibly some manual calculation) must be done as


well to evaluate the size of various capacitances (the gate–sourceand gate–bulk parasitic capacitances of the input differential pairand the total capacitance connected to the common source netof the input differential pair) and the transconductance gain ofthe input pair (see Fig. 11). For this analysis, the following datawere obtained from a dc simulation and used to evaluate thebandgap dc shift:

gm = 100µS

CGS = 370 fF

CS = 50 fF

CN = 300 fF.

Using the results of ac simulations, the output voltage shiftcan be calculated using (16). In Fig. 10, the bandgap dc outputvoltage variation due to the distortion phenomenon induced bya 200−mVrms RF noise superimposed on the bandgap powersupply is plotted. It is interesting to compare the contribution ofthe distortion phenomenon to the rectification effect; the latterclearly appears to be more relevant.

Finally, the global effect of RF noises superimposed to thepower supply net, as caused by both phenomena, can be approx-imately evaluated by means of the following expression:

VREF = −∆VIN |Diff .PairDistortion@DC

(1 +

R2

R3

)

+ VEB1 +R2

R3(VEB1 − VEB2) . (17)

The global dc shift is compared (in Fig. 10) to the measurementson the test chip demonstrating that the simplified analyticalapproach can adequately describe the chip’s susceptibility toRF interference (RFI).

V. SOLUTIONS TO IMPROVE THE BANDGAP IMMUNITY

Having understood the main propagation paths and the twomain performance degradation mechanisms, some solutions canbe suggested and tested at the circuit and layout levels. We firstperformed SPICE transient simulations and/or approximatedanalyses to identify possible changes to improve the immunityto RFI. Afterward, a second test chip was created to check andvalidate these solutions. The EMI measurement results on thenew test chip will be used to evaluate the suggested solutions.We did not perform an optimization of proposed solutions, forinstance, the size of resistive or capacitive filters do not representthe best choice for susceptibility reduction. The main purposeof this discussion is indeed to describe a typical approach toinvestigate EMS issues in a bandgap voltage reference and pro-pose possible solutions to increase immunity. The optimizationprocess is left for the possible final design phase.

A. Layout and/or Technology Modifications

Some layout or technology solutions can be applied to reducethe noise coupled from the resistors and injected in the tran-sistors base–emitter junctions or possibly superimposed to thedifferential pair inputs.

Fig. 12. Kuijk bandgap scheme with additional components to increase im-munity to EMI.

The immunity of the bandgap toward noise coming from thesupply net can be drastically increased by designing the resis-tors without the N-well below. The drawback of this choice isclearly represented by an increased coupling toward substrate,and so, by a possible reduction of bulk current injection im-munity. To partially overcome this limit, the designer can puta substrate guard ring around the bandgap cell resistors in or-der to reduce the disturbances below the bandgap cell. Anotherpossible solution, though not always available, as in the caseof low-cost or nonautomotive technologies, is represented bythe use of a triple-well beneath the resistors that would createa series capacitive connection toward both the supply net andthe substrate. Triple wells are commonly available and used inmodern Bi-CMOS-DMOS technology (below 0.35 µm). Thetradeoff is represented in this case by the silicon cost, whichwill be higher because of the presence of a buried N -layer andtrenches.

Otherwise, as tested in our chip, a simple resistor can beput in series to the N-wells below the polysilicon resistors (aspresented in Fig. 12) in order to create a low-pass RC filter withthe well to substrate capacitance. The filtering provision justdescribed has been considered in the following as the “base”configuration for comparison with other solutions. In particular,all further solutions have been tested on the Kuijk bandgap witha 33 kΩ RFILTER−N−Well resistor in series to the polysiliconresistor N-wells. The effect of this provision can be appreciatedby comparing Fig. 13 with Fig. 4. As can be seen, the maximumdc output voltage deviation is reduced by a factor of 0.5.

It is also very interesting to notice, as depicted in Fig. 14, thatin the base configuration, the bandgap dc shift can be explainedby the rectification phenomenon only, while the distortion effectis completely negligible. The same result can also be foundin the case of a layout with no N-well below the polysiliconresistors. Such a layout, comparable to the use of triple-wells,again suggests the relevance of the rectification effect on thebandgap voltage dc shift.

B. Change of the Bias Current

The bandgap cell bias current is determined by the size ofresistor R1 using the formula

IR1 =1

R1

KT

qln

(JQ2

JQ1

)(18)


Fig. 13. Measurements and simulations of dc output voltage variation inducedby a 564 mVPP interfering noise superimposed on the bandgap power supply.Continuos lines are used for simulation results while markers for measure-ments on test ICs. Comparison of EMI tests on the “base” configuration (useof RFILTER−N−Well on the basic scheme) represented by diamonds with theother three provisions suggested. Squares are used for RFILTER−OTA (addedto the base configuration); stars for the use of two additional 250 fF capaci-tors on p-n-p emitter–base (plus the RFILTER−N−Well ); triangles for a “base”topology with doubled bandgap cell bias current. Finally, the previous resultson original first design are compared, using circle markers for measurements.

Fig. 14. DC output voltage variation induced by a 564 mVPP interferingnoise superimposed on the bandgap power supply for the base configuration.The overall estimated dc shift is plotted and compared to the two separatecontributions given by the rectification effect and the op-amp distortion.

where JQ1 and JQ2 represent the current density of the twobipolar transistors.

The ratio JQ1/JQ2 becomes a fixed value after the choiceof the ratio R1/R2 (usually unity) and that of the ratioAreaQ1/AreaQ2 . The value of resistor R3 is then chosen soas to minimize the temperature drift at a particular operatingtemperature.

Changing the bias current in the bandgap cell means chang-ing the resistors R1 and R2 values. In particular, from (18), anincrease of the bias current implies a reduction of resistance R1 ,which intrinsically determines a decrease of the occupied area,and consequently, of the capacitive coupling from the polysili-con resistor and the underlying N-well.

The comparison between 3 µA (“base” configuration) and6 µA (a double bias current applied to the “base” configuration)

bandgap bias currents is depicted in Fig. 13. Even if no N-wells are used below polysilicon resistors, an improvement canbe observed, because the greater current flowing in the p-n-pbipolar transistors doubles the forward bias capacitances thatact as bypass filters.

C. Capacitive Filtering

In order to reduce the noise coupled to the BJTs emitter–base, some filtering solutions can be used. To validate the as-sertion, two bypass capacitors, each one 250 fF in size, havebeen added to the bandgap cell in parallel to the p-n-p tran-sistors, as depicted in Fig. 12 (as in the case of the doubledbias current, also the capacitive filters are applied together withthe 33 kΩ RFILTER−N−Well). These two capacitors act in thesame way as the parasitic capacitances, i.e., reducing the RFnoise between emitter and base of p-n-ps (reduction of the rec-tification phenomenon) and also applied to the op-amp inputs(reduction of differential- and common-mode noise voltages andconsequently of differential pair distortion). Fig. 13 shows theeffect of this provision through a comparison with the “base”configuration.

While the bandgap cell bias current increase represents atradeoff between power consumption and immunity to EMI, theuse of additional capacitors requires extra silicon area.

It is worth noticing that the susceptibility decrease has amonotonic but not linear dependence to capacitor size. A para-metric ac simulation (in a fine tuned-SPICE netlist as previouslydescribed) can also be used to choose the optimal value of thefiltering capacitor. The size of the bypass capacitors must be cho-sen verifying that the bandgap closed-loop stability constraintsare also met. Indeed, depending on the bandgap and op-amptopologies, a large capacitor size could lead to voltage refer-ence oscillations. This is not the case for the Kuijk bandgapthat was tested (at simulation level) also using 2-pF bypasscapacitors.

D. Resistive Filtering

The last provision investigated, and probably the best onefor both increasing immunity and saving area, is the use of anadditional resistor to filter the OTA bias current, as depictedin Fig. 12. The main idea is that in the “base” configuration,no noise comes from the polysilicon resistors. As described inSection III, the other possible way for RF interferences to coupleand propagate is represented by the op-amp bias net. The 4-kΩ resistor acts as a filter with the parasitic capacitance of thecascode current mirror, reducing the noise injected in the device.The resistor value must be chosen carefully to prevent op-ampmalfunctions, due to the dc voltage drop on RFILTER−OTA . Forthis reason, and to allow the insertion of a larger resistor, thesource follower stage has not been filtered, so as to allow thedesired bandgap output current.

Fig. 13 plots the results of this provision as compared to the“base” configuration, showing an improvement in the immunitylevel.


VI. CONCLUSION

In this paper, the EMI immunity of a Kuijk bandgap hasbeen discussed. The comparison between measurements andsimulations pointed out the importance of the layout parasiticcapacitances, in particular those introduced by the bandgap cellresistors (N-well to polyparasitic capacitance), for accuratelyestimating the bandgap susceptibility.

An analysis focused on the scattering parameters, measuredand simulated, was used as a starting point to obtain a goodmodel description of the Kuijk bandgap together with EMI mea-surements and simulations. Mathematical analyses, validated bycomparison with immunity tests and SPICE simulations, pointedout the critical role of the bandgap cell to explain the voltagereference susceptibility. In particular, the bipolar rectificationeffect has been proven to be more relevant than the op-ampdistortion induced by RF noise applied to the differential inputpair. Some simple design solutions (use of resistive or capacitivefiltering and change of bias current) and layout modifications(technology improvements for the bandgap cell resistors) wereproposed and experimentally verified to reduce the rectificationphenomenon and op-amp distortion effect. The solutions inves-tigated pointed out a tradeoff between bandgap EMI immunityand silicon cost, supply current or occupied area, suggesting todesigners some possible ways to reduce bandgap susceptibility.The filter size optimization has been omitted to focus the atten-tion on the proposed approach to this fundamental issue ratherthan on the specific immunity level obtained for this particulardevice.

ACKNOWLEDGMENT

This work has been carried out within the national researchprograms “PRIN”: “Reliability issues, design, and modeling ofintegrated circuits (ICs) with high immunity against RF dis-turbances and electrostatic discharge, manufactured in BCD(Bipolar-CMOS-DMOS) technology” (2004–2005) and “Elec-tromagnetic interference immunity analysis of analog/digital in-tegrated controllers for smart power applications” (2006–2007).The authors would like to thank the support in device manufac-turing provided by Europractice-IMEC.

REFERENCES

[1] M. Citron, M. Corradin, S. Buso, G. Spiazzi, and F. Fiori, “Susceptibilityof integrated circuits to RFI: Analysis of PWM current-mode controllersfor SMPS,” in Proc. IEEE 28th Annu. Conf. Ind. Electron. Soc. (IECON2002), vol. 4, pp. 3227–3231.

[2] F. Fiori, “Prediction of RF interferences effects in smart power integratedcircuits,” in Proc. Int. Symp. Electromagn. Compat., Washington, DC,Aug. 2000, pp. 345–347.

[3] G. Masetti, G. Setti, and N. Speciale, “On the key role of parasitic ca-pacitances in the determination of susceptibility to EMI of integrated op-erational amplifiers,” presented at the Int. Symp. Electromagn. Compat.(EMC), Zurich, Switzerland, 1999.

[4] F. Fiori and P. S. Crovetti, “Nonlinear effects of radio-frequency inter-ference in operational amplifiers,” IEEE Trans. Circuits Syst. I, vol. 49,no. 3, pp. 367–372, Mar. 2002.

[5] A. Pretelli, A. Richelli, L. Colalongo, and Z. M. Kovacs-Vajna, “Robustdesign of bandgap voltage references with low EMI susceptibility,” inProc. IEEE Int. Symp. Electromagn. Compat., Aug. 2003, vol. 1, pp. 298–302.

[6] A. Pretelli, A. Richelli, L. Colalongo, and Z. M. Kovacs-Vajna, “Reductionof EMI susceptibility in CMOS bandgap reference circuits,” IEEE Trans.Electromagn. Compat., vol. 48, no. 4, pp. 760–765, Nov. 2006.

[7] F. Fiori and P. S. Provetti, “Investigation on EMI effects in bandgap voltagereferences,” in Proc. Int. Workshop EMC (CEM COMPO), Toulouse,France, Nov. 2002, pp. 35–39.

[8] M. Corradin, G. Spiazzi, and S. Buso, “Effects of RFI and undergroundcurrents on a smart power bandgap voltage reference,” presented at the Int.Symp. Electromagn. Compat.—EMC Europe, Eindhoven, The Nether-lands, Sep. 2004.

[9] K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-StateCircuits, vol. 8, no. 3, pp. 222–226, Jun. 1973.

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[12] M. Corradin, G. Spiazzi, and S. Buso, “Effects of radio frequency in-terefernce in opamp differential input stages,” presented at the Int. Symp.Electromagn. Compat., Chicago, IL, vol. 3, 2005.

Enrico Orietti (S’06–M’07) received the Laurea de-gree in electronic engineering and the Ph.D. degree inindustrial electronics and informatics from the Uni-versity of Padova, Padova, Italy, in 2003 and 2006,respectively.

Since 2003, he has been with the Power Elec-tronics Research Group, Department of InformationEngineering, University of Padova, where he is cur-rently a Research Fellow. His current research inter-ests include electromagnetic compatibility issues atchip level, smart power ICs (analog and mixed signal

design), and dc/dc switch-mode power supplies.

Nicola Montemezzo (S’06–M’07) was born in Dolo,Venezia, Italy, on December 21, 1978. He received theLaurea degree in electronic engineering in 2003 andthe Ph.D. degree in electronic and telecommunica-tion engineering in 2007, both from the Universityof Padova, Padova, Italy, while he was engaged inresearch on electromagnetic compatibility issues atintegrated circuits.

He has been with STMicroelectronics, where hewas engaged in advance modeling of bipolar transis-tors for RF and SOI applications. In 2007, he joined

Canova Tech Srl., Padova, as an Analog Design Engineer, where he is currentlyleading different designs of ICs for low power and biomedical applications.

Simone Buso (M’98) received the Graduate degreein electronic engineering and the Ph.D. degree in in-dustrial electronics and informatics from the Uni-versity of Padova, Padova, Italy, in 1992 and 1997,respectively.

Since 1993, he has been with the Power Elec-tronics Research Group, Department of InformationEngineering, University of Padova, where he is cur-rently an Associate Professor of electronics. His cur-rent research interests include industrial and powerelectronics fields and are specifically related to dc/dc

and ac/dc converters, smart power integrated circuits, digital control and robustcontrol of power converters, solid-state lighting, electromagnetic compatibilityapplied to integrated circuits, and switch-mode power supplies.


Gaudenzio Meneghesso (S’95–M’97–SM’07) wasborn in Padova, Italy, in 1967. He received the Lau-rea degree in electronics engineering in 1992 andthe Ph.D. degree in electrical and telecommunica-tion engineering in 1997, both from the University ofPadova, Padova.

In 1995, he was at the University of Twente,Twente, The Netherlands, where he was engaged inresearch on the dynamic behavior of protection struc-tures against electrostatic discharge (ESD). Since2002, he has been with the University of Padova, as

an Associate Professor. He is the author or coauthor of more than 250 technicalpapers (30 invited papers). He is a Reviewer of several international journals:IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE ELECTRON DEVICE LETTERS,Institution of Electrical Engineers Electronics Letters, Semiconductor Scienceand Technology (IOP), Microelectronics Reliability (Elsevier). His current re-search interests include electrical characterization, modeling, and reliability ofmicrowave devices on III–V semiconductors such as GaAs and InP (MESFETs,HEMTs, and pseudomorphic high electron mobility transistors), electrical char-acterization, modeling and reliability of electronic and optoelectronic devicesgrown on wide bandgap semiconductors (SiC and GaN), electrical characteri-zation, modeling and reliability of RF-microelectromechanical system switchesfor reconfigurable antenna switches, design, characterization and modeling ofESD protection structures for CMOS and SMART POWER integrated circuits,including electromagnetic interference issues.

Dr. Meneghesso has been the Technical program Chair of Workshop on Com-pound Semiconductor Devices and Integrated Circuits (WOCSDICE) 2001,General Chair of HETECH 2001, and General Chair of WOCSDICE 2007.He served on the Technical Program Committee of several international confer-ences: European Microwave Week (EuMW) 2005 and 2006, IEEE-InternationalReliability Physics Symposium (IRPS) 2005, 2006, and 2007, EOS-ESD Symp.2006. He served several years for the IEEE International Electron Device Meet-ing (IEDM): he was in the Quantum Electronics and Compound SemiconductorsSubcommittee as a member in 2003, as Chair in 2004 and 2005, while in 2006and 2007, he has been in the Executive Committee as European ArrangementsChair. Finally, he is Editor of the IEEE ELECTRON DEVICE LETTERS for the com-pound semiconductor devices area. He received the Italian Telecom Award forhis thesis work in 1993. He was the receipient of four Best Paper Awards at the1996, 1999, and 2007 European Symposium Reliability of Electron Devices,Failure Physics, and Analysis (ESREF) conferences and at the 2006 ElectricalOverstress/Electrostatic Discharge Symposium (EOS/ESD).

Andrea Neviani (S’92–M’05) received the Laureadegree (cum laude) in physics from the Universityof Modena, Modena, Italy, in 1989, and the Ph.D.degree in electronics and telecommunication engi-neering from the University of Padova, Padova, Italy,in 1994.

From 1994 to 1998, he was a Research Associateat the University of Padova, where, since November1998, he is an Associate Professor. From November1998 to November 1999, he was a Visiting Engineer atRutherford Appleton Laboratory, Oxfordshire, U.K.

In his early career, he worked on numerical simulation, modeling, and charac-terization of compound semiconductor devices for high-frequency applications,and silicon devices from BiCMOS processes, with emphasis on effects inducedby hot carriers. In the recent past, he has contributed to the study of methods forthe statistical simulation of Very-large-scale integration (VLSI) circuits. He isthe coauthor of more than 90 journal articles and conference papers. His currentresearch interests include design of analog and mixed-signal CMOS circuits foranalog signal processing, low-power implantable biomedical devices, and RFultra-wideband receivers.

Giorgio Spiazzi (S’91–M’93) received the Graduate(cum laude) degree in electronic engineering and thePh.D. degree in industrial electronics from the Uni-versity of Padova, Padova, Italy, in 1988 and 1993,respectively.

He started working as a Researcher at the De-partment of Information Engineering, University ofPadova, where he is an Associate Professor since2001. His current research interests include advancedcontrol techniques of dc/dc converters, high powerfactor rectifiers, soft-switching techniques, electronic

ballasts, and electromagnetic compatibility in power electronics.

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Reducing the EMI Susceptibility of a Kuijk Bandgap